Place & Route TRACE Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version ispLever_v72_PROD_Build (44) Wed Dec 02 16:16:08 2009 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce.exe -v 1 -o receiver_dpram.twr receiver_dpram.ncd receiver_dpram.prf Design file: receiver_dpram.ncd Preference file: receiver_dpram.prf Device,speed: LCMXO2280C,3 Report level: verbose report, limited to 1 item per preference -------------------------------------------------------------------------------- Preference SummaryFREQUENCY PORT "RXC" 100.000000 MHz (1 errors) 918 items scored, 1 timing error detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY PORT "RXC" 100.000000 MHz ; 918 items scored, 1 timing error detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 0.181ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RECEIVE_CONTROL/rd_adr_i_0 (from RXC_c -) Destination: FF Unknown RAM_B/mem_0_1/RAM1 (to RXC_c +) Delay: 4.513ns (21.8% logic, 78.2% route), 2 logic levels. Constraint Details: 4.513ns physical path delay RECEIVE_CONTROL/SLICE_8 to RAM_B/mem_0_1/SLICE_22 exceeds 5.000ns delay constraint less 0.000ns skew and 0.668ns WAD_SET requirement (totaling 4.332ns) by 0.181ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.613 R13C9A.CLK to R13C9A.Q0 RECEIVE_CONTROL/SLICE_8 (from RXC_c) ROUTE 3 1.647 R13C9A.Q0 to R10C10D.D0 RECEIVE_CONTROL/rd_adr_i_0 CTOF_DEL --- 0.371 R10C10D.D0 to R10C10D.F0 RECEIVE_CONTROL/SLICE_73 ROUTE 8 1.882 R10C10D.F0 to R9C9D.A1 RECEIVE_CONTROL_N_284_i (to RXC_c) -------- 4.513 (21.8% logic, 78.2% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 4.968ns 55.PADDI to R13C9A.CLK Destination Clock Path: Destination Clock: Delay Connection 4.968ns 55.PADDI to R9C9D.CLK2 Warning: 96.506MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY PORT "RXC" 100.000000 MHz ; | 100.000 MHz| 96.506 MHz| 2 * | | | ---------------------------------------------------------------------------- 1 preference(marked by "*" above) not met. ---------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total ---------------------------------------------------------------------------- RECEIVE_CONTROL/rd_adr_i_0 | 3| 1| 100.00% | | | RECEIVE_CONTROL_N_284_i | 8| 1| 100.00% | | | ---------------------------------------------------------------------------- Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: RXC_c Source: RXC.PAD Loads: 46 Covered under: FREQUENCY PORT "RXC" 100.000000 MHz ; Timing summary: --------------- Timing errors: 1 Score: 362 Cumulative negative slack: 181 Constraints cover 918 paths, 1 nets, and 476 connections (77.3% coverage) -------------------------------------------------------------------------------- Generated from the file 'C:\ispTOOLS7_2_STRT\work\i2s_ip_25_receiver_v2\receiver_dpram.twr'