progxmega.elf: file format elf32-avr Sections: Idx Name Size VMA LMA File off Algn 0 .text 0000087e 00000000 00000000 00000094 2**1 CONTENTS, ALLOC, LOAD, READONLY, CODE 1 .data 00000004 00802000 0000087e 00000912 2**0 CONTENTS, ALLOC, LOAD, DATA 2 .bss 00000014 00802004 00802004 00000916 2**0 ALLOC 3 .debug_aranges 00000040 00000000 00000000 00000916 2**0 CONTENTS, READONLY, DEBUGGING 4 .debug_pubnames 00000168 00000000 00000000 00000956 2**0 CONTENTS, READONLY, DEBUGGING 5 .debug_info 00000bd7 00000000 00000000 00000abe 2**0 CONTENTS, READONLY, DEBUGGING 6 .debug_abbrev 000002bc 00000000 00000000 00001695 2**0 CONTENTS, READONLY, DEBUGGING 7 .debug_line 00000584 00000000 00000000 00001951 2**0 CONTENTS, READONLY, DEBUGGING 8 .debug_frame 000000f0 00000000 00000000 00001ed8 2**2 CONTENTS, READONLY, DEBUGGING 9 .debug_str 00000673 00000000 00000000 00001fc8 2**0 CONTENTS, READONLY, DEBUGGING Disassembly of section .text: 00000000 <__vectors>: 0: 0c 94 fa 00 jmp 0x1f4 ; 0x1f4 <__ctors_end> 4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 10: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 14: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 18: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 20: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 24: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 28: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 2c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 30: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 34: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 38: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 3c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 40: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 44: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 48: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 4c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 50: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 54: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 58: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 5c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 60: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 64: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 68: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 6c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 70: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 74: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 78: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 7c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 80: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 84: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 88: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 8c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 90: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 94: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 98: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 9c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> a0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> a4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> a8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> ac: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> b0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> b4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> b8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> bc: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> c0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> c4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> c8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> cc: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> d0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> d4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> d8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> dc: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> e0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> e4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> e8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> ec: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> f0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> f4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> f8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> fc: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 100: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 104: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 108: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 10c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 110: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 114: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 118: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 11c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 120: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 124: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 128: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 12c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 130: 0c 94 87 01 jmp 0x30e ; 0x30e <__vector_76> 134: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 138: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 13c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 140: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 144: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 148: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 14c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 150: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 154: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 158: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 15c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 160: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 164: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 168: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 16c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 170: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 174: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 178: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 17c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 180: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 184: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 188: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 18c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 190: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 194: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 198: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 19c: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1a0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1a4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1a8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1ac: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1b0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1b4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1b8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1bc: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1c0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1c4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1c8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1cc: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1d0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1d4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1d8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1dc: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1e0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1e4: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1e8: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1ec: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 1f0: 0c 94 20 01 jmp 0x240 ; 0x240 <__bad_interrupt> 000001f4 <__ctors_end>: 1f4: 11 24 eor r1, r1 1f6: 1f be out 0x3f, r1 ; 63 1f8: cf ef ldi r28, 0xFF ; 255 1fa: df e3 ldi r29, 0x3F ; 63 1fc: de bf out 0x3e, r29 ; 62 1fe: cd bf out 0x3d, r28 ; 61 200: 00 e0 ldi r16, 0x00 ; 0 202: 0c bf out 0x3c, r16 ; 60 204: 18 be out 0x38, r1 ; 56 206: 19 be out 0x39, r1 ; 57 208: 1a be out 0x3a, r1 ; 58 20a: 1b be out 0x3b, r1 ; 59 0000020c <__do_copy_data>: 20c: 10 e2 ldi r17, 0x20 ; 32 20e: a0 e0 ldi r26, 0x00 ; 0 210: b0 e2 ldi r27, 0x20 ; 32 212: ee e7 ldi r30, 0x7E ; 126 214: f8 e0 ldi r31, 0x08 ; 8 216: 00 e0 ldi r16, 0x00 ; 0 218: 0b bf out 0x3b, r16 ; 59 21a: 02 c0 rjmp .+4 ; 0x220 <__do_copy_data+0x14> 21c: 07 90 elpm r0, Z+ 21e: 0d 92 st X+, r0 220: a4 30 cpi r26, 0x04 ; 4 222: b1 07 cpc r27, r17 224: d9 f7 brne .-10 ; 0x21c <__do_copy_data+0x10> 226: 1b be out 0x3b, r1 ; 59 00000228 <__do_clear_bss>: 228: 10 e2 ldi r17, 0x20 ; 32 22a: a4 e0 ldi r26, 0x04 ; 4 22c: b0 e2 ldi r27, 0x20 ; 32 22e: 01 c0 rjmp .+2 ; 0x232 <.do_clear_bss_start> 00000230 <.do_clear_bss_loop>: 230: 1d 92 st X+, r1 00000232 <.do_clear_bss_start>: 232: a8 31 cpi r26, 0x18 ; 24 234: b1 07 cpc r27, r17 236: e1 f7 brne .-8 ; 0x230 <.do_clear_bss_loop> 238: 0e 94 22 01 call 0x244 ; 0x244
23c: 0c 94 3d 04 jmp 0x87a ; 0x87a <_exit> 00000240 <__bad_interrupt>: 240: 0c 94 00 00 jmp 0 ; 0x0 <__vectors> 00000244
: /*! TWIC Master Interrupt vector. */ int main(void) { 244: df 93 push r29 246: cf 93 push r28 248: cd b7 in r28, 0x3d ; 61 24a: de b7 in r29, 0x3e ; 62 24c: 2a 97 sbiw r28, 0x0a ; 10 24e: cd bf out 0x3d, r28 ; 61 250: de bf out 0x3e, r29 ; 62 /*! Buffer with test data to send.*/ uint8_t sendBuffer[] = {0x07,0x00,0xff}; 252: ce 01 movw r24, r28 254: 01 96 adiw r24, 0x01 ; 1 256: 8e 83 std Y+6, r24 ; 0x06 258: 9f 83 std Y+7, r25 ; 0x07 25a: e0 e0 ldi r30, 0x00 ; 0 25c: f0 e2 ldi r31, 0x20 ; 32 25e: e8 87 std Y+8, r30 ; 0x08 260: f9 87 std Y+9, r31 ; 0x09 262: f3 e0 ldi r31, 0x03 ; 3 264: fa 87 std Y+10, r31 ; 0x0a 266: e8 85 ldd r30, Y+8 ; 0x08 268: f9 85 ldd r31, Y+9 ; 0x09 26a: 00 80 ld r0, Z 26c: 88 85 ldd r24, Y+8 ; 0x08 26e: 99 85 ldd r25, Y+9 ; 0x09 270: 01 96 adiw r24, 0x01 ; 1 272: 88 87 std Y+8, r24 ; 0x08 274: 99 87 std Y+9, r25 ; 0x09 276: ee 81 ldd r30, Y+6 ; 0x06 278: ff 81 ldd r31, Y+7 ; 0x07 27a: 00 82 st Z, r0 27c: 8e 81 ldd r24, Y+6 ; 0x06 27e: 9f 81 ldd r25, Y+7 ; 0x07 280: 01 96 adiw r24, 0x01 ; 1 282: 8e 83 std Y+6, r24 ; 0x06 284: 9f 83 std Y+7, r25 ; 0x07 286: 9a 85 ldd r25, Y+10 ; 0x0a 288: 91 50 subi r25, 0x01 ; 1 28a: 9a 87 std Y+10, r25 ; 0x0a 28c: ea 85 ldd r30, Y+10 ; 0x0a 28e: ee 23 and r30, r30 290: 51 f7 brne .-44 ; 0x266 uint8_t sendBuffer2[] = {0x03,0x00}; 292: 83 e0 ldi r24, 0x03 ; 3 294: 8c 83 std Y+4, r24 ; 0x04 296: 1d 82 std Y+5, r1 ; 0x05 /* Initialize PORTE for output and PORTD for inverted input. */ PORTF.DIRSET = 0b00000100; 298: e0 ea ldi r30, 0xA0 ; 160 29a: f6 e0 ldi r31, 0x06 ; 6 29c: 84 e0 ldi r24, 0x04 ; 4 29e: 81 83 std Z+1, r24 ; 0x01 PORTF.OUTCLR= 0b00000100; 2a0: e0 ea ldi r30, 0xA0 ; 160 2a2: f6 e0 ldi r31, 0x06 ; 6 2a4: 84 e0 ldi r24, 0x04 ; 4 2a6: 86 83 std Z+6, r24 ; 0x06 /* Initialize TWI master. */ TWI_MasterInit(&twiMaster,&TWID,TWI_MASTER_INTLVL_LO_gc,TWI_BAUDSETTING); 2a8: 84 e0 ldi r24, 0x04 ; 4 2aa: 90 e2 ldi r25, 0x20 ; 32 2ac: 60 e9 ldi r22, 0x90 ; 144 2ae: 74 e0 ldi r23, 0x04 ; 4 2b0: 40 e4 ldi r20, 0x40 ; 64 2b2: 25 e0 ldi r18, 0x05 ; 5 2b4: 0e 94 d3 01 call 0x3a6 ; 0x3a6 /* Initialize TWI slave. */ /* Enable LO interrupt level. */ PMIC.CTRL |= PMIC_LOLVLEN_bm; 2b8: a0 ea ldi r26, 0xA0 ; 160 2ba: b0 e0 ldi r27, 0x00 ; 0 2bc: e0 ea ldi r30, 0xA0 ; 160 2be: f0 e0 ldi r31, 0x00 ; 0 2c0: 82 81 ldd r24, Z+2 ; 0x02 2c2: 81 60 ori r24, 0x01 ; 1 2c4: 12 96 adiw r26, 0x02 ; 2 2c6: 8c 93 st X, r24 2c8: 12 97 sbiw r26, 0x02 ; 2 sei(); 2ca: 78 94 sei while (twiMaster.status != TWIM_STATUS_READY) { 2cc: 80 91 16 20 lds r24, 0x2016 2d0: 88 23 and r24, r24 2d2: e1 f7 brne .-8 ; 0x2cc /* Wait until transaction is complete. */ } TWI_MasterWrite(&twiMaster,SLAVE_ADDRESS,sendBuffer,3); 2d4: 84 e0 ldi r24, 0x04 ; 4 2d6: 90 e2 ldi r25, 0x20 ; 32 2d8: 60 e2 ldi r22, 0x20 ; 32 2da: 9e 01 movw r18, r28 2dc: 2f 5f subi r18, 0xFF ; 255 2de: 3f 4f sbci r19, 0xFF ; 255 2e0: a9 01 movw r20, r18 2e2: 23 e0 ldi r18, 0x03 ; 3 2e4: 0e 94 2a 02 call 0x454 ; 0x454 while (twiMaster.status != TWIM_STATUS_READY) { 2e8: 80 91 16 20 lds r24, 0x2016 2ec: 88 23 and r24, r24 2ee: e1 f7 brne .-8 ; 0x2e8 /* Wait until transaction is complete. */ } TWI_MasterWrite(&twiMaster,SLAVE_ADDRESS,sendBuffer2,2); 2f0: 84 e0 ldi r24, 0x04 ; 4 2f2: 90 e2 ldi r25, 0x20 ; 32 2f4: 9e 01 movw r18, r28 2f6: 2c 5f subi r18, 0xFC ; 252 2f8: 3f 4f sbci r19, 0xFF ; 255 2fa: 60 e2 ldi r22, 0x20 ; 32 2fc: a9 01 movw r20, r18 2fe: 22 e0 ldi r18, 0x02 ; 2 300: 0e 94 2a 02 call 0x454 ; 0x454 while (twiMaster.status != TWIM_STATUS_READY) { 304: 80 91 16 20 lds r24, 0x2016 308: 88 23 and r24, r24 30a: e1 f7 brne .-8 ; 0x304 30c: ff cf rjmp .-2 ; 0x30c 0000030e <__vector_76>: while(1); return 0; } ISR(TWID_TWIM_vect) { 30e: 1f 92 push r1 310: 0f 92 push r0 312: 0f b6 in r0, 0x3f ; 63 314: 0f 92 push r0 316: 00 90 38 00 lds r0, 0x0038 31a: 0f 92 push r0 31c: 00 90 39 00 lds r0, 0x0039 320: 0f 92 push r0 322: 00 90 3b 00 lds r0, 0x003B 326: 0f 92 push r0 328: 11 24 eor r1, r1 32a: 10 92 38 00 sts 0x0038, r1 32e: 10 92 39 00 sts 0x0039, r1 332: 10 92 3b 00 sts 0x003B, r1 336: 2f 93 push r18 338: 3f 93 push r19 33a: 4f 93 push r20 33c: 5f 93 push r21 33e: 6f 93 push r22 340: 7f 93 push r23 342: 8f 93 push r24 344: 9f 93 push r25 346: af 93 push r26 348: bf 93 push r27 34a: ef 93 push r30 34c: ff 93 push r31 34e: df 93 push r29 350: cf 93 push r28 352: cd b7 in r28, 0x3d ; 61 354: de b7 in r29, 0x3e ; 62 PORTF.OUTSET= 0b00000100; 356: e0 ea ldi r30, 0xA0 ; 160 358: f6 e0 ldi r31, 0x06 ; 6 35a: 84 e0 ldi r24, 0x04 ; 4 35c: 85 83 std Z+5, r24 ; 0x05 TWI_MasterInterruptHandler(&twiMaster); 35e: 84 e0 ldi r24, 0x04 ; 4 360: 90 e2 ldi r25, 0x20 ; 32 362: 0e 94 ee 02 call 0x5dc ; 0x5dc PORTF.OUTCLR= 0b00000100; 366: e0 ea ldi r30, 0xA0 ; 160 368: f6 e0 ldi r31, 0x06 ; 6 36a: 84 e0 ldi r24, 0x04 ; 4 36c: 86 83 std Z+6, r24 ; 0x06 } 36e: cf 91 pop r28 370: df 91 pop r29 372: ff 91 pop r31 374: ef 91 pop r30 376: bf 91 pop r27 378: af 91 pop r26 37a: 9f 91 pop r25 37c: 8f 91 pop r24 37e: 7f 91 pop r23 380: 6f 91 pop r22 382: 5f 91 pop r21 384: 4f 91 pop r20 386: 3f 91 pop r19 388: 2f 91 pop r18 38a: 0f 90 pop r0 38c: 00 92 3b 00 sts 0x003B, r0 390: 0f 90 pop r0 392: 00 92 39 00 sts 0x0039, r0 396: 0f 90 pop r0 398: 00 92 38 00 sts 0x0038, r0 39c: 0f 90 pop r0 39e: 0f be out 0x3f, r0 ; 63 3a0: 0f 90 pop r0 3a2: 1f 90 pop r1 3a4: 18 95 reti 000003a6 : */ void TWI_MasterInit(TWI_Master_t *twi, TWI_t *module, TWI_MASTER_INTLVL_t intLevel, uint8_t baudRateRegisterSetting) { 3a6: df 93 push r29 3a8: cf 93 push r28 3aa: 00 d0 rcall .+0 ; 0x3ac 3ac: 00 d0 rcall .+0 ; 0x3ae 3ae: cd b7 in r28, 0x3d ; 61 3b0: de b7 in r29, 0x3e ; 62 3b2: 89 83 std Y+1, r24 ; 0x01 3b4: 9a 83 std Y+2, r25 ; 0x02 3b6: 6b 83 std Y+3, r22 ; 0x03 3b8: 7c 83 std Y+4, r23 ; 0x04 3ba: 4d 83 std Y+5, r20 ; 0x05 3bc: 2e 83 std Y+6, r18 ; 0x06 twi->interface = module; 3be: e9 81 ldd r30, Y+1 ; 0x01 3c0: fa 81 ldd r31, Y+2 ; 0x02 3c2: 8b 81 ldd r24, Y+3 ; 0x03 3c4: 9c 81 ldd r25, Y+4 ; 0x04 3c6: 80 83 st Z, r24 3c8: 91 83 std Z+1, r25 ; 0x01 twi->interface->MASTER.CTRLA = intLevel | 3ca: e9 81 ldd r30, Y+1 ; 0x01 3cc: fa 81 ldd r31, Y+2 ; 0x02 3ce: 01 90 ld r0, Z+ 3d0: f0 81 ld r31, Z 3d2: e0 2d mov r30, r0 3d4: 8d 81 ldd r24, Y+5 ; 0x05 3d6: 88 63 ori r24, 0x38 ; 56 3d8: 81 83 std Z+1, r24 ; 0x01 TWI_MASTER_RIEN_bm | TWI_MASTER_WIEN_bm | TWI_MASTER_ENABLE_bm; twi->interface->MASTER.BAUD = baudRateRegisterSetting; 3da: e9 81 ldd r30, Y+1 ; 0x01 3dc: fa 81 ldd r31, Y+2 ; 0x02 3de: 01 90 ld r0, Z+ 3e0: f0 81 ld r31, Z 3e2: e0 2d mov r30, r0 3e4: 8e 81 ldd r24, Y+6 ; 0x06 3e6: 85 83 std Z+5, r24 ; 0x05 twi->interface->MASTER.STATUS = TWI_MASTER_BUSSTATE_IDLE_gc; 3e8: e9 81 ldd r30, Y+1 ; 0x01 3ea: fa 81 ldd r31, Y+2 ; 0x02 3ec: 01 90 ld r0, Z+ 3ee: f0 81 ld r31, Z 3f0: e0 2d mov r30, r0 3f2: 81 e0 ldi r24, 0x01 ; 1 3f4: 84 83 std Z+4, r24 ; 0x04 } 3f6: 26 96 adiw r28, 0x06 ; 6 3f8: cd bf out 0x3d, r28 ; 61 3fa: de bf out 0x3e, r29 ; 62 3fc: cf 91 pop r28 3fe: df 91 pop r29 400: 08 95 ret 00000402 : * \retval TWI_MASTER_BUSSTATE_IDLE_gc Bus state is idle. * \retval TWI_MASTER_BUSSTATE_OWNER_gc Bus state is owned by the master. * \retval TWI_MASTER_BUSSTATE_BUSY_gc Bus state is busy. */ TWI_MASTER_BUSSTATE_t TWI_MasterState(TWI_Master_t *twi) { 402: df 93 push r29 404: cf 93 push r28 406: 00 d0 rcall .+0 ; 0x408 408: cd b7 in r28, 0x3d ; 61 40a: de b7 in r29, 0x3e ; 62 40c: 8a 83 std Y+2, r24 ; 0x02 40e: 9b 83 std Y+3, r25 ; 0x03 TWI_MASTER_BUSSTATE_t twi_status; twi_status = (TWI_MASTER_BUSSTATE_t) (twi->interface->MASTER.STATUS & 410: ea 81 ldd r30, Y+2 ; 0x02 412: fb 81 ldd r31, Y+3 ; 0x03 414: 01 90 ld r0, Z+ 416: f0 81 ld r31, Z 418: e0 2d mov r30, r0 41a: 84 81 ldd r24, Z+4 ; 0x04 41c: 83 70 andi r24, 0x03 ; 3 41e: 89 83 std Y+1, r24 ; 0x01 TWI_MASTER_BUSSTATE_gm); return twi_status; 420: 89 81 ldd r24, Y+1 ; 0x01 } 422: 23 96 adiw r28, 0x03 ; 3 424: cd bf out 0x3d, r28 ; 61 426: de bf out 0x3e, r29 ; 62 428: cf 91 pop r28 42a: df 91 pop r29 42c: 08 95 ret 0000042e : * * \retval true If transaction could be started. * \retval false If transaction could not be started. */ bool TWI_MasterReady(TWI_Master_t *twi) { 42e: df 93 push r29 430: cf 93 push r28 432: 00 d0 rcall .+0 ; 0x434 434: 0f 92 push r0 436: cd b7 in r28, 0x3d ; 61 438: de b7 in r29, 0x3e ; 62 43a: 8a 83 std Y+2, r24 ; 0x02 43c: 9b 83 std Y+3, r25 ; 0x03 bool twi_status = (twi->status & TWIM_STATUS_READY); 43e: ea 81 ldd r30, Y+2 ; 0x02 440: fb 81 ldd r31, Y+3 ; 0x03 442: 82 89 ldd r24, Z+18 ; 0x12 444: 19 82 std Y+1, r1 ; 0x01 return twi_status; 446: 89 81 ldd r24, Y+1 ; 0x01 } 448: 24 96 adiw r28, 0x04 ; 4 44a: cd bf out 0x3d, r28 ; 61 44c: de bf out 0x3e, r29 ; 62 44e: cf 91 pop r28 450: df 91 pop r29 452: 08 95 ret 00000454 : */ bool TWI_MasterWrite(TWI_Master_t *twi, uint8_t address, uint8_t *writeData, uint8_t bytesToWrite) { 454: 0f 93 push r16 456: df 93 push r29 458: cf 93 push r28 45a: cd b7 in r28, 0x3d ; 61 45c: de b7 in r29, 0x3e ; 62 45e: 27 97 sbiw r28, 0x07 ; 7 460: cd bf out 0x3d, r28 ; 61 462: de bf out 0x3e, r29 ; 62 464: 8a 83 std Y+2, r24 ; 0x02 466: 9b 83 std Y+3, r25 ; 0x03 468: 6c 83 std Y+4, r22 ; 0x04 46a: 4d 83 std Y+5, r20 ; 0x05 46c: 5e 83 std Y+6, r21 ; 0x06 46e: 2f 83 std Y+7, r18 ; 0x07 bool twi_status = TWI_MasterWriteRead(twi, address, writeData, bytesToWrite, 0); 470: 8a 81 ldd r24, Y+2 ; 0x02 472: 9b 81 ldd r25, Y+3 ; 0x03 474: 2d 81 ldd r18, Y+5 ; 0x05 476: 3e 81 ldd r19, Y+6 ; 0x06 478: 6c 81 ldd r22, Y+4 ; 0x04 47a: a9 01 movw r20, r18 47c: 2f 81 ldd r18, Y+7 ; 0x07 47e: 00 e0 ldi r16, 0x00 ; 0 480: 0e 94 69 02 call 0x4d2 ; 0x4d2 484: 89 83 std Y+1, r24 ; 0x01 return twi_status; 486: 89 81 ldd r24, Y+1 ; 0x01 } 488: 27 96 adiw r28, 0x07 ; 7 48a: cd bf out 0x3d, r28 ; 61 48c: de bf out 0x3e, r29 ; 62 48e: cf 91 pop r28 490: df 91 pop r29 492: 0f 91 pop r16 494: 08 95 ret 00000496 : * \retval false If transaction could not be started. */ bool TWI_MasterRead(TWI_Master_t *twi, uint8_t address, uint8_t bytesToRead) { 496: 0f 93 push r16 498: df 93 push r29 49a: cf 93 push r28 49c: cd b7 in r28, 0x3d ; 61 49e: de b7 in r29, 0x3e ; 62 4a0: 25 97 sbiw r28, 0x05 ; 5 4a2: cd bf out 0x3d, r28 ; 61 4a4: de bf out 0x3e, r29 ; 62 4a6: 8a 83 std Y+2, r24 ; 0x02 4a8: 9b 83 std Y+3, r25 ; 0x03 4aa: 6c 83 std Y+4, r22 ; 0x04 4ac: 4d 83 std Y+5, r20 ; 0x05 bool twi_status = TWI_MasterWriteRead(twi, address, 0, 0, bytesToRead); 4ae: 8a 81 ldd r24, Y+2 ; 0x02 4b0: 9b 81 ldd r25, Y+3 ; 0x03 4b2: 6c 81 ldd r22, Y+4 ; 0x04 4b4: 40 e0 ldi r20, 0x00 ; 0 4b6: 50 e0 ldi r21, 0x00 ; 0 4b8: 20 e0 ldi r18, 0x00 ; 0 4ba: 0d 81 ldd r16, Y+5 ; 0x05 4bc: 0e 94 69 02 call 0x4d2 ; 0x4d2 4c0: 89 83 std Y+1, r24 ; 0x01 return twi_status; 4c2: 89 81 ldd r24, Y+1 ; 0x01 } 4c4: 25 96 adiw r28, 0x05 ; 5 4c6: cd bf out 0x3d, r28 ; 61 4c8: de bf out 0x3e, r29 ; 62 4ca: cf 91 pop r28 4cc: df 91 pop r29 4ce: 0f 91 pop r16 4d0: 08 95 ret 000004d2 : bool TWI_MasterWriteRead(TWI_Master_t *twi, uint8_t address, uint8_t *writeData, uint8_t bytesToWrite, uint8_t bytesToRead) { 4d2: 0f 93 push r16 4d4: df 93 push r29 4d6: cf 93 push r28 4d8: cd b7 in r28, 0x3d ; 61 4da: de b7 in r29, 0x3e ; 62 4dc: 2b 97 sbiw r28, 0x0b ; 11 4de: cd bf out 0x3d, r28 ; 61 4e0: de bf out 0x3e, r29 ; 62 4e2: 8c 83 std Y+4, r24 ; 0x04 4e4: 9d 83 std Y+5, r25 ; 0x05 4e6: 6e 83 std Y+6, r22 ; 0x06 4e8: 4f 83 std Y+7, r20 ; 0x07 4ea: 58 87 std Y+8, r21 ; 0x08 4ec: 29 87 std Y+9, r18 ; 0x09 4ee: 0a 87 std Y+10, r16 ; 0x0a /*Parameter sanity check. */ if (bytesToWrite > TWIM_WRITE_BUFFER_SIZE) { 4f0: 89 85 ldd r24, Y+9 ; 0x09 4f2: 84 30 cpi r24, 0x04 ; 4 4f4: 10 f0 brcs .+4 ; 0x4fa return false; 4f6: 1b 86 std Y+11, r1 ; 0x0b 4f8: 69 c0 rjmp .+210 ; 0x5cc } if (bytesToRead > TWIM_READ_BUFFER_SIZE) { 4fa: 8a 85 ldd r24, Y+10 ; 0x0a 4fc: 89 30 cpi r24, 0x09 ; 9 4fe: 10 f0 brcs .+4 ; 0x504 return false; 500: 1b 86 std Y+11, r1 ; 0x0b 502: 64 c0 rjmp .+200 ; 0x5cc } /*Initiate transaction if bus is ready. */ if (twi->status == TWIM_STATUS_READY) { 504: ec 81 ldd r30, Y+4 ; 0x04 506: fd 81 ldd r31, Y+5 ; 0x05 508: 82 89 ldd r24, Z+18 ; 0x12 50a: 88 23 and r24, r24 50c: 09 f0 breq .+2 ; 0x510 50e: 5d c0 rjmp .+186 ; 0x5ca twi->status = TWIM_STATUS_BUSY; 510: ec 81 ldd r30, Y+4 ; 0x04 512: fd 81 ldd r31, Y+5 ; 0x05 514: 81 e0 ldi r24, 0x01 ; 1 516: 82 8b std Z+18, r24 ; 0x12 twi->result = TWIM_RESULT_UNKNOWN; 518: ec 81 ldd r30, Y+4 ; 0x04 51a: fd 81 ldd r31, Y+5 ; 0x05 51c: 13 8a std Z+19, r1 ; 0x13 twi->address = address<<1; 51e: 8e 81 ldd r24, Y+6 ; 0x06 520: 88 0f add r24, r24 522: ec 81 ldd r30, Y+4 ; 0x04 524: fd 81 ldd r31, Y+5 ; 0x05 526: 82 83 std Z+2, r24 ; 0x02 /* Fill write data buffer. */ uint8_t bufferIndex=0; 528: 1b 82 std Y+3, r1 ; 0x03 for (bufferIndex=0; bufferIndex < bytesToWrite; bufferIndex++) { 52a: 1b 82 std Y+3, r1 ; 0x03 52c: 16 c0 rjmp .+44 ; 0x55a twi->writeData[bufferIndex] = writeData[bufferIndex]; 52e: 8b 81 ldd r24, Y+3 ; 0x03 530: 48 2f mov r20, r24 532: 50 e0 ldi r21, 0x00 ; 0 534: 8b 81 ldd r24, Y+3 ; 0x03 536: 28 2f mov r18, r24 538: 30 e0 ldi r19, 0x00 ; 0 53a: 8f 81 ldd r24, Y+7 ; 0x07 53c: 98 85 ldd r25, Y+8 ; 0x08 53e: fc 01 movw r30, r24 540: e2 0f add r30, r18 542: f3 1f adc r31, r19 544: 20 81 ld r18, Z 546: 8c 81 ldd r24, Y+4 ; 0x04 548: 9d 81 ldd r25, Y+5 ; 0x05 54a: 84 0f add r24, r20 54c: 95 1f adc r25, r21 54e: fc 01 movw r30, r24 550: 33 96 adiw r30, 0x03 ; 3 552: 20 83 st Z, r18 twi->address = address<<1; /* Fill write data buffer. */ uint8_t bufferIndex=0; for (bufferIndex=0; bufferIndex < bytesToWrite; bufferIndex++) { 554: 8b 81 ldd r24, Y+3 ; 0x03 556: 8f 5f subi r24, 0xFF ; 255 558: 8b 83 std Y+3, r24 ; 0x03 55a: 9b 81 ldd r25, Y+3 ; 0x03 55c: 89 85 ldd r24, Y+9 ; 0x09 55e: 98 17 cp r25, r24 560: 30 f3 brcs .-52 ; 0x52e twi->writeData[bufferIndex] = writeData[bufferIndex]; } twi->bytesToWrite = bytesToWrite; 562: ec 81 ldd r30, Y+4 ; 0x04 564: fd 81 ldd r31, Y+5 ; 0x05 566: 89 85 ldd r24, Y+9 ; 0x09 568: 86 87 std Z+14, r24 ; 0x0e twi->bytesToRead = bytesToRead; 56a: ec 81 ldd r30, Y+4 ; 0x04 56c: fd 81 ldd r31, Y+5 ; 0x05 56e: 8a 85 ldd r24, Y+10 ; 0x0a 570: 87 87 std Z+15, r24 ; 0x0f twi->bytesWritten = 0; 572: ec 81 ldd r30, Y+4 ; 0x04 574: fd 81 ldd r31, Y+5 ; 0x05 576: 10 8a std Z+16, r1 ; 0x10 twi->bytesRead = 0; 578: ec 81 ldd r30, Y+4 ; 0x04 57a: fd 81 ldd r31, Y+5 ; 0x05 57c: 11 8a std Z+17, r1 ; 0x11 /* If write command, send the START condition + Address + * 'R/_W = 0' */ if (twi->bytesToWrite > 0) { 57e: ec 81 ldd r30, Y+4 ; 0x04 580: fd 81 ldd r31, Y+5 ; 0x05 582: 86 85 ldd r24, Z+14 ; 0x0e 584: 88 23 and r24, r24 586: 69 f0 breq .+26 ; 0x5a2 uint8_t writeAddress = twi->address & ~0x01; 588: ec 81 ldd r30, Y+4 ; 0x04 58a: fd 81 ldd r31, Y+5 ; 0x05 58c: 82 81 ldd r24, Z+2 ; 0x02 58e: 8e 7f andi r24, 0xFE ; 254 590: 8a 83 std Y+2, r24 ; 0x02 twi->interface->MASTER.ADDR = writeAddress; 592: ec 81 ldd r30, Y+4 ; 0x04 594: fd 81 ldd r31, Y+5 ; 0x05 596: 01 90 ld r0, Z+ 598: f0 81 ld r31, Z 59a: e0 2d mov r30, r0 59c: 8a 81 ldd r24, Y+2 ; 0x02 59e: 86 83 std Z+6, r24 ; 0x06 5a0: 11 c0 rjmp .+34 ; 0x5c4 } /* If read command, send the START condition + Address + * 'R/_W = 1' */ else if (twi->bytesToRead > 0) { 5a2: ec 81 ldd r30, Y+4 ; 0x04 5a4: fd 81 ldd r31, Y+5 ; 0x05 5a6: 87 85 ldd r24, Z+15 ; 0x0f 5a8: 88 23 and r24, r24 5aa: 61 f0 breq .+24 ; 0x5c4 uint8_t readAddress = twi->address | 0x01; 5ac: ec 81 ldd r30, Y+4 ; 0x04 5ae: fd 81 ldd r31, Y+5 ; 0x05 5b0: 82 81 ldd r24, Z+2 ; 0x02 5b2: 81 60 ori r24, 0x01 ; 1 5b4: 89 83 std Y+1, r24 ; 0x01 twi->interface->MASTER.ADDR = readAddress; 5b6: ec 81 ldd r30, Y+4 ; 0x04 5b8: fd 81 ldd r31, Y+5 ; 0x05 5ba: 01 90 ld r0, Z+ 5bc: f0 81 ld r31, Z 5be: e0 2d mov r30, r0 5c0: 89 81 ldd r24, Y+1 ; 0x01 5c2: 86 83 std Z+6, r24 ; 0x06 } return true; 5c4: 81 e0 ldi r24, 0x01 ; 1 5c6: 8b 87 std Y+11, r24 ; 0x0b 5c8: 01 c0 rjmp .+2 ; 0x5cc } else { return false; 5ca: 1b 86 std Y+11, r1 ; 0x0b 5cc: 8b 85 ldd r24, Y+11 ; 0x0b } } 5ce: 2b 96 adiw r28, 0x0b ; 11 5d0: cd bf out 0x3d, r28 ; 61 5d2: de bf out 0x3e, r29 ; 62 5d4: cf 91 pop r28 5d6: df 91 pop r29 5d8: 0f 91 pop r16 5da: 08 95 ret 000005dc : * Check current status and calls the appropriate handler. * * \param twi The TWI_Master_t struct instance. */ void TWI_MasterInterruptHandler(TWI_Master_t *twi) { 5dc: df 93 push r29 5de: cf 93 push r28 5e0: 00 d0 rcall .+0 ; 0x5e2 5e2: cd b7 in r28, 0x3d ; 61 5e4: de b7 in r29, 0x3e ; 62 5e6: 8a 83 std Y+2, r24 ; 0x02 5e8: 9b 83 std Y+3, r25 ; 0x03 uint8_t currentStatus = twi->interface->MASTER.STATUS; 5ea: ea 81 ldd r30, Y+2 ; 0x02 5ec: fb 81 ldd r31, Y+3 ; 0x03 5ee: 01 90 ld r0, Z+ 5f0: f0 81 ld r31, Z 5f2: e0 2d mov r30, r0 5f4: 84 81 ldd r24, Z+4 ; 0x04 5f6: 89 83 std Y+1, r24 ; 0x01 /* If arbitration lost or bus error. */ if ((currentStatus & TWI_MASTER_ARBLOST_bm) || 5f8: 89 81 ldd r24, Y+1 ; 0x01 5fa: 88 2f mov r24, r24 5fc: 90 e0 ldi r25, 0x00 ; 0 5fe: 88 70 andi r24, 0x08 ; 8 600: 90 70 andi r25, 0x00 ; 0 602: 00 97 sbiw r24, 0x00 ; 0 604: 39 f4 brne .+14 ; 0x614 606: 89 81 ldd r24, Y+1 ; 0x01 608: 88 2f mov r24, r24 60a: 90 e0 ldi r25, 0x00 ; 0 60c: 84 70 andi r24, 0x04 ; 4 60e: 90 70 andi r25, 0x00 ; 0 610: 00 97 sbiw r24, 0x00 ; 0 612: 29 f0 breq .+10 ; 0x61e (currentStatus & TWI_MASTER_BUSERR_bm)) { TWI_MasterArbitrationLostBusErrorHandler(twi); 614: 8a 81 ldd r24, Y+2 ; 0x02 616: 9b 81 ldd r25, Y+3 ; 0x03 618: 0e 94 2e 03 call 0x65c ; 0x65c 61c: 19 c0 rjmp .+50 ; 0x650 } /* If master write interrupt. */ else if (currentStatus & TWI_MASTER_WIF_bm) { 61e: 89 81 ldd r24, Y+1 ; 0x01 620: 88 2f mov r24, r24 622: 90 e0 ldi r25, 0x00 ; 0 624: 80 74 andi r24, 0x40 ; 64 626: 90 70 andi r25, 0x00 ; 0 628: 00 97 sbiw r24, 0x00 ; 0 62a: 29 f0 breq .+10 ; 0x636 TWI_MasterWriteHandler(twi); 62c: 8a 81 ldd r24, Y+2 ; 0x02 62e: 9b 81 ldd r25, Y+3 ; 0x03 630: 0e 94 5d 03 call 0x6ba ; 0x6ba 634: 0d c0 rjmp .+26 ; 0x650 } /* If master read interrupt. */ else if (currentStatus & TWI_MASTER_RIF_bm) { 636: 89 81 ldd r24, Y+1 ; 0x01 638: 88 23 and r24, r24 63a: 2c f4 brge .+10 ; 0x646 TWI_MasterReadHandler(twi); 63c: 8a 81 ldd r24, Y+2 ; 0x02 63e: 9b 81 ldd r25, Y+3 ; 0x03 640: 0e 94 cf 03 call 0x79e ; 0x79e 644: 05 c0 rjmp .+10 ; 0x650 } /* If unexpected state. */ else { TWI_MasterTransactionFinished(twi, TWIM_RESULT_FAIL); 646: 8a 81 ldd r24, Y+2 ; 0x02 648: 9b 81 ldd r25, Y+3 ; 0x03 64a: 66 e0 ldi r22, 0x06 ; 6 64c: 0e 94 28 04 call 0x850 ; 0x850 } } 650: 23 96 adiw r28, 0x03 ; 3 652: cd bf out 0x3d, r28 ; 61 654: de bf out 0x3e, r29 ; 62 656: cf 91 pop r28 658: df 91 pop r29 65a: 08 95 ret 0000065c : * Handles TWI responses to lost arbitration and bus error. * * \param twi The TWI_Master_t struct instance. */ void TWI_MasterArbitrationLostBusErrorHandler(TWI_Master_t *twi) { 65c: df 93 push r29 65e: cf 93 push r28 660: 00 d0 rcall .+0 ; 0x662 662: cd b7 in r28, 0x3d ; 61 664: de b7 in r29, 0x3e ; 62 666: 8a 83 std Y+2, r24 ; 0x02 668: 9b 83 std Y+3, r25 ; 0x03 uint8_t currentStatus = twi->interface->MASTER.STATUS; 66a: ea 81 ldd r30, Y+2 ; 0x02 66c: fb 81 ldd r31, Y+3 ; 0x03 66e: 01 90 ld r0, Z+ 670: f0 81 ld r31, Z 672: e0 2d mov r30, r0 674: 84 81 ldd r24, Z+4 ; 0x04 676: 89 83 std Y+1, r24 ; 0x01 /* If bus error. */ if (currentStatus & TWI_MASTER_BUSERR_bm) { 678: 89 81 ldd r24, Y+1 ; 0x01 67a: 88 2f mov r24, r24 67c: 90 e0 ldi r25, 0x00 ; 0 67e: 84 70 andi r24, 0x04 ; 4 680: 90 70 andi r25, 0x00 ; 0 682: 00 97 sbiw r24, 0x00 ; 0 684: 29 f0 breq .+10 ; 0x690 twi->result = TWIM_RESULT_BUS_ERROR; 686: ea 81 ldd r30, Y+2 ; 0x02 688: fb 81 ldd r31, Y+3 ; 0x03 68a: 84 e0 ldi r24, 0x04 ; 4 68c: 83 8b std Z+19, r24 ; 0x13 68e: 04 c0 rjmp .+8 ; 0x698 } /* If arbitration lost. */ else { twi->result = TWIM_RESULT_ARBITRATION_LOST; 690: ea 81 ldd r30, Y+2 ; 0x02 692: fb 81 ldd r31, Y+3 ; 0x03 694: 83 e0 ldi r24, 0x03 ; 3 696: 83 8b std Z+19, r24 ; 0x13 } /* Clear interrupt flag. */ twi->interface->MASTER.STATUS = currentStatus | TWI_MASTER_ARBLOST_bm; 698: ea 81 ldd r30, Y+2 ; 0x02 69a: fb 81 ldd r31, Y+3 ; 0x03 69c: 01 90 ld r0, Z+ 69e: f0 81 ld r31, Z 6a0: e0 2d mov r30, r0 6a2: 89 81 ldd r24, Y+1 ; 0x01 6a4: 88 60 ori r24, 0x08 ; 8 6a6: 84 83 std Z+4, r24 ; 0x04 twi->status = TWIM_STATUS_READY; 6a8: ea 81 ldd r30, Y+2 ; 0x02 6aa: fb 81 ldd r31, Y+3 ; 0x03 6ac: 12 8a std Z+18, r1 ; 0x12 } 6ae: 23 96 adiw r28, 0x03 ; 3 6b0: cd bf out 0x3d, r28 ; 61 6b2: de bf out 0x3e, r29 ; 62 6b4: cf 91 pop r28 6b6: df 91 pop r29 6b8: 08 95 ret 000006ba : * Handles TWI transactions (master write) and responses to (N)ACK. * * \param twi The TWI_Master_t struct instance. */ void TWI_MasterWriteHandler(TWI_Master_t *twi) { 6ba: df 93 push r29 6bc: cf 93 push r28 6be: 00 d0 rcall .+0 ; 0x6c0 6c0: 00 d0 rcall .+0 ; 0x6c2 6c2: cd b7 in r28, 0x3d ; 61 6c4: de b7 in r29, 0x3e ; 62 6c6: 8d 83 std Y+5, r24 ; 0x05 6c8: 9e 83 std Y+6, r25 ; 0x06 /* Local variables used in if tests to avoid compiler warning. */ uint8_t bytesToWrite = twi->bytesToWrite; 6ca: ed 81 ldd r30, Y+5 ; 0x05 6cc: fe 81 ldd r31, Y+6 ; 0x06 6ce: 86 85 ldd r24, Z+14 ; 0x0e 6d0: 8c 83 std Y+4, r24 ; 0x04 uint8_t bytesToRead = twi->bytesToRead; 6d2: ed 81 ldd r30, Y+5 ; 0x05 6d4: fe 81 ldd r31, Y+6 ; 0x06 6d6: 87 85 ldd r24, Z+15 ; 0x0f 6d8: 8b 83 std Y+3, r24 ; 0x03 /* If NOT acknowledged (NACK) by slave cancel the transaction. */ if (twi->interface->MASTER.STATUS & TWI_MASTER_RXACK_bm) { 6da: ed 81 ldd r30, Y+5 ; 0x05 6dc: fe 81 ldd r31, Y+6 ; 0x06 6de: 01 90 ld r0, Z+ 6e0: f0 81 ld r31, Z 6e2: e0 2d mov r30, r0 6e4: 84 81 ldd r24, Z+4 ; 0x04 6e6: 88 2f mov r24, r24 6e8: 90 e0 ldi r25, 0x00 ; 0 6ea: 80 71 andi r24, 0x10 ; 16 6ec: 90 70 andi r25, 0x00 ; 0 6ee: 00 97 sbiw r24, 0x00 ; 0 6f0: 79 f0 breq .+30 ; 0x710 twi->interface->MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc; 6f2: ed 81 ldd r30, Y+5 ; 0x05 6f4: fe 81 ldd r31, Y+6 ; 0x06 6f6: 01 90 ld r0, Z+ 6f8: f0 81 ld r31, Z 6fa: e0 2d mov r30, r0 6fc: 83 e0 ldi r24, 0x03 ; 3 6fe: 83 83 std Z+3, r24 ; 0x03 twi->result = TWIM_RESULT_NACK_RECEIVED; 700: ed 81 ldd r30, Y+5 ; 0x05 702: fe 81 ldd r31, Y+6 ; 0x06 704: 85 e0 ldi r24, 0x05 ; 5 706: 83 8b std Z+19, r24 ; 0x13 twi->status = TWIM_STATUS_READY; 708: ed 81 ldd r30, Y+5 ; 0x05 70a: fe 81 ldd r31, Y+6 ; 0x06 70c: 12 8a std Z+18, r1 ; 0x12 70e: 41 c0 rjmp .+130 ; 0x792 } /* If more bytes to write, send data. */ else if (twi->bytesWritten < bytesToWrite) { 710: ed 81 ldd r30, Y+5 ; 0x05 712: fe 81 ldd r31, Y+6 ; 0x06 714: 90 89 ldd r25, Z+16 ; 0x10 716: 8c 81 ldd r24, Y+4 ; 0x04 718: 98 17 cp r25, r24 71a: e0 f4 brcc .+56 ; 0x754 uint8_t data = twi->writeData[twi->bytesWritten]; 71c: ed 81 ldd r30, Y+5 ; 0x05 71e: fe 81 ldd r31, Y+6 ; 0x06 720: 80 89 ldd r24, Z+16 ; 0x10 722: 28 2f mov r18, r24 724: 30 e0 ldi r19, 0x00 ; 0 726: 8d 81 ldd r24, Y+5 ; 0x05 728: 9e 81 ldd r25, Y+6 ; 0x06 72a: 82 0f add r24, r18 72c: 93 1f adc r25, r19 72e: fc 01 movw r30, r24 730: 33 96 adiw r30, 0x03 ; 3 732: 80 81 ld r24, Z 734: 8a 83 std Y+2, r24 ; 0x02 twi->interface->MASTER.DATA = data; 736: ed 81 ldd r30, Y+5 ; 0x05 738: fe 81 ldd r31, Y+6 ; 0x06 73a: 01 90 ld r0, Z+ 73c: f0 81 ld r31, Z 73e: e0 2d mov r30, r0 740: 8a 81 ldd r24, Y+2 ; 0x02 742: 87 83 std Z+7, r24 ; 0x07 ++twi->bytesWritten; 744: ed 81 ldd r30, Y+5 ; 0x05 746: fe 81 ldd r31, Y+6 ; 0x06 748: 80 89 ldd r24, Z+16 ; 0x10 74a: 8f 5f subi r24, 0xFF ; 255 74c: ed 81 ldd r30, Y+5 ; 0x05 74e: fe 81 ldd r31, Y+6 ; 0x06 750: 80 8b std Z+16, r24 ; 0x10 752: 1f c0 rjmp .+62 ; 0x792 } /* If bytes to read, send repeated START condition + Address + * 'R/_W = 1' */ else if (twi->bytesRead < bytesToRead) { 754: ed 81 ldd r30, Y+5 ; 0x05 756: fe 81 ldd r31, Y+6 ; 0x06 758: 91 89 ldd r25, Z+17 ; 0x11 75a: 8b 81 ldd r24, Y+3 ; 0x03 75c: 98 17 cp r25, r24 75e: 68 f4 brcc .+26 ; 0x77a uint8_t readAddress = twi->address | 0x01; 760: ed 81 ldd r30, Y+5 ; 0x05 762: fe 81 ldd r31, Y+6 ; 0x06 764: 82 81 ldd r24, Z+2 ; 0x02 766: 81 60 ori r24, 0x01 ; 1 768: 89 83 std Y+1, r24 ; 0x01 twi->interface->MASTER.ADDR = readAddress; 76a: ed 81 ldd r30, Y+5 ; 0x05 76c: fe 81 ldd r31, Y+6 ; 0x06 76e: 01 90 ld r0, Z+ 770: f0 81 ld r31, Z 772: e0 2d mov r30, r0 774: 89 81 ldd r24, Y+1 ; 0x01 776: 86 83 std Z+6, r24 ; 0x06 778: 0c c0 rjmp .+24 ; 0x792 } /* If transaction finished, send STOP condition and set RESULT OK. */ else { twi->interface->MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc; 77a: ed 81 ldd r30, Y+5 ; 0x05 77c: fe 81 ldd r31, Y+6 ; 0x06 77e: 01 90 ld r0, Z+ 780: f0 81 ld r31, Z 782: e0 2d mov r30, r0 784: 83 e0 ldi r24, 0x03 ; 3 786: 83 83 std Z+3, r24 ; 0x03 TWI_MasterTransactionFinished(twi, TWIM_RESULT_OK); 788: 8d 81 ldd r24, Y+5 ; 0x05 78a: 9e 81 ldd r25, Y+6 ; 0x06 78c: 61 e0 ldi r22, 0x01 ; 1 78e: 0e 94 28 04 call 0x850 ; 0x850 } } 792: 26 96 adiw r28, 0x06 ; 6 794: cd bf out 0x3d, r28 ; 61 796: de bf out 0x3e, r29 ; 62 798: cf 91 pop r28 79a: df 91 pop r29 79c: 08 95 ret 0000079e : * reading bytes from the TWI slave. * * \param twi The TWI_Master_t struct instance. */ void TWI_MasterReadHandler(TWI_Master_t *twi) { 79e: df 93 push r29 7a0: cf 93 push r28 7a2: 00 d0 rcall .+0 ; 0x7a4 7a4: 0f 92 push r0 7a6: cd b7 in r28, 0x3d ; 61 7a8: de b7 in r29, 0x3e ; 62 7aa: 8b 83 std Y+3, r24 ; 0x03 7ac: 9c 83 std Y+4, r25 ; 0x04 /* Fetch data if bytes to be read. */ if (twi->bytesRead < TWIM_READ_BUFFER_SIZE) { 7ae: eb 81 ldd r30, Y+3 ; 0x03 7b0: fc 81 ldd r31, Y+4 ; 0x04 7b2: 81 89 ldd r24, Z+17 ; 0x11 7b4: 88 30 cpi r24, 0x08 ; 8 7b6: e0 f4 brcc .+56 ; 0x7f0 uint8_t data = twi->interface->MASTER.DATA; 7b8: eb 81 ldd r30, Y+3 ; 0x03 7ba: fc 81 ldd r31, Y+4 ; 0x04 7bc: 01 90 ld r0, Z+ 7be: f0 81 ld r31, Z 7c0: e0 2d mov r30, r0 7c2: 87 81 ldd r24, Z+7 ; 0x07 7c4: 89 83 std Y+1, r24 ; 0x01 twi->readData[twi->bytesRead] = data; 7c6: eb 81 ldd r30, Y+3 ; 0x03 7c8: fc 81 ldd r31, Y+4 ; 0x04 7ca: 81 89 ldd r24, Z+17 ; 0x11 7cc: 28 2f mov r18, r24 7ce: 30 e0 ldi r19, 0x00 ; 0 7d0: 8b 81 ldd r24, Y+3 ; 0x03 7d2: 9c 81 ldd r25, Y+4 ; 0x04 7d4: 82 0f add r24, r18 7d6: 93 1f adc r25, r19 7d8: fc 01 movw r30, r24 7da: 36 96 adiw r30, 0x06 ; 6 7dc: 89 81 ldd r24, Y+1 ; 0x01 7de: 80 83 st Z, r24 twi->bytesRead++; 7e0: eb 81 ldd r30, Y+3 ; 0x03 7e2: fc 81 ldd r31, Y+4 ; 0x04 7e4: 81 89 ldd r24, Z+17 ; 0x11 7e6: 8f 5f subi r24, 0xFF ; 255 7e8: eb 81 ldd r30, Y+3 ; 0x03 7ea: fc 81 ldd r31, Y+4 ; 0x04 7ec: 81 8b std Z+17, r24 ; 0x11 7ee: 0c c0 rjmp .+24 ; 0x808 } /* If buffer overflow, issue STOP and BUFFER_OVERFLOW condition. */ else { twi->interface->MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc; 7f0: eb 81 ldd r30, Y+3 ; 0x03 7f2: fc 81 ldd r31, Y+4 ; 0x04 7f4: 01 90 ld r0, Z+ 7f6: f0 81 ld r31, Z 7f8: e0 2d mov r30, r0 7fa: 83 e0 ldi r24, 0x03 ; 3 7fc: 83 83 std Z+3, r24 ; 0x03 TWI_MasterTransactionFinished(twi, TWIM_RESULT_BUFFER_OVERFLOW); 7fe: 8b 81 ldd r24, Y+3 ; 0x03 800: 9c 81 ldd r25, Y+4 ; 0x04 802: 62 e0 ldi r22, 0x02 ; 2 804: 0e 94 28 04 call 0x850 ; 0x850 } /* Local variable used in if test to avoid compiler warning. */ uint8_t bytesToRead = twi->bytesToRead; 808: eb 81 ldd r30, Y+3 ; 0x03 80a: fc 81 ldd r31, Y+4 ; 0x04 80c: 87 85 ldd r24, Z+15 ; 0x0f 80e: 8a 83 std Y+2, r24 ; 0x02 /* If more bytes to read, issue ACK and start a byte read. */ if (twi->bytesRead < bytesToRead) { 810: eb 81 ldd r30, Y+3 ; 0x03 812: fc 81 ldd r31, Y+4 ; 0x04 814: 91 89 ldd r25, Z+17 ; 0x11 816: 8a 81 ldd r24, Y+2 ; 0x02 818: 98 17 cp r25, r24 81a: 40 f4 brcc .+16 ; 0x82c twi->interface->MASTER.CTRLC = TWI_MASTER_CMD_RECVTRANS_gc; 81c: eb 81 ldd r30, Y+3 ; 0x03 81e: fc 81 ldd r31, Y+4 ; 0x04 820: 01 90 ld r0, Z+ 822: f0 81 ld r31, Z 824: e0 2d mov r30, r0 826: 82 e0 ldi r24, 0x02 ; 2 828: 83 83 std Z+3, r24 ; 0x03 82a: 0c c0 rjmp .+24 ; 0x844 } /* If transaction finished, issue NACK and STOP condition. */ else { twi->interface->MASTER.CTRLC = TWI_MASTER_ACKACT_bm | 82c: eb 81 ldd r30, Y+3 ; 0x03 82e: fc 81 ldd r31, Y+4 ; 0x04 830: 01 90 ld r0, Z+ 832: f0 81 ld r31, Z 834: e0 2d mov r30, r0 836: 87 e0 ldi r24, 0x07 ; 7 838: 83 83 std Z+3, r24 ; 0x03 TWI_MASTER_CMD_STOP_gc; TWI_MasterTransactionFinished(twi, TWIM_RESULT_OK); 83a: 8b 81 ldd r24, Y+3 ; 0x03 83c: 9c 81 ldd r25, Y+4 ; 0x04 83e: 61 e0 ldi r22, 0x01 ; 1 840: 0e 94 28 04 call 0x850 ; 0x850 } } 844: 24 96 adiw r28, 0x04 ; 4 846: cd bf out 0x3d, r28 ; 61 848: de bf out 0x3e, r29 ; 62 84a: cf 91 pop r28 84c: df 91 pop r29 84e: 08 95 ret 00000850 : * * \param twi The TWI_Master_t struct instance. * \param result The result of the operation. */ void TWI_MasterTransactionFinished(TWI_Master_t *twi, uint8_t result) { 850: df 93 push r29 852: cf 93 push r28 854: 00 d0 rcall .+0 ; 0x856 856: cd b7 in r28, 0x3d ; 61 858: de b7 in r29, 0x3e ; 62 85a: 89 83 std Y+1, r24 ; 0x01 85c: 9a 83 std Y+2, r25 ; 0x02 85e: 6b 83 std Y+3, r22 ; 0x03 twi->result = result; 860: e9 81 ldd r30, Y+1 ; 0x01 862: fa 81 ldd r31, Y+2 ; 0x02 864: 8b 81 ldd r24, Y+3 ; 0x03 866: 83 8b std Z+19, r24 ; 0x13 twi->status = TWIM_STATUS_READY; 868: e9 81 ldd r30, Y+1 ; 0x01 86a: fa 81 ldd r31, Y+2 ; 0x02 86c: 12 8a std Z+18, r1 ; 0x12 } 86e: 23 96 adiw r28, 0x03 ; 3 870: cd bf out 0x3d, r28 ; 61 872: de bf out 0x3e, r29 ; 62 874: cf 91 pop r28 876: df 91 pop r29 878: 08 95 ret 0000087a <_exit>: 87a: f8 94 cli 0000087c <__stop_program>: 87c: ff cf rjmp .-2 ; 0x87c <__stop_program>