library ieee;
library ice40UP;
use ice40UP.Components.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity top is 
  port (
    led_red: out std_logic;
    led_green: out std_logic;
    led_blue: out std_logic
  );
end top;

architecture rtl of top is
  signal cnt : std_logic_vector(27 downto 0) := (others => '0');
  signal clkHSOSC : std_logic := '0';
  signal led_red_int : std_logic := '0';
  signal led_green_int : std_logic := '0';
  signal led_blue_int : std_logic := '0';
begin
	top_state : process(clkHSOSC)
    begin
		if (rising_edge(clkHSOSC)) then
			cnt <= cnt + 1;
      led_red_int <= cnt(25) and cnt(24);
      led_green_int <= cnt(25) and not cnt(24);
      led_blue_int <= not cnt(25) and cnt(24);
		end if;				
	end process top_state;
  
  -- oscillator instantiation
  hsosc2 : HSOSC
    generic map (
      CLKHF_DIV  => "0b00"
    )
    port map (
      CLKHFPU => '1',
      CLKHFEN => '1',
      CLKHF   => clkHSOSC
    );
  
  -- led instantiation
  rgb2 : RGB
    generic map (
      CURRENT_MODE  => "0",
      RGB0_CURRENT  => "0b000001",
      RGB1_CURRENT  => "0b000001",
      RGB2_CURRENT  => "0b000001"
    )
    port map (
      CURREN   => '1',  -- I
      RGBLEDEN => '1',  -- I
      RGB0PWM  => led_red_int,  -- I
      RGB1PWM  => led_green_int,  -- I
      RGB2PWM  => led_blue_int,  -- I
      RGB2     => led_red,  -- O
      RGB1     => led_green,  -- O
      RGB0     => led_blue   -- O
    );
end rtl;