void TD_Init(void)			// Called once at startup
{
	CPUCS = 0x10;	// CLKSPD[1:0]=10, for 48 MHz operation
	SYNCDELAY;

	OEA	= 0xFF;	// Set PORTA direction, output enable A (1 = output, 0 = input)
	IOA = 0x00;

	PA0 = 0;

	IFCONFIG = 0x8B; // vorher 0xCB , zum test 0x8B
	SYNCDELAY;
	// IFCLKSRC=1 , FIFOs executes on internal clk source
	// x MHz=1 -> 48 MHz ; x MHz = 0 -> 30 MHz internal clk rate
	// IFCLKOE=0 , Don't drive IFCLK pin signal at 48 MHz
	// IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
	// ASYNC=1 , master samples asynchronous
	// GSTATE=0 , Don't drive GPIF states out on PORTE[2:0], debug WF
	// IFCFG[1:0]=11, FX2 in slave FIFO mode

	// Registers which require a synchronization delay, see section 15.14
	// FIFORESET FIFOPINPOLAR
	// INPKTEND OUTPKTEND
	// EPxBCH:L REVCTL
	// GPIFTCB3 GPIFTCB2
	// GPIFTCB1 GPIFTCB0
	// EPxFIFOPFH:L EPxAUTOINLENH:L
	// EPxFIFOCFG EPxGPIFFLGSEL
	// PINFLAGSxx EPxFIFOIRQ
	// EPxFIFOIE GPIFIRQ
	// GPIFIE GPIFADRH:L
	// UDMACRCH:L EPxGPIFTRIG
	// GPIFTRIG		
	
	REVCTL = 0x03;	// When DYN_OUT=1(REVCTL.1), the core disables auto-arming of the endpoints when AUTOOUT transitions from ‘0’ to ‘1’.
	SYNCDELAY;

	// Configure endpoints. EP4 and EP8 are not used
	EP1OUTCFG = 0x00;	// EP1 OUT aus
	SYNCDELAY;
	EP1INCFG = 0x00;	// EP1 IN aus
	SYNCDELAY; 
	EP2CFG = 0xA2;	// EP2, valid=1, direction=out, bulk, size=512, doublebuffered
	SYNCDELAY;
	EP4CFG = 0xA0;	// EP4, valid=1, direction=out, bulk, size=512, doublebuffered
	SYNCDELAY;
	EP6CFG = 0xE2;	// EP6, valid=1, direction=in, bulk, size=512, doublebuffered
	SYNCDELAY;
	EP8CFG = 0xE0;	// EP8, valid=1, direction=in, bulk, size=512, doublebuffered
	SYNCDELAY;

	// Reset all FIFOs
	FIFORESET = 0x80;	// activate NAK-ALL to avoid race conditions (NAK all tranfers from host)
	SYNCDELAY;			// see TRM section 15.14
	FIFORESET = 0x82;	// reset FIFO 2
	SYNCDELAY;			//
	FIFORESET = 0x84;	// reset FIFO 4
	SYNCDELAY;			//
	FIFORESET = 0x86;	// reset FIFO 6
	SYNCDELAY;			//
	FIFORESET = 0x88;	// reset FIFO 8
	SYNCDELAY;			//
	FIFORESET = 0x00;	// deactivate NAK-ALL
	SYNCDELAY;

	OUTPKTEND = 0x82;	// buffer leeren
	SYNCDELAY;
	OUTPKTEND = 0x82;
	SYNCDELAY;
	OUTPKTEND = 0x84;
	SYNCDELAY;
	OUTPKTEND = 0x84;
	SYNCDELAY;


	PORTACFG = 0x40; // Disable FLAGD, PA7 = SLCS#
	SYNCDELAY;
	PINFLAGSAB = 0xF9;	// FLAGB - fixed EP6FF, FLAGA - fixed EP2EF
						// NORMAL (EP6FF, EP2EF) EP2OUT, EP6IN -> 0xE8
						// TEST (EP2FF, EP6EF) EP2IN, EP6OUT -> 0xCA
						// TEST (EP4FF, EP8EF) EP4OUT, EP8IN -> 0xF9
	SYNCDELAY;
	PINFLAGSCD = 0x99; // NICHT BEACHTEN (Disabled due PORTACFG)FLAGD - fixed EP4EF, FLAGC - fixed EP4EF
	SYNCDELAY;
	FIFOPINPOLAR = 0x00; // all signals active low
	SYNCDELAY;

	EP2FIFOCFG = 0x10; // AUTOOUT=1, WORDWIDE=0
	SYNCDELAY;
	EP4FIFOCFG = 0x10; // AUTOOUT=1, WORDWIDE=0
	SYNCDELAY;
	EP6FIFOCFG = 0x0C; // AUTOIN=1, ZEROLENIN=1, WORDWIDE=0
	SYNCDELAY;
	EP8FIFOCFG = 0x0C; // AUTOIN=1, ZEROLENIN=1, WORDWIDE=0
	SYNCDELAY;

	EP6AUTOINLENH = 0x02;	// Set EP6INAUTOIN Packetlength to 512
	SYNCDELAY;
	EP6AUTOINLENL = 0x00;
	SYNCDELAY;
	EP8AUTOINLENH = 0x02;	// Set EP8INAUTOIN Packetlength to 512
	SYNCDELAY;
	EP8AUTOINLENL = 0x00;
	SYNCDELAY;
/*
	APTR1H = MSB( &EP2FIFOBUF );
	APTR1L = LSB( &EP2FIFOBUF );

    AUTOPTRH2 = MSB( &EP6FIFOBUF );
    AUTOPTRL2 = LSB( &EP6FIFOBUF );

	for(i = 0; i < 512; i++) {	// Buffer testweise vom Microcontroller aus füllen.
		EXTAUTODAT2 = 0x03;
	}

	EP6BCH = 0x02;
	SYNCDELAY;  
	EP6BCL = 0x00;
	SYNCDELAY;
*/

	PA0 = 1;
}