.nolist
.include "tn13adef.inc" ; Define device ATtiny13A
.list

.def rSreg = R15 ; Save/Restore status port
.def rmp = R16 ; Define multipurpose register

.dseg
.org SRAM_START

.cseg
.org 000000
	rjmp Main ; Reset vector
	reti ; INT0
	reti ; PCI0
	reti ; OVF0
	reti ; ERDY
	reti ; ACI
	rjmp isr_timermatch_oc0a ; OC0A
	rjmp isr_timermatch_oc0b ; OC0B
	reti ; WDT
	reti ; ADCC


isr_timermatch_oc0a:
 reti

isr_timermatch_oc0b:
 in rSreg, SREG
 cbi PORTB,PB0
 out SREG,rSreg
 reti


Main:
 ldi rmp,Low(RAMEND)
 out SPL,rmp ; Init LSB stack pointer
 sbi DDRB,PORTB0
 rcall init_timer0
 sei ; Enable interrupts

Loop:
	rjmp loop


init_timer0:
 ldi rmp,128
 out OCR0A,rmp
 ldi rmp, 1
 out OCR0B,rmp
 ldi rmp,(1<<WGM01)|(1<<COM0A0)|(1<<COM0A1) ; ctc, set on compare match
 out TCCR0A,rmp
 ldi rmp,(1<<CS00)|(1<<CS02) ; prescaler 1024
 out TCCR0B,rmp
 ldi rmp,(1<<OCIE0A)|(1<<OCIE0B)
 out TIMSK0, rmp
 ret