----------------------------------------------------------------------------------
-- Company: 			Circuit-Break
-- Engineer: 			Jens Weiss
-- 
-- Create Date:    	15:14:22 01/01/2025 
-- Design Name: 		VHDL Library
-- Module Name:    	DualPort_SRamInterface - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 	ISE 14.7 (P20121013)
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity DualPort_SRamInterface is
    Port ( clk : in  std_logic;
           reset : in  std_logic;
			  --Status Signals
			  busy : out std_logic;
			  error : out std_logic;
			  --PortA
           PortA_Adress : in  std_logic_vector (18 downto 0);
           PortA_DataIn : in  std_logic_vector (7 downto 0);
           PortA_DataOut : out  std_logic_vector (7 downto 0);
           PortA_CE : in  std_logic;
           PortA_OE : in  std_logic;
           PortA_WE : in  std_logic;
			  --PortB
           PortB_Adress : in  std_logic_vector (18 downto 0);
           PortB_DataIn : in  std_logic_vector (7 downto 0);
           PortB_DataOut : out  std_logic_vector (7 downto 0);
           PortB_CE : in  std_logic;
           PortB_OE : in  std_logic;
           PortB_WE : in  std_logic;
			  --SRam Memory Interface
           SRam_Adress : out  std_logic_vector (18 downto 0);
           SRam_Data : inout  std_logic_vector (7 downto 0);
           SRam_nCE : out  std_logic;
           SRam_nOE : out  std_logic;
           SRam_nWE : out  std_logic);
end DualPort_SRamInterface;

architecture Behavioral of DualPort_SRamInterface is

signal internal_SRamAdress : std_logic_vector(18 downto 0);
signal internal_SRamData : std_logic_vector(7 downto 0);
signal internal_SRam_CE : std_logic;
signal internal_SRam_OE : std_logic;
signal internal_SRam_WE : std_logic;
signal internal_busy : std_logic;
signal internal_error : std_logic;

begin

	--Memory Controller process
	process
	begin
		wait until rising_edge(clk);
		
		if(reset = '1') then
			internal_busy <= '0';
			internal_error <= '0';
			internal_SRamAdress <= (others => '0');
			internal_SRamData <= (others => 'Z');
			internal_SRam_CE <= '0';
			internal_SRam_OE <= '0';
			internal_SRam_WE <= '0';
		else
			--PortA selects Ram
			if(PortA_CE = '1') and (PortB_CE = '0') then
				internal_busy <= '1';
				internal_SRam_CE <= '1';
				internal_SRamAdress <= PortA_Adress;
				if(PortA_OE = '1') then
					internal_SRam_OE <= '1';
					PortA_DataOut <= SRam_Data;
				else
					internal_SRam_OE <= '0';					
				end if;
				
				if(PortA_WE = '1') then
					internal_SRam_WE <= '1';
					internal_SRamData <= PortA_DataIn;
				else
					internal_SRam_WE <= '0';
				end if;
			
			--PortB selects Ram
			elsif(PortA_CE = '0') and (PortB_CE = '1') then
				internal_busy <= '1';
				internal_SRam_CE <= '1';
				internal_SRamAdress <= PortB_Adress;
				if(PortB_OE = '1') then
					internal_SRam_OE <= '1';
					PortB_DataOut <= SRam_Data;
				else
					internal_SRam_OE <= '0';
				end if;
				
				if(PortB_WE = '1') then
					internal_SRam_WE <= '1';
					internal_SRamData <= PortB_DataIn;
				else
					internal_SRam_WE <= '0';
				end if;
			
			--nobody selects Ram
			elsif(PortA_CE = '0') and (PortB_CE = '0') then
				internal_busy <= '0';
				internal_error <= '0';
				internal_SRam_CE <= '0';
				internal_SRam_OE <= '0';
				internal_SRam_WE <= '0';
				internal_SRamData <= (others => 'Z');
			
			--both Ports select Ram
			else --elsif(PortA_CE = '1') and (PortB_CE = '1') then
				internal_busy <= '1';
				internal_error <= '1';
				internal_SRam_CE <= '0';
				internal_SRam_OE <= '0';
				internal_SRam_WE <= '0';
				internal_SRamData <= (others => 'Z');
			end if;		
		end if;		
	end process;
	
	SRam_Adress <= internal_SramAdress;
   SRam_Data <= internal_SramData;
	SRam_nCE <= not internal_SRam_CE;
   SRam_nOE <= not internal_SRam_OE;
   SRam_nWE <= not internal_SRam_WE;
	error <= internal_error;
	busy <= internal_busy;

end Behavioral;