----------------------------------------------------------------------------------
-- Company: 			Circuit-Break
-- Engineer: 			Jens Weiss
-- 
-- Create Date:    	12:39:50 01/01/2025 
-- Design Name: 		VHDL Library
-- Module Name:    	EBI_Interface - Behavioral 
-- Project Name: 
-- Target Devices: 	
-- Tool versions: 	ISE 14.7 (P20121013)
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity EBI_Interface is
    Port ( 	clk : in  std_logic;
				reset : in  std_logic;
				--EBI Interface
				DataAdress : inout  std_logic_vector (7 downto 0);
				Adress16 : in  std_logic;
				Adress17 : in  std_logic;
				Adress18 : in  std_logic;
				ALE0 : in  std_logic;
				ALE1 : in  std_logic;
				nCE : in  std_logic;
				nOE : in  std_logic;
				nWE : in  std_logic;
				--Internal Interface
				DataOut : out std_logic_vector(7 downto 0);
				DataIn : in std_logic_vector(7 downto 0);
				Adress : out std_logic_vector(18 downto 0);
				CE : out std_logic;
				OE : out std_logic;
				WE : out std_logic
				);
end EBI_Interface;

architecture Behavioral of EBI_Interface is

signal internal_DataAdress : std_logic_vector(7 downto 0);
signal internal_Adress : std_logic_vector(18 downto 0);
signal internal_DataOut : std_logic_vector(7 downto 0);
signal internal_CE : std_logic;
signal internal_OE : std_logic;
signal internal_WE : std_logic;

begin

	-- latch Data EBI-Bus for Adress
	process
	begin
		wait until rising_edge(clk);
		
		if (reset = '1') then
			internal_Adress <= (others => '0');
		else
			if (ALE1 = '1') and (ALE0 = '0') then
				internal_Adress(15 downto 8) <= DataAdress;
			else
				internal_Adress(15 downto 8) <= internal_Adress(15 downto 8);
			end if;
			
			if (ALE0 = '1') and (ALE1 = '0') then
				internal_Adress(7 downto 0) <= DataAdress;
			else
				internal_Adress(7 downto 0) <= internal_Adress(7 downto 0);
			end if;
			internal_Adress(16) <= Adress16;
			internal_Adress(17) <= Adress17;
			internal_Adress(18) <= Adress18;	
		end if;
	end process;
	
	-- transfer Data
	process
	begin
		wait until (rising_edge(clk));
		
		if (reset = '1') then
			internal_CE <= '0';
			internal_OE <= '0';
			internal_WE <= '0';
			internal_DataAdress <= (others => '0');
			internal_DataOut <= (others => '0');
		else		
			--EBI selects RAM
			if(nCE = '0')then				
				internal_CE <= '1';
					
				if (nOE = '0') then
					internal_DataAdress <= DataIn;
					internal_OE <= '1';
				else
					internal_OE <= '0';
				end if;
				
				if (nWE = '0') then
					internal_DataOut <= DataAdress;
					internal_WE <= '1';
				else
					internal_WE <= '0';
				end if;
				
			--EBI deselects RAM
			else
				internal_CE <= '0';
				internal_OE <= '0';
				internal_WE <= '0';
				internal_DataAdress <= (others => 'Z');
				internal_DataOut <= (others => 'Z');
			end if;					
		end if;		
	end process;

	Adress <= internal_Adress;
	DataOut <= internal_DataOut;
	DataAdress <= internal_DataAdress;
	CE <= internal_CE;
	OE <= internal_OE;
	WE <= internal_WE;

end Behavioral;