--------------------------------------------------------------------------------
-- Company: 			Circuit-Break
-- Engineer:			Jens Weiss
--
-- Create Date:   	20:57:27 01/01/2025
-- Design Name:   	VHDL Library
-- Module Name:   	DualPort_SRamInterface_tb.vhd
-- Project Name:  
-- Target Device:  
-- Tool versions:  	ISE 14.7 (P20121013)
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: DualPort_MemoryController
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY DualPort_SRamInterface_tb IS
END DualPort_SRamInterface_tb;
 
ARCHITECTURE behavior OF DualPort_SRamInterface_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT DualPort_SRamInterface
    PORT(
         clk : IN  std_logic;
         reset : IN  std_logic;
         busy : OUT  std_logic;
         error : OUT  std_logic;
         PortA_Adress : IN  std_logic_vector(18 downto 0);
         PortA_DataIn : IN  std_logic_vector(7 downto 0);
         PortA_DataOut : OUT  std_logic_vector(7 downto 0);
         PortA_CE : IN  std_logic;
         PortA_OE : IN  std_logic;
         PortA_WE : IN  std_logic;
         PortB_Adress : IN  std_logic_vector(18 downto 0);
         PortB_DataIn : IN  std_logic_vector(7 downto 0);
         PortB_DataOut : OUT  std_logic_vector(7 downto 0);
         PortB_CE : IN  std_logic;
         PortB_OE : IN  std_logic;
         PortB_WE : IN  std_logic;
         SRam_Adress : OUT  std_logic_vector(18 downto 0);
         SRam_Data : INOUT  std_logic_vector(7 downto 0);
         SRam_nCE : OUT  std_logic;
         SRam_nOE : OUT  std_logic;
         SRam_nWE : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';
   signal PortA_Adress : std_logic_vector(18 downto 0) := (others => '0');
   signal PortA_DataIn : std_logic_vector(7 downto 0) := (others => '0');
   signal PortA_CE : std_logic := '0';
   signal PortA_OE : std_logic := '0';
   signal PortA_WE : std_logic := '0';
   signal PortB_Adress : std_logic_vector(18 downto 0) := (others => '0');
   signal PortB_DataIn : std_logic_vector(7 downto 0) := (others => '0');
   signal PortB_CE : std_logic := '0';
   signal PortB_OE : std_logic := '0';
   signal PortB_WE : std_logic := '0';

	--BiDirs
   signal SRam_Data : std_logic_vector(7 downto 0);

 	--Outputs
   signal busy : std_logic;
   signal error : std_logic;
   signal PortA_DataOut : std_logic_vector(7 downto 0);
   signal PortB_DataOut : std_logic_vector(7 downto 0);
   signal SRam_Adress : std_logic_vector(18 downto 0);
   signal SRam_nCE : std_logic;
   signal SRam_nOE : std_logic;
   signal SRam_nWE : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
	
	-- Steuerleitung für SRAM
	signal file_download : boolean := FALSE;
	signal file_dump : boolean := FALSE;
--	signal nCE : std_logic := '1';
--	signal nOE : std_logic := '1';
--	signal nWE : std_logic := '1';
--	signal A : std_logic_vector(18 downto 0) := (others => '0');
--	signal D : std_logic_vector(7 downto 0) := (others => '0'); 
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: DualPort_SRamInterface PORT MAP (
          clk => clk,
          reset => reset,
          busy => busy,
          error => error,
          PortA_Adress => PortA_Adress,
          PortA_DataIn => PortA_DataIn,
          PortA_DataOut => PortA_DataOut,
          PortA_CE => PortA_CE,
          PortA_OE => PortA_OE,
          PortA_WE => PortA_WE,
          PortB_Adress => PortB_Adress,
          PortB_DataIn => PortB_DataIn,
          PortB_DataOut => PortB_DataOut,
          PortB_CE => PortB_CE,
          PortB_OE => PortB_OE,
          PortB_WE => PortB_WE,
          SRam_Adress => SRam_Adress,
          SRam_Data => SRam_Data,
          SRam_nCE => SRam_nCE,
          SRam_nOE => SRam_nOE,
          SRam_nWE => SRam_nWE
        );
		  
	Sram_Model: entity work.Sram_Model 
	PORT MAP(
		nCE => SRam_nCE,
		nOE => SRam_nOE,
		nWE => SRam_nWE,
		download => file_download,
		dump => file_dump,
		A => SRam_Adress,
		D => SRam_Data		
		);

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      -- insert stimulus here 
		reset <= '1';
		wait for 100ns;
		reset <= '0';
		PortA_CE <= '0';
		PortA_OE <= '0';
 		PortA_WE <= '0';
		PortA_Adress <= (others => '0');
		PortA_DataOut <= (others => '0');
		
		PortB_CE <= '0';
		PortB_OE <= '0';
 		PortB_WE <= '0';
		PortB_Adress <= (others => '0');
		PortB_DataOut <= (others => '0');
		wait for 100ns;
		
		PortA_CE <= '1';
--		PortB_CE <= '1';
		PortA_Adress <= std_logic_vector(to_unsigned(1, 19));
		PortA_DataIn <= std_logic_vector(to_unsigned(100, 8));
		wait for 32ns;
		PortA_WE <= '1';
		wait for 32ns;
		PortA_WE <= '0';
		wait for 10ns;
		PortA_CE <= '0';
--		PortB_CE <= '0';

      wait;
   end process;

END;