--------------------------------------------------------------------------------
-- Company: 			Circuit-Break
-- Engineer:			Jens Weiss
--
-- Create Date:   	14:01:05 01/01/2025
-- Design Name:   	VHDL Library
-- Module Name:   	EBI_Interface_tb.vhd
-- Project Name:  	
-- Target Device:  
-- Tool versions:  	ISE 14.7 (P20121013)
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: EBI_Interface
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY EBI_Interface_tb IS
END EBI_Interface_tb;
 
ARCHITECTURE behavior OF EBI_Interface_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT EBI_Interface
    PORT(
         clk : IN  std_logic;
         reset : IN  std_logic;
         DataAdress : INOUT  std_logic_vector(7 downto 0);
         Adress16 : IN  std_logic;
         Adress17 : IN  std_logic;
         Adress18 : IN  std_logic;
         ALE0 : IN  std_logic;
         ALE1 : IN  std_logic;
         nCE : IN  std_logic;
         nOE : IN  std_logic;
         nWE : IN  std_logic;
         DataOut : OUT  std_logic_vector(7 downto 0);
         DataIn : IN  std_logic_vector(7 downto 0);
         Adress : OUT  std_logic_vector(18 downto 0);
         CE : OUT  std_logic;
         OE : OUT  std_logic;
         WE : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';
   signal Adress16 : std_logic := '0';
   signal Adress17 : std_logic := '0';
   signal Adress18 : std_logic := '0';
   signal ALE0 : std_logic := '0';
   signal ALE1 : std_logic := '0';
   signal nCE : std_logic := '1';
   signal nOE : std_logic := '1';
   signal nWE : std_logic := '1';
   signal DataIn : std_logic_vector(7 downto 0) := (others => '0');

	--BiDirs
   signal DataAdress : std_logic_vector(7 downto 0);

 	--Outputs
   signal DataOut : std_logic_vector(7 downto 0);
   signal Adress : std_logic_vector(18 downto 0);
   signal CE : std_logic;
   signal OE : std_logic;
   signal WE : std_logic;
	
	--Signal for Testbench
	signal EBI_memory_address : integer range 0 to 525287;
	signal EBI_memory_address_vector : std_logic_vector(18 downto 0);
	signal EBI_memory_data : integer range 0 to 255;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: EBI_Interface PORT MAP (
          clk => clk,
          reset => reset,
          DataAdress => DataAdress,
          Adress16 => Adress16,
          Adress17 => Adress17,
          Adress18 => Adress18,
          ALE0 => ALE0,
          ALE1 => ALE1,
          nCE => nCE,
          nOE => nOE,
          nWE => nWE,
          DataOut => DataOut,
          DataIn => DataIn,
          Adress => Adress,
          CE => CE,
          OE => OE,
          WE => WE
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      -- insert stimulus here 
		reset <= '1';
		wait for 100ns;
		reset <= '0';
		nCE <= '1';	
		nOE <= '1';
		nWE <= '1';
		Adress16 <= '0';
		Adress17 <= '0';
		Adress18 <= '0';
		ALE0 <= '0';
		ALE1 <= '0';
		DataAdress <= (others => '0');
		EBI_memory_address <= 0;
		EBI_memory_data <= 0;
		EBI_memory_address_vector <= (others => '0');
		DataIn <= (others => '0');
		wait for 100ns;
		
--		for J in 0 to 1024 loop
--			--uc write
--			EBI_memory_address <= EBI_memory_address + 1;
--			EBI_memory_address_vector <= std_logic_vector(to_unsigned(EBI_memory_address, 19));
--			EBI_memory_data <= J;
--			wait for 100ns;
--			
--			nCE <= '0';
--			Adress16	<= EBI_memory_address_vector(16); 
--			Adress17	<= EBI_memory_address_vector(17); 
--			Adress18	<= EBI_memory_address_vector(18);
--			DataAdress <= EBI_memory_address_vector(15 downto 8);	--High Address
--			ALE1 <= '1';
--			wait for 24ns;
--			ALE1 <= '0';
--			wait for 32ns;
--			
--			DataAdress <= EBI_memory_address_vector(7 downto 0);	--Low Address
--			ALE0 <= '1';
--			wait for 25ns;
--			ALE0 <= '0';
--			wait for 32ns;
--			
--			DataAdress <= std_logic_vector(to_unsigned(EBI_memory_data, 8));	--Data
--			nWE <= '0';
--			wait for 32ns;
--			nWE <= '1';	
--			wait for 18ns;	
--			DataAdress <= (others => 'Z');
--			nCE <= '1';		
--			wait for 120ns;			
--		end loop;
		
		for J in 0 to 1024 loop
			--uc read
			EBI_memory_address <= EBI_memory_address + 1;
			EBI_memory_address_vector <= std_logic_vector(to_unsigned(EBI_memory_address, 19));
			EBI_memory_data <= J;
			wait for 100ns;
			
			nCE <= '0';
			Adress16	<= EBI_memory_address_vector(16); 
			Adress17	<= EBI_memory_address_vector(17); 
			Adress18	<= EBI_memory_address_vector(18);
			DataAdress <= EBI_memory_address_vector(15 downto 8);	--High Address
			ALE1 <= '1';
			wait for 24ns;
			ALE1 <= '0';
			wait for 32ns;
			
			DataAdress <= EBI_memory_address_vector(7 downto 0);	--Low Address
			ALE0 <= '1';
			wait for 25ns;
			ALE0 <= '0';
			wait for 32ns;
			
			DataAdress <= std_logic_vector(to_unsigned(J+5, 8));		--Data
			nOE <= '0';
			wait for 32ns;
			nOE <= '1';	
			wait for 18ns;	
			DataAdress <= (others => 'Z');
			nCE <= '1';		
			wait for 120ns;			
		end loop;

      wait;
   end process;

END;