// File generated from source:
//     /home/cyrite/src/cyhdl/myhdl.v2we/howto/../../library/xcd/xclkdomain.py
// (c) 2016-2022 section5.ch
// Modifications may be lost, edit the source file instead.

`timescale 1 ns / 1 ps
// Architecture cyriteHDL



module flagx
    (
        input wire  reset,
        input wire  clki,
        input wire  di,
        input wire  clko,
        output reg /* std_ulogic */ do
    );
    // Local type declarations
    // Signal declarations
    reg /* std_ulogic */ isig_d;
    reg /* std_ulogic */ sig;
    reg /* std_ulogic */ syncpipe1;
    reg /* std_ulogic */ syncpipe2;
    reg /* std_ulogic */ toggle;
    reg /* std_ulogic */ syncpipe0;
    
    always @ (posedge clki or posedge reset) begin : IN_DELAY
        if (reset == 1'b1) begin
            isig_d <= 1'b0; /* default */
        end else begin
            isig_d <= di;
        end
    end
    
    always @ (di or isig_d) begin : ASSIGN_RISING
        sig <= (di & ~isig_d);
    end
    
    always @ (syncpipe1 or syncpipe2) begin : ASSIGN_OUT
        do <= (syncpipe1 ^ syncpipe2);
    end
    
    always @ (posedge clki or posedge reset) begin : IN_WORKER
        if (reset == 1'b1) begin
            toggle <= 1'b0; /* default */
        end else begin
            toggle <= (toggle ^ sig);
        end
    end
    
    always @ (posedge clko or posedge reset) begin : OUT_WORKER
        if (reset == 1'b1) begin
            syncpipe2 <= 1'b0; /* default */
            syncpipe1 <= 1'b0; /* default */
            syncpipe0 <= 1'b0; /* default */
        end else begin
            syncpipe2 <= syncpipe1;
            syncpipe1 <= syncpipe0;
            syncpipe0 <= toggle;
        end
    end
endmodule // flagx