---------------------
entity ADDER is
port(clr,E1,E2,cyin : 	in bit;
	aus, cyaus : 		out bit);
end ADDER;
---------------------
architecture TEST of ADDER is
	constant prop_delay:  time := 10ns;
begin
	FADD:process(clr,E1,E2,cyin)
	begin
		if clr = '1' then
			aus <= '0' after prop_delay;
			cyaus <= '0' after prop_delay;
		else
			aus <= E1 xor E2 xor cyin after prop_delay;
			cyaus <= (E1 and E2) or (E1 and cyin) or (E2 and cyin) after prop_delay;
		end if;
	end process;
end TEST;
-----------------------------------
-----------------------------------
entity ersterTest is
end ersterTest;
---------------------
architecture aersterTest of ersterTest is
	signal rst, in1, in2, carry, Erg, cyErg :bit;
	
	component ADDER is
		port(clr,E1,E2,cyin : 	in bit;
			aus, cyaus : 		out bit);
	end component;
begin
--------------------------------------
	MOD1: ADDER
    port map(rst, in1, in2, carry, Erg, cyErg);
-----------------------------------
	STIMULUS: process
	begin
      rst <= '1';
      wait for 40ns;
      rst <= '0'; in1 <= '0'; in2 <= '0'; carry <= '0';
      wait for 40 ns;
      in1 <= '1'; in2 <= '0'; carry <= '0';
      wait for 40 ns;
      in1 <= '0'; in2 <= '1'; carry <= '0';
      wait for 40 ns;
      in1 <= '1'; in2 <= '1'; carry <= '0';
      wait for 40 ns;
      in1 <= '0'; in2 <= '0'; carry <= '1';
      wait for 40 ns;
      in1 <= '1'; in2 <= '0'; carry <= '1';
      wait for 40 ns;
      in1 <= '0'; in2 <= '1'; carry <= '1';
      wait for 40 ns;
      in1 <= '1'; in2 <= '1'; carry <= '1';
      wait for 40 ns;
      rst <= '1';
   end process STIMULUS;
-----------------------------------
end architecture;