entity Testbench is port(rst,in1,in2,carry : out bit); end entity Testbench; ------------------------- architecture TST of Testbench is begin STIMULUS: process begin rst <= '1'; wait for 40 ns; rst <= '0'; in1 <= '0'; in2 <= '0'; carry <= '0'; wait for 40 ns; in1 <= '1'; in2 <= '0'; carry <= '0'; wait for 40 ns; in1 <= '0'; in2 <= '1'; carry <= '0'; wait for 40 ns; in1 <= '1'; in2 <= '1'; carry <= '0'; wait for 40 ns; in1 <= '0'; in2 <= '0'; carry <= '1'; wait for 40 ns; in1 <= '1'; in2 <= '0'; carry <= '1'; wait for 40 ns; in1 <= '0'; in2 <= '1'; carry <= '1'; wait for 40 ns; in1 <= '1'; in2 <= '1'; carry <= '1'; wait for 40 ns; rst <= '1'; end process STIMULUS; end architecture TST;