;
; 328P_Timer2Mode0
;
; Created: 19.03.2025 15:33:59
; Author : Andreas
; C:\Program Files (x86)\Atmel\Studio\7.0\packs\atmel\ATmega_DFP\1.7.374\avrasm\inc\m328Pdef.inc


.device ATmega328P
.EQU    takt = 16000000 ; Systemtakt 16 MHz intern => 1 CPU clk = 62,5ns
.def	dummy = r17		; Dummy verwendung


;**********************************************************************	
.CSEG                   ; Programm-Flash => 'CodeSegment'
.org	$00				; Beginn Flash section for interrupt vectors

		jmp I_RESET			; #1 Reset, 3 cycl 
		jmp I_INT0			; #2 INT0 - Externer Interrupt 0 
		jmp I_INT1			; #3 INT1 - Externer Interrupt 1
		jmp I_PCINT0		; #4 PCINT0 - Pin Change Interrupt Request 0
		jmp I_PCINT1		; #5 PCINT1 - Pin Change Interrupt Request 1
		jmp I_PCINT2		; #6 PCINT2 - Pin Change Interrupt Request 2
		jmp I_WDT			; #7 WDT - Watchdog Time-out Interrupt 
		jmp I_TIMER2_COMPA	; #8 TIMER2_COMPA - Timer/Counter2 Compare Match A
		jmp I_TIMER2_COMPB	; #9 TIMER2_COMPB - Timer/Counter2 Compare Match B
		jmp I_TIMER2_OVF	; #10 TIMER2_OVF - Timer/Counter2 Overflow, 3 cycl
		jmp I_TIMER1_CAPT	; #11 TIMER1_CAPT 	Timer/Counter1 Capture Event
		jmp I_TIMER1_COMPA	; #12 TIMER1_COMPA 	Timer/Counter1 Compare Match A
		jmp I_TIMER1_COMPB	; #13 TIMER1_COMPB 	Timer/Counter1 Compare Match B
		jmp I_TIMER1_OVF	; #14 TIMER1_OVF 	Timer/Counter1 Overflow
		jmp I_TIMER0_COMPA	; #15 TIMER0_COMPA 	Timer/Counter0 Compare Match A
		jmp I_TIMER0_COMPB	; #16 TIMER0_COMPB 	Timer/Counter0 Compare Match B
		jmp I_TIMER0_OVF	; #17 TIMER0_OVF    Timer/Counter0 Overflow 
		jmp I_SPI_STC		; #18 SPI_STC 	SPI-Übertragung abgeschlossen
		jmp I_USART_RX		; #19 USART_RX 	USART-Empfang abgeschlossen
		jmp	I_USART_UDRE	; #20 USART_UDRE 	USART-Datenregister leer
		jmp I_USART_TX		; #21 USART_TX 	USART-Sendung abgeschlossen
		jmp I_ADC			; #22 ADC 	ADC Conversion Complete 
		jmp I_EE_READY		; #23 EE_READY 	EEPROM bereit
		jmp I_ANALOG_COMP	; #24 ANALOG_COMP 	Analogkomparator
		jmp I_TWI			; #25 TWI 	Two-Wire Interface
		jmp I_SPM_RDY		; #26 SPM_RDY 	Store Program Memory Ready 


;**********************************************************************
; Reset
;**********************************************************************
I_RESET:  
		; Init the stackpointer, no subroutines will be fine before 
		ldi dummy,LOW(RAMEND)	; 1 cycl, load immeddiate, R16 = LB(RAM Ende), Stapel anlegen
        out SPL,dummy			; 1 cycl, Store register to I/O, Stackpointer L = R16
        ldi dummy,HIGH(RAMEND)	; 1 cycl, load immeddiate, R16 = HB(RAM Ende),
        out SPH,dummy			; 1 cycl, Store register to I/O, Stackpointer H = R16

		; Set all ports (B,C,D) to output
		ldi dummy,0xff		; 1 cycl, output
		out DDRB,dummy		; 1 cycl, set portb
		out DDRC,dummy       ; 1 cycl, set portc
		out DDRD,dummy       ; 1 cycl, set portd
		sbi portd,7			; 2 cycl, enable pullup D7

		; generate interrupt on each Timer overflow/Timer output compare
		sei					; 1 cycl, enable global interrupts
		; ocie2a = "Output Compare Flag 2 A2"; TOIE2 = "Timer/Counter2 Overflow Flag"
		ldi dummy,(0<<ocie2a)|(1<<TOIE2) ; 1 cycl, enable specified interrupts
		sts TIMSK2,dummy	; 2 cycl, SFR 70, set "Timer/Counter2 Interrupt Mask Register"
		
		call T2_SetMode0		; 4 + 10 cycl, complete setup timer2
		
x1:		jmp x1				; 3 cycl, deadloop and timer are freerunning		 
	

;**********************************************************************
; TIMER 2 playing, 1 CPU clk ~ 62,5ns
;**********************************************************************		; Output OC2A (PB3), 
T2_SetMode0:
		; === Mode 0 ===
		;.equ COM2A = 0b00	; Normal port operation, OC0A disconnected
		.equ COM2A = 0b01	; Toggle OC2A on Compare Match
		;.equ COM2A = 0b10	; Clear OC2A on Compare Match
		;.equ COM2A = 0b11	; Set OC2A on Compare Match
		.equ COM2B = 0b00	; Normal port operation, OC2B disconnected
		;.equ COM2B = 0b01	; Toggle OC2B on Compare Match
		;.equ COM2B = 0b10	; Clear OC2B on Compare Match
		;.equ COM2B = 0b11	; Set OC2B on Compare Match


		; ==== Prescaler for timer 2 ====
		;.equ CS2 = 0b000	; No clock source (Timer/Counter stopped)
		.equ CS2 = 0b001	; clkT2S/(No prescaling) -> (62,5ns*256) = 16.000ns toggle (on freerunning)
		;.equ CS2 = 0b010	; clkT2S/8 (From prescaler) -> (62,5ns*256*8) = 128.000ns toggle (on freerunning)
		;.equ CS2 = 0b011	; clkT2S/32 (From prescaler) -> (62,5ns*256*32) = 512.000ns toggle (on freerunning)
		;.equ CS2 = 0b100	; clkT2S/64 (From prescaler) -> (62,5ns*256*64) = 1024.000ns toggle (on freerunning)
		;.equ CS2 = 0b101	; clkT2S/128 (From prescaler) -> (62,5ns*256*128) = 2.048.000ns toggle (on freerunning)
		;.equ CS2 = 0b110	; clkT2S/256 (From prescaler) -> (62,5ns*256*256) = 4.096.000ns toggle (on freerunning)
		;.equ CS2 = 0b111	; clkT2S/1024 (From prescaler) -> (62,5ns*256*1024) = 16.384.000ns toggle (on freerunning)
		
		; TCCR2A Timer/Counter Control Register A, SFR B0
		; CompOutputA (COM2Ax), CompOutputB (COM2Bx), Waveform Generation Mode (WGM20/21)
		ldi dummy,(COM2A<<6)|(COM2B<<4)|(0<<WGM21)|(0<<WGM20) ; 1 cycl
		sts TCCR2A,dummy	; 2 cycl, SFR B0, 
		
		; TCCR2B Timer/Counter Control Register B, SFR B1
		; Waveform Generation Mode (WGM22); Prescaler (CS2 -> CS22-CS20, F=(62,5ns*256*prescaler)
		ldi dummy,(0<<WGM22)|(CS2) ; 1 cycl
		sts TCCR2B,dummy	; 2 cycl, SFR B1

		ret					; 4 cycl


;**********************************************************************
; PD7: TIMER2 overflow interrupt, 12cycl * 62,5ns = (750ns)
;**********************************************************************
I_TIMER2_OVF:
		
		ldi dummy,0x80		; 1 cycl, output
		out portd,dummy		; 1 cycl, set portd
		nop					; 1 cycl, sync latch
		ldi dummy,0x00		; 1 cycl, output
		out portd,dummy		; 1 cycl, clear portd
		nop					; 1 cycl, sync latch
		
		ldi dummy,0x80		; 1 cycl, output
		out portd,dummy		; 1 cycl, set portd
		nop					; 1 cycl, sync latch
		ldi dummy,0x00		; 1 cycl, output
		out portd,dummy		; 1 cycl, clear portd
		nop					; 1 cycl, sync latch
		
		reti				; 4 cycl, bye


;**********************************************************************
I_INT0:			reti ; #2 INT0 - Externer Interrupt 0 
I_INT1:			reti ; #3 INT1 - Externer Interrupt 1
I_PCINT0:		reti ; #4 PCINT0 - Pin Change Interrupt Request 0
I_PCINT1:		reti ; #5 PCINT1 - Pin Change Interrupt Request 1
I_PCINT2:		reti ; #6 PCINT2 - Pin Change Interrupt Request 2
I_WDT:			reti ; #7 WDT - Watchdog Time-out Interrupt 
I_TIMER2_COMPA:	reti ; #8 TIMER2_COMPA - Timer/Counter2 Compare Match A
I_TIMER2_COMPB:	reti ; #9 TIMER2_COMPB - Timer/Counter2 Compare Match B
;I_TIMER2_OVF:	reti ; #10 TIMER2_OVF - Timer/Counter2 Overflow
I_TIMER1_CAPT:	reti ; #11 TIMER1_CAPT 	Timer/Counter1 Capture Event
I_TIMER1_COMPA:	reti ; #12 TIMER1_COMPA 	Timer/Counter1 Compare Match A
I_TIMER1_COMPB:	reti ; #13 TIMER1_COMPB 	Timer/Counter1 Compare Match B
I_TIMER1_OVF:	reti ; #14 TIMER1_OVF 	Timer/Counter1 Overflow
I_TIMER0_COMPA:	reti ; #15 TIMER0_COMPA 	Timer/Counter0 Compare Match A
I_TIMER0_COMPB:	reti ; #16 TIMER0_COMPB 	Timer/Counter0 Compare Match B
I_TIMER0_OVF:	reti ; #17 TIMER0_OVF    Timer/Counter0 Overflow 
I_SPI_STC:		reti ; #18 SPI_STC 	SPI-Übertragung abgeschlossen
I_USART_RX:		reti ; #19 USART_RX 	USART-Empfang abgeschlossen
I_USART_UDRE:	reti ; #20 USART_UDRE 	USART-Datenregister leer
I_USART_TX:		reti ; #21 USART_TX 	USART-Sendung abgeschlossen
I_ADC:			reti ; #22 ADC 	ADC Conversion Complete 
I_EE_READY:		reti ; #23 EE_READY 	EEPROM bereit
I_ANALOG_COMP:	reti ; #24 ANALOG_COMP 	Analogkomparator
I_TWI:			reti ; #25 TWI 	Two-Wire Interface
I_SPM_RDY:		reti ; #26 SPM_RDY 	Store Program Memory Ready