// spi.h // Source: stm32l431xx.h V1.7.3 2023-06-07 by MCD Application Team // * Copyright (c) 2017 STMicroelectronics. // * All rights reserved. // * // * This software is licensed under terms that can be found in the LICENSE file // * in the root directory of this software component. // * If no LICENSE file comes with this software, it is provided AS-IS. typedef enum spi_prescaler_enum { SPICLK_DIV_2, SPICLK_DIV_4, SPICLK_DIV_8, SPICLK_DIV_16, SPICLK_DIV_32, SPICLK_DIV_64, SPICLK_DIV_128, SPICLK_DIV_256 } spi_prescaler_enum; typedef enum spi_data_size_enum { SPI_DS_4 = 3, SPI_DS_5, SPI_DS_6, SPI_DS_7, SPI_DS_8, SPI_DS_9, SPI_DS_10, SPI_DS_11, SPI_DS_12, SPI_DS_13, SPI_DS_14, SPI_DS_15, SPI_DS_16 } spi_data_size_enum; // Serial Peripheral Interface typedef volatile struct spi_struct { // 0x00 SPI_CR1 SPI Control register 1 uint32_t CPHA : 1; // 0 Clock Phase uint32_t CPOL : 1; // 1 Clock Polarity uint32_t MSTR : 1; // 2 Master Selection uint32_t BR : 3; // 3 BR[2:0] bits (Baud Rate Control) uint32_t SPE : 1; // 6 SPI Enable uint32_t LSBFIRST : 1; // 7 Frame Format uint32_t SSI : 1; // 8 Internal slave select uint32_t SSM : 1; // 9 Software slave management uint32_t RXONLY : 1; // 10 Receive only uint32_t CRCL : 1; // 11 CRC Length uint32_t CRCNEXT : 1; // 12 Transmit CRC next uint32_t CRCEN : 1; // 13 Hardware CRC calculation enable uint32_t BIDIOE : 1; // 14 Output enable in bidirectional mode uint32_t BIDIMODE : 1; // 15 Bidirectional data mode enable uint32_t : 16; // 0x04 SPI_CR2 SPI Control register 2 uint32_t RXDMAEN : 1; // 0 Rx Buffer DMA Enable uint32_t TXDMAEN : 1; // 1 Tx Buffer DMA Enable uint32_t SSOE : 1; // 2 SS Output Enable uint32_t NSSP : 1; // 3 NSS pulse management Enable uint32_t FRF : 1; // 4 Frame Format Enable uint32_t ERRIE : 1; // 5 Error Interrupt Enable uint32_t RXNEIE : 1; // 6 RX buffer Not Empty Interrupt Enable uint32_t TXEIE : 1; // 7 Tx buffer Empty Interrupt Enable uint32_t DS : 4; // 8 DS[3:0] Data Size uint32_t FRXTH : 1; // 12 FIFO reception Threshold uint32_t LDMARX : 1; // 13 Last DMA transfer for reception uint32_t LDMATX : 1; // 14 Last DMA transfer for transmission uint32_t : 17; // 0x08 SPI_SR SPI Status register uint32_t RXNE : 1; // 0 Receive buffer Not Empty uint32_t TXE : 1; // 1 Transmit buffer Empty uint32_t CHSIDE : 1; // 2 Channel side uint32_t UDR : 1; // 3 Underrun flag uint32_t CRCERR : 1; // 4 CRC Error flag uint32_t MODF : 1; // 5 Mode fault uint32_t OVR : 1; // 6 Overrun flag uint32_t BSY : 1; // 7 Busy flag uint32_t FRE : 1; // 8 TI frame format error uint32_t FRLVL : 2; // 9 FIFO Reception Level uint32_t FTLVL : 2; // 11 FIFO Transmission Level uint32_t : 19; // 0x0c SPI_DR SPI data register union { uint32_t DR; // Data Register uint8_t DR8; // 8: 4 .. 8 Bit Frames; FRXTH = 0 uint16_t DR16; // 16: 9 .. 16 Bit Frames; FRXTH = 1 }; // 0x10 SPI_CRCPR SPI CRC polynomial register uint32_t CRCPR; // 16; // 0 CRC polynomial register // 0x14 SPI_RXCRCR SPI Rx CRC register uint32_t RXCRCR; // 16; // 0 Rx CRC Register // 0x18 SPI_TXCRCR SPI Tx CRC register uint32_t TXCRCR; // 16; // 0 Tx CRC Register } spi_struct; _Static_assert (sizeof(spi_struct) == 28, " spi_struct: bad size"); static spi_struct * const SPI2 = (spi_struct *)0x40003800; static spi_struct * const SPI3 = (spi_struct *)0x40003c00; static spi_struct * const SPI1 = (spi_struct *)0x40013000;