---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12:15:03 12/28/2009 -- Design Name: -- Module Name: filter_module - filter_module_arch -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity filter_module is port ( clk : in std_logic; reset : in std_logic; rx_data_in : in std_logic_vector(7 downto 0); rx_sof_in_n : in std_logic; rx_eof_in_n : in std_logic; rx_src_rdy_in_n : in std_logic; rx_dst_rdy_out_n : out std_logic; tx_data_out : out std_logic_vector(7 downto 0); tx_sof_out_n : out std_logic; tx_eof_out_n : out std_logic; tx_src_rdy_out_n : out std_logic; tx_dst_rdy_in_n : in std_logic ); end filter_module; architecture filter_module_arch of filter_module is -- component declarations component pic_bram_64k port ( clka : IN std_logic; dina : IN std_logic_VECTOR(7 downto 0); addra : IN std_logic_VECTOR(15 downto 0); wea : IN std_logic_VECTOR(0 downto 0); douta : OUT std_logic_VECTOR(7 downto 0); clkb : IN std_logic; dinb : IN std_logic_VECTOR(7 downto 0); addrb : IN std_logic_VECTOR(15 downto 0); web : IN std_logic_VECTOR(0 downto 0); doutb : OUT std_logic_VECTOR(7 downto 0) ); end component; component sobel_bram_128k port ( clka : IN std_logic; dina : IN std_logic_VECTOR(15 downto 0); addra : IN std_logic_VECTOR(15 downto 0); wea : IN std_logic_VECTOR(0 downto 0); douta : OUT std_logic_VECTOR(15 downto 0); clkb : IN std_logic; dinb : IN std_logic_VECTOR(15 downto 0); addrb : IN std_logic_VECTOR(15 downto 0); web : IN std_logic_VECTOR(0 downto 0); doutb : OUT std_logic_VECTOR(15 downto 0) ); end component; component data_to_bram port ( clk : in std_logic; reset : in std_logic; rx_data_in : in std_logic_vector(7 downto 0); rx_sof_in_n : in std_logic; rx_eof_in_n : in std_logic; rx_src_rdy_in_n : in std_logic; rx_dst_rdy_out_n : out std_logic; bram_din : out std_logic_vector(7 downto 0); bram_addr : out std_logic_vector(15 downto 0); bram_we : out std_logic_vector(0 downto 0); bram_dout : in std_logic_vector(7 downto 0); finish : out std_logic; k1, k2, p1, p2 : out std_logic_vector(15 downto 0); fx, fy, cx, cy : out std_logic_vector(15 downto 0) ); end component; component data_from_bram port ( clk : in std_logic; reset : in std_logic; tx_data_out : out std_logic_vector(7 downto 0); tx_sof_out_n : out std_logic; tx_eof_out_n : out std_logic; tx_src_rdy_out_n : out std_logic; tx_dst_rdy_in_n : in std_logic; res_bram_addr : out std_logic_vector(15 downto 0); res_bram_dout : in std_logic_vector(7 downto 0); sobelx_bram_addr : out std_logic_vector(15 downto 0); sobelx_bram_dout : in std_logic_vector(15 downto 0); sobely_bram_addr : out std_logic_vector(15 downto 0); sobely_bram_dout : in std_logic_vector(15 downto 0); start : in std_logic ); end component; -- undistortion coefficients signal k1_con, k2_con, p1_con, p2_con : std_logic_vector(15 downto 0) := (others => '0'); signal fx_con, fy_con, cx_con, cy_con : std_logic_vector(15 downto 0) := (others => '0'); -- notification signals signal store_into_bram : std_logic; -- BRAM conncetion signals signal data_to_bram_din : std_logic_vector(7 downto 0); signal data_to_bram_addr : std_logic_vector(15 downto 0); signal data_to_bram_wea : std_logic_vector(0 downto 0); signal data_to_bram_dout : std_logic_vector(7 downto 0); signal data_from_res_bram_addr : std_logic_vector(15 downto 0); signal data_from_res_bram_dout : std_logic_vector(7 downto 0); signal data_from_sobelx_bram_addr : std_logic_vector(15 downto 0); signal data_from_sobelx_bram_dout : std_logic_vector(15 downto 0); signal data_from_sobely_bram_addr : std_logic_vector(15 downto 0); signal data_from_sobely_bram_dout : std_logic_vector(15 downto 0); -- internal output signals signal rx_dst_rdy_out_n_i : std_logic := '1'; signal tx_data_out_i : std_logic_vector(7 downto 0) := (others => '0'); signal tx_sof_out_n_i : std_logic := '1'; signal tx_eof_out_n_i : std_logic := '1'; signal tx_src_rdy_out_n_i : std_logic := '1'; begin -- component instantiations pic_bram_inst : pic_bram_64k port map ( clka => clk, dina => data_to_bram_din, addra => data_to_bram_addr, wea => data_to_bram_wea, douta => data_to_bram_dout, clkb => clk, dinb => (others => '0'), addrb => data_from_res_bram_addr, --TEMP web => (others => '0'), doutb => data_from_res_bram_dout --TEMP ); res_bram_inst : pic_bram_64k port map ( clka => clk, dina => (others => '0'), addra => (others => '0'), wea => (others => '0'), douta => open, clkb => clk, dinb => (others => '0'), addrb => (others => '0'), -- TEMP web => (others => '0'), doutb => open -- TEMP ); data_to_bram_inst : data_to_bram PORT MAP ( clk => clk, reset => reset, rx_data_in => rx_data_in, rx_sof_in_n => rx_sof_in_n, rx_eof_in_n => rx_eof_in_n, rx_src_rdy_in_n => rx_src_rdy_in_n, rx_dst_rdy_out_n => rx_dst_rdy_out_n_i, bram_din => data_to_bram_din, bram_addr => data_to_bram_addr, bram_we => data_to_bram_wea, bram_dout => data_to_bram_dout, finish => store_into_bram, k1 => k1_con, k2 => k2_con, p1 => p1_con, p2 => p2_con, fx => fx_con, fy => fy_con, cx => cx_con, cy => cy_con ); data_from_bram_inst : data_from_bram PORT MAP( clk => clk, reset => reset, tx_data_out => tx_data_out_i, tx_sof_out_n => tx_sof_out_n_i, tx_eof_out_n => tx_eof_out_n_i, tx_src_rdy_out_n => tx_src_rdy_out_n_i, tx_dst_rdy_in_n => tx_dst_rdy_in_n, res_bram_addr => data_from_res_bram_addr, res_bram_dout => data_from_res_bram_dout, sobelx_bram_addr => data_from_sobelx_bram_addr, sobelx_bram_dout => data_from_sobelx_bram_dout, sobely_bram_addr => data_from_sobely_bram_addr, sobely_bram_dout => data_from_sobely_bram_dout, start => store_into_bram ); -- assign output ports rx_dst_rdy_out_n <= rx_dst_rdy_out_n_i; tx_data_out <= tx_data_out_i; tx_sof_out_n <= tx_sof_out_n_i; tx_eof_out_n <= tx_eof_out_n_i; tx_src_rdy_out_n <= tx_src_rdy_out_n_i; end filter_module_arch;