---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12:56:56 12/28/2009 -- Design Name: -- Module Name: data_to_bram - data_to_bram_arch -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use work.filter_module_pkg.all; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity data_to_bram is port ( clk : in std_logic; reset : in std_logic; rx_data_in : in std_logic_vector(7 downto 0); rx_sof_in_n : in std_logic; rx_eof_in_n : in std_logic; rx_src_rdy_in_n : in std_logic; rx_dst_rdy_out_n : out std_logic; bram_din : out std_logic_vector(7 downto 0); bram_addr : out std_logic_vector(15 downto 0); bram_we : out std_logic_vector(0 downto 0); bram_dout : in std_logic_vector(7 downto 0); finish : out std_logic; k1, k2, p1, p2 : out std_logic_vector(15 downto 0); fx, fy, cx, cy : out std_logic_vector(15 downto 0) ); end data_to_bram; architecture data_to_bram_arch of data_to_bram is type fsm_state is ( WAIT_FOR_SOF, GET_DEST_MAC, GET_SRC_MAC, GET_TYPE, GET_FRAME_NR, GET_COEFF, GET_AND_STORE_DATA ); type mem_state is ( INIT_WRITE_BACK, WRITE_BACK, DONE ); signal current_fsm_state : fsm_state := WAIT_FOR_SOF; signal current_mem_state : mem_state := INIT_WRITE_BACK; -- counter signal frame_nr : integer range 0 to 50 := 0; -- 0-49: #picframe; 50: undistortion coefficents signal offset_cnt : integer range 0 to PIC_FRAME_SIZE-1 := 0; -- frame offset signal mac_byte_cnt : integer range 0 to NR_MAC_BYTES-1 := 0; signal type_byte_cnt : integer range 0 to NR_TYPE_BYTES-1 := 0; signal coeff_byte_cnt : integer range 0 to COEFF_SIZE-1 := 0; -- internal output signals signal rx_dst_rdy_out_n_i : std_logic := '0'; signal bram_din_i : std_logic_vector(7 downto 0) := (others => '0'); signal bram_addr_i : std_logic_vector(15 downto 0) := (others => '0'); signal bram_we_i : std_logic := '0'; signal finish_i : std_logic := '0'; signal k1_i, k2_i, p1_i, p2_i : std_logic_vector(15 downto 0) := (others => '0'); signal fx_i, fy_i, cx_i, cy_i : std_logic_vector(15 downto 0) := (others => '0'); begin -- main fsm process begin wait until rising_edge(clk); rx_dst_rdy_out_n_i <= '0'; -- normally i'm ready bram_we_i <= '0'; -- normally data is not written bram_addr_i <= std_logic_vector(to_unsigned((frame_nr * PIC_FRAME_SIZE) + offset_cnt, 16)); bram_din_i <= rx_data_in; finish_i <= '0'; -- normally operation is not finished if (reset = '1') then current_fsm_state <= WAIT_FOR_SOF; else case (current_fsm_state) is when WAIT_FOR_SOF => if (rx_src_rdy_in_n = '0') then -- got sof signal if (rx_sof_in_n = '0') then -- get first mac byte finish_i <= '1'; -- TEMPORARY SET TO 1 FOR TESTING PURPOSES if (rx_data_in = DEST_MAC(0)) then -- mac bytes must match otherwise it isn't a packet for me offset_cnt <= 0; mac_byte_cnt <= 1; current_fsm_state <= GET_DEST_MAC; end if; end if; end if; when GET_DEST_MAC => if (rx_src_rdy_in_n = '0') then -- src must be ready if (rx_data_in = DEST_MAC(mac_byte_cnt)) then -- does dest mac byte match if (mac_byte_cnt = NR_MAC_BYTES - 1) then -- all dest mac bytes received mac_byte_cnt <= 0; current_fsm_state <= GET_SRC_MAC; else mac_byte_cnt <= mac_byte_cnt + 1; end if; else current_fsm_state <= WAIT_FOR_SOF; end if; end if; when GET_SRC_MAC => -- same procedure for src mac if (rx_src_rdy_in_n = '0') then if (rx_data_in = SRC_MAC(mac_byte_cnt)) then if (mac_byte_cnt = NR_MAC_BYTES - 1) then mac_byte_cnt <= 0; type_byte_cnt <= 0; current_fsm_state <= GET_TYPE; else mac_byte_cnt <= mac_byte_cnt + 1; end if; else current_fsm_state <= WAIT_FOR_SOF; end if; end if; when GET_TYPE => -- packet type has to match too if (rx_src_rdy_in_n = '0') then if (rx_data_in = PKT_TYPE(type_byte_cnt)) then if (type_byte_cnt = NR_TYPE_BYTES - 1) then type_byte_cnt <= 0; current_fsm_state <= GET_FRAME_NR; else type_byte_cnt <= type_byte_cnt + 1; end if; else current_fsm_state <= WAIT_FOR_SOF; end if; end if; when GET_FRAME_NR => -- get #frame if (rx_src_rdy_in_n = '0') then frame_nr <= to_integer(unsigned(rx_data_in)); if (unsigned(rx_data_in) = 50) then -- #50 indicates coefficents data current_fsm_state <= GET_COEFF; coeff_byte_cnt <= 0; else current_fsm_state <= GET_AND_STORE_DATA; current_mem_state <= INIT_WRITE_BACK; end if; end if; when GET_COEFF => -- get coeffiecients data if (rx_src_rdy_in_n = '0') then case (coeff_byte_cnt) is when 0 => k1_i(7 downto 0) <= rx_data_in; when 1 => k1_i(15 downto 8) <= rx_data_in; when 2 => k2_i(7 downto 0) <= rx_data_in; when 3 => k2_i(15 downto 8) <= rx_data_in; when 4 => p1_i(7 downto 0) <= rx_data_in; when 5 => p1_i(15 downto 8) <= rx_data_in; when 6 => p2_i(7 downto 0) <= rx_data_in; when 7 => p2_i(15 downto 8) <= rx_data_in; when 8 => fx_i(7 downto 0) <= rx_data_in; when 9 => fx_i(15 downto 8) <= rx_data_in; when 10 => fy_i(7 downto 0) <= rx_data_in; when 11 => fy_i(15 downto 8) <= rx_data_in; when 12 => cx_i(7 downto 0) <= rx_data_in; when 13 => cx_i(15 downto 8) <= rx_data_in; when 14 => cy_i(7 downto 0) <= rx_data_in; when 15 => cy_i(15 downto 8) <= rx_data_in; current_fsm_state <= WAIT_FOR_SOF; end case; coeff_byte_cnt <= coeff_byte_cnt + 1; end if; when GET_AND_STORE_DATA => if (rx_src_rdy_in_n = '0') then if (frame_nr = 49 and offset_cnt = 1279) then -- last byte is processed if (current_mem_state = WRITE_BACK) then -- write back last byte done finish_i <= '1'; current_fsm_state <= WAIT_FOR_SOF; end if; end if; case (current_mem_state) is when INIT_WRITE_BACK => bram_we_i <= '1'; -- start write back rx_dst_rdy_out_n_i <= '1'; -- no new data until write back is finished current_mem_state <= WRITE_BACK; when WRITE_BACK => bram_we_i <= '1'; current_mem_state <= DONE; when DONE => offset_cnt <= offset_cnt + 1; rx_dst_rdy_out_n_i <= '1'; current_mem_state <= INIT_WRITE_BACK; end case; end if; end case; end if; end process; -- assign output ports rx_dst_rdy_out_n <= rx_dst_rdy_out_n_i; bram_din <= bram_din_i; bram_addr <= bram_addr_i; bram_we(0) <= bram_we_i; finish <= finish_i; k1 <= k1_i; k2 <= k2_i; p1 <= p1_i; p2 <= p2_i; fx <= fx_i; fy <= fy_i; cx <= cx_i; cy <= cy_i; end data_to_bram_arch;