#include <msp430g2553.h>
#include <stdint.h>
#include <stdarg.h>
#include <w5500.h>


// SPI function prototypes
void w5500_write(uint16_t offset_addr, uint8_t control_phase);
void w5500_data_phase(uint8_t length, uint8_t WR_data, uint8_t *received_data,  ...);
void w5500_CS(int w5500_transfer);

// Data
int delay;
int counter = 0;
uint8_t socket_status[1] = 0;


uint8_t subnet_mask[] = {255, 255, 255, 0};
uint8_t ip_gateway[] = {192, 168, 0, 1};
uint8_t mac_address[] = {0x00, 0x08, 0xdc, 0x01, 0x02, 0x03};
uint8_t ip_destination[] = {192, 168, 0, 10};
uint8_t port_source[] = {0x13, 0x88};
uint8_t port_destitnation[] = {0x17, 0x70};

uint8_t subnet_mask_temp[] = {0, 0, 0, 0};
uint8_t ip_gateway_temp[] = {0, 0, 0, 0};
uint8_t mac_address_temp[] = {0, 0, 0, 0, 0, 0};
uint8_t ip_destination_temp[] = {0, 0, 0, 0};
uint8_t port_source_temp[] = {0, 0};
uint8_t port_destitnation_temp[] = {0, 0};


void main(void) {
    WDTCTL = WDTPW | WDTHOLD;  // Stop watchdog

    spi_init();

    P1DIR |= BIT1;
    P1OUT |= BIT1;

    uint8_t rx_buffer[6] = 0;
    int err_temp = 0;
    int socket_open_error =0;
    
    //Reset
    w5500_CS(1);
    w5500_write(MR, CREG_BLOCK|OM_FDM1|RWB_WRITE);
    w5500_data_phase(1, 1, rx_buffer, CR_RST);
    w5500_CS(0);

    // Delay
	delay_ms(1);
	
    // Check version register
    w5500_CS(1);
    w5500_write(VERSIONR, CREG_BLOCK|OM_FDM1|RWB_READ);
    w5500_data_phase(1, 0, rx_buffer);
    w5500_CS(0);
    
    
    
    // Set Gateway IP
    for(counter=0; counter<4;counter++)
    {
      w5500_CS(1);
      w5500_write(GAR(counter), CREG_BLOCK|OM_FDM1|RWB_WRITE);
      w5500_data_phase(1, 1, rx_buffer, ip_gateway[counter]);
      w5500_CS(0);
    }
    
    for(int counter=0;counter<4; counter++)
    {
      w5500_CS(1);
      w5500_write(GAR(counter), CREG_BLOCK|OM_FDM1|RWB_READ);
      w5500_data_phase(1, 0, &ip_gateway_temp[counter]);
      w5500_CS(0);
    }
    
	
    // Set Subnet Mask
        for(int counter=0;counter<4; counter++)
    {
      w5500_CS(1);
      w5500_write(SUBR(counter), CREG_BLOCK|OM_FDM1|RWB_WRITE);
      w5500_data_phase(1, 1, 0x00, subnet_mask[counter]);
      w5500_CS(0);
    }
    
    for(int counter=0;counter<4; counter++)
    {
      w5500_CS(1);
      w5500_write(SUBR(counter), CREG_BLOCK|OM_FDM1|RWB_READ);
      w5500_data_phase(1, 0, &subnet_mask_temp[counter]);
      w5500_CS(0);
    }
    

    // Set MAC Address

    for(counter=0; counter<6;counter++)
    {
      w5500_CS(1);
      w5500_write(SHAR(counter), CREG_BLOCK|OM_FDM1|RWB_WRITE);
      w5500_data_phase(1, 1, 0x00, mac_address[counter]);
      w5500_CS(0);
    }
    
    for(int counter=0;counter<6; counter++)
    {
      w5500_CS(1);
      w5500_write(SHAR(counter), CREG_BLOCK|OM_FDM1|RWB_READ);
      w5500_data_phase(1, 0, &mac_address_temp[counter]);
      w5500_CS(0);
    }
    
    
    
    // Set IP Address
     for(int counter=0;counter<4; counter++)
    {
      w5500_CS(1);
      w5500_write(SIPR(counter), CREG_BLOCK|OM_FDM1|RWB_WRITE);
      w5500_data_phase(1, 1, 0x00, ip_gateway[counter]);
      w5500_CS(0);
    }
    
    
    for(int counter=0;counter<4; counter++)
    {
      w5500_CS(1);
      w5500_write(SIPR(counter), CREG_BLOCK|OM_FDM1|RWB_READ);
      w5500_data_phase(1, 0, &ip_gateway_temp[counter]);
      w5500_CS(0);
    }
    

    // Set UDP Mode
    w5500_CS(1);
    w5500_write(Sn_MR, SREG_BLOCK(0)|OM_FDM1|RWB_WRITE);
    w5500_data_phase(1, 1, 0x00, Sn_MR_UDP);
    w5500_CS(0);
    
    w5500_CS(1);
    w5500_write(Sn_MR, SREG_BLOCK(0)|OM_FDM1|RWB_READ);
    w5500_data_phase(1, 0, rx_buffer);
    w5500_CS(0);
     
    if(0x02!=rx_buffer[0]) err_temp = 1;



    // Set Source Port (Port 5000)
    for(int counter=0;counter<2; counter++)
    {
      w5500_CS(1);
      w5500_write(Sn_PORT(counter), SREG_BLOCK(0)|OM_FDM1|RWB_WRITE);
      w5500_data_phase(1, 1, 0x00, port_source[counter]);
      w5500_CS(0);
    }
    
     for(int counter=0;counter<2; counter++)
    {
      w5500_CS(1);
      w5500_write(Sn_PORT(counter), SREG_BLOCK(0)|OM_FDM1|RWB_READ);
      w5500_data_phase(1, 0, &port_source_temp[counter]);
      w5500_CS(0);
    }
    
    // Set Desitination IP
    for(int counter=0;counter<4; counter++)
    {
      w5500_CS(1);
      w5500_write(Sn_DIPR(counter), SREG_BLOCK(0)|OM_FDM1|RWB_WRITE);
      w5500_data_phase(1, 1, 0x00, ip_destination[counter]);
      w5500_CS(0);
    }
    
    for(int counter=0;counter<4; counter++)
    {
      w5500_CS(1);
      w5500_write(Sn_DIPR(counter), SREG_BLOCK(0)|OM_FDM1|RWB_READ);
      w5500_data_phase(1, 0, &ip_destination_temp[counter]);
      w5500_CS(0);
    }

    // Destination PORT------------------------------------------------------------------
    for(int counter=0;counter<2; counter++)
    {
      w5500_CS(1);
      w5500_write(Sn_DPORT(counter), SREG_BLOCK(0)|OM_FDM1|RWB_WRITE);
      w5500_data_phase(1, 1, 0x00, port_source[counter]);
      w5500_CS(0);
    }
    

     for(int counter=0;counter<2; counter++)
    {
      w5500_CS(1);
      w5500_write(Sn_DPORT(counter), SREG_BLOCK(0)|OM_FDM1|RWB_READ);
      w5500_data_phase(1, 0, &port_destitnation_temp[counter]);
      w5500_CS(0);
    }
    
    //Buffer Size TX/RX
    w5500_CS(1);
    w5500_write(Sn_TXBUF_SIZE, SREG_BLOCK(0)|OM_FDM1|RWB_WRITE);
    w5500_data_phase(1, 1, rx_buffer, 0x01);  
    w5500_CS(0);
    
    w5500_CS(1);
    w5500_write(Sn_TXBUF_SIZE, SREG_BLOCK(0)|OM_FDM1|RWB_READ);
    w5500_data_phase(1, 0, rx_buffer);  
    w5500_CS(0);
    if((rx_buffer[0]==0x01) != 1) err_temp=1;

    
    w5500_CS(1);
    w5500_write(Sn_RXBUF_SIZE, SREG_BLOCK(0)|OM_FDM1|RWB_WRITE);
    w5500_data_phase(1, 1, rx_buffer, 0x01);  
    w5500_CS(0);
    
    w5500_CS(1);
    w5500_write(Sn_RXBUF_SIZE, SREG_BLOCK(0)|OM_FDM1|RWB_READ);
    w5500_data_phase(1, 0, rx_buffer);  
    w5500_CS(0);
   
    
    //Open Socket
    w5500_CS(1);
    w5500_write(Sn_CR, SREG_BLOCK(0)|OM_FDM1|RWB_WRITE);
    w5500_data_phase(1, 1, 0x00, Sn_CR_OPEN);
    w5500_CS(0);

    w5500_CS(1);
    w5500_write(Sn_CR, SREG_BLOCK(0)|OM_FDM1|RWB_READ);
    w5500_data_phase(1, 1, rx_buffer);
    w5500_CS(0);
    
    while(1);
}