// w5500.h - WIZnet W5500 Register Definitions #ifndef W5500_H #define W5500_H //2.2.2 Control Phase #define CREG_BLOCK 0x00 // Common register block #define SREG_BLOCK(N) (1+4*N) // Socket N register block #define TXBUF_BLOCK(N) (2+4*N) // Socket N Tx buffer address block #define RXBUF_BLOCK(N) (3+4*N) // Socket N Rx buffer address block #define OM_VDM 0x00 // Variable Data Length Mode #define OM_FDM1 0x01 // Fixed Data Length Mode - 1 Byte #define OM_FDM2 0x02 // Fixed Data Length Mode - 2 Bytes #define OM_FDM4 0x03 // Fixed Data Length Mode - 4 Bytes #define RWB_READ 0x00 #define RWB_WRITE 0x04 // 3.1 Common Register Block - CRB // Mode - MR #define MR 0x0000 // Gateway Address - GAR #define GAR(N) (N+1) // Subnet Mask - SUBR #define SUBR(N) (N+0x0005) // Source Hardware Address - SHAR #define SHAR(N) (0x0009+N) // Source IP Address - SIPR #define SIPR(N) (N+0x000F) // Interrupt Low Level Timer - INTLEVEL #define INTLEVEL0 0x0013 #define INTLEVEL1 0x0014 // Interrupt - IR #define IR 0x0015 // Interrupt Mask - IMR #define IMR 0x0016 // Socket Interrupt #define SIR 0x0017 // Socket Interrupt Mask - SIMR #define SIMR 0x0018 // Retry Time - RTR #define RTR0 0x0019 #define RTR1 0x001A // Retry Count - RCR #define RCR 0x001B // PPP LCP Request Timer - PTIMER #define PTIMER 0x001C // PPP LCP Magic number - PMAGIC #define PMAGIC 0x001D // PPP Destination MAC Address - PHAR #define PHAR0 0x001E #define PHAR1 0x001F #define PHAR2 0x0020 #define PHAR3 0x0021 #define PHAR4 0x0022 #define PHAR5 0x0023 // PPP Session Identification - PSID #define PSID0 0x0024 #define PSID1 0x0025 // PPP Maximum Segment Size - PMRU #define PMRU0 0x0026 #define PMRU1 0x0027 // Unreachable IP address - UIPR #define UIPR0 0x0028 #define UIPR1 0x0029 #define UIPR2 0x002A #define UIPR3 0x002B // Unreachable Port - UPORT #define UPORT0 0x002C #define UPORT1 0x002D // PHY Configuration - PHYCFGR #define PHYCFGR 0x002E // Chip Version - VERSIONR #define VERSIONR 0x0039 // 3.2 Socket Register Block - SRB #define Sn_MR 0x0000 // Socket n Mode #define Sn_CR 0x0001 // Socket n Command #define Sn_IR 0x0002 // Socket n Interrupt #define Sn_SR 0x0003 // Socket n Status #define Sn_PORT(N) (N+0x0004) // Socket n Source Port #define Sn_DHAR0 0x0006 // Destination MAC #define Sn_DHAR1 0x0007 #define Sn_DHAR2 0x0008 #define Sn_DHAR3 0x0009 #define Sn_DHAR4 0x000A #define Sn_DHAR5 0x000B #define Sn_DIPR(N) (N+0x000C) // Destination IP #define Sn_DPORT(N) (N+0x0010) // Destination IP #define Sn_MSSR0 0x0012 // Max Segment Size #define Sn_MSSR1 0x0013 #define Sn_TOS 0x0015 // IP TOS #define Sn_TTL 0x0016 // IP TTL #define Sn_RXBUF_SIZE 0x001E // RX Buffer Size #define Sn_TXBUF_SIZE 0x001F // TX Buffer Size #define Sn_TX_FSR0 0x0020 // TX Free Size #define Sn_TX_FSR1 0x0021 #define Sn_TX_RD0 0x0022 // TX Read Pointer #define Sn_TX_RD1 0x0023 #define Sn_TX_WR0 0x0024 // TX Write Pointer #define Sn_TX_WR1 0x0025 #define Sn_RX_RSR0 0x0026 // RX Received Size #define Sn_RX_RSR1 0x0027 #define Sn_RX_RD0 0x0028 // RX Read Pointer #define Sn_RX_RD1 0x0029 #define Sn_RX_WR0 0x002A // RX Write Pointer #define Sn_RX_WR1 0x002B #define Sn_IMR 0x002C // Interrupt Mask #define Sn_FRAG0 0x002D // Fragment Offset #define Sn_FRAG1 0x002E #define Sn_KPALVTR 0x002F // Keep Alive Timer // 4.1 Common Register #define CR_RST 0x40 // Reset #define CR_WOL 0x20 // Wake on LAN #define CR_PB 0x10 // Ping Block #define CR_PPPoE 0x08 // PPPoE Mode #define CR_FARP 0x02 // Force ARP // 4.2 IR Register Bits #define IR_CONFLICT 0x80 #define IR_UNREACH 0x40 #define IR_PPPoE 0x20 #define IR_MP 0x10 // 4.3 IMR Bits #define IM_IR7 0x80 #define IM_IR6 0x40 #define IM_IR5 0x20 #define IM_IR4 0x10 // 4.4 PHYCFGR Bits #define PHYCFGR_RST (1 << 7) #define PHYCFGR_OPMD (1 << 6) #define PHYCFGR_OPMDC_ALLA (7 << 3) #define PHYCFGR_OPMDC_PDOWN (6 << 3) #define PHYCFGR_OPMDC_100FA (4 << 3) #define PHYCFGR_OPMDC_100F (3 << 3) #define PHYCFGR_OPMDC_100H (2 << 3) #define PHYCFGR_OPMDC_10F (1 << 3) #define PHYCFGR_OPMDC_10H (0 << 3) #define PHYCFGR_DPX_FULL (1 << 2) #define PHYCFGR_DPX_HALF (0 << 2) #define PHYCFGR_SPD_100 (1 << 1) #define PHYCFGR_SPD_10 (0 << 1) #define PHYCFGR_LNK_ON (1 << 0) #define PHYCFGR_LNK_OFF (0 << 0) // 5.1 Sn_MR Bits #define Sn_MR_MULTI 0x80 #define Sn_MR_BCASTB 0x40 #define Sn_MR_ND 0x20 #define Sn_MR_UCASTB 0x10 #define Sn_MR_MACRAW 0x04 #define Sn_MR_UDP 0x02 #define Sn_MR_TCP 0x01 #define Sn_MR_CLOSE 0x00 // 5.2 Sn_CR Commands #define Sn_CR_OPEN 0x01 #define Sn_CR_LISTEN 0x02 #define Sn_CR_CONNECT 0x04 #define Sn_CR_DISCON 0x08 #define Sn_CR_CLOSE 0x10 #define Sn_CR_SEND 0x20 #define Sn_CR_SEND_MAC 0x21 #define Sn_CR_SEND_KEEP 0x22 #define Sn_CR_RECV 0x40 // 5.3 Sn_IR Bits #define Sn_IR_SENDOK 0x10 #define Sn_IR_TIMEOUT 0x08 #define Sn_IR_RECV 0x04 #define Sn_IR_DISCON 0x02 #define Sn_IR_CON 0x01 // 5.4 Sn_SR Values #define SOCK_CLOSED 0x00 #define SOCK_INIT 0x13 #define SOCK_LISTEN 0x14 #define SOCK_SYNSENT 0x15 #define SOCK_SYNRECV 0x16 #define SOCK_ESTABLISHED 0x17 #define SOCK_FIN_WAIT 0x18 #define SOCK_CLOSING 0x1A #define SOCK_TIME_WAIT 0x1B #define SOCK_CLOSE_WAIT 0x1C #define SOCK_LAST_ACK 0x1D #define SOCK_UDP 0x22 #define SOCK_MACRAW 0x42 #endif // W5500_H