library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity tb_mmcm_vs_pll is end tb_mmcm_vs_pll; architecture testbench of tb_mmcm_vs_pll is constant CLK_PERIOD : time := 4 ns; constant CLKFBOUT_PHASE : real := 60.0; signal reset : std_logic := '1'; signal clkin : std_logic := '0'; signal clkfb_pll : std_logic; signal clkout0_pll : std_logic; signal locked_pll : std_logic; signal clkfb_mmcm : std_logic; signal clkout0_mmcm : std_logic; signal locked_mmcm : std_logic; begin clkin <= not clkin after CLK_PERIOD / 2; main : process begin wait for CLK_PERIOD * 20; reset <= '0'; wait; end process; uut_pll : PLLE4_ADV generic map ( CLKFBOUT_MULT => 6, -- Multiply value for all CLKOUT CLKFBOUT_PHASE => CLKFBOUT_PHASE, -- Phase offset in degrees of CLKFB CLKIN_PERIOD => 4.0, -- Input clock period in ns to ps resolution (i.e., 33.333 is 30 MHz). CLKOUT0_DIVIDE => 6, -- Divide amount for CLKOUT0 CLKOUT0_PHASE => 0.0, -- Phase offset for CLKOUT0 DIVCLK_DIVIDE => 1 -- Master division value ) port map ( CLKFBOUT => clkfb_pll, -- 1-bit output: Feedback clock CLKOUT0 => clkout0_pll, -- 1-bit output: CLKOUT0 CLKOUT0B => open, -- 1-bit output: Inverted CLKOUT0 CLKOUT1 => open, -- 1-bit output: CLKOUT1 CLKOUT1B => open, -- 1-bit output: Inverted CLKOUT1 CLKOUTPHY => open, -- 1-bit output: Bitslice clock DO => open, -- 16-bit output: DRP data output DRDY => open, -- 1-bit output: DRP ready LOCKED => locked_pll, -- 1-bit output: LOCK CLKFBIN => clkfb_pll, -- 1-bit input: Feedback clock CLKIN => clkin, -- 1-bit input: Primary clock CLKOUTPHYEN => '0', -- 1-bit input: CLKOUTPHY enable DADDR => (others => '0'), -- 7-bit input: DRP address DCLK => '0', -- 1-bit input: DRP clock DWE => '0', -- 1-bit input: DRP write enable DEN => '0', -- 1-bit input: DRP enable DI => (others => '0'), -- 16-bit input: DRP data input PWRDWN => '0', -- 1-bit input: Power-down RST => reset -- 1-bit input: Reset ); uut_mmcm : MMCME4_ADV generic map ( CLKFBOUT_MULT_F => 6.0, -- Multiply value for all CLKOUT CLKFBOUT_PHASE => CLKFBOUT_PHASE, -- Phase offset in degrees of CLKFB CLKIN1_PERIOD => 4.0, -- Input clock period in ns to ps resolution (i.e., 33.333 is 30 MHz). CLKOUT0_DIVIDE_F => 6.0, -- Divide amount for CLKOUT0 CLKOUT0_PHASE => 0.0, -- Phase offset for CLKOUT0 DIVCLK_DIVIDE => 1 -- Master division value ) port map ( CDDCDONE => open, -- 1-bit output: Clock dynamic divide done CLKFBOUT => clkfb_mmcm, -- 1-bit output: Feedback clock CLKFBOUTB => open, -- 1-bit output: Inverted CLKFBOUT CLKFBSTOPPED => open, -- 1-bit output: Feedback clock stopped CLKINSTOPPED => open, -- 1-bit output: Input clock stopped CLKOUT0 => clkout0_mmcm, -- 1-bit output: CLKOUT0 CLKOUT0B => open, -- 1-bit output: Inverted CLKOUT0 CLKOUT1 => open, -- 1-bit output: CLKOUT1 CLKOUT1B => open, -- 1-bit output: Inverted CLKOUT1 CLKOUT2 => open, -- 1-bit output: CLKOUT2 CLKOUT2B => open, -- 1-bit output: Inverted CLKOUT2 CLKOUT3 => open, -- 1-bit output: CLKOUT3 CLKOUT3B => open, -- 1-bit output: Inverted CLKOUT3 CLKOUT4 => open, -- 1-bit output: CLKOUT4 CLKOUT5 => open, -- 1-bit output: CLKOUT5 CLKOUT6 => open, -- 1-bit output: CLKOUT6 DO => open, -- 16-bit output: DRP data output DRDY => open, -- 1-bit output: DRP ready LOCKED => locked_mmcm, -- 1-bit output: LOCK PSDONE => open, -- 1-bit output: Phase shift done CDDCREQ => '0', -- 1-bit input: Request to dynamic divide clock CLKFBIN => clkfb_mmcm, -- 1-bit input: Feedback clock CLKIN1 => clkin, -- 1-bit input: Primary clock CLKIN2 => '0', -- 1-bit input: Secondary clock CLKINSEL => '1', -- 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2 DADDR => (others => '0'), -- 7-bit input: DRP address DCLK => '0', -- 1-bit input: DRP clock DEN => '0', -- 1-bit input: DRP enable DI => (others => '0'), -- 16-bit input: DRP data input DWE => '0', -- 1-bit input: DRP write enable PSCLK => '0', -- 1-bit input: Phase shift clock PSEN => '0', -- 1-bit input: Phase shift enable PSINCDEC => '0', -- 1-bit input: Phase shift increment/decrement PWRDWN => '0', -- 1-bit input: Power-down RST => reset -- 1-bit input: Reset ); end testbench;