LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY tb_spiel_vhd IS END tb_spiel_vhd; ARCHITECTURE behavior OF tb_spiel_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT SPIEL PORT( TAKT : IN std_logic; RESET : IN std_logic; BUTTON_1 : IN std_logic; BUTTON_2 : IN std_logic; ZIEL : IN std_logic_vector(4 downto 1); SIEGERLED : OUT std_logic_vector(8 downto 1); MUSTERLED : OUT std_logic_vector(4 downto 1); ZEITBALKENLED : OUT std_logic_vector(16 downto 1); STATUS : OUT std_logic_vector(4 downto 1) ); END COMPONENT; --Inputs SIGNAL TAKT : std_logic := '0'; SIGNAL RESET : std_logic := '0'; SIGNAL BUTTON_1 : std_logic := '1'; SIGNAL BUTTON_2 : std_logic := '1'; SIGNAL ZIEL : std_logic_vector(4 downto 1) := (others=>'0'); --Outputs SIGNAL SIEGERLED : std_logic_vector(8 downto 1); SIGNAL MUSTERLED : std_logic_vector(4 downto 1); SIGNAL ZEITBALKENLED : std_logic_vector(16 downto 1); SIGNAL STATUS : std_logic_vector(4 downto 1); BEGIN -- Instantiate the Unit Under Test (UUT) uut: SPIEL PORT MAP( TAKT => TAKT, RESET => RESET, BUTTON_1 => BUTTON_1, BUTTON_2 => BUTTON_2, ZIEL => ZIEL, SIEGERLED => SIEGERLED, MUSTERLED => MUSTERLED, ZEITBALKENLED => ZEITBALKENLED, STATUS => STATUS ); TAKT <= not TAKT after 10 ns; tb : PROCESS BEGIN reset <= '1'; wait for 100 ns; reset <= '0'; wait for 100 ns; reset <= '1'; wait; -- will wait forever END PROCESS; END;