// ATtiny824 #include #include uint8_t i; // SW counter uint8_t j; // SW counter ISR(RTC_PIT_vect) { RTC.PITINTFLAGS = RTC_PI_bm; // clear PIT flag } int main(void) { _PROTECTED_WRITE(CLKCTRL.MCLKCTRLB, CLKCTRL_PDIV_10X_gc | CLKCTRL_PEN_bm); // 2MHz main clock PORTA.PIN1CTRL = PORT_ISC_INPUT_DISABLE_gc; // disable PA1 digital input buffer PORTA.PIN2CTRL = PORT_ISC_INPUT_DISABLE_gc; // disable PA2 digital input buffer PORTA.PIN3CTRL = PORT_ISC_INPUT_DISABLE_gc; // disable PA3 digital input buffer PORTA.PIN4CTRL = PORT_ISC_INPUT_DISABLE_gc; // disable PA4 digital input buffer PORTA.PIN5CTRL = PORT_ISC_INPUT_DISABLE_gc; // disable PA5 digital input buffer PORTA.PIN6CTRL = PORT_ISC_INPUT_DISABLE_gc; // disable PA6 digital input buffer PORTA.PIN7CTRL = PORT_ISC_INPUT_DISABLE_gc; // disable PA7 digital input buffer PORTB.PIN0CTRL = PORT_ISC_INPUT_DISABLE_gc; // disable PB0 digital input buffer PORTB.PIN1CTRL = PORT_ISC_INPUT_DISABLE_gc; // disable PB1 digital input buffer PORTB.PIN2CTRL = PORT_ISC_INPUT_DISABLE_gc; // disable PB2 digital input buffer PORTB.PIN3CTRL = PORT_ISC_INPUT_DISABLE_gc; // disable PB3 digital input buffer RTC.CLKSEL = RTC_CLKSEL_INT1K_gc; // 1024 Hz from OSCULP32K while(RTC.PITSTATUS > 0) {} // wait for RTC.PITCTRLA synchronization RTC.PITINTCTRL = RTC_PI_bm; // enable periodic interrupt RTC.PITCTRLA = RTC_PERIOD_CYC8192_gc | RTC_PITEN_bm; // 8s, enable PIT TCB0.CCMP = 0x9C3F; // 40ms @ 1MHz TCB0 clock TCB0.CTRLA = TCB_CLKSEL_DIV2_gc | TCB_ENABLE_bm; // 1 MHz clock, enable TCB0 PORTA.DIRSET = PIN3_bm; // PA3 output (LED) SLPCTRL.CTRLA = SLPCTRL_SMODE_PDOWN_gc | SLPCTRL_SEN_bm; // POWER-DOWN sleep mode, Sleep Enable sei(); // enable interrupts while(1) { if(TCB0.INTFLAGS) { TCB0.INTFLAGS = TCB_CAPT_bm; // clear TCB0 interrupt flag i++; if(i == 4) // 160 ms { PORTA.OUTSET = PIN3_bm; // PA3 on } else if(i == 5) // 200 ms { PORTA.OUTCLR = PIN3_bm; // PA3 off i = 0; j++; if(j == 6) // 6 pulses { j = 0; TCB0.CNT = 0; // clear TCB0 __asm__ __volatile__ ("sleep" "\n\t" :: ); } } } } }