library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity tb is
--  Port ( );
end tb;

architecture Behavioral of tb is

subtype slv16           is std_logic_vector(15 downto 0);
type slv16_array        is array (natural range <>) of slv16;

signal count : unsigned(15 downto 0) := (others => '0');
signal clk_int : std_logic := '0';
constant c_clk_del : natural := 2;
signal time_stamp : slv16_array(c_clk_del downto 0) := (others => (others => '0'));
signal time_stamp2 : slv16_array(c_clk_del downto 0) := (others => (others => '0'));

signal time_stamp_final : std_logic_vector(15 downto 0);
signal time_stamp_final2 : std_logic_vector(15 downto 0);



begin

process
    begin
        clk_int <= '0';
        wait for 5 ns;
        clk_int <= '1';
        wait for 5 ns;
end process;


process(clk_int)
begin
    if rising_edge(clk_int) then
        count <= count + 1;
    end if;
end process;


-- Beispeil1:
time_stamp(0) <= std_logic_vector(count);
   
clk_del: process(clk_int)
begin
  if rising_edge(clk_int) then
    if c_clk_del > 0 then
      for i in 1 to c_clk_del loop
        time_stamp(i) <=  time_stamp(i-1);
      end loop;
    end if;
  end if;
end process clk_del; 

time_stamp_final <= time_stamp(c_clk_del);


-- Beispiel2:
time_stamp2(0) <= std_logic_vector(count);

clk_del2 : FOR i in 1 TO c_clk_del+1 GENERATE
begin
 
del_reg: process(clk_int)
begin
  if rising_edge(clk_int) then
        time_stamp2(i) <=  time_stamp2(i-1);
  end if;
end process del_reg; 

end;
END GENERATE clk_del2; 

time_stamp_final2 <= time_stamp2(c_clk_del);



end Behavioral;