library ieee;
use ieee.std_logic_1164.all;

entity x_und_u is
end entity x_und_u;


architecture testbench of x_und_u is

    signal clk   : std_ulogic := '0';

    signal sig_u : std_ulogic;
    signal sig_x : std_ulogic_vector( 2 downto 0);

begin

    clk <= not clk after 1 us;

    process( clk)
    begin
        if rising_edge( clk) then
            sig_u   <= '0';
            sig_x   <= ( others => '0');
        end if;
    end process;

end architecture testbench;