module arm_test(
                input  wire xosc,               /* oscillator, system clock */
                input  wire ext_reset_n,        /* reset, active low */
                output wire [1:0] gpio,         /* GPIO */
                output wire test1,              /* testpin */
                output wire test2,              /* testpin */
                output wire cpuclkout,          /* CPU clock output */
                output wire cpureset            /* synchroneous CPU reset, active high */
                ) ;

parameter CLKDIV_WIDTH = 8 ;    /* width of CPU clock prescaler */
parameter DLYDIV_WIDTH = 4 ;    /* width of reset delay clock prescaler */
parameter COUNT_LOW  = 'd12 ;   /* clock count-1 for low phase */
parameter COUNT_HIGH = 'd13 ;   /* clock count-1 for high phase */

        reg     [CLKDIV_WIDTH-1:0] clkdiv_cpu ;
        reg     [DLYDIV_WIDTH-1:0] reset_delay ; /* CPU clock count during active reset */
        reg     cpuclk ;
        reg     cpuresetn_sync ;
        wire    [15:0] gpioout ;
        wire    [15:0] gpioouten ;
        wire    [15:0] gpioin ;

assign cpuclkout = cpuclk ;
assign cpureset = ~cpuresetn_sync ;
assign test1 = ext_reset_n ;
assign test2 = xosc ;
assign gpioin[15:0] = 16'h0000 ;
assign gpio[1:0] = gpioout[1:0] ;

/*
╭─────────────────────────────────────────────────────────────────────────────────────────────────╮
│       xosc clock domain                                                                         │
╰─────────────────────────────────────────────────────────────────────────────────────────────────╯
*/
always @(posedge xosc or negedge ext_reset_n)
begin
   if (~ext_reset_n)
   begin
      clkdiv_cpu <= 0 ;
      reset_delay <= 0 ;
      cpuclk <= 0 ;
      cpuresetn_sync <= 0 ;
   end
   else
   begin
/* generate 1 MHz CPU clock */
      if (cpuclk & (clkdiv_cpu == COUNT_HIGH)) /* clock count-1 for high phase */
      begin
         clkdiv_cpu <= 0 ;
         cpuclk <= 0 ;
         if (reset_delay <= 'd10)
         begin
            reset_delay <= reset_delay + {{DLYDIV_WIDTH-1{1'b0}},1'b1} ;
         end
      end
      else
      if (~cpuclk & (clkdiv_cpu == COUNT_LOW)) /* clock count-1 for low phase */
      begin
         clkdiv_cpu <= 0 ;
         cpuclk <= 1 ;
         if (reset_delay == 'd10)
         begin
            cpuresetn_sync <= 1 ;
         end
      end
      else
      begin
         clkdiv_cpu <= clkdiv_cpu + {{CLKDIV_WIDTH-1{1'b0}},1'b1} ;
      end
   end
end

/*
╭─────────────────────────────────────────────────────────────────────────────────────────────────╮
│       ARM CPU-core instantiation                                                                │
╰─────────────────────────────────────────────────────────────────────────────────────────────────╯
*/
Gowin_EMPU_Top cpu_core(
        .sys_clk(cpuclk),       //input sys_clk
        .gpioin(gpioin),        //input [15:0] gpioin
        .gpioout(gpioout),      //output [15:0] gpioout
        .gpioouten(gpioouten),  //output [15:0] gpioouten
        .reset_n(cpuresetn_sync)       //synchronous reset_n
//        .reset_n(ext_reset_n)       //input reset_n
);

endmodule