Date start: 2024-06-20
Date end: 2025-07-24 Operator: FBä

Overview

DUT

No.: 1
BMM version: 0.1.0

Power supply

Switching regulator U3 (MAX17552AUB)

Start-up

Tested between 20V and 60V (still with 2x1mH inductor).

Switching waveforms

Several improvements were made:

• Added snubber to secondary side to dampen resonance and dissipate energy from leakage inductance.
• Chose lower inductance dual inductor (SRF0703-221M) for higher SRF and less leakage inductance.
• Added more primary output capacitance because of the smaller inductor.
• Reduced f_sw for higher efficiency and less effect of leakage inductance on secondary side regulation.
• PFM mode for higher efficiency in majority of situations.

Result:

• Switching frequency as expected (210kHz).
• Switching node waveform is quite clean.

Frequency and mode test

It is “hardest” to supply the isolated switch supply 10Vsw in with low primary output load and in PFM mode. The latter disables negative pri. inductor current for U3 (MAX17552AUB) which also supplies the isolated output. The isolated output must remain well below 20V under all circumstances.

Test configuration:

• Updated parts
  • L3: 2x220µH, C53: 4.4µF (3µF eff.)
  • R_Snub: 1kΩ, C_Snub: 100pF
• Load
  • Primary +10V
    • idle (core: standby (35μA_(typ)), isoSPI: ready (5.1mA_(typ)))
    • idle + 30mA (167Ω/5V)
  • Secondary 10Vsw
    • idle with PG (ca. 1.5mA)
    • idle+8.5mA (using 1.3kΩ/11V)
• f_sw: 210kHz (R191: 200kΩ)
• Modes: Both forced-PWM (safe bet) and PFM

Result: +10V ripple is about 50mVpp at 10mA load on 10Vsw in PWM mode. PFM is especially effective to reduce losses at higher input voltages and light load. As 10Vsw decreases in PFM mode, it might not generate exactly 10V at 10Vsw at high load and (unusally!) low input voltages. Also mind, that 10mA load is more than twice the expected load on 10Vsw. PFM creates about 100mV ripple on +10V when skipping pulses, which is acceptable because of the linear regulator downstream.

Temperature rise

Surprisingly there is greater power loss at a special operating point in PFM than in PWM mode at very low input voltage and maximum load. Increase in temperature is below 20°C (linear post-regulator).

Linear regulator U2 (TPS7A2450DBVR)

Linear regulator puts out stable 5V as expected.

Switch

Power

Start-up

Very similar behaviour from 20..60V supply.

Idle current

This includes one half of the gate date driver U16 (primary side unpowered) and the power good circuitry.

Power-good signal

These levels include various modifications from version 0.1.0 and do not exactly reflect 0.1.2 status.

Measurements at a room temperature of 24..27 °C.

Control

Blocking Sw_En if Oc is low:

Turn-on/turn-off time

Turn-on with 8x IPT012N08N5 assembled, 54V, 100Ω resistive load: ≪5µs for V_GS of >10V

Turn-off with 8x IPT012N08N5 assembled, 54V, 100Ω resistive load: ≪5µs for V_GS of <2V

Isolated gate driver propagation time

Examplary image:

Measurements at a room temperature of 21..22 °C.

AFE

Core states

State “extended balancing” is not used.

isoSPI-port states

V_Ref2Buf

• Output is stable
• Offset to V_Ref2: ≈4µV

Cell balancing

This was tested using fixed 3.7V voltage for all channels, balancing all channels at once, no cooling at all, just laying on the bench at root temperature. Balancing was deactivated in software once a temperature sensor exceeded 80°C.

All channels are visibly active. Note: When all channels are balancing (can’t happen in reality) the hottest spot is the center of the balancing resistors - not the temperature sensors (darker spots above and below).

The balancing current is about 205mA at 3.7V cell voltage. In the follwing pictures only cells 1, 8, 9 and 16 are balanced as they are the most distant from the sensors. It must be verified, hat all all parts’ operating temperatures are within limits if only a few cells (1, 8, 9 and 16) far are actively balancing:

Sensor temperatures were 44.8/45.3°C. There is a substantial temperature gradient which is not. In case more channels are activated, the peak temperature will increase but the temperature difference can be expected to decrease. This way the balancing over-temperature protection using the current sensor positioning is believed to be sufficient.

I2C

800kHZ isoSPI = 400kHz I2C

Auxiliary output

Activating the auxiliary output by bridging J17 works as expected. The level of ManEn drops while the supplying power supply limits the current in these measurements.

On a longer timescale, the firmware activates the aux. output using the logic signal after starting up for three seconds:

The rugged switching FET is not only required for its avalanche behaviour, but gelesenalso to be able to “survive” a slow turn-off of the load. This can happen it ManEn is let go before the AuxEn is activated and the grate voltage slowly drains via R199.

Fan output

This circuitry was already tested on CVTCS-C initial operation.

Start-up with resistive load:

Start-up into high mode with 2.8W fan as load:

Fan shutdown:

This test was conducted still without diodes protecting the IO-expander in case the Bat_-fused is blown. Therefore logic levels are recorded as 5V instead of 4.4V or similar.

Main fuse diagnosis

Diagnosis function works as expected.

Switch voltage measurement diagnosis

Results:

• Works as expected (V_Bat = 51.2V)
  • 500Ω output load: Computed voltage difference is 2.93V
  • Open output: Vsw difference 2.98V
• Increase of 150mV on Vsw input signal during diagnosis.

Pre-charge

EMC

Notes:

• Overshoot ca. 6V (at Vbat of 51.2V) after FET-turn-off
• Snubber on FET/Free wheeling diode possible but not required - only tiny ringing visible.

Function: Low capacitance

Load: 2x GRM32EC72A106KE05 (nom. 20µ/100V, 4.9µV/51.5V) + 1kΩ

Expected ringing after actual pre-charge is resonance of inductor and load capacitance.

Function: High capacitance

Notes:

• Even though the output current is relatively constant vs. output voltage, the (module) I_Bat current measurement only measures the averaged current of the switch. This creates the illusion that the current would rise together with V_Mod, but actually mainly the switch’s duty cycle increases over time.
• A capacity of 25mF with 31mA constant current dummy load is charged within 5s. If the current I_calc is calculated from the change in capacitor voltage (i(t) = C * dV/dt), this actually shows the highest current at the start of the pre-charge process. This is due to the, compared to the situation at the end of the process, steeper rise of current a constant propagation delay of the circuit.

Modification 2: Short Q31-3 to GND (shorts out Q31B)

Removal of M3 ensures better (ensured) start-up behaviour and might delete the source of the double pulses… (?) at the cost of a higher swithcing frequency - especially into short circuits (watch temperature!).

Results:

• Double pulse still occurs, but are pushed to the very end of the pre-charge process. Their effect is reduced, too. The re-turn on happens much faster and the inductor is not discharged fully as without modifications
• While this is not a “perfect” behaviour it is still much improved and considered sufficient.

Pre-charge into short circuit

Setup:

• PCB flat on desk
• Room temperature (25°C)
• V_Bat: 51.2V
• Using modification 2

Results:

• Switch current: 485mA(pk) (expected: 540mA(pk))
• Frequency: 128kHz (expected: 112kHz)
• Case temperatures are so low that computation of T_J is not necessary.
• Safe to operate in continuous short-circuit.

Temperature rise (T_C at aforementioned room temperature):

I_Bat pulse on switch turn-on

Setup:

• Protections against connecting the load if warnings or errors are set are commented out in code.
• V_Bat is represented by a 55mF electrolytic capacitor bank in parallel to a current limited lab. power supply.
• DC-link capacitance is represented by a 25mF electrolytic capacitor bank, which is pre-charged before enabling the main switch.
• Two indicators are used to determine wether the main switch will be enabled (“closed”):
  • V_Sw < threshold (e.g. 1V) protects against switching into short, excessive capacitance or another battery with differing voltage.
  • ΔV_Sw = V_Sw[n-1] V_Sw[n-1] - V_Sw[n] < threshold (e.g. .1V) makes sure the maximum achievable voltage (at given external load) is reached
  • The cycle time currently is 250ms.
• Comparator (U15) short circuit detection threshold: I_SC = 57mV/R_Shunt ≈ 190A

Dependency on V_Bat/Wiring

Setup 1:

• R_Shunt = 300µΩ
• V_Sw(max) = 1V
• ΔV_Sw = 0.1V
• Wiring
  • V_Bat cap.: ca. 10cm 1mm² wire to J18/J19
  • DC-link cap.: ca. 6cm 0.5mm² wire to J21/J22

Setup 2:

• Wiring
  • V_Bat cap. neg.: ca. 8cm 1mm² wire to J18
  • V_Bat cap. pos.: ca. 8cm 1mm² wire to pos. term. of DC-link cap. (skipping fuse connection)
  • DC-link cap. bank neg. ca. 3cm 0.5mm² wire to J21

Result:

• Improved wiring has reduced inductance (shorter and higher pulse) and resistance (high pulse)
• By skipping the current path via the fuse, this should really represent the worst-case achievable with correct (and heavier) wiring.
• The peak current is always less than I_SC.

Dependency on V_Sw/ΔV_Sw

Notes:

• Using Setup 2 with V_Bat = 51.2V.
• Main contributors to V_Sw(min) are V_F of D12 (0.5V/200mA/25°C) and R_DC of L3 (1.35Ω = 0.27V/200mA)
• Previous tests showed the voltages required for V_Sw(max) at 25°C to finish pre-charging at given external load current:
  • 31mA load: 490mV
  • 200mA load: 850mV

Overview table of tested settings:

Result:

• As the sampling interval is quite long compared to changes in voltage towards the end of the pre-charge using “constant” current, the influence of the actual sampling time is big.
• There is little room to optimize V_Sw(max) below previously tested values
• Lowering ΔV_Sw makes susceptible to (already existing) load changes and/or noise.
• Using the last two tested settings, the peak current is always less than I_SC.
• 440Apk with a rise time of 20µs and pulse duration of 35µs lead to over-current turn-off (first implicit short circuit test).

Current measurement

Flip-flop status/reset

Simulated length of the Oc_RstPls was 75ns, measurement is 98ns. This is sufficiently short to prevent harm due to a stuck reset signal.

Over-current diagnosis

This mainly tests the short-circuit comparator as well als the _OCset to _OC-signal path.

Results:

• OC-comparator propagation delay: 38ns (100mV overdrive; room temperature)
• OC-flip flop propagation delay: 5.2ns

On a longer time span the charge-time for the coupling capacitor C109 is visible (ca. 1ms). Mind that the discharge time, via R275, will be much slower. The latter limits the max. cadence of over-current diagnoses couldn’t be executed (simulated about 50ms).

Over-current detection levels

Idle comparator voltages:

The actual functionality of the discharge/charge-limits cannot be confirmed in hardware - a controllable current source is missing at this point.

Short-circuit protection

Actual test not conducted. Operator did not have the courage to dump 99J from capacitor bank into 210mΩ cable, which was prepared relying on current set of physical protections available.

The pre-charge test, enabling the main switch with voltage differential confirms that the over-current circuit itself is functional (even tough the rise time without any additional wiring inductance was short).

Changes

Version 0.1.0 to 0.1.2 (retroactive)

• Switch power-good
  • Add 33k in parallel to R247 and R248 (results in 17.5kΩ).
  • Replace R249 with 100kΩ.
  • Remove R252.
  • Cut R250’s connection to R245 in layout; connect to U14 pin 1 (parallel to optocoupler LED).
  • Connect R245’s “lower pin” to U13 pin 1 (TLV431 reference input)

TODO (other than DUT1):

• I2C
  • Lower R208/R209 to 2.2kΩ (I2C pullups for 400kHz), or add 4.3kΩ in parallel
• Short R132 or replace by 0Ω resistor
• Add 15pF in parallel to R128/R192 (TP122 to U3-5)
• Replace L1 with 220µH
• Fit new snubber
• Add another 2.2µF on top of C53
• Short R132 or replace by 0Ω resistor
• Pre-charge
  • Short Q31-3 to GND (instead of replacing Q31A/B (dual FET) with BSS123 (single FET))

Version 0.1.2

• Switch power-good
  • Replace R247 and R248 with 16kΩ.
  • Replaced R249 with 100kΩ.
  • Removed R252.
  • Connect R250 from U14 pin 1 to GND1.
  • Connect R245 from Sw_{Pg}/TP199 to U13 pin 1.
• isoSPI interface
  • Replace R183, R184 and R310 with 1.3kΩ to increase signal level.
• I2C
  • Lower R208/R209 to 2.2kΩ (pullups for 400kHz)
• Supply
  • Remove R132 (use forced PWM mode)
  • Replace R191 with 200kΩ (f_sw: 210kHz)
  • Add 15pF in parallel to R128/R192 (TP122 to U3-5)
  • Replace L1 with 220µH
  • Replace C53 with 4.7µF
  • Secondary side snubber across L4-1/4 (R_Snub: 1kΩ, C_Snub: 100pF)
• Fan output
  • Add missing testpoint to Fan_{+} (TP14).
  • Add diodes D9/D7 (protect controlling IO expander if Bat_-fused fuse blows).
• Pre-charge
  • Tie pins 4 and 6 of U20 together.
  • Replace Q31A/B (dual FET) with BSS123 (single FET), connect R299 to GND
  • Increase R308 to 220k (Ipk: 475mA)

Addendum

Power supply

Frequency and mode test

• Updated parts
  • L3: 2x220µH, C53: 4.4µF (3µF eff.)
  • R_Snub: 1kΩ, C_Snub: 100pF
• Load
  • Primary +10V: core: standby (35μA_(typ)), isoSPI: ready
  • Secondary 10Vsw: idle with PG (ca. 1.5mA), idle+8.5mA (using 1.3kΩ/11V)
• f_sw
  • 420kHz (R191: 100kΩ)
  • 250kHz (R191: 165kΩ)
• Mode: Both forced-PWM (safe bet) and PFM

Result: 250kHz forced-PWM switching frequency reduces the power consumption by up to 22%/20% without and with additional load respectively, compared to 60V/400kHz. +10V ripple is about 50mVpp at 10mA load on 10Vsw. PFM is especially effective to reduce losses at higher input voltages and little load.

Secondary snubber testing, L1 = SRF0703-221M (2x220µH)

Current situation (2024-06-26)

• Much better behaviour, even without snubber, with 220µH inductor (much less leakage inductance).
• Further improved switching with doubled C53 capacitance.
• Remaining ringing without snubber ca. 10.5MHz.

Secondary snubber testing, L1 = SRF0703-102M (2x1mH)

Current situation (2024-06-23)

• Secondary waveform ringing (needs snubber across rectifier diode)
• Audible noise starts at 25V at 10VSw (34V input voltage). This might be induced by digital isolator U16 (UCC5304DWV) breaking down?
• Secondary oscillation peak-voltage is so high, that it charges the barely loaded secondary to a much higher level than expected (23V at 30V input)
• The oscillation (4.5MHz) is connected to the inductor leakage inductance. This allows the secondary output voltage to rise over the primary output voltage: Experiment: Just laying a tiny piece of steel (on top of the inductor) reduces the oscillation and hence the 10Vsw output voltage by about 10%. The resonance additionally seems to be excited by the short on-pulses of the switching regulator.
  Using simulation and judging by secondary output voltage at given load and primary input voltage, the secondary’s parallel capacitance may be ca. 100pF/4.3MHz. These values do fit the reality on the bench quite well.
• Loading the secondary with 1kΩ, the SRF is heavily damped. When the switching node goes high, the secondary winding oscillates with the diode’s capacitance in series.

Empirical characterization of layout/hardware to check: how much worst-case power dissipation to expect at R_Snub with 60V input.

Notes:

• f_sw: 420 kHz, mode: forced-PWM
• Start at V_In=24V as this results in a safe Voltage on 10Vsw net without snubber.
• Ambient temperature: 24..25°C
• The number of consecutive erratic short turn-ons increases with input voltage: (currently) zero 30V, one at 40V, one at 50V, four at 55V and five at 60V.
  • Reduced with 400Ω/1410pF to one at 55V, 1..4/5 at 60V.
  • Reduced with 400Ω/2410pF to zero 60V.
  • Reduced with 300Ω/2410pF to two at 60V.
• Adding capacitance over R192 and R128 reduces erratic switching a little bit, but not much.
• The snubber dissipates more energy than the rest of the circuit altogether.

Last tries with C0G/450V capacitors, only:

This result is sufficient to continue working on a single development board while waiting for different dual inductors.

Pre-charge

Function: High capacitance

The kink in current after about 50% (exactly 3.166s, trigger 3.96s/2.4V with 25mF, 300Ω, 51.2V) of the voltage-increase could be investigated further. A transition in switching behaviour occurs, wherein the inductor is fully discharged, following a double turn-on of the switch. Around this time, the time required to charge the inductor increases strongly while its discharge time (in the free-wheeling loop) decreases evenly rapid.

• This lowers the average pre-charge current quite a bit below the desired value, but it is not critical.
• The comparator seems to be low only for such a short time, that the re-turn-on delay is not met.
• The switching behaviour normalises at >95% of the pre-charge process. This can be observed by the final measured current peak right before the end of the process.

Simulation shows, that for for a stable operation, without double pulse after >50% pre-charge process, it is important that the time constant R298 × C120 is significantly lower than R299 × C123. If comparator input+ is too low, C123 seems to charge, even though Q31B is switched off. Either this is capacitance within Q31B or U21A input current. Goal is to keep the comparator input+ >2V to seemingly avoid this.

Modification 1: Reduce R298 to 16kΩ (or mount 62kΩ in parallel), increase R299 to 33k.

Results:

• Change in switching behaviour happens 900ms later, but very similar
• When probing the pos. comparator input it confirms, that the potential is acutally stable whel Q31B is not conducting.
• Actual source of double pulses remains unclear at this point.