CVTCS-C Initial operation

Date start: 2023-12-03
Date end: 2023-12-11
Operator: FBä

DUT

No.: 1
CVTCS-C Version: 0.1.1
CVTCS-P Version: 0.1.0

Modifications

CVTCS-C

• Corrected various capacitor part-numbers (correct package 0201 → 0402)
  • ☒ C18: GRM0335C2A150JA01? → GRM1555C2A150JA01?
  • ☒ C43, C44, C47, C48, C96: GRM0335C2A101JA01? → GRM1555C2A101JA01?
• Supply
  • ☒ Corrected erroneous schematic symbol for 750315125 (T1): pin 2→3 and pin 4→5 as well as the layout implications.
  • ☒ Swap T1 pins 10/7 (connect pin 10 to pos. rectifying diode (D3) and pin 7 to neg. rectifying diode (D4))
  • ☒ Corrected footprint numbering of T2 (750313734) (no electrical change if previously mounted 180° rotated)
  • ☒ Add 6.8Ω resistor in parallel to D9/D22 to enable control of cell voltage (lowers voltage difference between GNDA/Bat- without being connected BMS on J15).
  • ☒ Lowered R_FB (R6) to 330kΩ to adjust max. supply output voltage ≤ 5.8V.
  • ☒ Replaced MIC5205-5.0YM5 (U8) with TPS7A2450DBVR (stable with ceramic capacitors); removed C37.
  • ☒ Added testpoint (TP117) to +5VA net
• Controller
  • ☒ Replaced V_Iso trace towards the RPi Pico by much wider zone on bottom layer.
• DACs
  • ☒ Reference bypass capacitors (C2, C3, C5, C7, C9, C11) increased from 100nF → 220nF (CGA2B3X7R1E224K050??)
  • ☒ Supply bypass capacitors (C1, C4, C6, C8, C10, C12) increased from 100n → 1µF (GCM188R71C105KA64?)
• Temperature outputs
  • ☒ Added 100pF in parallel to existing compensation (against potentially very low capacitive load, 1..10nF).
• Current outputs
  • ☒ Added 470pF in parallel to existing compensation (against oscillation with low differential capacitive load, 10..100nF).
• Fan
  • ☒ Removed MCP23S08 (U13) (its SPI modes 0/3 incompatible with DAC’s/ADC’s SPI modes)
  • ☒ Connected SPI isolator (U12) pin 11 to MUX (U23) pin 1 (/CS3_Iso → ADC_IsoInSel)
  • ☒ Added digital isolator ISO6731FDWR (2/1 IOs) to control the fan output (Fan_EnIso → U14-20 (GP15), Fan_ModeIso → U14-19 (GP14), Fan_PGIso → U14-17 (GP13)); Removed R35.
  • ☒ Added ZXTR2005P5 (fan isolator logic supply from Bat+/Bat-).
  • ☒ Added gate voltage slope limiter (C37, R139, R39, D23) for Q1A (GCM188R71C105KA64D); changed R29 to 1M.
  • ☒ Added 100µF capacitor to output (reduces voltage spikes due to BLDC-switching).

CVTCS-P

• ☒ Corrected C9, C15, C16, C22, C23, C29, C30, C36, C37, C43, C44, C50, C51, C57, C58, C64, C65, C120 part-numbers (correct package 0201 → 0402): GRM0335C2A101JA01? → GRM1555C2A101JA01?
• ☒ Added 100pF in parallel to existing compensation in temperature outputs (against potentially very low capacitive load, 1..10nF).
• ☒ Correct Silkscreen “Bat+” to “Bat-” on the negative supply.

General notes

• Operation without CVTCS-P connected to check CVTCS-C power supply functions on their own.
• Testing took place at room temperature (19..22 °C).
• Most values are not tested against tolerances because this is documenting the general functionality, only.

Power supplies

• Flyback (U7, T1)
• Push-pull (U11, T2)

U7 UVLO threshold

Threshold tolerance consists of LT8304’s tolerance (-5.5%, +3%) and resistor divider tolerance (2%): -7.4% +5.1%

U7 switching node

After correcting the transformer-diode connections, the switching node shows the expected waveform.

Switching frequency while idling is about 33kHz.

U7 startup (R6 = 330kΩ)

• The 2.5V shunt regulator enters regulation gracefully when 5V8 rails reach 3.5V.
• U11’s is properly protected from over-voltage by the resistor-zener-combination R15/D5.

U8 startup (R6 = 330kΩ)

The U8 replacement TPS7A2450DBVR shows no oscillation with ceramic output capacitor. The start-up behaviour from 0V input is very good.

In case there is some residual voltage left on the input before startup, a 0.2..0.3V overshoot occurs. It is quite short (<400µs) sand well within input voltage ratings of downstream parts.

U11 startup (R6 = 330kΩ)

Note: For this measurement GNDA and GND_Iso were connected.

The operation if the RPi Pico’s buck-boost regulator can be observed after V_iso reaches 1.8V. The drop in 5V8, 6ms after start, can be attributed to the RPi Pico’s startup.
V_Iso was measured directly on the microcontroller PCB. Therefore, the noise induced by the input current is at least partly a result of the the connecting 35mm long trace.

Output voltage

Tolerances

Note: Only applicable with minimum load

Tuning flyback (U7) feedback resistor F_FB (R6)

Goal is to not exceed the 5V8 tolerances stated above.

• Input voltage: 51.2V
• Different loads are realized by resistors.
  • 30mA: Load generated by parts on PCB itself (parts onboard the CVTCS-C are powered, like the 2.5V supplies (~30mA at 6V input).)
  • 150mA: 30mA + 2 paralleled 100Ω/2W resistor (147mA/5.85V)
  • 390mA: 30mA + 3 paralleled 47Ω/2W resistors (387mA/5.6V)

Result: According to above measurement 340kΩ would be ideal. Later measurements under (almost full) load showed, that the load regulation of 5V8 - and in turn V_Iso - is better than expected/simulated. At lowest input voltages and no load, 5V8 and V_Iso were shown to exceed their tolerances by very small amount 340kΩ. This does not happen at 330kΩ. Because of this the latter is more suitable.

Load: None (no RPi Pico mounted; no CVTCS-P, R6 = 330kΩ)

Note: U15 was disconnected during measurements (defect)

Load: RPi Pico idling (no CVTCS-P, R6 = 330kΩ)

Note: U15 was disconnected during measurements (defect)

Load: RPi Pico idling + 280mA on 3V3 (no CVTCS-P, R6 = 330kΩ)

By loading the 3V3 output of the RPi Pico, all upstream supplies are affected. The load is realized using 4 paralleled 47Ω/2W resistors (280mA/3.3V)

Note: U15 was disconnected during measurements (defect)

U7 switching frequency

Measured at at 51.2 V input:

This is well below the parts’s max. 350 kHz switching frequency, up to where the frequency will be increased. Beyond that, the peak current limit will be raised to satisfy the current sourced from the output.

U7 output noise

The U7 switching frequency dominates the measured noise:

Table of noise measurements at 51.2 V input, 20 MHz bandwidth, 50 ms/div:

The virtually equal noise at all operating points makes one wonder, if the measurement setup was chosen in the best possible way. On the other hand, the actual noise performance by filtering seems quite good.

Heating

Because of the power supplies being fairly low power and the comparatively large cooling surface, no burn-in tests are conducted.

Digital isolator (U12)

Function validated (even with 5VA with some 100mVpp ripple).

GPIO-expander control (U13)

Datasheet: MCP23S08x-E/SS

Output control and reading back input state using SPI0 and /CS3 works flawlessly. Test frequency: 1 MHz.

Fan supply (U15)

Tolerances

Fan voltage is measured TP15→TP83.

Output voltage

• Fan_PG returns high via the IO expander while Fan_En is active.
• A load of 350mA/12V was achieved with two different fans connected.

Switching

All input voltages were tested. The behaviour at 51.2V input voltage is a good representation for differing voltages as well.

In general, the switching waveforms are very clean and only show minimal overshoot.

Transient, 0→6.7V output

Static, 6.7V output, unloaded

Static, 6.7V output, 200mA

At a longer timebase, it is visible that there are gaps in the switching wave form. It is possible that this is the case because of the brushless fans connected stopping current consumption once in a while completely. This leads to sharply increased output voltage, due to low output capacitance. The switcher in turn stops operating momentarily.

The output voltage current peaks can be reduced a bit by adding output capacitance.

Transient, 6.7→12.1V output

The operation is prone to false triggering over-current protection. The converter tries to increase the output voltage very quickly while the soft-start functionality of the IC timed out after reaching 6.7V starting from 0V. Of course, added output capacitance worsens the problem further.

To prevent this from happening the switch to higher output voltage must be slower to limit the current required to charge the output capacitance. Using a high value gate resistor (R_g), adding substantial capacitance (C_g) from gate to source of Q1A has been evaluated. Output capacitance was 110µF during all tests:

A fast voltage 0→6.7→12.1→6.7V output voltage control looks like follows:

To speedup the 12.1V→6.7V transition, optionally a diode (similar to 1N4148) + 4.7kΩ parallel to R_g can be used.

Independently from how slow the 6.7V to 12.1V transition becomes, with 200µF output capacitance U15 has trouble starting from time to time; with 330µF it does not start properly at all.

Static, 12.1V output, 385mA

Looked as expected - no screenshots haven been saved.

ADC

Control (U21, U23)

Prototype functions to control U21/U23 have been developed successfully (Micropython). Both parts showed proper functionality at first glance.

• Temperature readings and interpolation between -30°C and +50°C tested.
• V_TBias is very stable. As temperatures are calculated relative to V_TBias this would not be necessary, though.
• V_Bat readings are quite accurate, even without calibration
• I_Bat seems to be ca. 10% off in the around 50mA, 10% off at 100mA and spot on at 500mA and above.
• V_DropGND works and puts out very good results.

MUX leakage (U23)

There is not measurable leakage between two adjacent channels on U23 without buffering. For example, T2 (S2A) does not get lower (!) while I_Bat (S2B) increases.

High side supply

The voltage Bat_+GND shall be more then 3.3V below V_Bat, even at low V_Sup .

V_Bat voltage measurement (uncalibrated)

I_Bat current measurement (uncalibrated)

A shunt resistor (R387) in series to the cell voltage shut regulators is used to sense the current. While the series circuit currently cannot be opened to insert an amp-meter, the voltage across the shunt is measured to determine the “theoretical” current. The shunt resistor has a initial tolerance of 1% and a temperature drift of 50ppm.

Expected uncalibrated tolerance is 14.4 %/2.4 % (10 mA/1 A). For low current these result does exceed this error by far.
The calibration should reduce this error substantially to a third or less.

V_DropGND (uncalibrated)

Expected uncalibrated tolerance is 67.9 %/0.91 % (100 µV/10 mV). The results are much better than expected, even below expected calibrated values.

V_5V8 (uncalibrated)

The measurement is 5.8257V instead of 5.7928V for a random operating point. This is an error of 0.57%.

DAC

Why do the DACs start at 2.5V output?

The DACx0508M start at mid-scale, but the internal buffer defaults to gain = 2 (datasheet chapter 8.3.1.1). This is the equivalent mid-scale of 2× V_Ref full-scale. One wonders why… There seems not way to start at actual 1.25V output voltage.

A workaround might be to change resistance following the DAC outputs towards the current sinks.

Control

Notes concerning DACx0508:

• Setting DIV applies to all channels simultaneously, GAIN applies to single channels.
• The reason to not recommend the setting DIV/GAIN ÷1/×1 is that the performance with lower supply voltages is not as good as with ÷1/×1. At 5V supply voltage there is not difference.

Cell voltage 1 (lowest) control problem without connection to BMS

If V(CE1,CE0) is too low, measured 0.93V at room temperature, the controlling current source cannot source sufficient current through R223 to increase the cell voltage to the desired level. The aforementioned voltage is just sufficient for the op-amp to the drive the shunt-regulator transistors. The latter reduce the op-amp’s supply voltage to a break-even level for it to operate. Reason for this is problem is GNDA, towards the controlling current is sourced, being 0.7..0.8V more positive then CE0/Bat-. The current flowing from GNDA to Bat- via the anti-parallel diodes D9/D22 limiting the voltage difference. The possibility of GNDA to float in a limited manner vs. Bat- is intentional. It prevents analog offsets on temperature sensor voltages/current shunt simulator voltages to be effective.

Connecting GNDA to BMSGND (meaning Bat- without a BMS being connected), like done in operation by J15-3/4, resolves the problem. To make testing easier D9/D22 can be shorted. Or, preferably, a “high value” resistor compared the intended cable to the BMS, like 10Ω, should be used in parallel to D9/D22.

Cell voltage output

Testing the step response (stepping channel 1 and channel 3 from 2V to 4V and vice versa) and increasing/lowering channel 2 and 4 simultaneously shows:

• Actual transient response is very much dependent on the power supply used. Here, all three channels of the RS NGE-103 are in series - all with their own current limiting ant two-step regulation (buck-converter, linear post regulator). If the step size is reduced to about 100mV/20ms, all change in voltage seems to be handled in analogue circuitry without digital interference.
• The set current limit of the power supply limits the step response speed if the limit it hardly above current consumption of the PCB itself.
• If two voltages are set in opposing “directions” at one, to keep the sum of all cells identical and the power supply from reacting, the switching is very gracefully. This suggests that the very most of the ringing during steps is induced by the following control of the power supply.
• Some very short overshoots/undershoots can be observed during DAC updates (200µs, <500mV at most) if the sum of all cells is changed.

Capacitive loading of for example 220µF at lower currents like 150mA leads to some overshoot/undershot. This is reduced at high currents, of course. No oscillation to be observed at all.

As stated before, unsing the NGE-103 with changes of 100mV/20ms does not trigger any parts/logic interfering with the cell voltage regulation.

Conclusion: The cell voltage outputs work as expected.

Temperature output

Temperature voltage output behaves exactly exactly like simulated: Stable with load capacittane but still, quite fast (ca. 250µs rise time for 1µF load).

Shunt output

According to simulation the worst-case capacitive load is in the range of 1..10nF. After a lot of experimentation adding 470pF in parallel to the compensation network should tame the oscillations.

Step responses without load, 100nF, 1µF and 10µF now are like expected.

Measured rise times and overshoot:

The goal of (comparatively) fast risetimes with high capacitive load are achieved. An 100x increase in load capacitance results in 20x rise time increase, only.

EEPROM (U24)

I2C communication works fine. No changes in hardware required (except for more memory, maybe).

Signal integrity, with simple probing, at is good:

TODO

• Software
  • Develop memory map for calibration data
  • Read calibration data into respective parts
  • Firmware concept
    • How does communication work? JSON?
    • Send message with action keywords: set, get, get_config, set_config?

Removed/updated parts

Paragraphs below are left for documentation purposes. They do no represent the lastest state of affairs.

SPI modes

The native SPI modes on the (galvanically isolated) are the following:

The MCP23S08 is to be replaced by a digital isolator connecting the fan output (invertign SCLK line for mode 1 does not work). Its SPI modes 0/3 simply are incompatible without switching the mode of the SPI peripheral all the time.

Power supplies

U7 startup (R6 = 360kΩ)

• During startup it becomes obvious that the linear regulator U8 MIC5205-5.0 is either unstable or a connected load creates current surges that force it into current limiting
• The 2.5V shunt regulator enter regulation gracefully when 5V8 rails reach 3.5V.
• U11’s is properly protected from over-voltage by the resistor-zener-combination R15/D5.

U8 oscillation (with CVTCS-P)

Reason seems to be that the MIC5205 is unstable with ceramic output capacitors. The datasheet states:

For low-dropout regulators that are stable with ceramic output capacitors, see the μCap MIC5245/6/7 family. […]
The output capacitor should have an ESR (effective series resistance) of about 5Ω or less and a resonant frequency above 1MHz. Ultra-low-ESR capacitors can cause a low amplitude oscillation on the output and/or underdamped transient response

The MIC5205 was chosen because there are various suppliers for it. Possible cure can be to ei insert a 1Ω series resistance between regulator and capacitor (even less might work). Or replace the regulator with a suitable part.

U8 startup (with CVTCS-P, R6 = 360kΩ)

The U8 replacement TPS7A2450DBVR shows no oscillation with ceramic output capacitor. The start-up behaviour from 0V input is very good.

In case there is some residual voltage left on the input before startup, a 0.2..0.3V overshoot occurs. It is quite short (<400µs) sand well within input voltage ratings of downstream parts.

U11 startup (with CVTCS-P, R6 = 360kΩ)

Note: For this measurement GNDA and GND_Iso were connected.

The operation if the RPi Pico’s buck-boost regulator can be observed after V_iso reaches 1.8V. The drop in 5V8, 6ms after start, can be attributed to the RPi Pico’s startup.
V_Iso was measured directly on the microcontroller PCB. Therefore, the noise induced by the input current is at least partly a result of the the connecting 35mm long trace.

Output voltage

Load: None (no RPi Pico mounted; no CVTCS-P) (R6 = 360kΩ)

Notes:

• 5.8V rails are on the high side, but for zero load this might be acceptable.
• Check if +5VA is actually stable → No, U8 was oascillating
• V_Iso is greater then the V_in(max) of the Pi Pico (5.5V), but below V_in(max) of the RT6150B used there.

Load: None (no RPi Pico mounted; no CVTCS-P) (R6 = 340kΩ)

V_Iso is unregulated and a result of 5V8. Once the RPi Pico is mounted, even its few mA current draw will bring the voltages down into their expected ranges.

Notes:

• U15 was disconnected during measurements (defect)
• At lowest input voltage…
  • 5V8 is on the high side, but for zero load this might be acceptable.
  • V_Iso is greater then the V_in(max) of the Pi Pico (5.5V), but below V_in(max) of the RT6150B used there.

Load: RPi Pico idling (no CVTCS-P, R6 = 360kΩ)

Notes:

• To reduce 5V8 to within it’s limits, R_FB (R6) should be reduced to 330kΩ (or parallel 4.7MΩ).
• V_Iso ≤ 5.5V is tolerated. V_Iso(max) of 4.9V was a simulation result.
• It seems that all DACs output 2.5 on each channel leading to ~4.5V/cell settings. This clamps the max. input voltage at just below 70V. Therefore, a test with V_Sup = 80V was not performed.

Load: RPi Pico idling (no CVTCS-P, R6 = 340kΩ)

Notes:

• U15 was disconnected during measurements (defect)
• At lowest input voltage, 5V8 exceeds its range by a negligible amount.

Load: RPi Pico idling + 280mA on 3V3 (no CVTCS-P, R6 = 340kΩ)

By loading the 3V3 output of the RPi Pico, all upstream supplies are affected. The load is realized using 4 paralleled 47Ω/2W resistors (280mA/3.3V)

Note: U15 was disconnected during measurements (defect)

Fan supply

Switching

Falsely triggered over-current protection

Connecting both fans as loads to an already active fan output at 12.1V, this triggers the over current/short circuit detection. A bit more output capacitance (electrolytic) might help to absorb the first current draw of the fans..

Something similar can happen when switching from 6.7V to 12.1V.

Current output

Step response without load, 1µF and 10µF is like expected. However, with 100nF (without zero series resistance) instability can be observed:

According to simulation the worst-case capacitive load is in the range of 1..10nF.