-- prbs_tx.vhd
-- VHDL-93 synthesizable PRBS-16 transmitter (one 16-bit frame per clock when enable='1')
-- Polynomial: x^16 + x^14 + x^13 + x^11 + 1
-- Frame is the current LFSR state; next frame advances per polynomial.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity prbs_tx is
  generic (
    SEED : std_logic_vector(15 downto 0) := "1010110011100001"  -- non-zero seed
  );
  port (
    clk       : in  std_logic;
    rst       : in  std_logic;                         -- synchronous reset, active '1'
    enable    : in  std_logic;                         -- advance one frame when '1'
    frame_out : out std_logic_vector(15 downto 0)      -- 16-bit PRBS frame
  );
end entity prbs_tx;

architecture rtl of prbs_tx is

  -- LFSR state (LSB = bit 0). We use Fibonacci form: shift right, MSB gets XOR of taps.
 signal lfsr : std_logic_vector(15 downto 0) := SEED;

  -- Next-state function for PRBS-16 (poly x^16 + x^14 + x^13 + x^11 + 1)
  -- Taps map to bit positions: 0, 2, 3, 5 when using right-shift/insert-at-MSB form.
  function lfsr16_next(s : std_logic_vector(15 downto 0)) return std_logic_vector is
    variable fb : std_logic;                               -- feedback bit
    variable n  : std_logic_vector(15 downto 0);
  begin
    fb := s(0) xor s(2) xor s(3) xor s(5);
    n  := fb & s(15 downto 1);                             -- insert at MSB, shift right
    return n;
  end function;

begin

  -- Output current frame (combinational)
  frame_out <= lfsr;

  -- State update (sequential)
  process(clk)
  begin
    if rising_edge(clk) then
      if rst = '1' then
        lfsr <= SEED;
      else
        if enable = '1' then
          lfsr <= lfsr16_next(lfsr);
        end if;
      end if;
    end if;
  end process;

end architecture rtl;