#include <atmel_start.h>

/* uC: ATMEGA88 */

#include <avr/io.h>
#include <avr/interrupt.h>
#include <util/delay.h>
#include <NRC_UDS_protocol.h>
#define FOSC 8000000 // Clock Speed
#define BAUD 9600
#define MYUBRR FOSC/16/BAUD-1
#define sizeOfReceiveBuffer 50
unsigned char receivebuffer[sizeOfReceiveBuffer];
uint8_t returnFlagOfReceiveBuffer;
bool dataAreRead = false;

/*
void UART_Flush( void )
{
	unsigned char dummy;
	while ( UCSR0A & (1<<RXC0) ) dummy = UDR0;
}
*/



void USART_Init( unsigned int ubrr)
{
	/*Set baud rate */
	/* ubrr  at 8Mhz and 9600 Baud in Manual ubrr = 51 with 0.2% error */
	UBRR0H = (ubrr>>8);
	UBRR0L = ubrr;
	
	
	/* 	 7		   6		 5		   4		 3		  2		  1		  0		            */
	/*  RXCn      TXCn     UDREn      FEn       DORn     UPEn    U2Xn    MPCMn     = UCSRnA */
	/*   R   |    R/W   |    R    |    R    |    R    |   R   |  R/W   | R/W                */
	/*   0   |     0    |    1    |    0    |    0    |   0   |   0    |  0                 */
	
	
	/*
	• Bit 7 – RXCn: USART Receive Complete
	This flag bit is set when there are unread data in the receive buffer and cleared when the receive
	buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive
	buffer will be flushed and consequently the RXCn bit will become zero. The RXCn Flag can be
	used to generate a Receive Complete interrupt (see description of the RXCIEn bit).
	
	• Bit 6 – TXCn: USART Transmit Complete
	This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and
	there are no new data currently present in the transmit buffer (UDRn). The TXCn Flag bit is automatically
	cleared when a transmit complete interrupt is executed, or it can be cleared by writing
	a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see
	description of the TXCIEn bit).
	
	• Bit 5 – UDREn: USART Data Register Empty
	The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn
	is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a
	Data Register Empty interrupt (see description of the UDRIEn bit).
	UDREn is set after a reset to indicate that the Transmitter is ready.
	
	• Bit 4 – FEn: Frame Error
	This bit is set if the next character in the receive buffer had a Frame Error when received. I.e.,
	when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the
	receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one.
	Always set this bit to zero when writing to UCSRnA.
	
	• Bit 3 – DORn: Data OverRun
	This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive
	buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a
	new start bit is detected. This bit is valid until the receive buffer (UDRn) is read. Always set this
	bit to zero when writing to UCSRnA.
	
	• Bit 2 – UPEn: USART Parity Error
	This bit is set if the next character in the receive buffer had a Parity Error when received and the
	Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer
	(UDRn) is read. Always set this bit to zero when writing to UCSRnA.
	
	• Bit 1 – U2Xn: Double the USART Transmission Speed
	This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous
	operation.
	Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling
	the transfer rate for asynchronous communication.
	
	• Bit 0 – MPCMn: Multi-processor Communication Mode
	This bit enables the Multi-processor Communication mode. When the MPCMn bit is written to
	one, all the incoming frames received by the USART Receiver that do not contain address information
	will be ignored. The Transmitter is unaffected by the MPCMn setting. For more detailed
	information see
	*/
	
	
	
	/*Enable receiver and transmitter no interrupt enabled */
	UCSR0B |= (1<<RXEN0)|(1<<TXEN0);
	/* 	 7		   6		5		   4		 3		  2		  1		    0		         */
	/* RXCIEn   TXCIEn     UDRIEn    RXENn     TXENn    UCSZn2    RXB8n   TXB8n     = UCSRnB */
	/*  R/W  |    R/W   |   R/W   |   R/W   |   R/W   |  R/W   |   R    | R/W                */
	/*   0   |     0    |    0    |    0    |    0    |   0    |   0    |  0                 */
	
	/*
	• Bit 7 – RXCIEn: RX Complete Interrupt Enable n
	Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt
	will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is
	written to one and the RXCn bit in UCSRnA is set.
	
	• Bit 6 – TXCIEn: TX Complete Interrupt Enable n
	Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt
	will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is
	written to one and the TXCn bit in UCSRnA is set.
	
	• Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n
	Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will
	be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written
	to one and the UDREn bit in UCSRnA is set.
	
	• Bit 4 – RXENn: Receiver Enable n
	Writing this bit to one enables the USART Receiver. The Receiver will override normal port operation
	for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer
	invalidating the FEn, DORn, and UPEn Flags.
	
	• Bit 3 – TXENn: Transmitter Enable n
	Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port
	operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to
	zero) will not become effective until ongoing and pending transmissions are completed, i.e.,
	when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted.
	When disabled, the Transmitter will no longer override the TxDn port.
	
	• Bit 2 – UCSZn2: Character Size n
	The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits
	(Character SiZe) in a frame the Receiver and Transmitter use.
	
	• Bit 1 – RXB8n: Receive Data Bit 8 n   (can be ignored on 8Bit mode)
	RXB8n is the ninth data bit of the received character when operating with serial frames with nine
	data bits. Must be read before reading the low bits from UDRn.
	
	• Bit 0 – TXB8n: Transmit Data Bit 8 n   (can be ignored on 8Bit mode)
	TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames
	with nine data bits. Must be written before writing the low bits to UDRn.
	*/
	
	
	
	
	
	/* Configuration of the UART0:
	Set frame format: 8data, 1stop bit */
	/* config of BT module is (8 bits data, no parity bit, 1 stopbit) */
	
	UCSR0C |= (1<<UCSZ00) | (1<<UCSZ01);
	
	/* 	 7		   6		 5		   4		 3		  2		   1	   0		         */
	/*UMSELn1	UMSELn0	   UPMn1	 UPMn0     USBSn    UCSZn1   UCSZn0   UCPOLn   =  UCSRnC */
	/*  R/W  |    R/W   |   R/W   |   R/W   |   R/W   |  R/W   |  R/W   | R/W                */
	/*   0   |     0    |    0    |    0    |    0    |   1    |   1    |  0                 */
	/*
				UMSELn1 UMSELn0	Mode
				   0		0		Asynchronous USART
				   0		1		Synchronous USART
				   1		0		(Reserved)
				   1		1		Master SPI (MSPIM)(1)
	*/
	/* UMSEL00 and UMSEL01 = 0 (default) -> asynchron */
	
	/*	
				 UPMn1    UPMn0		Parity Mode
				   0		0		Disabled
				   0		1		Reserved
				   1		0		Enabled, Even Parity
				   1		1		Enabled, Odd Parity
	*/
	/* UPMn1 and UPMn0 = 0 (default) -> Paritiy bit disabled */
		
	/*	
						  USBSn		Stop Bit(s)
							0		1-bit
							1		2-bit
	*/
	/* USBSn = 0 (default) -> 1 Stop bit */	
	
	/*
	  UCSZn2	UCSZn1	  UCSZn0	Character Size
		0		  0		    0		5-bit
		0		  0			1		6-bit
		0		  1			0		7-bit
		0		  1			1		8-bit
		1		  0			0		Reserved
		1		  0			1		Reserved
		1		  1			0		Reserved
		1		  1			1		9-bit
	*/
	/* UCSZn1 and  UCSZn0 = 1 (default) -> 8 bit */	
	
	/*
						  UCPOLn	Transmitted Data Changed    Received Data Sampled 
									(Output of TxDn Pin)		(Input on RxDn Pin)										
	
							0		Rising XCKn Edge			Falling XCKn Edge
							1		Falling XCKn Edge			Rising XCKn Edge
	*/
}



unsigned char UART_Receive(void)
{
	while (!(UCSR0A & (1<<RXC0)))
	;
	/* Get and return received data from buffer */
    return  UDR0;
}

void fillReceiveBuffer(void)
{
	
		uint8_t indexBuffer =0;
		while ((UCSR0A & (1<<RXC0)))
		{
			receivebuffer[indexBuffer] =UART_Receive();
			indexBuffer = indexBuffer +1;	
		}
		
	//receivebuffer[0]=UART_Receive();
}
void UART_Transmit( unsigned char data )
{
	/* Wait for empty transmit buffer */
	while ( !( UCSR0A & (1<<UDRE0)) )
	;
	/* Put data into buffer, sends the data */
	UDR0 = data;
}

void stateMachine(void)
{
	if(receivebuffer[0]==UDS_WRITE_DATA) //0x2E
	{		
		dataAreRead = true;
		PORTC= 0xFF;
		UART_Transmit(0x44);
		if(receivebuffer[1]== 0x33)
		{
			UART_Transmit(0x55);
			dataAreRead = true;
		}
	}
	
	
	if(receivebuffer[0]==UDS_READ_DATA) //0x22
	{
		/*
		UART_Transmit(0x7F);
		UART_Transmit(UDS_READ_DATA);
		UART_Transmit(UDS_NRC_requestOutOfRange);
		*/
		
		dataAreRead = true;
		PORTC= 0x00;
		UART_Transmit(0x77);
		if(receivebuffer[1]== 0x33)
		{
			UART_Transmit(0x55);
			dataAreRead = true;
		}
	}
	
	
	
}
void deleteReceiveBuffer(void)
{
	if(dataAreRead){
		uint8_t i=0;
		for(i=0;i<sizeOfReceiveBuffer;i++)
		{
			receivebuffer[i]=0;
		}
		dataAreRead = false;
	}
}

int main( void )
{
	//atmel_start_init();
	USART_Init(51); //attention ckdiv8 flag must be deleted
	DDRC |= (1 << DDC0) |(1 << DDC1)|(1 << DDC2) |(1 << DDC4)|(1 << DDC5);
	PORTC = 0x10;
	while(1)
	{
		fillReceiveBuffer();
		stateMachine();
		deleteReceiveBuffer();
	}
	return 1;
}