---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 15:23:18 03/21/2026 -- Design Name: -- Module Name: Neuron - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity Neuron is Generic (ADDRESS_WIDTH : integer := 11; --Weight Memory Size DATA_WIDTH : integer := 16; --Float16 Format PAGE_WIDTH : integer := 4; --max. 16 Layers INPUT_WIDTH : integer := 7; --max 128 Input Signals INPUTS : integer := 10; --Number of used inputs LATENCY : integer := 6); Port ( --Control Signals clk : in std_logic; reset : in std_logic; execute : in std_logic; ready : out std_logic; error : out std_logic; Layer_page : in std_logic_vector(PAGE_WIDTH-1 downto 0); Layer_Input_Number : in std_logic_vector(INPUT_WIDTH-1 downto 0); --Weight Memory Signals (to read and write directly to Weight Memory) Mem_enable : in std_logic; Mem_write : in std_logic; Mem_Adr : in std_logic_vector (ADDRESS_WIDTH-1 downto 0); Mem_Data_In : in std_logic_vector (DATA_WIDTH-1 downto 0); Mem_Data_Out : out std_logic_vector (DATA_WIDTH-1 downto 0); --Input Data Signal Input : in std_logic_vector (DATA_WIDTH-1 downto 0); --Output Data Signal Output : out std_logic_vector (DATA_WIDTH-1 downto 0) ); end Neuron; architecture Behavioral of Neuron is signal int_ready : std_logic; type state_t is (idle, load, pipe, finish); signal Neuron_state : state_t; signal count_in : integer range 0 to INPUTS-1; signal count_wait : integer range 0 to 2*LATENCY; signal clk_enable : std_logic; signal int_Output : std_logic_vector(DATA_WIDTH-1 downto 0); component Weight_Memory port( clk : in std_logic; Port_A_Adr : in std_logic_vector(ADDRESS_WIDTH-1 downto 0); Port_B_enable : in std_logic; Port_B_write : in std_logic; Port_B_Adr : in std_logic_vector(ADDRESS_WIDTH-1 downto 0); Port_B_Data_In : in std_logic_vector(DATA_WIDTH-1 downto 0); Port_A_Data_Out : out std_logic_vector(DATA_WIDTH-1 downto 0); Port_B_Data_Out : out std_logic_vector(DATA_WIDTH-1 downto 0) ); end component; signal Weight : std_logic_vector(DATA_WIDTH-1 downto 0); signal Weight_Adr : std_logic_vector(ADDRESS_WIDTH-1 downto 0); component Float_Multiply port ( a : in std_logic_vector(DATA_WIDTH-1 downto 0); b : in std_logic_vector(DATA_WIDTH-1 downto 0); clk : in std_logic; ce : in std_logic; result : out std_logic_vector(DATA_WIDTH-1 downto 0); underflow : out std_logic; overflow : out std_logic; invalid_op : out std_logic; rdy : out std_logic ); end component; signal Mult_a : std_logic_vector(DATA_WIDTH-1 downto 0); signal Mult_b : std_logic_vector(DATA_WIDTH-1 downto 0); signal Mult_result : std_logic_vector(DATA_WIDTH-1 downto 0); signal Mult_underflow : std_logic; signal Mult_overflow : std_logic; signal Mult_invalid_op : std_logic; signal Mult_rdy : std_logic; component Float_Addition port ( a : in std_logic_vector(DATA_WIDTH-1 downto 0); b : in std_logic_vector(DATA_WIDTH-1 downto 0); clk : in std_logic; ce : in std_logic; result : out std_logic_vector(DATA_WIDTH-1 downto 0); underflow : out std_logic; overflow : out std_logic; invalid_op : out std_logic; rdy : out std_logic ); end component; signal Add_result : std_logic_vector(DATA_WIDTH-1 downto 0); signal Add_sum : std_logic_vector(DATA_WIDTH-1 downto 0); signal Add_underflow : std_logic; signal Add_overflow : std_logic; signal Add_invalid_op : std_logic; signal Add_rdy : std_logic; begin My_Weight_Memory: Weight_Memory PORT MAP( clk => clk, Port_A_Adr => Weight_Adr, Port_A_Data_Out => Weight, Port_B_enable => Mem_enable, Port_B_write => Mem_write, Port_B_Adr => Mem_Adr, Port_B_Data_In => Mem_Data_In, Port_B_Data_Out => Mem_Data_Out ); My_Float_Multiply : Float_Multiply PORT MAP ( a => Mult_a, b => Mult_b, clk => clk, ce => clk_enable, result => Mult_result, underflow => Mult_underflow, overflow => Mult_overflow, invalid_op => Mult_invalid_op, rdy => Mult_rdy ); My_Float_Addition : Float_Addition PORT MAP ( a => Add_sum, b => Mult_result, clk => clk, ce => clk_enable, result => Add_result, underflow => Add_underflow, overflow => Add_overflow, invalid_op => Add_invalid_op, rdy => Add_rdy ); process begin wait until rising_edge(clk); if(reset = '1') then Add_sum <= (others => '0'); Mult_a <= (others => '0'); Mult_b <= (others => '0'); int_Output <= (others => '0'); int_ready <= '1'; Neuron_state <= idle; count_in <= 0; count_wait <= 0; clk_enable <= '0'; else case Neuron_state is when idle => if(execute = '1') then int_ready <= '0'; count_in <= 0; clk_enable <= '1'; Neuron_state <= load; else int_ready <= '1'; clk_enable <= '0'; end if; when load => int_ready <= '0'; Add_sum <= Add_result; Mult_a <= Input; Mult_b <= Weight; count_in <= count_in + 1; if(count_in = INPUTS-1) then count_wait <= 0; Neuron_state <= pipe; Mult_a <= (others => '0'); Mult_b <= (others => '0'); end if; when pipe => Add_sum <= Add_result; count_wait <= count_wait + 1; if(count_wait = (2*LATENCY)-1) then Neuron_state <= finish; end if; when finish => int_Output <= Add_result; if(execute = '0') then Neuron_state <= idle; end if; when others => Neuron_state <= idle; end case; end if; end process; Output <= int_Output; Weight_Adr <= Layer_page & Layer_Input_Number; ready <= int_ready and not(execute); error <= Mult_underflow or Mult_overflow or Mult_invalid_op or Add_underflow or Add_overflow or Add_invalid_op;-- or Sqrt_invalid_op; end Behavioral;