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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:37:33 03/21/2026 
-- Design Name: 
-- Module Name:    Weight_Memory - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Weight_Memory is
	Generic (ADDRESS_WIDTH 	: integer := 11;
				DATA_WIDTH 		: integer := 16);
	
    Port ( --Control Signals
			  clk : in std_logic;
			  --Port A Singals (read only)
			  Port_A_Adr : in std_logic_vector (ADDRESS_WIDTH-1 downto 0);
           Port_A_Data_Out : out std_logic_vector (DATA_WIDTH-1 downto 0);			  
			  --Port B Signals (read/write)
			  Port_B_enable : in std_logic;
			  Port_B_write : in std_logic;
			  Port_B_Adr : in std_logic_vector (ADDRESS_WIDTH-1 downto 0);
           Port_B_Data_In : in std_logic_vector (DATA_WIDTH-1 downto 0);
			  Port_B_Data_Out : out std_logic_vector (DATA_WIDTH-1 downto 0)
			  );
end Weight_Memory;

architecture Behavioral of Weight_Memory is

	type mem is array(0 to (2**(ADDRESS_WIDTH))-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
	signal memory : mem := (
	x"AE9B",
	x"3326",
	x"A687",
	x"2E08",
	x"B24D",
	x"2A9F",
	x"AD81",
	x"3216",
	x"B135",
	x"2841",
	x"B022",
	x"339B",
	x"A48B",
	x"2ED9",
	x"B31C",
	x"2C3D",
	x"ACE9",
	x"31D9",
	x"A245",
	x"3158",
	x"B1EF",
	x"29D2",
	x"AFF7",
	x"3302",
	x"AC7E",
	x"2FEB",
	x"B36C",
	x"274B",
	x"B172",
	x"2DD7",
	x"AB02",
	x"31A3",
	x"A88B",
	x"32A9",
	x"AF95",
	x"252F",
	x"B0DD",
	x"3381",
	x"AC9F",
	x"3028",
	x"B2DF",
	x"2A87",
	x"AF1A",
	x"3202",
	x"A76C",
	x"30A1",
	x"B28F",
	x"2F47",
	x"AC00",
	x"2D89",
	x"B3B6",
	x"2926",
	x"B066",
	x"3262",
	x"AE62",
	x"3189",
	x"AC62",
	x"335E",
	x"A820",
	x"2FD2",
	x"B1D2",
	x"33AC",
	x"ADE3",
	x"3072",
	x"B2FD",
	x"2AC0",
	x"AFDF",
	x"31EB",
	x"A947",
	x"30F5",
	x"B2B6",
	x"2F85",
	x"AC97",
	x"2DCA",
	x"B3C8",
	x"28AC",
	x"B0AE",
	x"3278",
	x"AEB8",
	x"3197",
	x"ACB8",
	x"3370",
	x"A883",
	x"3000",
	x"B1DB",
	x"33BE",
	x"AE10",
	x"3085",
	x"B316",
	x"2B1A",
	x"B006",
	x"31F7",
	x"A9A9",
	x"3106",
	x"B366",
	x"2EB8",
	others => (others =>'0'));

begin

	Port_A:process 
	begin
		wait until falling_edge(clk);
		Port_A_Data_Out <= memory(to_integer(unsigned(Port_A_Adr)));			--read operation
	end process;
	
	Port_B:process
	begin
		wait until falling_edge(clk);
		if(Port_B_enable = '0') then
			Port_B_Data_Out <= (others => 'Z');
		else
			if(Port_B_write = '1') then
				memory(to_integer(unsigned(Port_B_Adr))) <= Port_B_Data_In;		--write operation
				Port_B_Data_Out <= Port_B_Data_In;										--write first mode
			else
				Port_B_Data_Out <= memory(to_integer(unsigned(Port_B_Adr)));
			end if;
		end if;		
	end process;

end Behavioral;