--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   09:35:48 03/28/2026
-- Design Name:   
-- Module Name:   D:/Xilinx_Projekts/Neural_Network/Neuron_tb.vhd
-- Project Name:  Neural_Network
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Neuron
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY Neuron_tb IS
END Neuron_tb;
 
ARCHITECTURE behavior OF Neuron_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
	COMPONENT Neuron
	PORT(
		clk : IN  std_logic;
		reset : IN  std_logic;
		execute : IN  std_logic;
		ready : OUT  std_logic;
		error : OUT  std_logic;
		Layer_page : IN  std_logic_vector(3 downto 0);
		Layer_Input_Number : IN  std_logic_vector(6 downto 0);
		Mem_enable : IN  std_logic;
		Mem_write : IN  std_logic;
		Mem_Adr : IN  std_logic_vector(10 downto 0);
		Mem_Data_In : IN  std_logic_vector(15 downto 0);
		Mem_Data_Out : OUT  std_logic_vector(15 downto 0);
		Input : IN  std_logic_vector(15 downto 0);
		Output : OUT  std_logic_vector(15 downto 0)
		);
	END COMPONENT;
	 
	COMPONENT Input_Memory
	PORT(
		clk : IN std_logic;
		Address : IN std_logic_vector(6 downto 0);          
		Data_out : OUT std_logic_vector(15 downto 0)
		);
	END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';
   signal execute : std_logic := '0';
   signal Layer_page : std_logic_vector(3 downto 0) := (others => '0');
   signal Layer_Input_Number : std_logic_vector(6 downto 0) := (others => '0');
   signal Mem_enable : std_logic := '0';
   signal Mem_write : std_logic := '0';
   signal Mem_Adr : std_logic_vector(10 downto 0) := (others => '0');
   signal Mem_Data_In : std_logic_vector(15 downto 0) := (others => '0');
   signal Input : std_logic_vector(15 downto 0) := (others => '0');
	signal Address : std_logic_vector(6 downto 0) := (others => '0');

 	--Outputs
   signal ready : std_logic;
   signal error : std_logic;
   signal Mem_Data_Out : std_logic_vector(15 downto 0);
   signal Output : std_logic_vector(15 downto 0);
	signal Data_out : std_logic_vector(15 downto 0);
	
	--internal Signals
	signal Address_counter : unsigned(6 downto 0) := (others => '0');
	signal int_execute : std_logic;
	signal input_state : integer range 0 to 96 := 0;

   -- Clock period definitions
   constant clk_period : time := 5 ns;
 
BEGIN
 
	tb_Input_Memory: Input_Memory PORT MAP(
		clk => clk,
		Address => Address,
		Data_out => Data_out
	);	
	
	-- Instantiate the Unit Under Test (UUT)
   uut: Neuron PORT MAP (
          clk => clk,
          reset => reset,
          execute => int_execute,
          ready => ready,
          error => error,
          Layer_page => Layer_page,
          Layer_Input_Number => Layer_Input_Number,
          Mem_enable => Mem_enable,
          Mem_write => Mem_write,
          Mem_Adr => Mem_Adr,
          Mem_Data_In => Mem_Data_In,
          Mem_Data_Out => Mem_Data_Out,
          Input => Data_out,
          Output => Output
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
	
	stim_Input: process
	begin
		wait until rising_edge(clk);
		
		if(reset = '1') then
			Address_counter <= (others => '0');
			Layer_Input_Number <= (others => '0');
			Layer_page <= (others => '0');
			input_state <= 0;
			int_execute <= '0';
		else
			if(execute = '1') then	
				input_state <= 1;	
				int_execute <= '1';
--			else
--				input_state <= 1;	
			end if;			
			
			case input_state is
				when 0			=>	Address_counter <= (others => '0');
														
				when 10			=> Address_counter <= (others => '0');
										int_execute <= '0';
														
				when others 	=>	Address_counter <= Address_counter + 1;
										input_state <= input_state + 1;
			end case;										
			Layer_Input_Number <= std_logic_vector(Address_counter);
			Address <= std_logic_vector(Address_counter);			
		end if;
	end process;
	
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	
		reset <= '1';
		wait for 100ns;
		reset <= '0';
		wait for 100ns;
		
		-- insert stimulus here 
		execute <= '1';	
		wait for 10ns;	
		execute <= '0';		
		
      wait;
   end process;

END;