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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:16:52 03/28/2026 
-- Design Name: 
-- Module Name:    Input_Memory - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Input_Memory is
    Port ( clk : in  std_logic;
			  Address : in std_logic_vector(6 downto 0);
			  Data_out : out std_logic_vector(15 downto 0));
end Input_Memory;

architecture Behavioral of Input_Memory is

	type mem is array(0 to (2**(7))-1) of std_logic_vector(15 downto 0);
	signal memory : mem := (
	x"3174",
	x"A906",
	x"3006",
	x"B35E",
	x"2BCE",
	x"B0E3",
	x"32A5",
	x"AE39",
	x"2818",
	x"B21C",
	x"3126",
	x"AA6E",
	x"331C",
	x"AD6C",
	x"2F8D",
	x"B287",
	x"2A2D",
	x"B097",
	x"33DB",
	x"AC35",
	x"2EBC",
	x"B2C6",
	x"2D43",
	x"B181",
	x"30CE",
	x"A981",
	x"328D",
	x"AF43",
	x"254F",
	x"B3CC",
	x"3012",
	x"AD91",
	x"332F",
	x"AAD9",
	x"3166",
	x"B145",
	x"28B4",
	x"B043",
	x"32E3",
	x"A46A",
	x"2C72",
	x"B393",
	x"30B6",
	x"ACE1",
	x"31E9",
	x"AFAE",
	x"2968",
	x"B268",
	x"334D",
	x"A85A",
	x"2F3B",
	x"B122",
	x"2CE1",
	x"B360",
	x"3043",
	x"A224",
	x"32BE",
	x"AB53",
	x"319F",
	x"B076",
	x"28FD",
	x"B2AE",
	x"333B",
	x"9C5A",
	x"2CA7",
	x"B3AC",
	x"3110",
	x"AC6A",
	x"3239",
	x"AEB8",
	x"2A3D",
	x"B278",
	x"3362",
	x"A828",
	x"2F81",
	x"B13D",
	x"2D26",
	x"B37C",
	x"3060",
	x"A160",
	x"32C8",
	x"AB2B",
	x"31B8",
	x"B087",
	x"2970",
	x"B2C4",
	x"3347",
	x"9AA7",
	x"2CBC",
	x"B3BA",
	x"3120",
	x"AC87",
	x"3256",
	x"AEE5",
	x"2BCE",
	x"B1E1",
	others => (others =>'0'));

begin
	
	process 
	begin
		wait until falling_edge(clk);
		Data_out <= memory(to_integer(unsigned(Address)));			--read operation
	end process;

end Behavioral;