---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 11:13:33 03/02/2010 -- Design Name: -- Module Name: adc - Behavioral -- Project Name: -- Target Devices: Spartan 3e -- Tool versions: -- Description: Einlesen einer Spannung vom ADC, verstärken des Signals im FPGA --und Ausgabe an den DAC -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity adc is --constrained in ucf file Port ( clk : in std_logic; -- Spartan3e Takt ADC_in : in std_logic; -- Einlesen der ADC-Daten über SPI-Bus SPI_clk : out std_logic; -- Takt für SPI-Bus DAC_out : out std_logic; -- Ausgabe an DAC über SPI-Bus DAC_CS : out std_logic; -- Active Low chip-select DAC_CLR : out std_logic; -- Reset des DAC wenn '0' SPI_SS_B : out std_logic; --SPI Serial Flash AMP_CS : out std_logic; --Preamplifier SF_CE0 : out std_logic; --StrataFlash Parallel Flash PROM FPGA_INIT_B : out std_logic; --Platform Flash PROM ADC_CONV: out std_logic -- Umwandlung der Daten bei steigender -- Flanke ); end adc; architecture Behavioral of adc is type adcstatetype is (start,readbit,clockadc,convhigh,func,setzen,sendbit,clockdac,cshigh); -- state machine für adc und dac signal adcstate : adcstatetype := start; signal daccounter : integer range 0 to 31 := 0 ; -- Zähler für dac signal adccounter : integer range 0 to 32 := 0; -- Zähler für ADC signal dacdata : unsigned(31 downto 0); -- DAC-Daten signal counter : integer range 0 to 2 := 2 ; -- Zähler für Taktteiler signal clkenable : std_logic := '0'; -- neuer Takt, da Spartantakt zu schnell signal dacsend : unsigned(11 downto 0); signal adcdata1 : unsigned (13 downto 0); signal adcdata2 : unsigned (13 downto 0); -- Daten vom ADC signal reset : std_logic := '0'; begin -- purpose: Taktteiler -- type : combinational -- inputs : clk -- outputs: newclk clkdiv : process(clk) begin if rising_edge(clk) then clkenable <= '0'; -- wir arbeiten mit Clock-Enable if reset = '0' then -- synchroner Reset if counter = 2 then clkenable <= '1'; counter <= 0; else counter <= counter + 1; end if; end if; end if; end process; -- purpose: Hauptprogramm -- type : combinational -- inputs : newclk -- outputs: alles main: process (clk,reset)--man sollte nur einen Takt verwenden variable temp:integer; --zwischenspeicher für ADC-Signal1 variable temp2:integer;--zwischenspeicher für ADC-Signal2 begin if rising_edge(clk) then if clkenable ='1' then case adcstate is when start => ADC_CONV <= '1'; -- alle Signale auf logisch 1 DAC_CLR <= '1'; DAC_CS <= '1'; --alle Bausteine die auch SPI-Bus nutzen, müssen auf logisch '1' SPI_SS_B <= '1'; AMP_CS <= '1'; SF_CE0 <= '1'; FPGA_INIT_B <= '1'; SPI_clk <= '1'; adccounter <= 0; -- Zähler auf Ausgangswerte daccounter <= 31; adcstate <= readbit; when readbit => ADC_CONV <= '0'; SPI_clk <= '0'; if adccounter < 2 then adcstate <= clockadc ; elsif adccounter > 1 and adccounter < 16 then adcdata1(adccounter-2) <= ADC_in; adcstate <= clockadc; elsif adccounter > 15 and adccounter < 18 then adcstate <= clockadc ; elsif adccounter > 17 and adccounter < 32 then adcdata2(adccounter - 18) <= ADC_in; adcstate <= clockadc; elsif adccounter = 32 then adcstate <= clockadc; end if; when clockadc => SPI_clk <= '1'; if adccounter = 32 then adcstate <= convhigh; else adccounter <= adccounter + 1; adcstate <= readbit; end if; when convhigh => ADC_CONV <= '1'; SPI_clk <= '0'; adcstate <= func; when func => temp := conv_integer(adcdata1); temp := temp*2; temp2 := conv_integer(adcdata2); temp2 := temp2*2; dacsend <= conv_unsigned(adcdata1,12); adcstate <= setzen; when setzen => dacdata <= "00000000"&"0011" & "0000" & dacsend & "0000"; adcstate <= sendbit; when sendbit => --ab hier ausgabe an den DAC -- CS und Dac-Takt auf '0' SPI_clk <= '0'; DAC_CS <= '0'; DAC_out <= dacdata(daccounter); adcstate <= clockdac; when clockdac => --DAC-Takt wieder auf '1' SPI_clk <= '1'; if daccounter = 0 then adcstate <= cshigh; else daccounter <= daccounter - 1; adcstate <= sendbit; end if; when cshigh => --Nach Übermittlung der Daten wieder CS auf '1' DAC_CS <= '1'; adcstate <= start ; end case; end if; end if; end process main; end Behavioral;