cpu	atmega8
	include	/home/nutzer/eigene/prj/avr/asl/appnotes/tn24adef.asm
	include /home/nutzer/eigene/prj/avr/inc/hilo.asm

#define	f_cpu		1000000

#define	lcd_clk_port	"A"
#define	lcd_clk_bit	5

#define	lcd_dat_port	"A"
#define	lcd_dat_bit	6

#define	lcd_ena_port	"A"
#define	lcd_ena_bit	4

	segment data
	org sram_start
ctr_byte:
	res	1
	segment code

	rjmp	isr_RESET
	rjmp	isr_INT0
	rjmp	isr_PCINT0
	rjmp	isr_PCINT1
	rjmp	isr_WDT
	rjmp	isr_TIM1_CAPT
	rjmp	isr_TIM1_COMPA
	rjmp	isr_TIM1_COMPB
	rjmp	isr_TIM1_OVF
	rjmp	isr_TIM0_COMPA
	rjmp	isr_TIM0_COMPB
	rjmp	isr_TIM0_OVF
	rjmp	isr_ANA_COMP
	rjmp	isr_ADC
	rjmp	isr_EE_RDY
	rjmp	isr_USI_STR
	rjmp	isr_USI_OVF

isr_INT0:
isr_PCINT0:
isr_PCINT1:
isr_WDT:
isr_TIM1_CAPT:
isr_TIM1_COMPA:
isr_TIM1_COMPB:
isr_TIM1_OVF:
isr_TIM0_COMPA:
isr_TIM0_COMPB:
isr_TIM0_OVF:
isr_ANA_COMP:
isr_ADC:
isr_EE_RDY:
isr_USI_STR:
isr_USI_OVF:
	reti

	include	/home/nutzer/eigene/prj/avr/inc/tnarx.asm
	include /home/nutzer/eigene/prj/avr/inc/adu_tiny.asm

delay:	clr	r17
delay1:
	ldi	r18,10
delay2:
	dec	r18
	brne	delay2
	dec	r17
	brne	delay1
	dec	r16
	brne	delay
	ret

v2temp:
	lsl	r0
	rol	r1
	lsl	r0
	rol	r1
	ldi	r16,low(740)
	ldi	r17,high(740)
	sub	r16,r0
	sbc	r17,r1
	sbrs	r17,7
	rjmp	v2temp1
	clr	r17
	ldi	r16,20
v2temp1:
	mov	r0,r16
	mov	r1,r17
	ret


isr_RESET:
	ldi	r16,ramend
	out	spl,r16
	rcall	lcd_init
	ldi	r16,3
	out	didr0,r16
	adu_init
	;lcd_clear_left
	;lcd_clear_right
	sbi	ddra,3

loop:
	;war ten auf nulldurchgang
	sbic	pina,2
	rjmp	loop
	;Heizung kurz an
	sbi	porta,3
	ldi	r16,10
	rcall	delay

	ldi	r16,0x80+0
	out	admux,r16
	rcall	adu_get
	rcall	adu_get
	mov	r18,r0
	mov	r19,r1
	rcall	v2temp
	lcd_out_rr0_left

	ldi	r16,0x80+1
	out	admux,r16
	rcall	adu_get
	rcall	adu_get
	mov	r20,r0
	mov	r21,r1
	rcall	v2temp
	lcd_out_rr0_right

	sub	r18,r20
	sbc	r19,r21
	brcs	loop1
	cbi	porta,3
	loop1:
	ldi	r16,255
	rcall	delay

	rjmp	loop