Teletext, Graphic, VPS and PDC

TVTEXT
MEGATEXT, VPS/PDC
MEGATEXT: Volume 1
MEGATEXT: Volume 2

Electronic Program Guides
( 222 K)

Type	Features	PDF Size	Status
TVTEXT
SDA 5250 SDA 5251 SDA 5252 SDA 5254 SDA 5255	TVTEXT 8-Bit Microcontroller, ROM- and ROMless-Version, Preliminary Data Sheet	1.075 K	04.98
SDA 5250 SDA 5254 SDA 5255	TVTEXT Firmware and Command Interface Description Version 0.01, (8 Pages) Firmware Version V3.3x, Target Specification	496 K	12.96
SDA 5251 SDA 5252	Firmware and Command Interface Description Version 0.01, (1 Page) Firmware Version V1.7x, Target Specification	416 K	12.96
SDA 525X to SDA 525X-2	Delta Specification	237 K	10.98
SDA 5250	TVTEXT - SDA 5250 with External 128 TTX Pages, Application Note	53 K	07.97
SDA 525x	How to Use TVTEXT - SDA 525x in 100 Hz TV Applications?, Application Note 1	112 K	07.97
SDA 525x	TVTEXT, SDA 525X in Deinterlaced Mode with Philips TV-Processor TDA 884X Application Note 2	28 K	06.98

MEGATEXT, VPS/PDC

Type Features PDF Size Status

SDA 5273 P
SDA 5275 P
SDA 5273 S
SDA 5275 S MEGATEXT IC (Preliminary Data). Features: Single chip teletext IC; Analog CVBS-input with onchip clamping circuitry; Slicer; Supports level 1, 2 and 3 WST-systems; Stores up to 14 teletext pages on chip; Stores up to 2048 teletext pages with external 16 M memory; Multinorm acquisition.
New Update 09.97
303 K 09.97

SDA 5275 Megatext(TM) plus (SDA 5275) is a dedicated consumer electronics data processing and on screen display (OSD) integrated circuit. Main features are: WST Level 2.5 teletext processing, more DRCS (>1000), full user definable CLUT and more. This document contains the description of the enhanced software features compared to the SDA 5273. Application Notes for common programming tasks are included. 453 K 01.97

SDA 5275-2 Valid for Version C01-11 and up 170 K 12.97

SDA 5273-2C Compacttext, Delta Specification, Application Note, Version B50-13. 277 K 07.97

SDA 5642 Single chip VPS Decoder (Preliminary Data). Features: micro C suitable VPS data editing direct from CVBS signal; n-channel MOS; Generating of the line synchronous 5-MHz clock for the time base and data clock by means of PLL operation; Very few external components necessary; Adaptative data separation; Frame signal recognition; Decoder for line 16 Bi-phase and start code checking; I² C-Bus interface; Operating voltage: 5 V; Video input signal level 1 ... 2.0 V pp 672 K 08.93

SDA 5642X

SDA 5642-6 On chip data slicer. Low external component count. I²C-Bus interface (communication with external microcontroller). 5 V supply voltage. Video input signal level: 0.7 Vpp to 2.0 Vpp. Technology: CMOS. P-DIP-14-1 and P-DSO-20-1 package. 688 K 02.97

SDA 5650/X Single chip receiver for PDC data for Broadcast Data Service Packet. Reception of BDSP packet 8/30/1. Reception of teletext header row. On chip data slicer. Low external component count. I²C-Bus interface (communication with external microcontroller). PDC/VPS operation mode selectable via I²C-Bus register. Pin and software compatible to PDC/VPS decoder SDA 5649. 5 V supply voltage. Video input signal level: 0.7 Vpp to 2.0 Vpp. Technology: CMOS. P-DIP-14-1 and P-DSO-20-1 package. 752 K 02.97

SDA 5648 Single chip VPS/PDC Decoder. Decoder for Program Delivery Control and Video Program System. Features: Single-chip receiver for PDC data, broadcast either in Broadcast Data Service Packet (BDSP) 8/30/2 according to CCIR teletext system B, or in dedicated line no. 16 of the vertical blanking interval (VPS). 485 K 12.94

SDA 5648X

SDA 5649 Single chip VPS/PDC Decoder. Expanded Decoder for Program Delivery Control and Video Program System EPDC / VPS Decoder. Features: Single-chip receiver for PDC data, broadcast either in Broadcast Data Service Packet (BDSP) 8/30/2 according to CCIR teletext system B, or in dedicated line no. 16 of the vertical blanking interval (VPS); Reception of Unified Date and Time (UDT), Network Identification code (NIC), and Short Program Label (SPL) broadcast in BDSP 8/30/1; Reception of bytes no.38 through 45 of teletext header row containing clock time. 512 K 12.94

SDA 5649X

MEGATEXT, VPS/PDC
Type	Features	PDF Size	Status
SDA 5273 P SDA 5275 P SDA 5273 S SDA 5275 S	MEGATEXT IC (Preliminary Data). Features: Single chip teletext IC; Analog CVBS-input with onchip clamping circuitry; Slicer; Supports level 1, 2 and 3 WST-systems; Stores up to 14 teletext pages on chip; Stores up to 2048 teletext pages with external 16 M memory; Multinorm acquisition. New Update 09.97	303 K	09.97
SDA 5275	Megatext(TM) plus (SDA 5275) is a dedicated consumer electronics data processing and on screen display (OSD) integrated circuit. Main features are: WST Level 2.5 teletext processing, more DRCS (>1000), full user definable CLUT and more. This document contains the description of the enhanced software features compared to the SDA 5273. Application Notes for common programming tasks are included.	453 K	01.97
SDA 5275-2	Valid for Version C01-11 and up	170 K	12.97
SDA 5273-2C	Compacttext, Delta Specification, Application Note, Version B50-13.	277 K	07.97
SDA 5642	Single chip VPS Decoder (Preliminary Data). Features: micro C suitable VPS data editing direct from CVBS signal; n-channel MOS; Generating of the line synchronous 5-MHz clock for the time base and data clock by means of PLL operation; Very few external components necessary; Adaptative data separation; Frame signal recognition; Decoder for line 16 Bi-phase and start code checking; I² C-Bus interface; Operating voltage: 5 V; Video input signal level 1 ... 2.0 V pp	672 K	08.93
SDA 5642X
SDA 5642-6	On chip data slicer. Low external component count. I²C-Bus interface (communication with external microcontroller). 5 V supply voltage. Video input signal level: 0.7 Vpp to 2.0 Vpp. Technology: CMOS. P-DIP-14-1 and P-DSO-20-1 package.	688 K	02.97
SDA 5650/X	Single chip receiver for PDC data for Broadcast Data Service Packet. Reception of BDSP packet 8/30/1. Reception of teletext header row. On chip data slicer. Low external component count. I²C-Bus interface (communication with external microcontroller). PDC/VPS operation mode selectable via I²C-Bus register. Pin and software compatible to PDC/VPS decoder SDA 5649. 5 V supply voltage. Video input signal level: 0.7 Vpp to 2.0 Vpp. Technology: CMOS. P-DIP-14-1 and P-DSO-20-1 package.	752 K	02.97
SDA 5648	Single chip VPS/PDC Decoder. Decoder for Program Delivery Control and Video Program System. Features: Single-chip receiver for PDC data, broadcast either in Broadcast Data Service Packet (BDSP) 8/30/2 according to CCIR teletext system B, or in dedicated line no. 16 of the vertical blanking interval (VPS).	485 K	12.94
SDA 5648X
SDA 5649	Single chip VPS/PDC Decoder. Expanded Decoder for Program Delivery Control and Video Program System EPDC / VPS Decoder. Features: Single-chip receiver for PDC data, broadcast either in Broadcast Data Service Packet (BDSP) 8/30/2 according to CCIR teletext system B, or in dedicated line no. 16 of the vertical blanking interval (VPS); Reception of Unified Date and Time (UDT), Network Identification code (NIC), and Short Program Label (SPL) broadcast in BDSP 8/30/1; Reception of bytes no.38 through 45 of teletext header row containing clock time.	512 K	12.94
SDA 5649X

MEGATEXT Volume 1

Topic PDF Size Status

Getting Started 105 K 10.94

Index 41 K 10.94

Hardware Functions 165 K 10.94

Firmware Overview 50 K 10.94

M3L-Bus Registers 732 K 10.94

ACQ Reference 252 K 10.94

Command Interface 1 MB 10.94

Display Functions 2.7 MB 10.94

Display Registers 226 K 10.94

MEGATEXT Volume 1
Topic	PDF Size	Status
Getting Started	105 K	10.94
Index	41 K	10.94
Hardware Functions	165 K	10.94
Firmware Overview	50 K	10.94
M3L-Bus Registers	732 K	10.94
ACQ Reference	252 K	10.94
Command Interface	1 MB	10.94
Display Functions	2.7 MB	10.94
Display Registers	226 K	10.94

MEGATEXT Volume 2

Topic PDF Size Status

Serial Bus Interface 84 K 10.94

Sync Applications 150 K 10.94

Crystal Oscillator 53 K 10.94

Slicer 20 K 10.94

Display Applications 25 K 10.94

DRAM 125 K 10.94

M3L-Register Control Routines 214 K 07.94

Software Development Tools 70 K 07.97

Display Register Control Routines 932 K 10.94

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Topic	PDF Size	Status
MEGATEXT Volume 2
Serial Bus Interface	84 K	10.94
Sync Applications	150 K	10.94
Crystal Oscillator	53 K	10.94
Slicer	20 K	10.94
Display Applications	25 K	10.94
DRAM	125 K	10.94
M3L-Register Control Routines	214 K	07.94
Software Development Tools	70 K	07.97
Display Register Control Routines	932 K	10.94