/**
  ******************************************************************************
  * @file    stm32c562xx.h
  * @brief   CMSIS STM32C562xx Device Peripheral Access Layer Header File.
  *
  *          This file contains:
  *           - Data structures and the address mapping for all peripherals
  *           - Peripheral's registers declarations and bits definition
  *           - Macros to access peripheral's registers hardware
  *
  ******************************************************************************
  * @attention
  *
  * Copyright (c) 2026 STMicroelectronics.
  * All rights reserved.
  *
  * This software is licensed under terms that can be found in the LICENSE file
  * in the root directory of this software component.
  * If no LICENSE file comes with this software, it is provided AS-IS.
  *
  ******************************************************************************
  */

#ifndef STM32C562xx_H
#define STM32C562xx_H

#ifdef __cplusplus
extern "C" {
#endif

/** @addtogroup ST
  * @{
  */


/** @addtogroup STM32C562xx
  * @{
  */


/** @addtogroup Configuration_of_CMSIS
  * @{
  */


/* ================================================================================================================== */
/* ==========                                 Interrupt Number Definition                                  ========== */
/* ================================================================================================================== */

typedef enum
{
/* ==================================  ARM Cortex-M33 Specific Interrupt Numbers  =================================== */
  Reset_IRQn                 = -15, /*!< -15 Reset                                                                    */
  NonMaskableInt_IRQn        = -14, /*!< -14 Non maskable interrupt. The RCC Clock Security System (CSS) is linked to
                                             the NMI vector.                                                          */
  HardFault_IRQn             = -13, /*!< -13 Hard fault                                                               */
  MemoryManagement_IRQn      = -12, /*!< -12 Memory management                                                        */
  BusFault_IRQn              = -11, /*!< -11 Pre-fetch fault, memory access fault                                     */
  UsageFault_IRQn            = -10, /*!< -10 Undefined instruction or illegal state                                   */
  SVCall_IRQn                =  -5, /*!<  -5 System service call via SWI instruction                                  */
  DebugMonitor_IRQn          =  -4, /*!<  -4 Debug monitor                                                            */
  PendSV_IRQn                =  -2, /*!<  -2 Pendable request for system service                                      */
  SysTick_IRQn               =  -1, /*!<  -1 System tick timer                                                        */
/* ==================================  STM32C562xx Specific Interrupt Numbers  ================================= */
  WWDG_IRQn                  =   0, /*!< Window Watchdog interrupt                                                    */
  PWR_PVD_IRQn               =   1, /*!< Power Voltage Monitor                                                        */
  RTC_IRQn                   =   2, /*!< RTC global non-secure interrupts                                             */
  TAMP_IRQn                  =   3, /*!< Tamper global interrupts                                                     */
  RAMCFG_IRQn                =   4, /*!< RAM configuration global interrupt                                           */
  FLASH_IRQn                 =   5, /*!< Flash non-secure global interrupt                                            */
  RCC_IRQn                   =   6, /*!< RCC non-secure global interrupt                                              */
  EXTI0_IRQn                 =   7, /*!< EXTI Line0 interrupt                                                         */
  EXTI1_IRQn                 =   8, /*!< EXTI Line1 interrupt                                                         */
  EXTI2_IRQn                 =   9, /*!< EXTI Line2 interrupt                                                         */
  EXTI3_IRQn                 =  10, /*!< EXTI Line3 interrupt                                                         */
  EXTI4_IRQn                 =  11, /*!< EXTI Line4 interrupt                                                         */
  EXTI5_IRQn                 =  12, /*!< EXTI Line5 interrupt                                                         */
  EXTI6_IRQn                 =  13, /*!< EXTI Line6 interrupt                                                         */
  EXTI7_IRQn                 =  14, /*!< EXTI Line7 interrupt                                                         */
  EXTI8_IRQn                 =  15, /*!< EXTI Line8 interrupt                                                         */
  EXTI9_IRQn                 =  16, /*!< EXTI Line9 interrupt                                                         */
  EXTI10_IRQn                =  17, /*!< EXTI Line10 interrupt                                                        */
  EXTI11_IRQn                =  18, /*!< EXTI Line11 interrupt                                                        */
  EXTI12_IRQn                =  19, /*!< EXTI Line12 interrupt                                                        */
  EXTI13_IRQn                =  20, /*!< EXTI Line13 interrupt                                                        */
  EXTI14_IRQn                =  21, /*!< EXTI Line14 interrupt                                                        */
  EXTI15_IRQn                =  22, /*!< EXTI Line15 interrupt                                                        */
  LPDMA1_CH0_IRQn            =  23, /*!< LPDMA1 channel0 global interrupt                                             */
  LPDMA1_CH1_IRQn            =  24, /*!< LPDMA1 channel1 global interrupt                                             */
  LPDMA1_CH2_IRQn            =  25, /*!< LPDMA1 channel2 global interrupt                                             */
  LPDMA1_CH3_IRQn            =  26, /*!< LPDMA1 channel3 global interrupt                                             */
  LPDMA1_CH4_IRQn            =  27, /*!< LPDMA1 channel4 global interrupt                                             */
  LPDMA1_CH5_IRQn            =  28, /*!< LPDMA1 channel5 global interrupt                                             */
  LPDMA1_CH6_IRQn            =  29, /*!< LPDMA1 channel6 global interrupt                                             */
  LPDMA1_CH7_IRQn            =  30, /*!< LPDMA1 channel7 global interrupt                                             */
  IWDG_IRQn                  =  31, /*!< Independent watchdog interrupt                                               */
  ADC1_IRQn                  =  32, /*!< ADC1 global interrupt                                                        */
  ADC2_IRQn                  =  33, /*!< ADC2 global interrupt                                                        */
  FDCAN1_IT0_IRQn            =  34, /*!< FDCAN1 Interrupt 0                                                           */
  FDCAN1_IT1_IRQn            =  35, /*!< FDCAN1 Interrupt 1                                                           */
  TIM1_BRK_TERR_IERR_IRQn    =  36, /*!< TIM1 Break/TIM1 Transition error/TIM1 Index error                            */
  TIM1_UPD_IRQn              =  37, /*!< TIM1 Update                                                                  */
  TIM1_TRGI_COM_DIR_IDX_IRQn =  38, /*!< TIM1 trigger and commutation/TIM1 Direction Change interrupt/TIM1 Index      */
  TIM1_CC_IRQn               =  39, /*!< TIM1 capture compare interrupt                                               */
  TIM2_IRQn                  =  40, /*!< TIM2 global interrupt                                                        */
  TIM5_IRQn                  =  41, /*!< TIM5 global interrupt                                                        */
  TIM6_IRQn                  =  42, /*!< TIM6 global interrupt                                                        */
  TIM7_IRQn                  =  43, /*!< TIM7 global interrupt                                                        */
  I2C1_EV_IRQn               =  44, /*!< I2C1 event interrupt                                                         */
  I2C1_ERR_IRQn              =  45, /*!< I2C1 error interrupt                                                         */
  I3C1_EV_IRQn               =  46, /*!< I3C1 event interrupt                                                         */
  I3C1_ERR_IRQn              =  47, /*!< I3C1 error interrupt                                                         */
  SPI1_IRQn                  =  48, /*!< SPI1 global interrupt                                                        */
  SPI2_IRQn                  =  49, /*!< SPI2 global interrupt                                                        */
  SPI3_IRQn                  =  50, /*!< SPI3 global interrupt                                                        */
  USART1_IRQn                =  51, /*!< USART1 global interrupt                                                      */
  USART2_IRQn                =  52, /*!< USART2 global interrupt                                                      */
  USART3_IRQn                =  53, /*!< USART3 global interrupt                                                      */
  UART4_IRQn                 =  54, /*!< UART4 global interrupt                                                       */
  UART5_IRQn                 =  55, /*!< UART5 global interrupt                                                       */
  LPUART1_IRQn               =  56, /*!< LPUART1 Rx interrupt OR LPUART1 Tx interrupt                                 */
  LPTIM1_IRQn                =  57, /*!< LPTIM1 global interrupt                                                      */
  TIM12_IRQn                 =  58, /*!< TIM12 global interrupt                                                       */
  TIM15_IRQn                 =  59, /*!< TIM15 global interrupt                                                       */
  TIM16_IRQn                 =  60, /*!< TIM16 global interrupt                                                       */
  TIM17_IRQn                 =  61, /*!< TIM17 global interrupt                                                       */
  USB_DRD_FS_IRQn            =  62, /*!< USB OTG FS global interrupt                                                  */
  CRS_IRQn                   =  63, /*!< Clock Recovery System global interrupt                                       */
  RNG_IRQn                   =  64, /*!< RNG global interrupt                                                         */
  FPU_IRQn                   =  65, /*!< Floating point interrupt                                                     */
  ICACHE_IRQn                =  66, /*!< Instruction cache global interrupt                                           */
  CORDIC_IRQn                =  67, /*!< CORDIC interrupt                                                             */
  AES_IRQn                   =  68, /*!< AES global interrupt                                                         */
  HASH_IRQn                  =  69, /*!< HASH interrupt                                                               */
  I2C2_EV_IRQn               =  70, /*!< I2C2 event interrupt                                                         */
  I2C2_ERR_IRQn              =  71, /*!< I2C2 error interrupt                                                         */
  TIM8_BRK_TERR_IERR_IRQn    =  72, /*!< TIM8 Break interrupt/TIM8 Transition error/TIM8 Index error                  */
  TIM8_UPD_IRQn              =  73, /*!< TIM8 Update interrupt                                                        */
  TIM8_TRGI_COM_DIR_IDX_IRQn =  74, /*!< TIM8 trigger and commutation interrupt/TIM8 Direction Change interrupt/TIM8
                                         Index                                                                        */
  TIM8_CC_IRQn               =  75, /*!< TIM8 capture compare interrupt                                               */
  COMP1_IRQn                 =  76, /*!< COMP global interrupt                                                        */
  DAC1_IRQn                  =  77, /*!< DAC1 global interrupt                                                        */
  LPDMA2_CH0_IRQn            =  78, /*!< LPDMA2 channel0 global interrupt                                             */
  LPDMA2_CH1_IRQn            =  79, /*!< LPDMA2 channel1 global interrupt                                             */
  LPDMA2_CH2_IRQn            =  80, /*!< LPDMA2 channel2 global interrupt                                             */
  LPDMA2_CH3_IRQn            =  81, /*!< LPDMA2 channel3 global interrupt                                             */
} IRQn_Type;

/* ================================================================================================================== */
/* ================                       Processor and Core Peripheral Section                      ================ */
/* ================================================================================================================== */

/* -------  Start of section using anonymous unions and disabling warnings  ------- */
#if   defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif /*__CC_ARM */

/* --------  Configuration of the Cortex-M33 Processor and Core Peripherals  ---------------- */
#define __CM33_REV                0x0004U   /*!< Cortex-M33 revision r0p4_p1                  */
#define __SAUREGION_PRESENT       0U        /*!< SAU regions not present                      */
#define __MPU_PRESENT             1U        /*!< MPU present                                  */
#define __VTOR_PRESENT            1U        /*!< VTOR present                                 */
#define __NVIC_PRIO_BITS          4U        /*!< Number of Bits used for Priority Levels      */
#define __Vendor_SysTickConfig    0U        /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT             1U        /*!< FPU present                                  */
#define __DSP_PRESENT             1U        /*!< DSP extension present                        */

/** @} */ /* End of group Configuration_of_CMSIS */

#include <core_cm33.h>                       /*!< ARM Cortex-M33 processor and core peripherals */
#include "system_stm32c5xx.h"                /*!< STM32C5xx System */


/* ================================================================================================================== */
/* ================                         Device Specific Peripheral Section                       ================ */
/* ================================================================================================================== */


/** @addtogroup STM32C5xx_peripherals
  * @{
  */

/**
  * @brief ADC Analog to Digital Converter
  */
typedef struct
{
  __IOM uint32_t ISR;          /*!< ADC interrupt and status register,                     Address offset: 0x000 */
  __IOM uint32_t IER;          /*!< ADC interrupt enable register,                         Address offset: 0x004 */
  __IOM uint32_t CR;           /*!< ADC control register,                                  Address offset: 0x008 */
  __IOM uint32_t CFGR1;        /*!< ADC configuration register 1,                          Address offset: 0x00C */
  __IOM uint32_t CFGR2;        /*!< ADC configuration register 2,                          Address offset: 0x010 */
  __IOM uint32_t SMPR1;        /*!< ADC sample time register 1,                            Address offset: 0x014 */
  __IOM uint32_t SMPR2;        /*!< ADC sample time register 2,                            Address offset: 0x018 */
  __IOM uint32_t PCSEL;        /*!< ADC channel preselection register,                     Address offset: 0x01C */
        uint32_t RESERVED1[4]; /*!< Reserved,                                              Address offset: 0x020 */
  __IOM uint32_t SQR1;         /*!< ADC regular sequence register 1,                       Address offset: 0x030 */
  __IOM uint32_t SQR2;         /*!< ADC regular sequence register 2,                       Address offset: 0x034 */
  __IOM uint32_t SQR3;         /*!< ADC regular sequence register 3,                       Address offset: 0x038 */
  __IOM uint32_t SQR4;         /*!< ADC regular sequence register 4,                       Address offset: 0x03C */
  __IM  uint32_t DR;           /*!< ADC regular data register,                             Address offset: 0x040 */
        uint32_t RESERVED2[2]; /*!< Reserved,                                              Address offset: 0x044 */
  __IOM uint32_t JSQR;         /*!< ADC injected sequence register,                        Address offset: 0x04C */
  __IOM uint32_t OFCFGR[4];    /*!< ADC offset configuration register                      Address offset: 0x050 */
  __IOM uint32_t OFR[4];       /*!< ADC offset register                                    Address offset: 0x060 */
  __IOM uint32_t GCOMP;        /*!< ADC gain compensation register,                        Address offset: 0x070 */
        uint32_t RESERVED3[3]; /*!< Reserved,                                              Address offset: 0x074 */
  __IM  uint32_t JDR[4];       /*!< ADC injected channel data register                     Address offset: 0x080 */
        uint32_t RESERVED4[4]; /*!< Reserved,                                              Address offset: 0x090 */
  __IOM uint32_t AWD2CR;       /*!< ADC analog watchdog 2 configuration register,          Address offset: 0x0A0 */
  __IOM uint32_t AWD3CR;       /*!< ADC analog watchdog 3 configuration register,          Address offset: 0x0A4 */
  __IOM uint32_t AWD1LTR;      /*!< ADC analog watchdog 1 lower threshold register,        Address offset: 0x0A8 */
  __IOM uint32_t AWD1HTR;      /*!< ADC analog watchdog 1 higher threshold register,       Address offset: 0x0AC */
  __IOM uint32_t AWD2LTR;      /*!< ADC analog watchdog 2 lower threshold register,        Address offset: 0x0B0 */
  __IOM uint32_t AWD2HTR;      /*!< ADC analog watchdog 2 higher threshold register,       Address offset: 0x0B4 */
  __IOM uint32_t AWD3LTR;      /*!< ADC analog watchdog 3 lower threshold register,        Address offset: 0x0B8 */
  __IOM uint32_t AWD3HTR;      /*!< ADC analog watchdog 3 higher threshold register,       Address offset: 0x0BC */
        uint32_t RESERVED5;    /*!< Reserved,                                              Address offset: 0x0C0 */
  __IOM uint32_t CALFACT;      /*!< ADC calibration factors,                               Address offset: 0x0C4 */
} ADC_TypeDef;

typedef struct
{
  __IM  uint32_t CSR;          /*!< ADC common status register,                            Address offset: 0x000 */
        uint32_t RESERVED;     /*!< Reserved,                                              Address offset: 0x004 */
  __IOM uint32_t CCR;          /*!< ADC common control register,                           Address offset: 0x008 */
  __IM  uint32_t CDR;          /*!< ADC common regular data register for dual mode,        Address offset: 0x00C */
  __IM  uint32_t CDR2;         /*!< ADC common regular data register for dual mode,        Address offset: 0x010 */
} ADC_Common_TypeDef;

/**
  * @brief AES hardware accelerator (AES)
  */
typedef struct
{
  __IOM uint32_t CR;              /*!< AES control register,                                    Address offset: 0x000 */
  __IM  uint32_t SR;              /*!< AES status register,                                     Address offset: 0x004 */
  __OM  uint32_t DINR;            /*!< AES data input register,                                 Address offset: 0x008 */
  __IM  uint32_t DOUTR;           /*!< AES data output register,                                Address offset: 0x00C */
  __OM  uint32_t KEYR0;           /*!< AES key register 0,                                      Address offset: 0x010 */
  __OM  uint32_t KEYR1;           /*!< AES key register 1,                                      Address offset: 0x014 */
  __OM  uint32_t KEYR2;           /*!< AES key register 2,                                      Address offset: 0x018 */
  __OM  uint32_t KEYR3;           /*!< AES key register 3,                                      Address offset: 0x01C */
  __IOM uint32_t IVR0;            /*!< AES initialization vector register 0,                    Address offset: 0x020 */
  __IOM uint32_t IVR1;            /*!< AES initialization vector register 1,                    Address offset: 0x024 */
  __IOM uint32_t IVR2;            /*!< AES initialization vector register 2,                    Address offset: 0x028 */
  __IOM uint32_t IVR3;            /*!< AES initialization vector register 3,                    Address offset: 0x02C */
  __OM  uint32_t KEYR4;           /*!< AES key register 4,                                      Address offset: 0x030 */
  __OM  uint32_t KEYR5;           /*!< AES key register 5,                                      Address offset: 0x034 */
  __OM  uint32_t KEYR6;           /*!< AES key register 6,                                      Address offset: 0x038 */
  __OM  uint32_t KEYR7;           /*!< AES key register 7,                                      Address offset: 0x03C */
  __IOM uint32_t SUSPR0;          /*!< AES suspend registers,                                   Address offset: 0x040 */
  __IOM uint32_t SUSPR1;          /*!< AES suspend registers,                                   Address offset: 0x044 */
  __IOM uint32_t SUSPR2;          /*!< AES suspend registers,                                   Address offset: 0x048 */
  __IOM uint32_t SUSPR3;          /*!< AES suspend registers,                                   Address offset: 0x04C */
  __IOM uint32_t SUSPR4;          /*!< AES suspend registers,                                   Address offset: 0x050 */
  __IOM uint32_t SUSPR5;          /*!< AES suspend registers,                                   Address offset: 0x054 */
  __IOM uint32_t SUSPR6;          /*!< AES suspend registers,                                   Address offset: 0x058 */
  __IOM uint32_t SUSPR7;          /*!< AES suspend registers,                                   Address offset: 0x05C */
        uint32_t RESERVED1[168];  /*!< Reserved,                                                Address offset: 0x060 */
  __IOM uint32_t IER;             /*!< AES interrupt enable register,                           Address offset: 0x300 */
  __IM  uint32_t ISR;             /*!< AES interrupt status register,                           Address offset: 0x304 */
  __OM  uint32_t ICR;             /*!< AES interrupt clear register,                            Address offset: 0x308 */
} AES_TypeDef;

/**
  * @brief Comparator
  */
typedef struct
{
  __IM  uint32_t SR;         /*!< Comparator status register,                   Address offset: 0x00 */
  __IOM uint32_t ICFR;       /*!< Comparator interrupt clear flag register,     Address offset: 0x04 */
        uint32_t RESERVED1;  /*!< Reserved,                                     Address offset: 0x08 */
  __IOM uint32_t CFGR1;      /*!< Comparator configuration register 1,          Address offset: 0x0C */
  __IOM uint32_t CFGR2;      /*!< Comparator configuration register 2,          Address offset: 0x10 */
} COMP_TypeDef;

/**
  * @brief CORDIC
  */
typedef struct
{
  __IOM uint32_t CSR;            /*!< CORDIC control and status register,        Address offset: 0x00 */
  __OM  uint32_t WDATA;          /*!< CORDIC argument register,                  Address offset: 0x04 */
  __IM  uint32_t RDATA;          /*!< CORDIC result register,                    Address offset: 0x08 */
} CORDIC_TypeDef;

/**
  * @brief CRC calculation unit
  */
typedef struct
{
  __IOM  uint32_t DR;               /*!< CRC Data register,                                   Address offset: 0x00 */
  __IOM  uint32_t IDR;              /*!< CRC Independent data register,                       Address offset: 0x04 */
  __IOM  uint32_t CR;               /*!< CRC Control register,                                Address offset: 0x08 */
         uint32_t RESERVED1;        /*!< Reserved,                                            Address offset: 0x0C */
  __IOM  uint32_t INIT;             /*!< Initial CRC value register,                          Address offset: 0x10 */
  __IOM  uint32_t POL;              /*!< CRC polynomial register,                             Address offset: 0x14 */
} CRC_TypeDef;

/**
  * @brief Clock Recovery System
  */
typedef struct
{
  __IOM uint32_t CR;           /*!< CRS control register,                           Address offset: 0x00 */
  __IOM uint32_t CFGR;         /*!< CRS configuration register,                     Address offset: 0x04 */
  __IM  uint32_t ISR;          /*!< CRS interrupt and status register,              Address offset: 0x08 */
  __IOM uint32_t ICR;          /*!< CRS interrupt flag clear register,              Address offset: 0x0C */
} CRS_TypeDef;

/**
  * @brief Digital to Analog Converter
  */
typedef struct
{
  __IOM uint32_t CR;            /*!< DAC control register,                                     Address offset: 0x000 */
  __OM  uint32_t SWTRGR;        /*!< DAC software trigger register,                            Address offset: 0x004 */
  __IOM uint32_t DHR12R1;       /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x008 */
  __IOM uint32_t DHR12L1;       /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x00C */
  __IOM uint32_t DHR8R1;        /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x010 */
        uint32_t RESERVED1[6];  /*!< Reserved,                                                 Address offset: 0x014 */
  __IM  uint32_t DOR1;          /*!< DAC channel1 data output register,                        Address offset: 0x02C */
        uint32_t RESERVED2;     /*!< Reserved,                                                 Address offset: 0x030 */
  __IOM uint32_t SR;            /*!< DAC status register,                                      Address offset: 0x034 */
  __IOM uint32_t CCR;           /*!< DAC calibration control register,                         Address offset: 0x038 */
  __IOM uint32_t MCR;           /*!< DAC mode control register,                                Address offset: 0x03C */
  __IOM uint32_t SHSR1;         /*!< DAC channel1 sample and hold sample time register,        Address offset: 0x040 */
        uint32_t RESERVED3;     /*!< Reserved,                                                 Address offset: 0x044 */
  __IOM uint32_t SHHR;          /*!< DAC sample and hold time register,                        Address offset: 0x048 */
  __IOM uint32_t SHRR;          /*!< DAC sample and hold refresh time register,                Address offset: 0x04C */
} DAC_TypeDef;

/**
  * @brief Debug MCU (DBGMCU)
  */
typedef struct
{
  __IM  uint32_t IDCODE;          /*!< DBGMCU identity code register,                           Address offset: 0x000 */
  __IOM uint32_t CR;              /*!< DBGMCU configuration register,                           Address offset: 0x004 */
  __IOM uint32_t APB1LFZR;        /*!< DBGMCU APB1L peripheral freeze register,                 Address offset: 0x008 */
  __IOM uint32_t APB1HFZR;        /*!< Debug MCU APB1 freeze register 2,                        Address offset: 0x00C */
  __IOM uint32_t APB2FZR;         /*!< DBGMCU APB2 peripheral freeze register,                  Address offset: 0x010 */
  __IOM uint32_t APB3FZR;         /*!< DBGMCU APB3 peripheral freeze register,                  Address offset: 0x014 */
        uint32_t RESERVED2[2];    /*!< Reserved,                                                Address offset: 0x018 */
  __IOM uint32_t AHB1FZR;         /*!< DBGMCU AHB1 peripheral freeze register,                  Address offset: 0x020 */
        uint32_t RESERVED3[54];   /*!< Reserved,                                                Address offset: 0x024 */
  __OM  uint32_t SR;              /*!< DBGMCU status register,                                  Address offset: 0x0FC */
  __IOM uint32_t DBG_AUTH_HOST;   /*!< DBGMCU debug authentication mailbox host register,       Address offset: 0x100 */
  __IM  uint32_t DBG_AUTH_DEVICE; /*!< DBGMCU debug authentication mailbox device register,     Address offset: 0x104 */
        uint32_t RESERVED4;       /*!< Reserved,                                                Address offset: 0x108 */
  __IOM uint32_t DBG_BSKEY_PWD;   /*!< DBGMCU boundary-scan key password register,              Address offset: 0x10C */
  __IM  uint32_t DBG_VALR;        /*!< DBGMCU debug OEMKEY validation register,                 Address offset: 0x110 */
        uint32_t RESERVED5[943];  /*!< Reserved,                                                Address offset: 0x114 */
  __IM  uint32_t PIDR4;           /*!< DBGMCU CoreSight peripheral identity register 4,         Address offset: 0xFD0 */
        uint32_t RESERVED6[3];    /*!< Reserved,                                                Address offset: 0xFD4 */
  __IM  uint32_t PIDR0;           /*!< DBGMCU CoreSight peripheral identity register 0,         Address offset: 0xFE0 */
  __IM  uint32_t PIDR1;           /*!< DBGMCU CoreSight peripheral identity register 1,         Address offset: 0xFE4 */
  __IM  uint32_t PIDR2;           /*!< DBGMCU CoreSight peripheral identity register 2,         Address offset: 0xFE8 */
  __IM  uint32_t PIDR3;           /*!< DBGMCU CoreSight peripheral identity register 3,         Address offset: 0xFEC */
  __IM  uint32_t CIDR0;           /*!< DBGMCU CoreSight component identity register 0,          Address offset: 0xFF0 */
  __IM  uint32_t CIDR1;           /*!< DBGMCU CoreSight component identity register 1,          Address offset: 0xFF4 */
  __IM  uint32_t CIDR2;           /*!< DBGMCU CoreSight component identity register 2,          Address offset: 0xFF8 */
  __IM  uint32_t CIDR3;           /*!< DBGMCU CoreSight component identity register 3,          Address offset: 0xFFC */
} DBGMCU_TypeDef;

/**
  * @brief DMA Controller (DMA)
  */
typedef struct
{
        uint32_t RESERVED1;     /*!< Reserved 1,                                      Address offset: 0x00 */
  __IOM uint32_t PRIVCFGR;      /*!< DMA privileged configuration register,           Address offset: 0x04 */
  __IOM uint32_t RCFGLOCKR;     /*!< DMA configuration lock register,                 Address offset: 0x08 */
  __IM  uint32_t MISR;          /*!< DMA masked interrupt status register,            Address offset: 0x0C */
        uint32_t RESERVED2;     /*!< Reserved 2,                                      Address offset: 0x10 */
} DMA_TypeDef;

typedef struct
{
  __IOM uint32_t CLBAR;          /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */
        uint32_t RESERVED1[2];   /*!< Reserved 1,                                      Address offset: 0x54 -- 0x58      */
  __OM  uint32_t CFCR;           /*!< DMA channel x flag clear register,               Address offset: 0x5C + (x * 0x80) */
  __IM  uint32_t CSR;            /*!< DMA channel x flag status register,              Address offset: 0x60 + (x * 0x80) */
  __IOM uint32_t CCR;            /*!< DMA channel x control register,                  Address offset: 0x64 + (x * 0x80) */
        uint32_t RESERVED2[10];  /*!< Reserved 2,                                      Address offset: 0x68 -- 0x8C      */
  __IOM uint32_t CTR1;           /*!< DMA channel x transfer register 1,               Address offset: 0x90 + (x * 0x80) */
  __IOM uint32_t CTR2;           /*!< DMA channel x transfer register 2,               Address offset: 0x94 + (x * 0x80) */
  __IOM uint32_t CBR1;           /*!< DMA channel x block register 1,                  Address offset: 0x98 + (x * 0x80) */
  __IOM uint32_t CSAR;           /*!< DMA channel x source address register,           Address offset: 0x9C + (x * 0x80) */
  __IOM uint32_t CDAR;           /*!< DMA channel x destination address register,      Address offset: 0xA0 + (x * 0x80) */
        uint32_t RESERVED3[10];  /*!< Reserved 3,                                      Address offset: 0xA4 -- 0xC8      */
  __IOM uint32_t CLLR;           /*!< DMA channel x linked-list address register,      Address offset: 0xCC + (x * 0x80) */
} DMA_Channel_TypeDef;

/**
  * @brief Extended interrupts and event controller (EXTI)
  */
typedef struct
{
  __IOM uint32_t RTSR1;          /*!< EXTI Rising Trigger Selection Register 1,        Address offset:   0x000 */
  __IOM uint32_t FTSR1;          /*!< EXTI Falling Trigger Selection Register 1,       Address offset:   0x004 */
  __IOM uint32_t SWIER1;         /*!< EXTI Software Interrupt event Register 1,        Address offset:   0x008 */
  __IOM uint32_t RPR1;           /*!< EXTI Rising Pending Register 1,                  Address offset:   0x00C */
  __IOM uint32_t FPR1;           /*!< EXTI Falling Pending Register 1,                 Address offset:   0x010 */
        uint32_t RESERVED1;      /*!< Reserved,                                        Address offset:   0x014 */
  __IOM uint32_t PRIVCFGR1;      /*!< EXTI Privilege Configuration Register 1,         Address offset:   0x018 */
        uint32_t RESERVED2;      /*!< Reserved,                                        Address offset:   0x01C */
  __IOM uint32_t RTSR2;          /*!< EXTI Rising Trigger Selection Register 2,        Address offset:   0x020 */
  __IOM uint32_t FTSR2;          /*!< EXTI Falling Trigger Selection Register 2,       Address offset:   0x024 */
  __IOM uint32_t SWIER2;         /*!< EXTI Software Interrupt event Register 2,        Address offset:   0x028 */
  __IOM uint32_t RPR2;           /*!< EXTI Rising Pending Register 2,                  Address offset:   0x02C */
  __IOM uint32_t FPR2;           /*!< EXTI Falling Pending Register 2,                 Address offset:   0x030 */
        uint32_t RESERVED3;      /*!< Reserved,                                        Address offset:   0x034 */
  __IOM uint32_t PRIVCFGR2;      /*!< EXTI Privilege Configuration Register 2,         Address offset:   0x038 */
        uint32_t RESERVED4[9];   /*!< Reserved,                                        Address offset:   0x03C */
  __IOM uint32_t EXTICR[4];      /*!< EXIT External Interrupt Configuration Register,  Address offset:   0x060 */
        uint32_t RESERVED5[4];   /*!< Reserved,                                        Address offset:   0x070 */
  __IOM uint32_t IMR1;           /*!< EXTI Interrupt Mask Register 1,                  Address offset:   0x080 */
  __IOM uint32_t EMR1;           /*!< EXTI Event Mask Register 1,                      Address offset:   0x084 */
        uint32_t RESERVED6[2];   /*!< Reserved,                                        Address offset:   0x088 */
  __IOM uint32_t IMR2;           /*!< EXTI Interrupt Mask Register 2,                  Address offset:   0x090 */
  __IOM uint32_t EMR2;           /*!< EXTI Event Mask Register 2,                      Address offset:   0x094 */
} EXTI_TypeDef;

/**
  * @brief FD Controller Area Network
  */
typedef struct
{
  __IM  uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
  __IM  uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */
        uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */
  __IOM uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
  __IOM uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */
  __IOM uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
  __IOM uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
  __IOM uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
  __IOM uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
  __IOM uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
  __IOM uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
  __IOM uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
        uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */
  __IM  uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
  __IM  uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
  __IOM uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
        uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */
  __IOM uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
  __IOM uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
  __IOM uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
  __IOM uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
        uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */
  __IOM uint32_t RXGFC;        /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
  __IOM uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x084 */
  __IM  uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x088 */
        uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */
  __IM  uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x090 */
  __IOM uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x094 */
  __IM  uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x098 */
  __IOM uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x09C */
        uint32_t RESERVED6[8]; /*!< Reserved,                                                                0x0A0 - 0x0BC */
  __IOM uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
  __IM  uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
  __IM  uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0C8 */
  __IOM uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0CC */
  __IOM uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D0 */
  __IM  uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D4 */
  __IM  uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0D8 */
  __IOM uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0DC */
  __IOM uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
  __IM  uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0E4 */
  __IOM uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0E8 */
} FDCAN_GlobalTypeDef;

/**
  * @brief FD Controller Area Network Configuration
  */
typedef struct
{
  __IOM uint32_t CKDIV;        /*!< FDCAN clock divider register,                            Address offset: 0x100 + 0x000 */
} FDCAN_Config_TypeDef;

/**
  * @brief FLASH Registers
  */
typedef struct
{
  __IOM uint32_t ACR;             /*!< FLASH access control register,                           Address offset: 0x000 */
  __OM  uint32_t KEYR;            /*!< FLASH key register,                                      Address offset: 0x004 */
        uint32_t RESERVED1;       /*!< Reserved,                                                Address offset: 0x008 */
  __OM  uint32_t OPTKEYR;         /*!< FLASH option key register,                               Address offset: 0x00C */
        uint32_t RESERVED2[2];    /*!< Reserved,                                                Address offset: 0x010 */
  __IM  uint32_t OPSR;            /*!< FLASH operation status register,                         Address offset: 0x018 */
  __IOM uint32_t OPTCR;           /*!< FLASH option control register,                           Address offset: 0x01C */
  __IM  uint32_t SR;              /*!< FLASH status register,                                   Address offset: 0x020 */
        uint32_t RESERVED3;       /*!< Reserved,                                                Address offset: 0x024 */
  __IOM uint32_t CR;              /*!< FLASH control register,                                  Address offset: 0x028 */
        uint32_t RESERVED4;       /*!< Reserved,                                                Address offset: 0x02C */
  __OM  uint32_t CCR;             /*!< FLASH clear control register,                            Address offset: 0x030 */
        uint32_t RESERVED5[2];    /*!< Reserved,                                                Address offset: 0x034 */
  __IOM uint32_t PRIVCFGR;        /*!< FLASH privilege configuration register,                  Address offset: 0x03C */
        uint32_t RESERVED6[2];    /*!< Reserved,                                                Address offset: 0x040 */
  __IOM uint32_t HDPEXTR;         /*!< FLASH HDP extension register,                            Address offset: 0x048 */
        uint32_t RESERVED7;       /*!< Reserved,                                                Address offset: 0x04C */
  __IM  uint32_t OPTSR_CUR;       /*!< FLASH option status register,                            Address offset: 0x050 */
  __IOM uint32_t OPTSR_PRG;       /*!< FLASH option status register,                            Address offset: 0x054 */
        uint32_t RESERVED8[6];    /*!< Reserved,                                                Address offset: 0x058 */
  __IM  uint32_t OPTSR2_CUR;      /*!< FLASH option status register 2,                          Address offset: 0x070 */
  __IOM uint32_t OPTSR2_PRG;      /*!< FLASH option status register 2,                          Address offset: 0x074 */
        uint32_t RESERVED9[2];    /*!< Reserved,                                                Address offset: 0x078 */
  __IM  uint32_t BOOTR_CUR;       /*!< FLASH unique boot entry register,                        Address offset: 0x080 */
  __IOM uint32_t BOOTR_PRG;       /*!< FLASH unique boot entry address,                         Address offset: 0x084 */
        uint32_t RESERVED10[2];   /*!< Reserved,                                                Address offset: 0x088 */
  __IM  uint32_t OTPBLR_CUR;      /*!< FLASH OTP block lock,                                    Address offset: 0x090 */
  __IOM uint32_t OTPBLR_PRG;      /*!< FLASH OTP block lock,                                    Address offset: 0x094 */
  __IM  uint32_t BL_COM_CFG_CUR;  /*!< FLASH Bootloader interface selection,                    Address offset: 0x098 */
  __IOM uint32_t BL_COM_CFG_PRG;  /*!< FLASH Bootloader interface selection,                    Address offset: 0x09C */
        uint32_t RESERVED11;      /*!< Reserved,                                                Address offset: 0x0A0 */
  __OM  uint32_t OEMKEYR1_PRG;    /*!< FLASH OEM Key register 1,                                Address offset: 0x0A4 */
        uint32_t RESERVED12;      /*!< Reserved,                                                Address offset: 0x0A8 */
  __OM  uint32_t OEMKEYR2_PRG;    /*!< FLASH OEM Key register 2,                                Address offset: 0x0AC */
        uint32_t RESERVED13;      /*!< Reserved,                                                Address offset: 0x0B0 */
  __OM  uint32_t OEMKEYR3_PRG;    /*!< FLASH OEM Key register 3,                                Address offset: 0x0B4 */
        uint32_t RESERVED14;      /*!< Reserved,                                                Address offset: 0x0B8 */
  __OM  uint32_t OEMKEYR4_PRG;    /*!< FLASH OEM Key register 4,                                Address offset: 0x0BC */
        uint32_t RESERVED15;      /*!< Reserved,                                                Address offset: 0x0C0 */
  __OM  uint32_t BSKEYR_PRG;      /*!< FLASH Boundary Scan key register,                        Address offset: 0x0C4 */
        uint32_t RESERVED16[8];   /*!< Reserved,                                                Address offset: 0x0C8 */
  __IM  uint32_t WRP1R_CUR;       /*!< FLASH write page protection for bank1,                   Address offset: 0x0E8 */
  __IOM uint32_t WRP1R_PRG;       /*!< FLASH write page protection for bank1,                   Address offset: 0x0EC */
        uint32_t RESERVED17[2];   /*!< Reserved,                                                Address offset: 0x0F0 */
  __IM  uint32_t HDP1R_CUR;       /*!< FLASH HDP bank1 register,                                Address offset: 0x0F8 */
  __IOM uint32_t HDP1R_PRG;       /*!< FLASH HDP bank1 register,                                Address offset: 0x0FC */
  __IOM uint32_t ECCCORR;         /*!< FLASH ECC correction register,                           Address offset: 0x100 */
  __IOM uint32_t ECCDETR;         /*!< FLASH ECC detection register,                            Address offset: 0x104 */
  __IM  uint32_t ECCDR;           /*!< FLASH ECC data,                                          Address offset: 0x108 */
        uint32_t RESERVED18[55];  /*!< Reserved,                                                Address offset: 0x10C */
  __IM  uint32_t WRP2R_CUR;       /*!< FLASH write page protection for bank2,                   Address offset: 0x1E8 */
  __IOM uint32_t WRP2R_PRG;       /*!< FLASH write page protection for bank2,                   Address offset: 0x1EC */
        uint32_t RESERVED19[2];   /*!< Reserved,                                                Address offset: 0x1F0 */
  __IM  uint32_t HDP2R_CUR;       /*!< FLASH HDP bank2 register,                                Address offset: 0x1F8 */
  __IOM uint32_t HDP2R_PRG;       /*!< FLASH HDP bank2 register,                                Address offset: 0x1FC */
} FLASH_TypeDef;

/**
  * @brief General Purpose I/O (GPIO)
  */
typedef struct
{
  __IOM uint32_t MODER;           /*!< GPIO port mode register,                                 Address offset: 0x000 */
  __IOM uint32_t OTYPER;          /*!< GPIO port output type register,                          Address offset: 0x004 */
  __IOM uint32_t OSPEEDR;         /*!< GPIO port output speed register,                         Address offset: 0x008 */
  __IOM uint32_t PUPDR;           /*!< GPIO port pull-up/pull-down register,                    Address offset: 0x00C */
  __IM  uint32_t IDR;             /*!< GPIO port input data register,                           Address offset: 0x010 */
  __IOM uint32_t ODR;             /*!< GPIO port output data register,                          Address offset: 0x014 */
  __OM  uint32_t BSRR;            /*!< GPIO port bit set/reset register,                        Address offset: 0x018 */
  __IOM uint32_t LCKR;            /*!< GPIO port configuration lock register,                   Address offset: 0x01C */
  __IOM uint32_t AFR[2];          /*!< GPIO alternate function register,                        Address offset: 0x020 */
  __OM  uint32_t BRR;             /*!< GPIO port bit reset register,                            Address offset: 0x028 */
} GPIO_TypeDef;

/**
  * @brief Hash processor (HASH)
  */
typedef struct
{
  __IOM uint32_t CR;              /*!< HASH control register,                                   Address offset: 0x000 */
  __OM  uint32_t DIN;             /*!< HASH data input register,                                Address offset: 0x004 */
  __IOM uint32_t STR;             /*!< HASH start register,                                     Address offset: 0x008 */
  __IM  uint32_t HRA[5];          /*!< HASH digest registers,                                   Address offset: 0x00C */
  __IOM uint32_t IMR;             /*!< HASH interrupt enable register,                          Address offset: 0x020 */
  __IOM uint32_t SR;              /*!< HASH status register,                                    Address offset: 0x024 */
        uint32_t RESERVED1[52];   /*!< Reserved,                                                Address offset: 0x028 */
  __IOM uint32_t CSR[54];         /*!< HASH context swap register,                              Address offset: 0x0F8 */
        uint32_t RESERVED2[80];   /*!< Reserved,                                                Address offset: 0x1D0 */
  __IM  uint32_t HR[8];           /*!< HASH digest register,                                    Address offset: 0x310 */
} HASH_TypeDef;

/**
  * @brief Inter-integrated Circuit Interface
  */
typedef struct
{
  __IOM uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
  __IOM uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
  __IOM uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
  __IOM uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
  __IOM uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
  __IOM uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
  __IOM uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
  __OM  uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
  __IM  uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
  __IM  uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
  __IOM uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
} I2C_TypeDef;

/**
  * @brief Improved Inter-integrated Circuit Interface
  */
typedef struct
{
  __OM  uint32_t CR;             /*!< I3C Control register,                      Address offset: 0x00      */
  __IOM uint32_t CFGR;           /*!< I3C Controller Configuration register,     Address offset: 0x04      */
        uint32_t RESERVED1[2];   /*!< Reserved,                                  Address offset: 0x08-0x0C */
  __IM  uint32_t RDR;            /*!< I3C Received Data register,                Address offset: 0x10      */
  __IM  uint32_t RDWR;           /*!< I3C Received Data Word register,           Address offset: 0x14      */
  __OM  uint32_t TDR;            /*!< I3C Transmit Data register,                Address offset: 0x18      */
  __OM  uint32_t TDWR;           /*!< I3C Transmit Data Word register,           Address offset: 0x1C      */
  __IOM uint32_t IBIDR;          /*!< I3C IBI payload Data register,             Address offset: 0x20      */
  __IOM uint32_t TGTTDR;         /*!< I3C Target Transmit register,              Address offset: 0x24      */
        uint32_t RESERVED2[2];   /*!< Reserved,                                  Address offset: 0x28-0x2C */
  __IM  uint32_t SR;             /*!< I3C Status register,                       Address offset: 0x30      */
  __IM  uint32_t SER;            /*!< I3C Status Error register,                 Address offset: 0x34      */
        uint32_t RESERVED3[2];   /*!< Reserved,                                  Address offset: 0x38-0x3C */
  __IM  uint32_t RMR;            /*!< I3C Received Message register,             Address offset: 0x40      */
        uint32_t RESERVED4[3];   /*!< Reserved,                                  Address offset: 0x44-0x4C */
  __IM  uint32_t EVR;            /*!< I3C Event register,                        Address offset: 0x50      */
  __IOM uint32_t IER;            /*!< I3C Interrupt Enable register,             Address offset: 0x54      */
  __OM  uint32_t CEVR;           /*!< I3C Clear Event register,                  Address offset: 0x58      */
  __IM  uint32_t MISR;           /*!< I3C Masked Interrupt Status register,      Address offset: 0x5C      */
  __IOM uint32_t DEVR0;          /*!< I3C own Target characteristics register,   Address offset: 0x60      */
  __IOM uint32_t DEVRX[4];       /*!< I3C Target x (1<=x<=4) register,           Address offset: 0x64-0x70 */
        uint32_t RESERVED5[7];   /*!< Reserved,                                  Address offset: 0x74-0x8C */
  __IOM uint32_t MAXRLR;         /*!< I3C Maximum Read Length register,          Address offset: 0x90      */
  __IOM uint32_t MAXWLR;         /*!< I3C Maximum Write Length register,         Address offset: 0x94      */
        uint32_t RESERVED6[2];   /*!< Reserved,                                  Address offset: 0x98-0x9C */
  __IOM uint32_t TIMINGR0;       /*!< I3C Timing 0 register,                     Address offset: 0xA0      */
  __IOM uint32_t TIMINGR1;       /*!< I3C Timing 1 register,                     Address offset: 0xA4      */
  __IOM uint32_t TIMINGR2;       /*!< I3C Timing 2 register,                     Address offset: 0xA8      */
        uint32_t RESERVED7[5];   /*!< Reserved,                                  Address offset: 0xAC-0xBC */
  __IOM uint32_t BCR;            /*!< I3C Bus Characteristics register,          Address offset: 0xC0      */
  __IOM uint32_t DCR;            /*!< I3C Device Characteristics register,       Address offset: 0xC4      */
  __IOM uint32_t GETCAPR;        /*!< I3C GET CAPabilities register,             Address offset: 0xC8      */
  __IOM uint32_t CRCAPR;         /*!< I3C Controller CAPabilities register,      Address offset: 0xCC      */
  __IOM uint32_t GETMXDSR;       /*!< I3C GET Max Data Speed register,           Address offset: 0xD0      */
  __IOM uint32_t EPIDR;          /*!< I3C Extended Provisioned ID register,      Address offset: 0xD4      */
} I3C_TypeDef;

/**
  * @brief Instruction cache (ICACHE)
  */
typedef struct
{
  __IOM uint32_t CR;              /*!< ICACHE control register,                                 Address offset: 0x000 */
  __IM  uint32_t SR;              /*!< ICACHE status register,                                  Address offset: 0x004 */
  __IOM uint32_t IER;             /*!< ICACHE interrupt enable register,                        Address offset: 0x008 */
  __OM  uint32_t FCR;             /*!< ICACHE flag clear register,                              Address offset: 0x00C */
  __IM  uint32_t HMONR;           /*!< ICACHE hit monitor register,                             Address offset: 0x010 */
  __IM  uint32_t MMONR;           /*!< ICACHE miss monitor register,                            Address offset: 0x014 */
        uint32_t RESERVED1[2];    /*!< Reserved,                                                Address offset: 0x018 */
  __IOM uint32_t CRR0;            /*!< ICACHE region 0 configuration register,                  Address offset: 0x020 */
  __IOM uint32_t CRR1;            /*!< ICACHE region 1 configuration register,                  Address offset: 0x024 */
  __IOM uint32_t CRR2;            /*!< ICACHE region 2 configuration register,                  Address offset: 0x028 */
  __IOM uint32_t CRR3;            /*!< ICACHE region 3 configuration register,                  Address offset: 0x02C */
} ICACHE_TypeDef;

/**
  * @brief IWDG
  */
typedef struct
{
__OM  uint32_t KR;               /*!< IWDG Key register,             Address offset: 0x00 */
__IOM uint32_t PR;               /*!< IWDG Prescaler register,       Address offset: 0x04 */
__IOM uint32_t RLR;              /*!< IWDG Reload register,          Address offset: 0x08 */
__IM  uint32_t SR;               /*!< IWDG Status register,          Address offset: 0x0C */
__IOM uint32_t WINR;             /*!< IWDG Window register,          Address offset: 0x10 */
__IOM uint32_t EWCR;             /*!< IWDG Early Wakeup register,    Address offset: 0x14 */
__IOM uint32_t ICR;              /*!< IWDG interrupt clear register, Address offset: 0x18 */
} IWDG_TypeDef;

/**
  * @brief LPTIMER
  */
typedef struct
{
__IM  uint32_t ISR;              /*!< LPTIM Interrupt and Status register,    Address offset: 0x00 */
__OM  uint32_t ICR;              /*!< LPTIM Interrupt Clear register,         Address offset: 0x04 */
__IOM uint32_t DIER;             /*!< LPTIM Interrupt Enable register,        Address offset: 0x08 */
__IOM uint32_t CFGR;             /*!< LPTIM Configuration register,           Address offset: 0x0C */
__IOM uint32_t CR;               /*!< LPTIM Control register,                 Address offset: 0x10 */
__IOM uint32_t CCR1;             /*!< LPTIM Capture/Compare register 1,       Address offset: 0x14 */
__IOM uint32_t ARR;              /*!< LPTIM Autoreload register,              Address offset: 0x18 */
__IM  uint32_t CNT;              /*!< LPTIM Counter register,                 Address offset: 0x1C */
      uint32_t RESERVED1;        /*!< Reserved,                               Address offset: 0x20 */
__IOM uint32_t CFGR2;            /*!< LPTIM Configuration register 2,         Address offset: 0x24 */
__IOM uint32_t RCR;              /*!< LPTIM Repetition register,              Address offset: 0x28 */
__IOM uint32_t CCMR1;            /*!< LPTIM Capture/Compare mode register,    Address offset: 0x2C */
      uint32_t RESERVED2;        /*!< Reserved,                               Address offset: 0x30 */
__IOM uint32_t CCR2;             /*!< LPTIM Capture/Compare register 2,       Address offset: 0x34 */
} LPTIM_TypeDef;


/**
  * @brief Power Control (PWR)
  */
typedef struct
{
  __IOM uint32_t PMCR;            /*!< PWR power mode control register,                         Address offset: 0x000 */
  __IM  uint32_t PMSR;            /*!< PWR status register,                                     Address offset: 0x004 */
        uint32_t RESERVED1[7];    /*!< Reserved,                                                Address offset: 0x008 */
  __IOM uint32_t RTCCR;           /*!< PWR RTC domain control register,                         Address offset: 0x024 */
        uint32_t RESERVED2[3];    /*!< Reserved,                                                Address offset: 0x028 */
  __IOM uint32_t VMCR;            /*!< PWR voltage monitor control register,                    Address offset: 0x034 */
        uint32_t RESERVED3;       /*!< Reserved,                                                Address offset: 0x038 */
  __IM  uint32_t VMSR;            /*!< PWR voltage monitor status register,                     Address offset: 0x03C */
  __OM  uint32_t WUSCR;           /*!< PWR wake-up status clear register,                       Address offset: 0x040 */
  __IM  uint32_t WUSR;            /*!< PWR wake-up status register,                             Address offset: 0x044 */
  __IOM uint32_t WUCR;            /*!< PWR wake-up configuration register,                      Address offset: 0x048 */
        uint32_t RESERVED4;       /*!< Reserved,                                                Address offset: 0x04C */
  __IOM uint32_t IORETR;          /*!< PWR I/O retention register,                              Address offset: 0x050 */
        uint32_t RESERVED5[44];   /*!< Reserved,                                                Address offset: 0x054 */
  __IOM uint32_t PRIVCFGR;        /*!< PWR privilege configuration register,                    Address offset: 0x104 */
} PWR_TypeDef;

/**
  * @brief RAMs configuration controller (RAMCFG)
  */
typedef struct
{
  __IOM uint32_t CR;              /*!< RAMCFG control register,                                 Address offset: 0x000 */
  __IOM uint32_t IER;             /*!< RAMCFG interrupt enable register,                        Address offset: 0x004 */
  __IM  uint32_t ISR;             /*!< RAMCFG interrupt status register,                        Address offset: 0x008 */
  __IM  uint32_t SEAR;            /*!< RAMCFG ECC single error address register,                Address offset: 0x00C */
  __IM  uint32_t DEAR;            /*!< RAMCFG ECC double error address register,                Address offset: 0x010 */
  __IOM uint32_t ICR;             /*!< RAMCFG interrupt clear register,                         Address offset: 0x014 */
  __IOM uint32_t WPR1;            /*!< RAMCFG write protection register 1,                      Address offset: 0x018 */
  __IOM uint32_t WPR2;            /*!< RAMCFG write protection register 2,                      Address offset: 0x01C */
        uint32_t RESERVED1;       /*!< Reserved,                                                Address offset: 0x020 */
  __OM  uint32_t ECCKEYR;         /*!< RAMCFG ECC key register,                                 Address offset: 0x024 */
  __OM  uint32_t ERKEYR;          /*!< RAMCFG erase key register,                               Address offset: 0x028 */
} RAMCFG_TypeDef;

/**
  * @brief Reset and clock control (RCC)
  */
typedef struct
{
  __IOM uint32_t CR1;             /*!< RCC clock control register,                              Address offset: 0x000 */
  __IOM uint32_t CR2;             /*!< RCC clock control register,                              Address offset: 0x004 */
        uint32_t RESERVED1[5];    /*!< Reserved,                                                Address offset: 0x008 */
  __IOM uint32_t CFGR1;           /*!< RCC clock configuration register1,                       Address offset: 0x01C */
  __IOM uint32_t CFGR2;           /*!< RCC CPU domain clock configuration register 2,           Address offset: 0x020 */
        uint32_t RESERVED2[11];   /*!< Reserved,                                                Address offset: 0x024 */
  __IOM uint32_t CIER;            /*!< RCC clock source interrupt enable register,              Address offset: 0x050 */
  __IM  uint32_t CIFR;            /*!< RCC clock source interrupt flag register,                Address offset: 0x054 */
  __IOM uint32_t CICR;            /*!< RCC clock source interrupt clear register,               Address offset: 0x058 */
        uint32_t RESERVED3;       /*!< Reserved,                                                Address offset: 0x05C */
  __IOM uint32_t AHB1RSTR;        /*!< RCC AHB1 reset register,                                 Address offset: 0x060 */
  __IOM uint32_t AHB2RSTR;        /*!< RCC AHB2 peripheral reset register,                      Address offset: 0x064 */
        uint32_t RESERVED4[3];    /*!< Reserved,                                                Address offset: 0x068 */
  __IOM uint32_t APB1LRSTR;       /*!< RCC APB1 peripheral low reset register,                  Address offset: 0x074 */
  __IOM uint32_t APB1HRSTR;       /*!< RCC APB1 peripheral high reset register,                 Address offset: 0x078 */
  __IOM uint32_t APB2RSTR;        /*!< RCC APB2 peripheral reset register,                      Address offset: 0x07C */
  __IOM uint32_t APB3RSTR;        /*!< RCC APB3 peripheral reset register,                      Address offset: 0x080 */
        uint32_t RESERVED5;       /*!< Reserved,                                                Address offset: 0x084 */
  __IOM uint32_t AHB1ENR;         /*!< RCC AHB1 peripheral clock register,                      Address offset: 0x088 */
  __IOM uint32_t AHB2ENR;         /*!< RCC AHB2 peripheral clock register,                      Address offset: 0x08C */
        uint32_t RESERVED6[3];    /*!< Reserved,                                                Address offset: 0x090 */
  __IOM uint32_t APB1LENR;        /*!< RCC APB1 peripheral clock register,                      Address offset: 0x09C */
  __IOM uint32_t APB1HENR;        /*!< RCC APB1 peripheral clock register,                      Address offset: 0x0A0 */
  __IOM uint32_t APB2ENR;         /*!< RCC APB2 peripheral clock register,                      Address offset: 0x0A4 */
  __IOM uint32_t APB3ENR;         /*!< RCC APB3 peripheral clock register,                      Address offset: 0x0A8 */
        uint32_t RESERVED7;       /*!< Reserved,                                                Address offset: 0x0AC */
  __IOM uint32_t AHB1LPENR;       /*!< RCC AHB1 sleep clock register,                           Address offset: 0x0B0 */
  __IOM uint32_t AHB2LPENR;       /*!< RCC AHB2 sleep clock register,                           Address offset: 0x0B4 */
        uint32_t RESERVED8[3];    /*!< Reserved,                                                Address offset: 0x0B8 */
  __IOM uint32_t APB1LLPENR;      /*!< RCC APB1 sleep clock register,                           Address offset: 0x0C4 */
  __IOM uint32_t APB1HLPENR;      /*!< RCC APB1 sleep clock register,                           Address offset: 0x0C8 */
  __IOM uint32_t APB2LPENR;       /*!< RCC APB2 sleep clock register,                           Address offset: 0x0CC */
  __IOM uint32_t APB3LPENR;       /*!< RCC APB3 sleep clock register,                           Address offset: 0x0D0 */
        uint32_t RESERVED9;       /*!< Reserved,                                                Address offset: 0x0D4 */
  __IOM uint32_t CCIPR1;          /*!< RCC kernel clock configuration register,                 Address offset: 0x0D8 */
  __IOM uint32_t CCIPR2;          /*!< RCC kernel clock configuration register,                 Address offset: 0x0DC */
        uint32_t RESERVED10[4];   /*!< Reserved,                                                Address offset: 0x0E0 */
  __IOM uint32_t RTCCR;           /*!< RCC RTC domain control register,                         Address offset: 0x0F0 */
  __IOM uint32_t RSR;             /*!< RCC reset status register,                               Address offset: 0x0F4 */
        uint32_t RESERVED11[7];   /*!< Reserved,                                                Address offset: 0x0F8 */
  __IOM uint32_t PRIVCFGR;        /*!< RCC privilege configuration register,                    Address offset: 0x114 */
} RCC_TypeDef;

/**
  * @brief True random number generator (RNG)
  */
typedef struct
{
  __IOM uint32_t CR;              /*!< RNG control register,                      Address offset: 0x00 */
  __IOM uint32_t SR;              /*!< RNG status register,                       Address offset: 0x04 */
  __IM  uint32_t DR;              /*!< RNG data register,                         Address offset: 0x08 */
  __IOM uint32_t NSCR;            /*!< RNG noise source control register,         Address offset: 0x0C */
  __IOM uint32_t HTCR[4];         /*!< RNG health test configuration register,    Address offset: 0x10-0x1C */
  __IM  uint32_t HTSR[2];         /*!< RNG health test status register,           Address offset: 0x20-0x24 */
        uint32_t RESERVED1[2];    /*!< Reserved,                                  Address offset: 0x28-0x2C */
  __IOM uint32_t NSMR;            /*!< RNG health test status register,           Address offset: 0x30      */
} RNG_TypeDef;

/*
* @brief RTC Specific device feature definitions
*/

/**
  * @brief Real-Time Clock
  */
typedef struct
{
  __IOM uint32_t TR;              /*!< RTC time register,                                       Address offset: 0x00 */
  __IOM uint32_t DR;              /*!< RTC date register,                                       Address offset: 0x04 */
  __IM  uint32_t SSR;             /*!< RTC subsecond register,                                  Address offset: 0x08 */
  __IOM uint32_t ICSR;            /*!< RTC initialization control and status register,          Address offset: 0x0C */
  __IOM uint32_t PRER;            /*!< RTC prescaler register,                                  Address offset: 0x10 */
  __IOM uint32_t WUTR;            /*!< RTC wake-up timer register,                              Address offset: 0x14 */
  __IOM uint32_t CR;              /*!< RTC control register,                                    Address offset: 0x18 */
  __IOM uint32_t PRIVCFGR;        /*!< RTC privilege mode control register,                     Address offset: 0x1C */
        uint32_t RESERVED1;       /*!< Reserved,                                                Address offset: 0x20 */
  __OM  uint32_t WPR;             /*!< RTC write protection register,                           Address offset: 0x24 */
  __IOM uint32_t CALR;            /*!< RTC calibration register,                                Address offset: 0x28 */
  __OM  uint32_t SHIFTR;          /*!< RTC shift control register,                              Address offset: 0x2C */
  __IM  uint32_t TSTR;            /*!< RTC timestamp time register,                             Address offset: 0x30 */
  __IM  uint32_t TSDR;            /*!< RTC timestamp date register,                             Address offset: 0x34 */
  __IM  uint32_t TSSSR;           /*!< RTC timestamp subsecond register,                        Address offset: 0x38 */
        uint32_t RESERVED2;       /*!< Reserved,                                                Address offset: 0x3C */
  __IOM uint32_t ALRMAR;          /*!< RTC alarm A register,                                    Address offset: 0x40 */
  __IOM uint32_t ALRMASSR;        /*!< RTC alarm A subsecond register,                          Address offset: 0x44 */
  __IOM uint32_t ALRMBR;          /*!< RTC alarm B register,                                    Address offset: 0x48 */
  __IOM uint32_t ALRMBSSR;        /*!< RTC alarm B subsecond register,                          Address offset: 0x4C */
  __IM  uint32_t SR;              /*!< RTC status register,                                     Address offset: 0x50 */
  __IM  uint32_t MISR;            /*!< RTC masked interrupt status register,                    Address offset: 0x54 */
        uint32_t RESERVED3;       /*!< Reserved,                                                Address offset: 0x58 */
  __OM  uint32_t SCR;             /*!< RTC status clear register,                               Address offset: 0x5C */
       uint32_t RESERVED4[4];     /*!< Reserved                                                 Address offset: 0x60-0x6C */
  __IOM uint32_t ALRABINR;        /*!< RTC alarm A binary mode register,                        Address offset: 0x70 */
  __IOM uint32_t ALRBBINR;        /*!< RTC alarm B binary mode register,                        Address offset: 0x74 */
} RTC_TypeDef;

/**
  * @brief System configuration, boot and security (SBS)
  */
typedef struct
{
        uint32_t RESERVED1[4];  /*!< Reserved,                                                  Address offset: 0x000 */
  __IOM uint32_t HDPLCR;        /*!< SBS temporal isolation control register,                   Address offset: 0x010 */
  __IM  uint32_t HDPLSR;        /*!< SBS temporal isolation status register,                    Address offset: 0x014 */
        uint32_t RESERVED2[59]; /*!< Reserved,                                                  Address offset: 0x018 */
  __IOM uint32_t FPUIMR;        /*!< SBS FPU interrupt mask register,                           Address offset: 0x104 */
  __IOM uint32_t MESR;          /*!< SBS memory erase status register,                          Address offset: 0x108 */
        uint32_t RESERVED3;     /*!< Reserved,                                                  Address offset: 0x10C */
  __IOM uint32_t CCCSR;         /*!< SBS compensation cell for I/Os control and status register,Address offset: 0x110 */
  __IM  uint32_t CCVALR;        /*!< SBS compensation cell for I/Os value register,             Address offset: 0x114 */
  __IOM uint32_t CCSWCR;        /*!< SBS compensation cell for I/Os software code register,     Address offset: 0x118 */
        uint32_t RESERVED4;     /*!< Reserved,                                                  Address offset: 0x11C */
  __IOM uint32_t CFGR2;         /*!< SBS Class B register,                                      Address offset: 0x120 */
        uint32_t RESERVED5[8];  /*!< Reserved,                                                  Address offset: 0x124 */
  __IOM uint32_t CLCKR;         /*!< SBS CPU lock register,                                     Address offset: 0x144 */
        uint32_t RESERVED6;     /*!< Reserved,                                                  Address offset: 0x148 */
  __IOM uint32_t ECCNMIR;       /*!< SBS ECC NMI mask register,                                 Address offset: 0x14C */
} SBS_TypeDef;

/**
  * @brief Serial peripheral interface (SPI)
  */
typedef struct
{
  __IOM uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */
  __IOM uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */
  __IOM uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */
  __IOM uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */
  __IOM uint32_t IER;           /*!< SPI Interrupt Enable register,                   Address offset: 0x10 */
  __IM  uint32_t SR;            /*!< SPI Status register,                             Address offset: 0x14 */
  __OM  uint32_t IFCR;          /*!< SPI Interrupt/Status Flags Clear register,       Address offset: 0x18 */
  __IOM uint32_t AUTOCR;        /*!< SPI Autonomous Mode Control register,            Address offset: 0x1C */
  __OM  uint32_t TXDR;          /*!< SPI Transmit data register,                      Address offset: 0x20 */
        uint32_t RESERVED1[3];  /*!< Reserved,                                        Address offset: 0x24 */
  __IM  uint32_t RXDR;          /*!< SPI/I2S data register,                           Address offset: 0x30 */
        uint32_t RESERVED2[3];  /*!< Reserved,                                        Address offset: 0x34 */
  __IOM uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */
  __IM  uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */
  __IM  uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */
  __IOM uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */
  __IOM uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */
} SPI_TypeDef;

/**
  * @brief Tamper and backup registers
  */
typedef struct
{
  __IOM uint32_t CR1;              /*!< TAMP control register 1,                         Address offset: 0x000 */
  __IOM uint32_t CR2;              /*!< TAMP control register 2,                         Address offset: 0x004 */
  __IOM uint32_t CR3;              /*!< TAMP control register 3,                         Address offset: 0x008 */
  __IOM uint32_t FLTCR;            /*!< TAMP filter control register,                    Address offset: 0x00C */
        uint32_t RESERVED1[4];     /*!< Reserved,                                        Address offset: 0x010-0x01C */
  __IOM uint32_t CFGR;             /*!< TAMP configuration register,                     Address offset: 0x020 */
  __IOM uint32_t PRIVCFGR;         /*!< TAMP privilege configuration register,           Address offset: 0x024 */
        uint32_t RESERVED2;        /*!< Reserved,                                        Address offset: 0x028 */
  __IOM uint32_t IER;              /*!< TAMP interrupt enable register,                  Address offset: 0x02C */
  __IM  uint32_t SR;               /*!< TAMP status register,                            Address offset: 0x030 */
  __IM  uint32_t MISR;             /*!< TAMP masked interrupt status register,           Address offset: 0x034 */
        uint32_t RESERVED3;        /*!< Reserved,                                        Address offset: 0x038 */
  __OM  uint32_t SCR;              /*!< TAMP status clear register,                      Address offset: 0x03C */
        uint32_t RESERVED4[4];     /*!< Reserved,                                        Address offset: 0x040-0x04C */
  __IOM uint32_t OR;               /*!< TAMP option register,                            Address offset: 0x050 */
        uint32_t RESERVED5[43];    /*!< Reserved,                                        Address offset: 0x054-0x0FC */
  __IOM uint32_t BKP0R;            /*!< TAMP backup register 0,                          Address offset: 0x100 */
  __IOM uint32_t BKP1R;            /*!< TAMP backup register 1,                          Address offset: 0x104 */
  __IOM uint32_t BKP2R;            /*!< TAMP backup register 2,                          Address offset: 0x108 */
  __IOM uint32_t BKP3R;            /*!< TAMP backup register 3,                          Address offset: 0x10C */
  __IOM uint32_t BKP4R;            /*!< TAMP backup register 4,                          Address offset: 0x110 */
  __IOM uint32_t BKP5R;            /*!< TAMP backup register 5,                          Address offset: 0x114 */
  __IOM uint32_t BKP6R;            /*!< TAMP backup register 6,                          Address offset: 0x118 */
  __IOM uint32_t BKP7R;            /*!< TAMP backup register 7,                          Address offset: 0x11C */
  __IOM uint32_t BKP8R;            /*!< TAMP backup register 8,                          Address offset: 0x120 */
  __IOM uint32_t BKP9R;            /*!< TAMP backup register 9,                          Address offset: 0x124 */
  __IOM uint32_t BKP10R;           /*!< TAMP backup register 10,                         Address offset: 0x128 */
  __IOM uint32_t BKP11R;           /*!< TAMP backup register 11,                         Address offset: 0x12C */
  __IOM uint32_t BKP12R;           /*!< TAMP backup register 12,                         Address offset: 0x130 */
  __IOM uint32_t BKP13R;           /*!< TAMP backup register 13,                         Address offset: 0x134 */
  __IOM uint32_t BKP14R;           /*!< TAMP backup register 14,                         Address offset: 0x138 */
  __IOM uint32_t BKP15R;           /*!< TAMP backup register 15,                         Address offset: 0x13C */
  __IOM uint32_t BKP16R;           /*!< TAMP backup register 16,                         Address offset: 0x140 */
  __IOM uint32_t BKP17R;           /*!< TAMP backup register 17,                         Address offset: 0x144 */
  __IOM uint32_t BKP18R;           /*!< TAMP backup register 18,                         Address offset: 0x148 */
  __IOM uint32_t BKP19R;           /*!< TAMP backup register 19,                         Address offset: 0x14C */
  __IOM uint32_t BKP20R;           /*!< TAMP backup register 20,                         Address offset: 0x150 */
  __IOM uint32_t BKP21R;           /*!< TAMP backup register 21,                         Address offset: 0x154 */
  __IOM uint32_t BKP22R;           /*!< TAMP backup register 22,                         Address offset: 0x158 */
  __IOM uint32_t BKP23R;           /*!< TAMP backup register 23,                         Address offset: 0x15C */
  __IOM uint32_t BKP24R;           /*!< TAMP backup register 24,                         Address offset: 0x160 */
  __IOM uint32_t BKP25R;           /*!< TAMP backup register 25,                         Address offset: 0x164 */
  __IOM uint32_t BKP26R;           /*!< TAMP backup register 26,                         Address offset: 0x168 */
  __IOM uint32_t BKP27R;           /*!< TAMP backup register 27,                         Address offset: 0x16C */
  __IOM uint32_t BKP28R;           /*!< TAMP backup register 28,                         Address offset: 0x170 */
  __IOM uint32_t BKP29R;           /*!< TAMP backup register 29,                         Address offset: 0x174 */
  __IOM uint32_t BKP30R;           /*!< TAMP backup register 30,                         Address offset: 0x178 */
  __IOM uint32_t BKP31R;           /*!< TAMP backup register 31,                         Address offset: 0x17C */
} TAMP_TypeDef;

/**
  * @brief TIM Address block
  */
typedef struct
{
  __IOM uint32_t CR1;             /*!< TIM control register 1,                                  Address offset: 0x000 */
  __IOM uint32_t CR2;             /*!< TIM control register 2,                                  Address offset: 0x004 */
  __IOM uint32_t SMCR;            /*!< TIM slave mode control register,                         Address offset: 0x008 */
  __IOM uint32_t DIER;            /*!< TIM DMA/interrupt enable register,                       Address offset: 0x00C */
  __IOM uint32_t SR;              /*!< TIM status register,                                     Address offset: 0x010 */
  __IOM uint32_t EGR;             /*!< TIM event generation register,                           Address offset: 0x014 */
  __IOM uint32_t CCMR1;           /*!< TIM capture/compare mode register 1 [alternate],         Address offset: 0x018 */
  __IOM uint32_t CCMR2;           /*!< TIM capture/compare mode register 2 [alternate],         Address offset: 0x01C */
  __IOM uint32_t CCER;            /*!< TIM capture/compare enable register,                     Address offset: 0x020 */
  __IOM uint32_t CNT;             /*!< TIM counter,                                             Address offset: 0x024 */
  __IOM uint32_t PSC;             /*!< TIM prescaler,                                           Address offset: 0x028 */
  __IOM uint32_t ARR;             /*!< TIM autoreload register,                                 Address offset: 0x02C */
  __IOM uint32_t RCR;             /*!< TIM repetition counter register,                         Address offset: 0x030 */
  __IOM uint32_t CCR1;            /*!< TIM capture/compare register 1,                          Address offset: 0x034 */
  __IOM uint32_t CCR2;            /*!< TIM capture/compare register 2,                          Address offset: 0x038 */
  __IOM uint32_t CCR3;            /*!< TIM capture/compare register 3,                          Address offset: 0x03C */
  __IOM uint32_t CCR4;            /*!< TIM capture/compare register 4,                          Address offset: 0x040 */
  __IOM uint32_t BDTR;            /*!< TIM break and dead-time register,                        Address offset: 0x044 */
  __IOM uint32_t CCR5;            /*!< TIM capture/compare register 5,                          Address offset: 0x048 */
  __IOM uint32_t CCR6;            /*!< TIM capture/compare register 6,                          Address offset: 0x04C */
  __IOM uint32_t CCMR3;           /*!< TIM capture/compare mode register 3,                     Address offset: 0x050 */
  __IOM uint32_t DTR2;            /*!< TIM timer deadtime register 2,                           Address offset: 0x054 */
  __IOM uint32_t ECR;             /*!< TIM timer encoder control register,                      Address offset: 0x058 */
  __IOM uint32_t TISEL;           /*!< TIM timer input selection register,                      Address offset: 0x05C */
  __IOM uint32_t AF1;             /*!< TIM alternate function option register 1,                Address offset: 0x060 */
  __IOM uint32_t AF2;             /*!< TIM alternate function register 2,                       Address offset: 0x064 */
       uint32_t RESERVED1[2];     /*!< Reserved,                                                Address offset: 0x068 - 0x06C */
  __IOM uint32_t CCR7;            /*!< TIM capture/compare register 7,                          Address offset: 0x070 */
       uint32_t RESERVED2;        /*!< Reserved,                                                Address offset: 0x074 */
  __IOM uint32_t CCMR4;           /*!< TIM capture/compare mode register 4,                     Address offset: 0x078 */
       uint32_t RESERVED3[5];     /*!< Reserved,                                                Address offset: 0x07C - 0x08C */
  __IOM uint32_t MPR1;            /*!< TIM multilevel protection register 1,                    Address offset: 0x090 */
  __IOM uint32_t MPR2;            /*!< TIM multilevel protection register 2,                    Address offset: 0x094 */
       uint32_t RESERVED4[2];     /*!< Reserved,                                                Address offset: 0x098 - 0x09C */
  __IOM uint32_t OOR;             /*!< TIM output override register,                            Address offset: 0x0A0 */
       uint32_t RESERVED5[206];   /*!< Reserved,                                                Address offset: 0x0A4 - 0x3D8 */
  __IOM uint32_t DCR;             /*!< TIM DMA control register,                                Address offset: 0x3DC */
  __IOM uint32_t DMAR;            /*!< TIM DMA address for full transfer,                       Address offset: 0x3E0 */
} TIM_TypeDef;

/**
  * @brief Universal Synchronous Asynchronous Receiver Transmitter
  */
typedef struct
{
  __IOM uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00  */
  __IOM uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04  */
  __IOM uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08  */
  __IOM uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C  */
  __IOM uint32_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10  */
  __IOM uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14  */
  __OM  uint32_t RQR;         /*!< USART Request register,                   Address offset: 0x18  */
  __IM  uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C  */
  __OM  uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20  */
  __IM  uint32_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24  */
  __IOM uint32_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28  */
  __IOM uint32_t PRESC;       /*!< USART Prescaler register,                 Address offset: 0x2C  */
} USART_TypeDef;

/**
  * @brief Universal Serial Bus Full Speed Dual Role Device
  */
typedef struct
{
  __IOM uint32_t CHEP0R;          /*!< USB Channel/Endpoint 0 register,      Address offset: 0x00 */
  __IOM uint32_t CHEP1R;          /*!< USB Channel/Endpoint 1 register,      Address offset: 0x04 */
  __IOM uint32_t CHEP2R;          /*!< USB Channel/Endpoint 2 register,      Address offset: 0x08 */
  __IOM uint32_t CHEP3R;          /*!< USB Channel/Endpoint 3 register,      Address offset: 0x0C */
  __IOM uint32_t CHEP4R;          /*!< USB Channel/Endpoint 4 register,      Address offset: 0x10 */
  __IOM uint32_t CHEP5R;          /*!< USB Channel/Endpoint 5 register,      Address offset: 0x14 */
  __IOM uint32_t CHEP6R;          /*!< USB Channel/Endpoint 6 register,      Address offset: 0x18 */
  __IOM uint32_t CHEP7R;          /*!< USB Channel/Endpoint 7 register,      Address offset: 0x1C */
        uint32_t RESERVED1[8];    /*!< Reserved,                             Address offset: 0x20 */
  __IOM uint32_t CNTR;            /*!< Control register,                     Address offset: 0x40 */
  __IOM uint32_t ISTR;            /*!< Interrupt status register,            Address offset: 0x44 */
  __IM  uint32_t FNR;             /*!< Frame number register,                Address offset: 0x48 */
  __IOM uint32_t DADDR;           /*!< Device address register,              Address offset: 0x4C */
        uint32_t RESERVED2;       /*!< Reserved,                             Address offset: 0x50 */
  __IOM uint32_t LPMCSR;          /*!< LPM Control and Status register,      Address offset: 0x54 */
  __IOM uint32_t BCDR;            /*!< Battery Charging detector register,   Address offset: 0x58 */
} USB_DRD_TypeDef;

/**
  * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table
  */
typedef struct
{
  __IOM uint32_t TXBD;             /*!<Transmission buffer address */
  __IOM uint32_t RXBD;             /*!<Reception buffer address    */
} USB_DRD_PMABuffDescTypeDef;

/**
  * @brief WWDG
  */
typedef struct
{
__IOM uint32_t CR;               /*!< WWDG Control register,       Address offset: 0x00 */
__IOM uint32_t CFR;              /*!< WWDG Configuration register, Address offset: 0x04 */
__IOM uint32_t SR;               /*!< WWDG Status register,        Address offset: 0x08 */
} WWDG_TypeDef;

/*@}*/ /* end of group STM32C5xx_peripherals */


/* --------  End of section using anonymous unions and disabling warnings  -------- */
#if   defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
  /* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif /*__CC_ARM */

/* ================================================================================================================== */
/* ================                      Internal Oscillator Values adaptation                       ================ */
/* ================================================================================================================== */
/**
  * @brief Internal High Speed oscillator (HSI) reset value.
  *        This value is the default HSI range value after Reset.
  */
#if !defined(HSI_RESET_VALUE)
#define HSI_RESET_VALUE          4800000UL /*!< HSI resetValue of the Internal oscillator in Hz */
#endif /* !HSI_RESET_VALUE */


/**
  * @brief Internal High Speed oscillator (HSI) value.
  *        This value is used by the RCC HAL module to compute the system frequency
  *        (when HSI is used as system clock source, directly or through the PSI).
  */
#if !defined(HSI_VALUE)
#define HSI_VALUE               144000000UL /*!< Value of the Internal oscillator in Hz */
#endif /* !HSI_VALUE */

/**
  * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG.
  *        This internal oscillator is mainly dedicated to provide a high precision clock to
  *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
  *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
  *        which is subject to manufacturing process variations.
  */
#if !defined(HSI48_VALUE)
#define HSI48_VALUE             48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz.
                                          The real value my vary depending on manufacturing process variations.*/
#endif /* !HSI48_VALUE */

/**
  * @brief Internal Low Speed oscillator (LSI) value.
  */
#if !defined(LSI_VALUE)
#define LSI_VALUE                  32000UL    /*!< LSI Typical Value in Hz*/
/*!< Value of the Internal Low Speed oscillator in Hz
   The real value may vary depending on the variations
   in voltage and temperature.*/
#endif /* !LSI_VALUE */

/* ================================================================================================================== */
/* ================                      Device Specific Peripheral Address Map                      ================ */
/* ================================================================================================================== */


/** @addtogroup STM32C5xx_Peripheral_peripheralAddr
  * @{
  */

/* Internal SRAMs size */
#define SRAM1_SIZE               (0x10000UL)    /*!< SRAM1=64k  */
#define SRAM2_SIZE               (0x10000UL)    /*!< SRAM2=64k  */

/* Flash, Peripheral and internal SRAMs base addresses */
#define FLASH_BASE               (0x08000000UL) /*!< FLASH (512 KB) base address            */
#define SRAM1_BASE               (0x20000000UL) /*!< SRAM1 (64 KB) base address             */
#define SRAM2_BASE               (0x20010000UL) /*!< SRAM2 (64 KB) base address             */
#define PERIPH_BASE              (0x40000000UL) /*!< Peripheral base address                */

/*!< Flash OTP area */
#define FLASH_OTP_BASE           (0x08FFE000UL) /*!< FLASH OTP (one-time programmable) base address */

/*!< Flash read-only area */
#define UID_BASE                 (0x08FFF800UL) /*!< Unique 96-bit device ID register base address */
#define FLASHSIZE_BASE           (0x08FFF80CUL) /*!< Flash size data register base address  */
#define PACKAGE_BASE             (0x08FFF80EUL) /*!< Package data register base address     */

/* Flash DATA Area */
#define FLASH_EXT_USER_BASE      (0x08400000UL) /*!< FLASH extended user base address   */
#define FLASH_EDATA_BASE         (0x09000000UL) /*!< FLASH high-cycle data base address */

/*!< Flash system area */
#define FLASH_SYSTEM_BASE        (0x0BF80000UL) /*!< System FLASH non-secure base address  */
#define FLASH_SYSTEM_SIZE        (0x10000U)     /*!< 64 Kbytes OTP (one-time programmable) */

/* Peripheral memory map */
#define APB1PERIPH_BASE          PERIPH_BASE
#define APB2PERIPH_BASE          (PERIPH_BASE + 0x00010000UL)
#define AHB1PERIPH_BASE          (PERIPH_BASE + 0x00020000UL)
#define AHB2PERIPH_BASE          (PERIPH_BASE + 0x02020000UL)
#define APB3PERIPH_BASE          (PERIPH_BASE + 0x04000000UL)
#define AHB3PERIPH_BASE          (PERIPH_BASE + 0x04020000UL)

/*!< APB1 peripherals */
#define TIM2_BASE                (APB1PERIPH_BASE + 0x0000UL)
#define TIM5_BASE                (APB1PERIPH_BASE + 0x0C00UL)
#define TIM6_BASE                (APB1PERIPH_BASE + 0x1000UL)
#define TIM7_BASE                (APB1PERIPH_BASE + 0x1400UL)
#define TIM12_BASE               (APB1PERIPH_BASE + 0x1800UL)
#define WWDG_BASE                (APB1PERIPH_BASE + 0x2C00UL)
#define IWDG_BASE                (APB1PERIPH_BASE + 0x3000UL)
#define SPI2_BASE                (APB1PERIPH_BASE + 0x3800UL)
#define SPI3_BASE                (APB1PERIPH_BASE + 0x3C00UL)
#define COMP1_BASE               (APB1PERIPH_BASE + 0x4000UL)
#define USART2_BASE              (APB1PERIPH_BASE + 0x4400UL)
#define USART3_BASE              (APB1PERIPH_BASE + 0x4800UL)
#define UART4_BASE               (APB1PERIPH_BASE + 0x4C00UL)
#define UART5_BASE               (APB1PERIPH_BASE + 0x5000UL)
#define I2C1_BASE                (APB1PERIPH_BASE + 0x5400UL)
#define I2C2_BASE                (APB1PERIPH_BASE + 0x5800UL)
#define I3C1_BASE                (APB1PERIPH_BASE + 0x5C00UL)
#define CRS_BASE                 (APB1PERIPH_BASE + 0x6000UL)
#define FDCAN1_BASE              (APB1PERIPH_BASE + 0xA400UL)
#define FDCAN_CONFIG_BASE        (APB1PERIPH_BASE + 0xA500UL)
#define SRAMCAN_BASE             (APB1PERIPH_BASE + 0xAC00UL)

/*!< APB2 peripherals */
#define TIM1_BASE                (APB2PERIPH_BASE + 0x2C00UL)
#define SPI1_BASE                (APB2PERIPH_BASE + 0x3000UL)
#define TIM8_BASE                (APB2PERIPH_BASE + 0x3400UL)
#define USART1_BASE              (APB2PERIPH_BASE + 0x3800UL)
#define TIM15_BASE               (APB2PERIPH_BASE + 0x4000UL)
#define TIM16_BASE               (APB2PERIPH_BASE + 0x4400UL)
#define TIM17_BASE               (APB2PERIPH_BASE + 0x4800UL)
#define USB_DRD_FS_BASE          (APB2PERIPH_BASE + 0x6000UL)
#define USB_DRD_PMAADDR          (APB2PERIPH_BASE + 0x6400UL)

/*!< APB3 peripherals */
#define SBS_BASE                 (APB3PERIPH_BASE + 0x0400UL)
#define LPUART1_BASE             (APB3PERIPH_BASE + 0x2400UL)
#define LPTIM1_BASE              (APB3PERIPH_BASE + 0x4400UL)
#define RTC_BASE                 (APB3PERIPH_BASE + 0x7800UL)
#define TAMP_BASE                (APB3PERIPH_BASE + 0x7C00UL)


/*!< AHB1 peripherals */
#define LPDMA1_BASE              (AHB1PERIPH_BASE)
#define LPDMA1_CH0_BASE          (LPDMA1_BASE + 0x0050UL)
#define LPDMA1_CH1_BASE          (LPDMA1_BASE + 0x00D0UL)
#define LPDMA1_CH2_BASE          (LPDMA1_BASE + 0x0150UL)
#define LPDMA1_CH3_BASE          (LPDMA1_BASE + 0x01D0UL)
#define LPDMA1_CH4_BASE          (LPDMA1_BASE + 0x0250UL)
#define LPDMA1_CH5_BASE          (LPDMA1_BASE + 0x02D0UL)
#define LPDMA1_CH6_BASE          (LPDMA1_BASE + 0x0350UL)
#define LPDMA1_CH7_BASE          (LPDMA1_BASE + 0x03D0UL)
#define LPDMA2_BASE              (AHB1PERIPH_BASE + 0x01000UL)
#define LPDMA2_CH0_BASE          (LPDMA2_BASE + 0x0050UL)
#define LPDMA2_CH1_BASE          (LPDMA2_BASE + 0x00D0UL)
#define LPDMA2_CH2_BASE          (LPDMA2_BASE + 0x0150UL)
#define LPDMA2_CH3_BASE          (LPDMA2_BASE + 0x01D0UL)
#define FLASH_R_BASE             (AHB1PERIPH_BASE + 0x02000UL)
#define CRC_BASE                 (AHB1PERIPH_BASE + 0x03000UL)
#define CORDIC_BASE              (AHB1PERIPH_BASE + 0x03800UL)
#define RAMCFG_BASE              (AHB1PERIPH_BASE + 0x06000UL)
#define RAMCFG_SRAM1_BASE        (RAMCFG_BASE)
#define RAMCFG_SRAM2_BASE        (RAMCFG_BASE + 0x0040UL)
#define ICACHE_BASE              (AHB1PERIPH_BASE + 0x10400UL)

/*!< AHB2 peripherals */
#define GPIOA_BASE               (AHB2PERIPH_BASE + 0x00000UL)
#define GPIOB_BASE               (AHB2PERIPH_BASE + 0x00400UL)
#define GPIOC_BASE               (AHB2PERIPH_BASE + 0x00800UL)
#define GPIOD_BASE               (AHB2PERIPH_BASE + 0x00C00UL)
#define GPIOE_BASE               (AHB2PERIPH_BASE + 0x01000UL)
#define GPIOH_BASE               (AHB2PERIPH_BASE + 0x01C00UL)
#define ADC1_BASE                (AHB2PERIPH_BASE + 0x08000UL)
#define ADC2_BASE                (AHB2PERIPH_BASE + 0x08100UL)
#define ADC12_COMMON_BASE        (AHB2PERIPH_BASE + 0x08300UL)
#define DAC1_BASE                (AHB2PERIPH_BASE + 0x08400UL)
#define AES_BASE                 (AHB2PERIPH_BASE + 0xA0000UL)
#define HASH_BASE                (AHB2PERIPH_BASE + 0xA0400UL)
#define RNG_BASE                 (AHB2PERIPH_BASE + 0xA0800UL)

/*!< AHB3 peripherals */
#define PWR_BASE                 (AHB3PERIPH_BASE + 0x0800UL)
#define RCC_BASE                 (AHB3PERIPH_BASE + 0x0C00UL)
#define EXTI_BASE                (AHB3PERIPH_BASE + 0x2000UL)
#define DBGMCU_BASE              (AHB3PERIPH_BASE + 0x4000UL)

/*!< Exit Hide Protection Library */
/* ***************************** EXITHDPLIB system Flash region definition constants ******************************** */
#define EXITHDPLIB_SYS_FLASH_PFUNC_START   (0x0BF883E0UL)

/* ********************************** EXITHDPLIB function return constants ****************************************** */
#define EXITHDPLIB_ERROR   (0xF5F5F5F5UL)

/*!< EXITHDPLIB pointer function structure address definition */
#define EXITHDPLIB_PFUNC_BASE EXITHDPLIB_SYS_FLASH_PFUNC_START
#define EXITHDPLIB_PFUNC      ((EXITHDPLIB_pFunc_TypeDef *)EXITHDPLIB_PFUNC_BASE)

/**
  * @brief  Prototype of EXITHDPLIB JumpHDPLvl2/3 Functions.
  * @detail This function close the requested hdp area passed in input
  *         parameter and jump to the reset handler present within the
  *         Vector table. The function does not return on successful execution.
  * @param  VectorTableAddr: Address of the next vector table to apply.
  * @param  MPUIndex: MPU region index to enable before jumping.
  * @retval EXITHDPLIB_ERROR on error, otherwise does not return.
  */
typedef uint32_t (*EXITHDPLIB_JumpHDP_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex);

/**
  * @brief  EXITHDPLIB function pointer structure
  */
typedef struct
{
  uint32_t                   Reserved[3];    /*!< Address offset: 0x00 */
  EXITHDPLIB_JumpHDP_TypeDef JumpHDPLvl2;    /*!< Address offset: 0x0C */
  EXITHDPLIB_JumpHDP_TypeDef JumpHDPLvl3;    /*!< Address offset: 0x10 */
} EXITHDPLIB_pFunc_TypeDef;

/** @} */ /* End of group STM32C5xx_Peripheral_peripheralAddr */


/* ================================================================================================================== */
/* ================                              Peripheral declaration                              ================ */
/* ================================================================================================================== */


/** @addtogroup STM32C5xx_Peripheral_declaration
  * @{
  */

/*!< APB1 peripherals */
#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
#define USART2              ((USART_TypeDef *) USART2_BASE)
#define USART3              ((USART_TypeDef *) USART3_BASE)
#define UART4               ((USART_TypeDef *) UART4_BASE)
#define UART5               ((USART_TypeDef *) UART5_BASE)
#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
#define I3C1                ((I3C_TypeDef *) I3C1_BASE)
#define CRS                 ((CRS_TypeDef *) CRS_BASE)
#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
#define FDCAN_CONFIG        ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE)

/*!< APB2 peripherals */
#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
#define USART1              ((USART_TypeDef *) USART1_BASE)
#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
#define USB_DRD_FS          ((USB_DRD_TypeDef *) USB_DRD_FS_BASE)
#define USB_DRD_PMA_BUFF    ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR)

/*!< APB3 peripherals */
#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
#define RTC                 ((RTC_TypeDef *) RTC_BASE)
#define SBS                 ((SBS_TypeDef *) SBS_BASE)
#define TAMP                ((TAMP_TypeDef *) TAMP_BASE)

/*!< AHB1 peripherals */
#define LPDMA1              ((DMA_TypeDef *) LPDMA1_BASE)
#define LPDMA1_CH0          ((DMA_Channel_TypeDef *) LPDMA1_CH0_BASE)
#define LPDMA1_CH1          ((DMA_Channel_TypeDef *) LPDMA1_CH1_BASE)
#define LPDMA1_CH2          ((DMA_Channel_TypeDef *) LPDMA1_CH2_BASE)
#define LPDMA1_CH3          ((DMA_Channel_TypeDef *) LPDMA1_CH3_BASE)
#define LPDMA1_CH4          ((DMA_Channel_TypeDef *) LPDMA1_CH4_BASE)
#define LPDMA1_CH5          ((DMA_Channel_TypeDef *) LPDMA1_CH5_BASE)
#define LPDMA1_CH6          ((DMA_Channel_TypeDef *) LPDMA1_CH6_BASE)
#define LPDMA1_CH7          ((DMA_Channel_TypeDef *) LPDMA1_CH7_BASE)
#define LPDMA2              ((DMA_TypeDef *) LPDMA2_BASE)
#define LPDMA2_CH0          ((DMA_Channel_TypeDef *) LPDMA2_CH0_BASE)
#define LPDMA2_CH1          ((DMA_Channel_TypeDef *) LPDMA2_CH1_BASE)
#define LPDMA2_CH2          ((DMA_Channel_TypeDef *) LPDMA2_CH2_BASE)
#define LPDMA2_CH3          ((DMA_Channel_TypeDef *) LPDMA2_CH3_BASE)
#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC                 ((CRC_TypeDef *) CRC_BASE)
#define CORDIC              ((CORDIC_TypeDef *) CORDIC_BASE)
#define RAMCFG_SRAM1        ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE)
#define RAMCFG_SRAM2        ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE)
#define ICACHE              ((ICACHE_TypeDef *) ICACHE_BASE)

/*!< AHB2 peripherals */
#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
#define DAC1                ((DAC_TypeDef *) DAC1_BASE)
#define AES                 ((AES_TypeDef *) AES_BASE)
#define HASH                ((HASH_TypeDef *) HASH_BASE)
#define RNG                 ((RNG_TypeDef *) RNG_BASE)

/*!< AHB3 peripherals */
#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
#define PWR                 ((PWR_TypeDef *) PWR_BASE)
#define RCC                 ((RCC_TypeDef *) RCC_BASE)

/** @addtogroup Hardware_Constant_Definition
  * @{
  */
#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */
/**
  * @}
  */

/**********************************************************************************************************************/
/*                                                                                                                    */
/*                                          Analog to Digital Converter (ADC)                                         */
/*                                                                                                                    */
/**********************************************************************************************************************/
#define ADC_INST_IN_COMMON_COUNT (2U) /*!< Number of ADC instances within ADC common instance
                                           Note: maximum number for all common instances (in case of multiple ADC
                                                 common instances, some may encompass less ADC instances). */
#define ADC_MULTIMODE_SUPPORT    (1U) /*!< ADC feature available only on specific devices: multimode available
                                        on devices with several ADC instances */

/* *************************************  Bit definition for ADC_ISR register  ************************************** */
#define ADC_ISR_ADRDY_Pos        (0U)
#define ADC_ISR_ADRDY_Msk        (0x1UL << ADC_ISR_ADRDY_Pos)          /*!< 0x00000001 */
#define ADC_ISR_ADRDY            ADC_ISR_ADRDY_Msk                     /*!< ADC ready */
#define ADC_ISR_EOSMP_Pos        (1U)
#define ADC_ISR_EOSMP_Msk        (0x1UL << ADC_ISR_EOSMP_Pos)          /*!< 0x00000002 */
#define ADC_ISR_EOSMP            ADC_ISR_EOSMP_Msk                     /*!< End of sampling flag */
#define ADC_ISR_EOC_Pos          (2U)
#define ADC_ISR_EOC_Msk          (0x1UL << ADC_ISR_EOC_Pos)            /*!< 0x00000004 */
#define ADC_ISR_EOC              ADC_ISR_EOC_Msk                       /*!< End of conversion flag */
#define ADC_ISR_EOS_Pos          (3U)
#define ADC_ISR_EOS_Msk          (0x1UL << ADC_ISR_EOS_Pos)            /*!< 0x00000008 */
#define ADC_ISR_EOS              ADC_ISR_EOS_Msk                       /*!< End of regular sequence flag */
#define ADC_ISR_OVR_Pos          (4U)
#define ADC_ISR_OVR_Msk          (0x1UL << ADC_ISR_OVR_Pos)            /*!< 0x00000010 */
#define ADC_ISR_OVR              ADC_ISR_OVR_Msk                       /*!< ADC overrun */
#define ADC_ISR_JEOC_Pos         (5U)
#define ADC_ISR_JEOC_Msk         (0x1UL << ADC_ISR_JEOC_Pos)           /*!< 0x00000020 */
#define ADC_ISR_JEOC             ADC_ISR_JEOC_Msk                      /*!< Injected channel end of conversion flag */
#define ADC_ISR_JEOS_Pos         (6U)
#define ADC_ISR_JEOS_Msk         (0x1UL << ADC_ISR_JEOS_Pos)           /*!< 0x00000040 */
#define ADC_ISR_JEOS             ADC_ISR_JEOS_Msk                      /*!< Injected channel end of sequence flag */
#define ADC_ISR_AWD1_Pos         (7U)
#define ADC_ISR_AWD1_Msk         (0x1UL << ADC_ISR_AWD1_Pos)           /*!< 0x00000080 */
#define ADC_ISR_AWD1             ADC_ISR_AWD1_Msk                      /*!< Analog watchdog 1 flag */
#define ADC_ISR_AWD2_Pos         (8U)
#define ADC_ISR_AWD2_Msk         (0x1UL << ADC_ISR_AWD2_Pos)           /*!< 0x00000100 */
#define ADC_ISR_AWD2             ADC_ISR_AWD2_Msk                      /*!< Analog watchdog 2 flag */
#define ADC_ISR_AWD3_Pos         (9U)
#define ADC_ISR_AWD3_Msk         (0x1UL << ADC_ISR_AWD3_Pos)           /*!< 0x00000200 */
#define ADC_ISR_AWD3             ADC_ISR_AWD3_Msk                      /*!< Analog watchdog 3 flag */
#define ADC_ISR_LDORDY_Pos       (12U)
#define ADC_ISR_LDORDY_Msk       (0x1UL << ADC_ISR_LDORDY_Pos)         /*!< 0x00001000 */
#define ADC_ISR_LDORDY           ADC_ISR_LDORDY_Msk                    /*!< ADC internal voltage regulator output ready
                                                                            flag */

/* *************************************  Bit definition for ADC_IER register  ************************************** */
#define ADC_IER_ADRDYIE_Pos      (0U)
#define ADC_IER_ADRDYIE_Msk      (0x1UL << ADC_IER_ADRDYIE_Pos)        /*!< 0x00000001 */
#define ADC_IER_ADRDYIE          ADC_IER_ADRDYIE_Msk                   /*!< ADC ready interrupt enable */
#define ADC_IER_EOSMPIE_Pos      (1U)
#define ADC_IER_EOSMPIE_Msk      (0x1UL << ADC_IER_EOSMPIE_Pos)        /*!< 0x00000002 */
#define ADC_IER_EOSMPIE          ADC_IER_EOSMPIE_Msk                   /*!< End of sampling flag interrupt enable for
                                                                            regular conversions */
#define ADC_IER_EOCIE_Pos        (2U)
#define ADC_IER_EOCIE_Msk        (0x1UL << ADC_IER_EOCIE_Pos)          /*!< 0x00000004 */
#define ADC_IER_EOCIE            ADC_IER_EOCIE_Msk                     /*!< End of regular conversion interrupt enable
                                                                            */
#define ADC_IER_EOSIE_Pos        (3U)
#define ADC_IER_EOSIE_Msk        (0x1UL << ADC_IER_EOSIE_Pos)          /*!< 0x00000008 */
#define ADC_IER_EOSIE            ADC_IER_EOSIE_Msk                     /*!< End of regular sequence of conversions
                                                                            interrupt enable */
#define ADC_IER_OVRIE_Pos        (4U)
#define ADC_IER_OVRIE_Msk        (0x1UL << ADC_IER_OVRIE_Pos)          /*!< 0x00000010 */
#define ADC_IER_OVRIE            ADC_IER_OVRIE_Msk                     /*!< Overrun interrupt enable */
#define ADC_IER_JEOCIE_Pos       (5U)
#define ADC_IER_JEOCIE_Msk       (0x1UL << ADC_IER_JEOCIE_Pos)         /*!< 0x00000020 */
#define ADC_IER_JEOCIE           ADC_IER_JEOCIE_Msk                    /*!< End of injected conversion interrupt enable
                                                                            */
#define ADC_IER_JEOSIE_Pos       (6U)
#define ADC_IER_JEOSIE_Msk       (0x1UL << ADC_IER_JEOSIE_Pos)         /*!< 0x00000040 */
#define ADC_IER_JEOSIE           ADC_IER_JEOSIE_Msk                    /*!< End of injected sequence of conversions
                                                                            interrupt enable */
#define ADC_IER_AWD1IE_Pos       (7U)
#define ADC_IER_AWD1IE_Msk       (0x1UL << ADC_IER_AWD1IE_Pos)         /*!< 0x00000080 */
#define ADC_IER_AWD1IE           ADC_IER_AWD1IE_Msk                    /*!< Analog watchdog 1 interrupt enable */
#define ADC_IER_AWD2IE_Pos       (8U)
#define ADC_IER_AWD2IE_Msk       (0x1UL << ADC_IER_AWD2IE_Pos)         /*!< 0x00000100 */
#define ADC_IER_AWD2IE           ADC_IER_AWD2IE_Msk                    /*!< Analog watchdog 2 interrupt enable */
#define ADC_IER_AWD3IE_Pos       (9U)
#define ADC_IER_AWD3IE_Msk       (0x1UL << ADC_IER_AWD3IE_Pos)         /*!< 0x00000200 */
#define ADC_IER_AWD3IE           ADC_IER_AWD3IE_Msk                    /*!< Analog watchdog 3 interrupt enable */
#define ADC_IER_LDORDYIE_Pos     (12U)
#define ADC_IER_LDORDYIE_Msk     (0x1UL << ADC_IER_LDORDYIE_Pos)       /*!< 0x00001000 */
#define ADC_IER_LDORDYIE         ADC_IER_LDORDYIE_Msk                  /*!< ADC internal voltage regulator interrupt
                                                                            enable */

/* **************************************  Bit definition for ADC_CR register  ************************************** */
#define ADC_CR_ADEN_Pos          (0U)
#define ADC_CR_ADEN_Msk          (0x1UL << ADC_CR_ADEN_Pos)            /*!< 0x00000001 */
#define ADC_CR_ADEN              ADC_CR_ADEN_Msk                       /*!< ADC enable control */
#define ADC_CR_ADDIS_Pos         (1U)
#define ADC_CR_ADDIS_Msk         (0x1UL << ADC_CR_ADDIS_Pos)           /*!< 0x00000002 */
#define ADC_CR_ADDIS             ADC_CR_ADDIS_Msk                      /*!< ADC disable command */
#define ADC_CR_ADSTART_Pos       (2U)
#define ADC_CR_ADSTART_Msk       (0x1UL << ADC_CR_ADSTART_Pos)         /*!< 0x00000004 */
#define ADC_CR_ADSTART           ADC_CR_ADSTART_Msk                    /*!< ADC start of regular conversion */
#define ADC_CR_JADSTART_Pos      (3U)
#define ADC_CR_JADSTART_Msk      (0x1UL << ADC_CR_JADSTART_Pos)        /*!< 0x00000008 */
#define ADC_CR_JADSTART          ADC_CR_JADSTART_Msk                   /*!< ADC start of injected conversion */
#define ADC_CR_ADSTP_Pos         (4U)
#define ADC_CR_ADSTP_Msk         (0x1UL << ADC_CR_ADSTP_Pos)           /*!< 0x00000010 */
#define ADC_CR_ADSTP             ADC_CR_ADSTP_Msk                      /*!< ADC stop of regular conversion command */
#define ADC_CR_JADSTP_Pos        (5U)
#define ADC_CR_JADSTP_Msk        (0x1UL << ADC_CR_JADSTP_Pos)          /*!< 0x00000020 */
#define ADC_CR_JADSTP            ADC_CR_JADSTP_Msk                     /*!< ADC stop of injected conversion command */
#define ADC_CR_ADVREGEN_Pos      (28U)
#define ADC_CR_ADVREGEN_Msk      (0x1UL << ADC_CR_ADVREGEN_Pos)        /*!< 0x10000000 */
#define ADC_CR_ADVREGEN          ADC_CR_ADVREGEN_Msk                   /*!< ADC internal voltage regulator enable */
#define ADC_CR_DEEPPWD_Pos       (29U)
#define ADC_CR_DEEPPWD_Msk       (0x1UL << ADC_CR_DEEPPWD_Pos)         /*!< 0x20000000 */
#define ADC_CR_DEEPPWD           ADC_CR_DEEPPWD_Msk                    /*!< Deep-power-down enable */
#define ADC_CR_ADCAL_Pos         (31U)
#define ADC_CR_ADCAL_Msk         (0x1UL << ADC_CR_ADCAL_Pos)           /*!< 0x80000000 */
#define ADC_CR_ADCAL             ADC_CR_ADCAL_Msk                      /*!< ADC calibration */

/* ************************************  Bit definition for ADC_CFGR1 register  ************************************* */
#define ADC_CFGR1_DMNGT_Pos      (0U)
#define ADC_CFGR1_DMNGT_Msk      (0x3UL << ADC_CFGR1_DMNGT_Pos)        /*!< 0x00000003 */
#define ADC_CFGR1_DMNGT          ADC_CFGR1_DMNGT_Msk                   /*!< Data management configuration */
#define ADC_CFGR1_DMNGT_0        (0x1UL << ADC_CFGR1_DMNGT_Pos)        /*!< 0x00000001 */
#define ADC_CFGR1_DMNGT_1        (0x2UL << ADC_CFGR1_DMNGT_Pos)        /*!< 0x00000002 */
#define ADC_CFGR1_RES_Pos        (2U)
#define ADC_CFGR1_RES_Msk        (0x3UL << ADC_CFGR1_RES_Pos)          /*!< 0x0000000C */
#define ADC_CFGR1_RES            ADC_CFGR1_RES_Msk                     /*!< Data resolution */
#define ADC_CFGR1_RES_0          (0x1UL << ADC_CFGR1_RES_Pos)          /*!< 0x00000004 */
#define ADC_CFGR1_RES_1          (0x2UL << ADC_CFGR1_RES_Pos)          /*!< 0x00000008 */
#define ADC_CFGR1_EXTSEL_Pos     (5U)
#define ADC_CFGR1_EXTSEL_Msk     (0x1FUL << ADC_CFGR1_EXTSEL_Pos)      /*!< 0x000003E0 */
#define ADC_CFGR1_EXTSEL         ADC_CFGR1_EXTSEL_Msk                  /*!< External trigger selection for regular group
                                                                            */
#define ADC_CFGR1_EXTSEL_0       (0x1UL << ADC_CFGR1_EXTSEL_Pos)       /*!< 0x00000020 */
#define ADC_CFGR1_EXTSEL_1       (0x2UL << ADC_CFGR1_EXTSEL_Pos)       /*!< 0x00000040 */
#define ADC_CFGR1_EXTSEL_2       (0x4UL << ADC_CFGR1_EXTSEL_Pos)       /*!< 0x00000080 */
#define ADC_CFGR1_EXTSEL_3       (0x8UL << ADC_CFGR1_EXTSEL_Pos)       /*!< 0x00000100 */
#define ADC_CFGR1_EXTSEL_4       (0x10UL << ADC_CFGR1_EXTSEL_Pos)      /*!< 0x00000200 */
#define ADC_CFGR1_EXTEN_Pos      (10U)
#define ADC_CFGR1_EXTEN_Msk      (0x3UL << ADC_CFGR1_EXTEN_Pos)        /*!< 0x00000C00 */
#define ADC_CFGR1_EXTEN          ADC_CFGR1_EXTEN_Msk                   /*!< External trigger enable and polarity
                                                                            selection for regular channels */
#define ADC_CFGR1_EXTEN_0        (0x1UL << ADC_CFGR1_EXTEN_Pos)        /*!< 0x00000400 */
#define ADC_CFGR1_EXTEN_1        (0x2UL << ADC_CFGR1_EXTEN_Pos)        /*!< 0x00000800 */
#define ADC_CFGR1_OVRMOD_Pos     (12U)
#define ADC_CFGR1_OVRMOD_Msk     (0x1UL << ADC_CFGR1_OVRMOD_Pos)       /*!< 0x00001000 */
#define ADC_CFGR1_OVRMOD         ADC_CFGR1_OVRMOD_Msk                  /*!< Overrun mode */
#define ADC_CFGR1_CONT_Pos       (13U)
#define ADC_CFGR1_CONT_Msk       (0x1UL << ADC_CFGR1_CONT_Pos)         /*!< 0x00002000 */
#define ADC_CFGR1_CONT           ADC_CFGR1_CONT_Msk                    /*!< Single / continuous conversion mode for
                                                                            regular conversions */
#define ADC_CFGR1_AUTDLY_Pos     (14U)
#define ADC_CFGR1_AUTDLY_Msk     (0x1UL << ADC_CFGR1_AUTDLY_Pos)       /*!< 0x00004000 */
#define ADC_CFGR1_AUTDLY         ADC_CFGR1_AUTDLY_Msk                  /*!< Delayed conversion mode */
#define ADC_CFGR1_DISCEN_Pos     (16U)
#define ADC_CFGR1_DISCEN_Msk     (0x1UL << ADC_CFGR1_DISCEN_Pos)       /*!< 0x00010000 */
#define ADC_CFGR1_DISCEN         ADC_CFGR1_DISCEN_Msk                  /*!< Discontinuous mode for regular channels */
#define ADC_CFGR1_DISCNUM_Pos    (17U)
#define ADC_CFGR1_DISCNUM_Msk    (0x7UL << ADC_CFGR1_DISCNUM_Pos)      /*!< 0x000E0000 */
#define ADC_CFGR1_DISCNUM        ADC_CFGR1_DISCNUM_Msk                 /*!< Discontinuous mode channel count */
#define ADC_CFGR1_DISCNUM_0      (0x1UL << ADC_CFGR1_DISCNUM_Pos)      /*!< 0x00020000 */
#define ADC_CFGR1_DISCNUM_1      (0x2UL << ADC_CFGR1_DISCNUM_Pos)      /*!< 0x00040000 */
#define ADC_CFGR1_DISCNUM_2      (0x4UL << ADC_CFGR1_DISCNUM_Pos)      /*!< 0x00080000 */
#define ADC_CFGR1_JDISCEN_Pos    (20U)
#define ADC_CFGR1_JDISCEN_Msk    (0x1UL << ADC_CFGR1_JDISCEN_Pos)      /*!< 0x00100000 */
#define ADC_CFGR1_JDISCEN        ADC_CFGR1_JDISCEN_Msk                 /*!< Discontinuous mode on injected channels */
#define ADC_CFGR1_AWD1SGL_Pos    (22U)
#define ADC_CFGR1_AWD1SGL_Msk    (0x1UL << ADC_CFGR1_AWD1SGL_Pos)      /*!< 0x00400000 */
#define ADC_CFGR1_AWD1SGL        ADC_CFGR1_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or
                                                                            on all channels */
#define ADC_CFGR1_AWD1EN_Pos     (23U)
#define ADC_CFGR1_AWD1EN_Msk     (0x1UL << ADC_CFGR1_AWD1EN_Pos)       /*!< 0x00800000 */
#define ADC_CFGR1_AWD1EN         ADC_CFGR1_AWD1EN_Msk                  /*!< Analog watchdog 1 enable on regular channels
                                                                            */
#define ADC_CFGR1_JAWD1EN_Pos    (24U)
#define ADC_CFGR1_JAWD1EN_Msk    (0x1UL << ADC_CFGR1_JAWD1EN_Pos)      /*!< 0x01000000 */
#define ADC_CFGR1_JAWD1EN        ADC_CFGR1_JAWD1EN_Msk                 /*!< Analog watchdog 1 enable on injected
                                                                            channels */
#define ADC_CFGR1_JAUTO_Pos      (25U)
#define ADC_CFGR1_JAUTO_Msk      (0x1UL << ADC_CFGR1_JAUTO_Pos)        /*!< 0x02000000 */
#define ADC_CFGR1_JAUTO          ADC_CFGR1_JAUTO_Msk                   /*!< Automatic injected group conversion */
#define ADC_CFGR1_AWD1CH_Pos     (26U)
#define ADC_CFGR1_AWD1CH_Msk     (0x1FUL << ADC_CFGR1_AWD1CH_Pos)      /*!< 0x7C000000 */
#define ADC_CFGR1_AWD1CH         ADC_CFGR1_AWD1CH_Msk                  /*!< Analog watchdog 1 channel selection */
#define ADC_CFGR1_AWD1CH_0       (0x1UL << ADC_CFGR1_AWD1CH_Pos)       /*!< 0x04000000 */
#define ADC_CFGR1_AWD1CH_1       (0x2UL << ADC_CFGR1_AWD1CH_Pos)       /*!< 0x08000000 */
#define ADC_CFGR1_AWD1CH_2       (0x4UL << ADC_CFGR1_AWD1CH_Pos)       /*!< 0x10000000 */
#define ADC_CFGR1_AWD1CH_3       (0x8UL << ADC_CFGR1_AWD1CH_Pos)       /*!< 0x20000000 */
#define ADC_CFGR1_AWD1CH_4       (0x10UL << ADC_CFGR1_AWD1CH_Pos)      /*!< 0x40000000 */

/* ************************************  Bit definition for ADC_CFGR2 register  ************************************* */
#define ADC_CFGR2_ROVSE_Pos      (0U)
#define ADC_CFGR2_ROVSE_Msk      (0x1UL << ADC_CFGR2_ROVSE_Pos)        /*!< 0x00000001 */
#define ADC_CFGR2_ROVSE          ADC_CFGR2_ROVSE_Msk                   /*!< Regular oversampling enable */
#define ADC_CFGR2_JOVSE_Pos      (1U)
#define ADC_CFGR2_JOVSE_Msk      (0x1UL << ADC_CFGR2_JOVSE_Pos)        /*!< 0x00000002 */
#define ADC_CFGR2_JOVSE          ADC_CFGR2_JOVSE_Msk                   /*!< ADC oversampler enable on scope ADC group injected */
#define ADC_CFGR2_OVSS_Pos       (5U)
#define ADC_CFGR2_OVSS_Msk       (0xFUL << ADC_CFGR2_OVSS_Pos)         /*!< 0x000001E0 */
#define ADC_CFGR2_OVSS           ADC_CFGR2_OVSS_Msk                    /*!< Oversampling shift */
#define ADC_CFGR2_OVSS_0         (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */
#define ADC_CFGR2_OVSS_1         (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */
#define ADC_CFGR2_OVSS_2         (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */
#define ADC_CFGR2_OVSS_3         (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */
#define ADC_CFGR2_TROVS_Pos      (9U)
#define ADC_CFGR2_TROVS_Msk      (0x1UL << ADC_CFGR2_TROVS_Pos)        /*!< 0x00000200 */
#define ADC_CFGR2_TROVS          ADC_CFGR2_TROVS_Msk                   /*!< Triggered regular oversampling */
#define ADC_CFGR2_ROVSM_Pos      (10U)
#define ADC_CFGR2_ROVSM_Msk      (0x1UL << ADC_CFGR2_ROVSM_Pos)        /*!< 0x00000400 */
#define ADC_CFGR2_ROVSM          ADC_CFGR2_ROVSM_Msk                   /*!< Regular oversampling mode */
#define ADC_CFGR2_BULB_Pos       (13U)
#define ADC_CFGR2_BULB_Msk       (0x1UL << ADC_CFGR2_BULB_Pos)         /*!< 0x00002000 */
#define ADC_CFGR2_BULB           ADC_CFGR2_BULB_Msk                    /*!< Bulb sampling mode */
#define ADC_CFGR2_SWTRIG_Pos     (14U)
#define ADC_CFGR2_SWTRIG_Msk     (0x1UL << ADC_CFGR2_SWTRIG_Pos)       /*!< 0x00004000 */
#define ADC_CFGR2_SWTRIG         ADC_CFGR2_SWTRIG_Msk                  /*!< Software trigger bit for sampling time
                                                                            control trigger mode */
#define ADC_CFGR2_SMPTRIG_Pos    (15U)
#define ADC_CFGR2_SMPTRIG_Msk    (0x1UL << ADC_CFGR2_SMPTRIG_Pos)      /*!< 0x00008000 */
#define ADC_CFGR2_SMPTRIG        ADC_CFGR2_SMPTRIG_Msk                 /*!< Sampling time control trigger mode */
#define ADC_CFGR2_OVSR_Pos       (16U)
#define ADC_CFGR2_OVSR_Msk       (0x3FFUL << ADC_CFGR2_OVSR_Pos)       /*!< 0x03FF0000 */
#define ADC_CFGR2_OVSR           ADC_CFGR2_OVSR_Msk                    /*!< Oversampling ratio */
#define ADC_CFGR2_OVSR_0         (0x1UL << ADC_CFGR2_OVSR_Pos)         /*!< 0x00010000 */
#define ADC_CFGR2_OVSR_1         (0x2UL << ADC_CFGR2_OVSR_Pos)         /*!< 0x00020000 */
#define ADC_CFGR2_OVSR_2         (0x4UL << ADC_CFGR2_OVSR_Pos)         /*!< 0x00040000 */
#define ADC_CFGR2_OVSR_3         (0x8UL << ADC_CFGR2_OVSR_Pos)         /*!< 0x00080000 */
#define ADC_CFGR2_OVSR_4         (0x10UL << ADC_CFGR2_OVSR_Pos)        /*!< 0x00100000 */
#define ADC_CFGR2_OVSR_5         (0x20UL << ADC_CFGR2_OVSR_Pos)        /*!< 0x00200000 */
#define ADC_CFGR2_OVSR_6         (0x40UL << ADC_CFGR2_OVSR_Pos)        /*!< 0x00400000 */
#define ADC_CFGR2_OVSR_7         (0x80UL << ADC_CFGR2_OVSR_Pos)        /*!< 0x00800000 */
#define ADC_CFGR2_OVSR_8         (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */
#define ADC_CFGR2_OVSR_9         (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */
#define ADC_CFGR2_LSHIFT_Pos     (28U)
#define ADC_CFGR2_LSHIFT_Msk     (0xFUL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0xF0000000 */
#define ADC_CFGR2_LSHIFT         ADC_CFGR2_LSHIFT_Msk                  /*!< Left shift factor */
#define ADC_CFGR2_LSHIFT_0       (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */
#define ADC_CFGR2_LSHIFT_1       (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */
#define ADC_CFGR2_LSHIFT_2       (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */
#define ADC_CFGR2_LSHIFT_3       (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */

/* ************************************  Bit definition for ADC_SMPR1 register  ************************************* */
#define ADC_SMPR1_SMP0_Pos       (0U)
#define ADC_SMPR1_SMP0_Msk       (0x7UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000007 */
#define ADC_SMPR1_SMP0           ADC_SMPR1_SMP0_Msk                    /*!< Channel x sampling time selection (x = 9 to
                                                                            0) */
#define ADC_SMPR1_SMP0_0         (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */
#define ADC_SMPR1_SMP0_1         (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */
#define ADC_SMPR1_SMP0_2         (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */
#define ADC_SMPR1_SMP1_Pos       (3U)
#define ADC_SMPR1_SMP1_Msk       (0x7UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000038 */
#define ADC_SMPR1_SMP1           ADC_SMPR1_SMP1_Msk                    /*!< Channel x sampling time selection (x = 9 to
                                                                            0) */
#define ADC_SMPR1_SMP1_0         (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */
#define ADC_SMPR1_SMP1_1         (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */
#define ADC_SMPR1_SMP1_2         (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */
#define ADC_SMPR1_SMP2_Pos       (6U)
#define ADC_SMPR1_SMP2_Msk       (0x7UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x000001C0 */
#define ADC_SMPR1_SMP2           ADC_SMPR1_SMP2_Msk                    /*!< Channel x sampling time selection (x = 9 to
                                                                            0) */
#define ADC_SMPR1_SMP2_0         (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */
#define ADC_SMPR1_SMP2_1         (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */
#define ADC_SMPR1_SMP2_2         (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */
#define ADC_SMPR1_SMP3_Pos       (9U)
#define ADC_SMPR1_SMP3_Msk       (0x7UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000E00 */
#define ADC_SMPR1_SMP3           ADC_SMPR1_SMP3_Msk                    /*!< Channel x sampling time selection (x = 9 to
                                                                            0) */
#define ADC_SMPR1_SMP3_0         (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */
#define ADC_SMPR1_SMP3_1         (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */
#define ADC_SMPR1_SMP3_2         (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */
#define ADC_SMPR1_SMP4_Pos       (12U)
#define ADC_SMPR1_SMP4_Msk       (0x7UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00007000 */
#define ADC_SMPR1_SMP4           ADC_SMPR1_SMP4_Msk                    /*!< Channel x sampling time selection (x = 9 to
                                                                            0) */
#define ADC_SMPR1_SMP4_0         (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */
#define ADC_SMPR1_SMP4_1         (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */
#define ADC_SMPR1_SMP4_2         (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */
#define ADC_SMPR1_SMP5_Pos       (15U)
#define ADC_SMPR1_SMP5_Msk       (0x7UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00038000 */
#define ADC_SMPR1_SMP5           ADC_SMPR1_SMP5_Msk                    /*!< Channel x sampling time selection (x = 9 to
                                                                            0) */
#define ADC_SMPR1_SMP5_0         (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */
#define ADC_SMPR1_SMP5_1         (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */
#define ADC_SMPR1_SMP5_2         (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */
#define ADC_SMPR1_SMP6_Pos       (18U)
#define ADC_SMPR1_SMP6_Msk       (0x7UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x001C0000 */
#define ADC_SMPR1_SMP6           ADC_SMPR1_SMP6_Msk                    /*!< Channel x sampling time selection (x = 9 to
                                                                            0) */
#define ADC_SMPR1_SMP6_0         (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */
#define ADC_SMPR1_SMP6_1         (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */
#define ADC_SMPR1_SMP6_2         (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */
#define ADC_SMPR1_SMP7_Pos       (21U)
#define ADC_SMPR1_SMP7_Msk       (0x7UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00E00000 */
#define ADC_SMPR1_SMP7           ADC_SMPR1_SMP7_Msk                    /*!< Channel x sampling time selection (x = 9 to
                                                                            0) */
#define ADC_SMPR1_SMP7_0         (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */
#define ADC_SMPR1_SMP7_1         (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */
#define ADC_SMPR1_SMP7_2         (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */
#define ADC_SMPR1_SMP8_Pos       (24U)
#define ADC_SMPR1_SMP8_Msk       (0x7UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x07000000 */
#define ADC_SMPR1_SMP8           ADC_SMPR1_SMP8_Msk                    /*!< Channel x sampling time selection (x = 9 to
                                                                            0) */
#define ADC_SMPR1_SMP8_0         (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */
#define ADC_SMPR1_SMP8_1         (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */
#define ADC_SMPR1_SMP8_2         (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */
#define ADC_SMPR1_SMP9_Pos       (27U)
#define ADC_SMPR1_SMP9_Msk       (0x7UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x38000000 */
#define ADC_SMPR1_SMP9           ADC_SMPR1_SMP9_Msk                    /*!< Channel x sampling time selection (x = 9 to
                                                                            0) */
#define ADC_SMPR1_SMP9_0         (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */
#define ADC_SMPR1_SMP9_1         (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */
#define ADC_SMPR1_SMP9_2         (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */

/* ************************************  Bit definition for ADC_SMPR2 register  ************************************* */
#define ADC_SMPR2_SMP10_Pos      (0U)
#define ADC_SMPR2_SMP10_Msk      (0x7UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000007 */
#define ADC_SMPR2_SMP10          ADC_SMPR2_SMP10_Msk                   /*!< Channel x sampling time selection (x = 13 to
                                                                            10) */
#define ADC_SMPR2_SMP10_0        (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */
#define ADC_SMPR2_SMP10_1        (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */
#define ADC_SMPR2_SMP10_2        (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */
#define ADC_SMPR2_SMP11_Pos      (3U)
#define ADC_SMPR2_SMP11_Msk      (0x7UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000038 */
#define ADC_SMPR2_SMP11          ADC_SMPR2_SMP11_Msk                   /*!< Channel x sampling time selection (x = 13 to
                                                                            10) */
#define ADC_SMPR2_SMP11_0        (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */
#define ADC_SMPR2_SMP11_1        (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */
#define ADC_SMPR2_SMP11_2        (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */
#define ADC_SMPR2_SMP12_Pos      (6U)
#define ADC_SMPR2_SMP12_Msk      (0x7UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x000001C0 */
#define ADC_SMPR2_SMP12          ADC_SMPR2_SMP12_Msk                   /*!< Channel x sampling time selection (x = 13 to
                                                                            10) */
#define ADC_SMPR2_SMP12_0        (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */
#define ADC_SMPR2_SMP12_1        (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */
#define ADC_SMPR2_SMP12_2        (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */
#define ADC_SMPR2_SMP13_Pos      (9U)
#define ADC_SMPR2_SMP13_Msk      (0x7UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000E00 */
#define ADC_SMPR2_SMP13          ADC_SMPR2_SMP13_Msk                   /*!< Channel x sampling time selection (x = 13 to
                                                                            10) */
#define ADC_SMPR2_SMP13_0        (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */
#define ADC_SMPR2_SMP13_1        (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */
#define ADC_SMPR2_SMP13_2        (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */

/* ************************************  Bit definition for ADC_PCSEL register  ************************************* */
#define ADC_PCSEL_PCSEL_Pos      (0U)
#define ADC_PCSEL_PCSEL_Msk      (0x3FFFUL << ADC_PCSEL_PCSEL_Pos)     /*!< 0x00003FFF */
#define ADC_PCSEL_PCSEL          ADC_PCSEL_PCSEL_Msk                   /*!< Channel i (V<sub>IN[i]</sub>) preselection
                                                                            */
#define ADC_PCSEL_PCSEL_0        (0x1UL << ADC_PCSEL_PCSEL_Pos)        /*!< 0x00000001 */
#define ADC_PCSEL_PCSEL_1        (0x2UL << ADC_PCSEL_PCSEL_Pos)        /*!< 0x00000002 */
#define ADC_PCSEL_PCSEL_2        (0x4UL << ADC_PCSEL_PCSEL_Pos)        /*!< 0x00000004 */
#define ADC_PCSEL_PCSEL_3        (0x8UL << ADC_PCSEL_PCSEL_Pos)        /*!< 0x00000008 */
#define ADC_PCSEL_PCSEL_4        (0x10UL << ADC_PCSEL_PCSEL_Pos)       /*!< 0x00000010 */
#define ADC_PCSEL_PCSEL_5        (0x20UL << ADC_PCSEL_PCSEL_Pos)       /*!< 0x00000020 */
#define ADC_PCSEL_PCSEL_6        (0x40UL << ADC_PCSEL_PCSEL_Pos)       /*!< 0x00000040 */
#define ADC_PCSEL_PCSEL_7        (0x80UL << ADC_PCSEL_PCSEL_Pos)       /*!< 0x00000080 */
#define ADC_PCSEL_PCSEL_8        (0x100UL << ADC_PCSEL_PCSEL_Pos)      /*!< 0x00000100 */
#define ADC_PCSEL_PCSEL_9        (0x200UL << ADC_PCSEL_PCSEL_Pos)      /*!< 0x00000200 */
#define ADC_PCSEL_PCSEL_10       (0x400UL << ADC_PCSEL_PCSEL_Pos)      /*!< 0x00000400 */
#define ADC_PCSEL_PCSEL_11       (0x800UL << ADC_PCSEL_PCSEL_Pos)      /*!< 0x00000800 */
#define ADC_PCSEL_PCSEL_12       (0x1000UL << ADC_PCSEL_PCSEL_Pos)     /*!< 0x00001000 */
#define ADC_PCSEL_PCSEL_13       (0x2000UL << ADC_PCSEL_PCSEL_Pos)     /*!< 0x00002000 */

/* *************************************  Bit definition for ADC_SQR1 register  ************************************* */
#define ADC_SQR1_LEN_Pos         (0U)
#define ADC_SQR1_LEN_Msk         (0xFUL << ADC_SQR1_LEN_Pos)           /*!< 0x0000000F */
#define ADC_SQR1_LEN             ADC_SQR1_LEN_Msk                      /*!< Regular channel sequence length */
#define ADC_SQR1_LEN_0           (0x1UL << ADC_SQR1_LEN_Pos)           /*!< 0x00000001 */
#define ADC_SQR1_LEN_1           (0x2UL << ADC_SQR1_LEN_Pos)           /*!< 0x00000002 */
#define ADC_SQR1_LEN_2           (0x4UL << ADC_SQR1_LEN_Pos)           /*!< 0x00000004 */
#define ADC_SQR1_LEN_3           (0x8UL << ADC_SQR1_LEN_Pos)           /*!< 0x00000008 */
#define ADC_SQR1_SQ1_Pos         (6U)
#define ADC_SQR1_SQ1_Msk         (0x1FUL << ADC_SQR1_SQ1_Pos)          /*!< 0x000007C0 */
#define ADC_SQR1_SQ1             ADC_SQR1_SQ1_Msk                      /*!< 1st conversion in regular sequence */
#define ADC_SQR1_SQ1_0           (0x1UL << ADC_SQR1_SQ1_Pos)           /*!< 0x00000040 */
#define ADC_SQR1_SQ1_1           (0x2UL << ADC_SQR1_SQ1_Pos)           /*!< 0x00000080 */
#define ADC_SQR1_SQ1_2           (0x4UL << ADC_SQR1_SQ1_Pos)           /*!< 0x00000100 */
#define ADC_SQR1_SQ1_3           (0x8UL << ADC_SQR1_SQ1_Pos)           /*!< 0x00000200 */
#define ADC_SQR1_SQ1_4           (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */
#define ADC_SQR1_SQ2_Pos         (12U)
#define ADC_SQR1_SQ2_Msk         (0x1FUL << ADC_SQR1_SQ2_Pos)          /*!< 0x0001F000 */
#define ADC_SQR1_SQ2             ADC_SQR1_SQ2_Msk                      /*!< 2nd conversion in regular sequence */
#define ADC_SQR1_SQ2_0           (0x1UL << ADC_SQR1_SQ2_Pos)           /*!< 0x00001000 */
#define ADC_SQR1_SQ2_1           (0x2UL << ADC_SQR1_SQ2_Pos)           /*!< 0x00002000 */
#define ADC_SQR1_SQ2_2           (0x4UL << ADC_SQR1_SQ2_Pos)           /*!< 0x00004000 */
#define ADC_SQR1_SQ2_3           (0x8UL << ADC_SQR1_SQ2_Pos)           /*!< 0x00008000 */
#define ADC_SQR1_SQ2_4           (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */
#define ADC_SQR1_SQ3_Pos         (18U)
#define ADC_SQR1_SQ3_Msk         (0x1FUL << ADC_SQR1_SQ3_Pos)          /*!< 0x007C0000 */
#define ADC_SQR1_SQ3             ADC_SQR1_SQ3_Msk                      /*!< 3rd conversion in regular sequence */
#define ADC_SQR1_SQ3_0           (0x1UL << ADC_SQR1_SQ3_Pos)           /*!< 0x00040000 */
#define ADC_SQR1_SQ3_1           (0x2UL << ADC_SQR1_SQ3_Pos)           /*!< 0x00080000 */
#define ADC_SQR1_SQ3_2           (0x4UL << ADC_SQR1_SQ3_Pos)           /*!< 0x00100000 */
#define ADC_SQR1_SQ3_3           (0x8UL << ADC_SQR1_SQ3_Pos)           /*!< 0x00200000 */
#define ADC_SQR1_SQ3_4           (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */
#define ADC_SQR1_SQ4_Pos         (24U)
#define ADC_SQR1_SQ4_Msk         (0x1FUL << ADC_SQR1_SQ4_Pos)          /*!< 0x1F000000 */
#define ADC_SQR1_SQ4             ADC_SQR1_SQ4_Msk                      /*!< 4th conversion in regular sequence */
#define ADC_SQR1_SQ4_0           (0x1UL << ADC_SQR1_SQ4_Pos)           /*!< 0x01000000 */
#define ADC_SQR1_SQ4_1           (0x2UL << ADC_SQR1_SQ4_Pos)           /*!< 0x02000000 */
#define ADC_SQR1_SQ4_2           (0x4UL << ADC_SQR1_SQ4_Pos)           /*!< 0x04000000 */
#define ADC_SQR1_SQ4_3           (0x8UL << ADC_SQR1_SQ4_Pos)           /*!< 0x08000000 */
#define ADC_SQR1_SQ4_4           (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */

/* *************************************  Bit definition for ADC_SQR2 register  ************************************* */
#define ADC_SQR2_SQ5_Pos         (0U)
#define ADC_SQR2_SQ5_Msk         (0x1FUL << ADC_SQR2_SQ5_Pos)          /*!< 0x0000001F */
#define ADC_SQR2_SQ5             ADC_SQR2_SQ5_Msk                      /*!< 5th conversion in regular sequence */
#define ADC_SQR2_SQ5_0           (0x1UL << ADC_SQR2_SQ5_Pos)           /*!< 0x00000001 */
#define ADC_SQR2_SQ5_1           (0x2UL << ADC_SQR2_SQ5_Pos)           /*!< 0x00000002 */
#define ADC_SQR2_SQ5_2           (0x4UL << ADC_SQR2_SQ5_Pos)           /*!< 0x00000004 */
#define ADC_SQR2_SQ5_3           (0x8UL << ADC_SQR2_SQ5_Pos)           /*!< 0x00000008 */
#define ADC_SQR2_SQ5_4           (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */
#define ADC_SQR2_SQ6_Pos         (6U)
#define ADC_SQR2_SQ6_Msk         (0x1FUL << ADC_SQR2_SQ6_Pos)          /*!< 0x000007C0 */
#define ADC_SQR2_SQ6             ADC_SQR2_SQ6_Msk                      /*!< 6th conversion in regular sequence */
#define ADC_SQR2_SQ6_0           (0x1UL << ADC_SQR2_SQ6_Pos)           /*!< 0x00000040 */
#define ADC_SQR2_SQ6_1           (0x2UL << ADC_SQR2_SQ6_Pos)           /*!< 0x00000080 */
#define ADC_SQR2_SQ6_2           (0x4UL << ADC_SQR2_SQ6_Pos)           /*!< 0x00000100 */
#define ADC_SQR2_SQ6_3           (0x8UL << ADC_SQR2_SQ6_Pos)           /*!< 0x00000200 */
#define ADC_SQR2_SQ6_4           (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */
#define ADC_SQR2_SQ7_Pos         (12U)
#define ADC_SQR2_SQ7_Msk         (0x1FUL << ADC_SQR2_SQ7_Pos)          /*!< 0x0001F000 */
#define ADC_SQR2_SQ7             ADC_SQR2_SQ7_Msk                      /*!< 7th conversion in regular sequence */
#define ADC_SQR2_SQ7_0           (0x1UL << ADC_SQR2_SQ7_Pos)           /*!< 0x00001000 */
#define ADC_SQR2_SQ7_1           (0x2UL << ADC_SQR2_SQ7_Pos)           /*!< 0x00002000 */
#define ADC_SQR2_SQ7_2           (0x4UL << ADC_SQR2_SQ7_Pos)           /*!< 0x00004000 */
#define ADC_SQR2_SQ7_3           (0x8UL << ADC_SQR2_SQ7_Pos)           /*!< 0x00008000 */
#define ADC_SQR2_SQ7_4           (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */
#define ADC_SQR2_SQ8_Pos         (18U)
#define ADC_SQR2_SQ8_Msk         (0x1FUL << ADC_SQR2_SQ8_Pos)          /*!< 0x007C0000 */
#define ADC_SQR2_SQ8             ADC_SQR2_SQ8_Msk                      /*!< 8th conversion in regular sequence */
#define ADC_SQR2_SQ8_0           (0x1UL << ADC_SQR2_SQ8_Pos)           /*!< 0x00040000 */
#define ADC_SQR2_SQ8_1           (0x2UL << ADC_SQR2_SQ8_Pos)           /*!< 0x00080000 */
#define ADC_SQR2_SQ8_2           (0x4UL << ADC_SQR2_SQ8_Pos)           /*!< 0x00100000 */
#define ADC_SQR2_SQ8_3           (0x8UL << ADC_SQR2_SQ8_Pos)           /*!< 0x00200000 */
#define ADC_SQR2_SQ8_4           (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */
#define ADC_SQR2_SQ9_Pos         (24U)
#define ADC_SQR2_SQ9_Msk         (0x1FUL << ADC_SQR2_SQ9_Pos)          /*!< 0x1F000000 */
#define ADC_SQR2_SQ9             ADC_SQR2_SQ9_Msk                      /*!< 9th conversion in regular sequence */
#define ADC_SQR2_SQ9_0           (0x1UL << ADC_SQR2_SQ9_Pos)           /*!< 0x01000000 */
#define ADC_SQR2_SQ9_1           (0x2UL << ADC_SQR2_SQ9_Pos)           /*!< 0x02000000 */
#define ADC_SQR2_SQ9_2           (0x4UL << ADC_SQR2_SQ9_Pos)           /*!< 0x04000000 */
#define ADC_SQR2_SQ9_3           (0x8UL << ADC_SQR2_SQ9_Pos)           /*!< 0x08000000 */
#define ADC_SQR2_SQ9_4           (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */

/* *************************************  Bit definition for ADC_SQR3 register  ************************************* */
#define ADC_SQR3_SQ10_Pos        (0U)
#define ADC_SQR3_SQ10_Msk        (0x1FUL << ADC_SQR3_SQ10_Pos)         /*!< 0x0000001F */
#define ADC_SQR3_SQ10            ADC_SQR3_SQ10_Msk                     /*!< 10th conversion in regular sequence */
#define ADC_SQR3_SQ10_0          (0x1UL << ADC_SQR3_SQ10_Pos)          /*!< 0x00000001 */
#define ADC_SQR3_SQ10_1          (0x2UL << ADC_SQR3_SQ10_Pos)          /*!< 0x00000002 */
#define ADC_SQR3_SQ10_2          (0x4UL << ADC_SQR3_SQ10_Pos)          /*!< 0x00000004 */
#define ADC_SQR3_SQ10_3          (0x8UL << ADC_SQR3_SQ10_Pos)          /*!< 0x00000008 */
#define ADC_SQR3_SQ10_4          (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */
#define ADC_SQR3_SQ11_Pos        (6U)
#define ADC_SQR3_SQ11_Msk        (0x1FUL << ADC_SQR3_SQ11_Pos)         /*!< 0x000007C0 */
#define ADC_SQR3_SQ11            ADC_SQR3_SQ11_Msk                     /*!< 11th conversion in regular sequence */
#define ADC_SQR3_SQ11_0          (0x1UL << ADC_SQR3_SQ11_Pos)          /*!< 0x00000040 */
#define ADC_SQR3_SQ11_1          (0x2UL << ADC_SQR3_SQ11_Pos)          /*!< 0x00000080 */
#define ADC_SQR3_SQ11_2          (0x4UL << ADC_SQR3_SQ11_Pos)          /*!< 0x00000100 */
#define ADC_SQR3_SQ11_3          (0x8UL << ADC_SQR3_SQ11_Pos)          /*!< 0x00000200 */
#define ADC_SQR3_SQ11_4          (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */
#define ADC_SQR3_SQ12_Pos        (12U)
#define ADC_SQR3_SQ12_Msk        (0x1FUL << ADC_SQR3_SQ12_Pos)         /*!< 0x0001F000 */
#define ADC_SQR3_SQ12            ADC_SQR3_SQ12_Msk                     /*!< 12th conversion in regular sequence */
#define ADC_SQR3_SQ12_0          (0x1UL << ADC_SQR3_SQ12_Pos)          /*!< 0x00001000 */
#define ADC_SQR3_SQ12_1          (0x2UL << ADC_SQR3_SQ12_Pos)          /*!< 0x00002000 */
#define ADC_SQR3_SQ12_2          (0x4UL << ADC_SQR3_SQ12_Pos)          /*!< 0x00004000 */
#define ADC_SQR3_SQ12_3          (0x8UL << ADC_SQR3_SQ12_Pos)          /*!< 0x00008000 */
#define ADC_SQR3_SQ12_4          (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */
#define ADC_SQR3_SQ13_Pos        (18U)
#define ADC_SQR3_SQ13_Msk        (0x1FUL << ADC_SQR3_SQ13_Pos)         /*!< 0x007C0000 */
#define ADC_SQR3_SQ13            ADC_SQR3_SQ13_Msk                     /*!< 13th conversion in regular sequence */
#define ADC_SQR3_SQ13_0          (0x1UL << ADC_SQR3_SQ13_Pos)          /*!< 0x00040000 */
#define ADC_SQR3_SQ13_1          (0x2UL << ADC_SQR3_SQ13_Pos)          /*!< 0x00080000 */
#define ADC_SQR3_SQ13_2          (0x4UL << ADC_SQR3_SQ13_Pos)          /*!< 0x00100000 */
#define ADC_SQR3_SQ13_3          (0x8UL << ADC_SQR3_SQ13_Pos)          /*!< 0x00200000 */
#define ADC_SQR3_SQ13_4          (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */
#define ADC_SQR3_SQ14_Pos        (24U)
#define ADC_SQR3_SQ14_Msk        (0x1FUL << ADC_SQR3_SQ14_Pos)         /*!< 0x1F000000 */
#define ADC_SQR3_SQ14            ADC_SQR3_SQ14_Msk                     /*!< 14th conversion in regular sequence */
#define ADC_SQR3_SQ14_0          (0x1UL << ADC_SQR3_SQ14_Pos)          /*!< 0x01000000 */
#define ADC_SQR3_SQ14_1          (0x2UL << ADC_SQR3_SQ14_Pos)          /*!< 0x02000000 */
#define ADC_SQR3_SQ14_2          (0x4UL << ADC_SQR3_SQ14_Pos)          /*!< 0x04000000 */
#define ADC_SQR3_SQ14_3          (0x8UL << ADC_SQR3_SQ14_Pos)          /*!< 0x08000000 */
#define ADC_SQR3_SQ14_4          (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */

/* *************************************  Bit definition for ADC_SQR4 register  ************************************* */
#define ADC_SQR4_SQ15_Pos        (0U)
#define ADC_SQR4_SQ15_Msk        (0x1FUL << ADC_SQR4_SQ15_Pos)         /*!< 0x0000001F */
#define ADC_SQR4_SQ15            ADC_SQR4_SQ15_Msk                     /*!< 15th conversion in regular sequence */
#define ADC_SQR4_SQ15_0          (0x1UL << ADC_SQR4_SQ15_Pos)          /*!< 0x00000001 */
#define ADC_SQR4_SQ15_1          (0x2UL << ADC_SQR4_SQ15_Pos)          /*!< 0x00000002 */
#define ADC_SQR4_SQ15_2          (0x4UL << ADC_SQR4_SQ15_Pos)          /*!< 0x00000004 */
#define ADC_SQR4_SQ15_3          (0x8UL << ADC_SQR4_SQ15_Pos)          /*!< 0x00000008 */
#define ADC_SQR4_SQ15_4          (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */
#define ADC_SQR4_SQ16_Pos        (6U)
#define ADC_SQR4_SQ16_Msk        (0x1FUL << ADC_SQR4_SQ16_Pos)         /*!< 0x000007C0 */
#define ADC_SQR4_SQ16            ADC_SQR4_SQ16_Msk                     /*!< 16th conversion in regular sequence */
#define ADC_SQR4_SQ16_0          (0x1UL << ADC_SQR4_SQ16_Pos)          /*!< 0x00000040 */
#define ADC_SQR4_SQ16_1          (0x2UL << ADC_SQR4_SQ16_Pos)          /*!< 0x00000080 */
#define ADC_SQR4_SQ16_2          (0x4UL << ADC_SQR4_SQ16_Pos)          /*!< 0x00000100 */
#define ADC_SQR4_SQ16_3          (0x8UL << ADC_SQR4_SQ16_Pos)          /*!< 0x00000200 */
#define ADC_SQR4_SQ16_4          (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */

/* **************************************  Bit definition for ADC_DR register  ************************************** */
#define ADC_DR_RDATA_Pos         (0U)
#define ADC_DR_RDATA_Msk         (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)    /*!< 0xFFFFFFFF */
#define ADC_DR_RDATA             ADC_DR_RDATA_Msk                      /*!< Regular data converted */
#define ADC_DR_RDATA_0           (0x1UL << ADC_DR_RDATA_Pos)           /*!< 0x00000001 */
#define ADC_DR_RDATA_1           (0x2UL << ADC_DR_RDATA_Pos)           /*!< 0x00000002 */
#define ADC_DR_RDATA_2           (0x4UL << ADC_DR_RDATA_Pos)           /*!< 0x00000004 */
#define ADC_DR_RDATA_3           (0x8UL << ADC_DR_RDATA_Pos)           /*!< 0x00000008 */
#define ADC_DR_RDATA_4           (0x10UL << ADC_DR_RDATA_Pos)          /*!< 0x00000010 */
#define ADC_DR_RDATA_5           (0x20UL << ADC_DR_RDATA_Pos)          /*!< 0x00000020 */
#define ADC_DR_RDATA_6           (0x40UL << ADC_DR_RDATA_Pos)          /*!< 0x00000040 */
#define ADC_DR_RDATA_7           (0x80UL << ADC_DR_RDATA_Pos)          /*!< 0x00000080 */
#define ADC_DR_RDATA_8           (0x100UL << ADC_DR_RDATA_Pos)         /*!< 0x00000100 */
#define ADC_DR_RDATA_9           (0x200UL << ADC_DR_RDATA_Pos)         /*!< 0x00000200 */
#define ADC_DR_RDATA_10          (0x400UL << ADC_DR_RDATA_Pos)         /*!< 0x00000400 */
#define ADC_DR_RDATA_11          (0x800UL << ADC_DR_RDATA_Pos)         /*!< 0x00000800 */
#define ADC_DR_RDATA_12          (0x1000UL << ADC_DR_RDATA_Pos)        /*!< 0x00001000 */
#define ADC_DR_RDATA_13          (0x2000UL << ADC_DR_RDATA_Pos)        /*!< 0x00002000 */
#define ADC_DR_RDATA_14          (0x4000UL << ADC_DR_RDATA_Pos)        /*!< 0x00004000 */
#define ADC_DR_RDATA_15          (0x8000UL << ADC_DR_RDATA_Pos)        /*!< 0x00008000 */
#define ADC_DR_RDATA_16          (0x10000UL << ADC_DR_RDATA_Pos)       /*!< 0x00010000 */
#define ADC_DR_RDATA_17          (0x20000UL << ADC_DR_RDATA_Pos)       /*!< 0x00020000 */
#define ADC_DR_RDATA_18          (0x40000UL << ADC_DR_RDATA_Pos)       /*!< 0x00040000 */
#define ADC_DR_RDATA_19          (0x80000UL << ADC_DR_RDATA_Pos)       /*!< 0x00080000 */
#define ADC_DR_RDATA_20          (0x100000UL << ADC_DR_RDATA_Pos)      /*!< 0x00100000 */
#define ADC_DR_RDATA_21          (0x200000UL << ADC_DR_RDATA_Pos)      /*!< 0x00200000 */
#define ADC_DR_RDATA_22          (0x400000UL << ADC_DR_RDATA_Pos)      /*!< 0x00400000 */
#define ADC_DR_RDATA_23          (0x800000UL << ADC_DR_RDATA_Pos)      /*!< 0x00800000 */
#define ADC_DR_RDATA_24          (0x1000000UL << ADC_DR_RDATA_Pos)     /*!< 0x01000000 */
#define ADC_DR_RDATA_25          (0x2000000UL << ADC_DR_RDATA_Pos)     /*!< 0x02000000 */
#define ADC_DR_RDATA_26          (0x4000000UL << ADC_DR_RDATA_Pos)     /*!< 0x04000000 */
#define ADC_DR_RDATA_27          (0x8000000UL << ADC_DR_RDATA_Pos)     /*!< 0x08000000 */
#define ADC_DR_RDATA_28          (0x10000000UL << ADC_DR_RDATA_Pos)    /*!< 0x10000000 */
#define ADC_DR_RDATA_29          (0x20000000UL << ADC_DR_RDATA_Pos)    /*!< 0x20000000 */
#define ADC_DR_RDATA_30          (0x40000000UL << ADC_DR_RDATA_Pos)    /*!< 0x40000000 */
#define ADC_DR_RDATA_31          (0x80000000UL << ADC_DR_RDATA_Pos)    /*!< 0x80000000 */

/* *************************************  Bit definition for ADC_JSQR register  ************************************* */
#define ADC_JSQR_JLEN_Pos        (0U)
#define ADC_JSQR_JLEN_Msk        (0x3UL << ADC_JSQR_JLEN_Pos)          /*!< 0x00000003 */
#define ADC_JSQR_JLEN            ADC_JSQR_JLEN_Msk                     /*!< Injected channel sequence length */
#define ADC_JSQR_JLEN_0          (0x1UL << ADC_JSQR_JLEN_Pos)          /*!< 0x00000001 */
#define ADC_JSQR_JLEN_1          (0x2UL << ADC_JSQR_JLEN_Pos)          /*!< 0x00000002 */
#define ADC_JSQR_JEXTSEL_Pos     (2U)
#define ADC_JSQR_JEXTSEL_Msk     (0x1FUL << ADC_JSQR_JEXTSEL_Pos)      /*!< 0x0000007C */
#define ADC_JSQR_JEXTSEL         ADC_JSQR_JEXTSEL_Msk                  /*!< External trigger selection for injected
                                                                            group */
#define ADC_JSQR_JEXTSEL_0       (0x1UL << ADC_JSQR_JEXTSEL_Pos)       /*!< 0x00000004 */
#define ADC_JSQR_JEXTSEL_1       (0x2UL << ADC_JSQR_JEXTSEL_Pos)       /*!< 0x00000008 */
#define ADC_JSQR_JEXTSEL_2       (0x4UL << ADC_JSQR_JEXTSEL_Pos)       /*!< 0x00000010 */
#define ADC_JSQR_JEXTSEL_3       (0x8UL << ADC_JSQR_JEXTSEL_Pos)       /*!< 0x00000020 */
#define ADC_JSQR_JEXTSEL_4       (0x10UL << ADC_JSQR_JEXTSEL_Pos)      /*!< 0x00000040 */
#define ADC_JSQR_JEXTEN_Pos      (7U)
#define ADC_JSQR_JEXTEN_Msk      (0x3UL << ADC_JSQR_JEXTEN_Pos)        /*!< 0x00000180 */
#define ADC_JSQR_JEXTEN          ADC_JSQR_JEXTEN_Msk                   /*!< External trigger enable and polarity
                                                                            selection for injected channels */
#define ADC_JSQR_JEXTEN_0        (0x1UL << ADC_JSQR_JEXTEN_Pos)        /*!< 0x00000080 */
#define ADC_JSQR_JEXTEN_1        (0x2UL << ADC_JSQR_JEXTEN_Pos)        /*!< 0x00000100 */
#define ADC_JSQR_JSQ1_Pos        (9U)
#define ADC_JSQR_JSQ1_Msk        (0x1FUL << ADC_JSQR_JSQ1_Pos)         /*!< 0x00003E00 */
#define ADC_JSQR_JSQ1            ADC_JSQR_JSQ1_Msk                     /*!< 1st conversion in the injected sequence */
#define ADC_JSQR_JSQ1_0          (0x1UL << ADC_JSQR_JSQ1_Pos)          /*!< 0x00000200 */
#define ADC_JSQR_JSQ1_1          (0x2UL << ADC_JSQR_JSQ1_Pos)          /*!< 0x00000400 */
#define ADC_JSQR_JSQ1_2          (0x4UL << ADC_JSQR_JSQ1_Pos)          /*!< 0x00000800 */
#define ADC_JSQR_JSQ1_3          (0x8UL << ADC_JSQR_JSQ1_Pos)          /*!< 0x00001000 */
#define ADC_JSQR_JSQ1_4          (0x10UL << ADC_JSQR_JSQ1_Pos)         /*!< 0x00002000 */
#define ADC_JSQR_JSQ2_Pos        (15U)
#define ADC_JSQR_JSQ2_Msk        (0x1FUL << ADC_JSQR_JSQ2_Pos)         /*!< 0x000F8000 */
#define ADC_JSQR_JSQ2            ADC_JSQR_JSQ2_Msk                     /*!< 2nd conversion in the injected sequence */
#define ADC_JSQR_JSQ2_0          (0x1UL << ADC_JSQR_JSQ2_Pos)          /*!< 0x00008000 */
#define ADC_JSQR_JSQ2_1          (0x2UL << ADC_JSQR_JSQ2_Pos)          /*!< 0x00010000 */
#define ADC_JSQR_JSQ2_2          (0x4UL << ADC_JSQR_JSQ2_Pos)          /*!< 0x00020000 */
#define ADC_JSQR_JSQ2_3          (0x8UL << ADC_JSQR_JSQ2_Pos)          /*!< 0x00040000 */
#define ADC_JSQR_JSQ2_4          (0x10UL << ADC_JSQR_JSQ2_Pos)         /*!< 0x00080000 */
#define ADC_JSQR_JSQ3_Pos        (21U)
#define ADC_JSQR_JSQ3_Msk        (0x1FUL << ADC_JSQR_JSQ3_Pos)         /*!< 0x03E00000 */
#define ADC_JSQR_JSQ3            ADC_JSQR_JSQ3_Msk                     /*!< 3rd conversion in the injected sequence */
#define ADC_JSQR_JSQ3_0          (0x1UL << ADC_JSQR_JSQ3_Pos)          /*!< 0x00200000 */
#define ADC_JSQR_JSQ3_1          (0x2UL << ADC_JSQR_JSQ3_Pos)          /*!< 0x00400000 */
#define ADC_JSQR_JSQ3_2          (0x4UL << ADC_JSQR_JSQ3_Pos)          /*!< 0x00800000 */
#define ADC_JSQR_JSQ3_3          (0x8UL << ADC_JSQR_JSQ3_Pos)          /*!< 0x01000000 */
#define ADC_JSQR_JSQ3_4          (0x10UL << ADC_JSQR_JSQ3_Pos)         /*!< 0x02000000 */
#define ADC_JSQR_JSQ4_Pos        (27U)
#define ADC_JSQR_JSQ4_Msk        (0x1FUL << ADC_JSQR_JSQ4_Pos)         /*!< 0xF8000000 */
#define ADC_JSQR_JSQ4            ADC_JSQR_JSQ4_Msk                     /*!< 4th conversion in the injected sequence */
#define ADC_JSQR_JSQ4_0          (0x1UL << ADC_JSQR_JSQ4_Pos)          /*!< 0x08000000 */
#define ADC_JSQR_JSQ4_1          (0x2UL << ADC_JSQR_JSQ4_Pos)          /*!< 0x10000000 */
#define ADC_JSQR_JSQ4_2          (0x4UL << ADC_JSQR_JSQ4_Pos)          /*!< 0x20000000 */
#define ADC_JSQR_JSQ4_3          (0x8UL << ADC_JSQR_JSQ4_Pos)          /*!< 0x40000000 */
#define ADC_JSQR_JSQ4_4          (0x10UL << ADC_JSQR_JSQ4_Pos)         /*!< 0x80000000 */

/* ************************************  Bit definition for ADC_OFCFGR register  ************************************ */
#define ADC_OFCFGR_POSOFF_Pos    (24U)
#define ADC_OFCFGR_POSOFF_Msk    (0x1UL << ADC_OFCFGR_POSOFF_Pos)      /*!< 0x01000000 */
#define ADC_OFCFGR_POSOFF        ADC_OFCFGR_POSOFF_Msk                 /*!< Positive offset enable */
#define ADC_OFCFGR_USAT_Pos      (25U)
#define ADC_OFCFGR_USAT_Msk      (0x1UL << ADC_OFCFGR_USAT_Pos)        /*!< 0x02000000 */
#define ADC_OFCFGR_USAT          ADC_OFCFGR_USAT_Msk                   /*!< Unsigned saturation enable */
#define ADC_OFCFGR_SSAT_Pos      (26U)
#define ADC_OFCFGR_SSAT_Msk      (0x1UL << ADC_OFCFGR_SSAT_Pos)        /*!< 0x04000000 */
#define ADC_OFCFGR_SSAT          ADC_OFCFGR_SSAT_Msk                   /*!< Signed saturation enable */
#define ADC_OFCFGR_OFFSET_CH_Pos (27U)
#define ADC_OFCFGR_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR_OFFSET_CH_Pos)  /*!< 0xF8000000 */
#define ADC_OFCFGR_OFFSET_CH     ADC_OFCFGR_OFFSET_CH_Msk              /*!< Channel selection for the data offset y */
#define ADC_OFCFGR_OFFSET_CH_0   (0x01UL << ADC_OFCFGR_OFFSET_CH_Pos)  /*!< 0x08000000 */
#define ADC_OFCFGR_OFFSET_CH_1   (0x02UL << ADC_OFCFGR_OFFSET_CH_Pos)  /*!< 0x10000000 */
#define ADC_OFCFGR_OFFSET_CH_2   (0x03UL << ADC_OFCFGR_OFFSET_CH_Pos)  /*!< 0x20000000 */
#define ADC_OFCFGR_OFFSET_CH_3   (0x04UL << ADC_OFCFGR_OFFSET_CH_Pos)  /*!< 0x40000000 */
#define ADC_OFCFGR_OFFSET_CH_4   (0x05UL << ADC_OFCFGR_OFFSET_CH_Pos)  /*!< 0x80000000 */

/* *************************************  Bit definition for ADC_OFR register  ************************************** */
#define ADC_OFR_OFFSET_Pos       (0U)
#define ADC_OFR_OFFSET_Msk       (0x3FFFFFUL << ADC_OFR_OFFSET_Pos)    /*!< 0x003FFFFF */
#define ADC_OFR_OFFSET           ADC_OFR_OFFSET_Msk                    /*!< Data offset y for the channel programmed in
                                                                            OFFSETy_CH[4:0] bits */
#define ADC_OFR_OFFSET_0         (0x1UL << ADC_OFR_OFFSET_Pos)         /*!< 0x00000001 */
#define ADC_OFR_OFFSET_1         (0x2UL << ADC_OFR_OFFSET_Pos)         /*!< 0x00000002 */
#define ADC_OFR_OFFSET_2         (0x4UL << ADC_OFR_OFFSET_Pos)         /*!< 0x00000004 */
#define ADC_OFR_OFFSET_3         (0x8UL << ADC_OFR_OFFSET_Pos)         /*!< 0x00000008 */
#define ADC_OFR_OFFSET_4         (0x10UL << ADC_OFR_OFFSET_Pos)        /*!< 0x00000010 */
#define ADC_OFR_OFFSET_5         (0x20UL << ADC_OFR_OFFSET_Pos)        /*!< 0x00000020 */
#define ADC_OFR_OFFSET_6         (0x40UL << ADC_OFR_OFFSET_Pos)        /*!< 0x00000040 */
#define ADC_OFR_OFFSET_7         (0x80UL << ADC_OFR_OFFSET_Pos)        /*!< 0x00000080 */
#define ADC_OFR_OFFSET_8         (0x100UL << ADC_OFR_OFFSET_Pos)       /*!< 0x00000100 */
#define ADC_OFR_OFFSET_9         (0x200UL << ADC_OFR_OFFSET_Pos)       /*!< 0x00000200 */
#define ADC_OFR_OFFSET_10        (0x400UL << ADC_OFR_OFFSET_Pos)       /*!< 0x00000400 */
#define ADC_OFR_OFFSET_11        (0x800UL << ADC_OFR_OFFSET_Pos)       /*!< 0x00000800 */
#define ADC_OFR_OFFSET_12        (0x1000UL << ADC_OFR_OFFSET_Pos)      /*!< 0x00001000 */
#define ADC_OFR_OFFSET_13        (0x2000UL << ADC_OFR_OFFSET_Pos)      /*!< 0x00002000 */
#define ADC_OFR_OFFSET_14        (0x4000UL << ADC_OFR_OFFSET_Pos)      /*!< 0x00004000 */
#define ADC_OFR_OFFSET_15        (0x8000UL << ADC_OFR_OFFSET_Pos)      /*!< 0x00008000 */
#define ADC_OFR_OFFSET_16        (0x10000UL << ADC_OFR_OFFSET_Pos)     /*!< 0x00010000 */
#define ADC_OFR_OFFSET_17        (0x20000UL << ADC_OFR_OFFSET_Pos)     /*!< 0x00020000 */
#define ADC_OFR_OFFSET_18        (0x40000UL << ADC_OFR_OFFSET_Pos)     /*!< 0x00040000 */
#define ADC_OFR_OFFSET_19        (0x80000UL << ADC_OFR_OFFSET_Pos)     /*!< 0x00080000 */
#define ADC_OFR_OFFSET_20        (0x100000UL << ADC_OFR_OFFSET_Pos)    /*!< 0x00100000 */
#define ADC_OFR_OFFSET_21        (0x200000UL << ADC_OFR_OFFSET_Pos)    /*!< 0x00200000 */

/* ************************************  Bit definition for ADC_GCOMP register  ************************************* */
#define ADC_GCOMP_GCOMPCOEFF_Pos (0U)
#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */
#define ADC_GCOMP_GCOMPCOEFF     ADC_GCOMP_GCOMPCOEFF_Msk              /*!< Gain compensation coefficient */
#define ADC_GCOMP_GCOMP_Pos      (31U)
#define ADC_GCOMP_GCOMP_Msk      (0x1UL << ADC_GCOMP_GCOMP_Pos)        /*!< 0x80000000 */
#define ADC_GCOMP_GCOMP          ADC_GCOMP_GCOMP_Msk                   /*!< Gain compensation mode */

/* *************************************  Bit definition for ADC_JDR register  ************************************** */
#define ADC_JDR_JDATA_Pos        (0U)
#define ADC_JDR_JDATA_Msk        (0xFFFFFFFFUL << ADC_JDR_JDATA_Pos)   /*!< 0xFFFFFFFF */
#define ADC_JDR_JDATA            ADC_JDR_JDATA_Msk                     /*!< Injected data */
#define ADC_JDR_JDATA_0          (0x1UL << ADC_JDR_JDATA_Pos)          /*!< 0x00000001 */
#define ADC_JDR_JDATA_1          (0x2UL << ADC_JDR_JDATA_Pos)          /*!< 0x00000002 */
#define ADC_JDR_JDATA_2          (0x4UL << ADC_JDR_JDATA_Pos)          /*!< 0x00000004 */
#define ADC_JDR_JDATA_3          (0x8UL << ADC_JDR_JDATA_Pos)          /*!< 0x00000008 */
#define ADC_JDR_JDATA_4          (0x10UL << ADC_JDR_JDATA_Pos)         /*!< 0x00000010 */
#define ADC_JDR_JDATA_5          (0x20UL << ADC_JDR_JDATA_Pos)         /*!< 0x00000020 */
#define ADC_JDR_JDATA_6          (0x40UL << ADC_JDR_JDATA_Pos)         /*!< 0x00000040 */
#define ADC_JDR_JDATA_7          (0x80UL << ADC_JDR_JDATA_Pos)         /*!< 0x00000080 */
#define ADC_JDR_JDATA_8          (0x100UL << ADC_JDR_JDATA_Pos)        /*!< 0x00000100 */
#define ADC_JDR_JDATA_9          (0x200UL << ADC_JDR_JDATA_Pos)        /*!< 0x00000200 */
#define ADC_JDR_JDATA_10         (0x400UL << ADC_JDR_JDATA_Pos)        /*!< 0x00000400 */
#define ADC_JDR_JDATA_11         (0x800UL << ADC_JDR_JDATA_Pos)        /*!< 0x00000800 */
#define ADC_JDR_JDATA_12         (0x1000UL << ADC_JDR_JDATA_Pos)       /*!< 0x00001000 */
#define ADC_JDR_JDATA_13         (0x2000UL << ADC_JDR_JDATA_Pos)       /*!< 0x00002000 */
#define ADC_JDR_JDATA_14         (0x4000UL << ADC_JDR_JDATA_Pos)       /*!< 0x00004000 */
#define ADC_JDR_JDATA_15         (0x8000UL << ADC_JDR_JDATA_Pos)       /*!< 0x00008000 */
#define ADC_JDR_JDATA_16         (0x10000UL << ADC_JDR_JDATA_Pos)      /*!< 0x00010000 */
#define ADC_JDR_JDATA_17         (0x20000UL << ADC_JDR_JDATA_Pos)      /*!< 0x00020000 */
#define ADC_JDR_JDATA_18         (0x40000UL << ADC_JDR_JDATA_Pos)      /*!< 0x00040000 */
#define ADC_JDR_JDATA_19         (0x80000UL << ADC_JDR_JDATA_Pos)      /*!< 0x00080000 */
#define ADC_JDR_JDATA_20         (0x100000UL << ADC_JDR_JDATA_Pos)     /*!< 0x00100000 */
#define ADC_JDR_JDATA_21         (0x200000UL << ADC_JDR_JDATA_Pos)     /*!< 0x00200000 */
#define ADC_JDR_JDATA_22         (0x400000UL << ADC_JDR_JDATA_Pos)     /*!< 0x00400000 */
#define ADC_JDR_JDATA_23         (0x800000UL << ADC_JDR_JDATA_Pos)     /*!< 0x00800000 */
#define ADC_JDR_JDATA_24         (0x1000000UL << ADC_JDR_JDATA_Pos)    /*!< 0x01000000 */
#define ADC_JDR_JDATA_25         (0x2000000UL << ADC_JDR_JDATA_Pos)    /*!< 0x02000000 */
#define ADC_JDR_JDATA_26         (0x4000000UL << ADC_JDR_JDATA_Pos)    /*!< 0x04000000 */
#define ADC_JDR_JDATA_27         (0x8000000UL << ADC_JDR_JDATA_Pos)    /*!< 0x08000000 */
#define ADC_JDR_JDATA_28         (0x10000000UL << ADC_JDR_JDATA_Pos)   /*!< 0x10000000 */
#define ADC_JDR_JDATA_29         (0x20000000UL << ADC_JDR_JDATA_Pos)   /*!< 0x20000000 */
#define ADC_JDR_JDATA_30         (0x40000000UL << ADC_JDR_JDATA_Pos)   /*!< 0x40000000 */
#define ADC_JDR_JDATA_31         (0x80000000UL << ADC_JDR_JDATA_Pos)   /*!< 0x80000000 */

/* ************************************  Bit definition for ADC_AWD2CR register  ************************************ */
#define ADC_AWD2CR_AWDCH_Pos     (0U)
#define ADC_AWD2CR_AWDCH_Msk     (0x3FFFUL << ADC_AWD2CR_AWDCH_Pos)    /*!< 0x00003FFF */
#define ADC_AWD2CR_AWDCH         ADC_AWD2CR_AWDCH_Msk                  /*!< Analog watchdog 2 channel selection */
#define ADC_AWD2CR_AWDCH_0       (0x1UL << ADC_AWD2CR_AWDCH_Pos)       /*!< 0x00000001 */
#define ADC_AWD2CR_AWDCH_1       (0x2UL << ADC_AWD2CR_AWDCH_Pos)       /*!< 0x00000002 */
#define ADC_AWD2CR_AWDCH_2       (0x4UL << ADC_AWD2CR_AWDCH_Pos)       /*!< 0x00000004 */
#define ADC_AWD2CR_AWDCH_3       (0x8UL << ADC_AWD2CR_AWDCH_Pos)       /*!< 0x00000008 */
#define ADC_AWD2CR_AWDCH_4       (0x10UL << ADC_AWD2CR_AWDCH_Pos)      /*!< 0x00000010 */
#define ADC_AWD2CR_AWDCH_5       (0x20UL << ADC_AWD2CR_AWDCH_Pos)      /*!< 0x00000020 */
#define ADC_AWD2CR_AWDCH_6       (0x40UL << ADC_AWD2CR_AWDCH_Pos)      /*!< 0x00000040 */
#define ADC_AWD2CR_AWDCH_7       (0x80UL << ADC_AWD2CR_AWDCH_Pos)      /*!< 0x00000080 */
#define ADC_AWD2CR_AWDCH_8       (0x100UL << ADC_AWD2CR_AWDCH_Pos)     /*!< 0x00000100 */
#define ADC_AWD2CR_AWDCH_9       (0x200UL << ADC_AWD2CR_AWDCH_Pos)     /*!< 0x00000200 */
#define ADC_AWD2CR_AWDCH_10      (0x400UL << ADC_AWD2CR_AWDCH_Pos)     /*!< 0x00000400 */
#define ADC_AWD2CR_AWDCH_11      (0x800UL << ADC_AWD2CR_AWDCH_Pos)     /*!< 0x00000800 */
#define ADC_AWD2CR_AWDCH_12      (0x1000UL << ADC_AWD2CR_AWDCH_Pos)    /*!< 0x00001000 */
#define ADC_AWD2CR_AWDCH_13      (0x2000UL << ADC_AWD2CR_AWDCH_Pos)    /*!< 0x00002000 */

/* ************************************  Bit definition for ADC_AWD3CR register  ************************************ */
#define ADC_AWD3CR_AWDCH_Pos     (0U)
#define ADC_AWD3CR_AWDCH_Msk     (0x3FFFUL << ADC_AWD3CR_AWDCH_Pos)    /*!< 0x00003FFF */
#define ADC_AWD3CR_AWDCH         ADC_AWD3CR_AWDCH_Msk                  /*!< Analog watchdog 3 channel selection */
#define ADC_AWD3CR_AWDCH_0       (0x1UL << ADC_AWD3CR_AWDCH_Pos)       /*!< 0x00000001 */
#define ADC_AWD3CR_AWDCH_1       (0x2UL << ADC_AWD3CR_AWDCH_Pos)       /*!< 0x00000002 */
#define ADC_AWD3CR_AWDCH_2       (0x4UL << ADC_AWD3CR_AWDCH_Pos)       /*!< 0x00000004 */
#define ADC_AWD3CR_AWDCH_3       (0x8UL << ADC_AWD3CR_AWDCH_Pos)       /*!< 0x00000008 */
#define ADC_AWD3CR_AWDCH_4       (0x10UL << ADC_AWD3CR_AWDCH_Pos)      /*!< 0x00000010 */
#define ADC_AWD3CR_AWDCH_5       (0x20UL << ADC_AWD3CR_AWDCH_Pos)      /*!< 0x00000020 */
#define ADC_AWD3CR_AWDCH_6       (0x40UL << ADC_AWD3CR_AWDCH_Pos)      /*!< 0x00000040 */
#define ADC_AWD3CR_AWDCH_7       (0x80UL << ADC_AWD3CR_AWDCH_Pos)      /*!< 0x00000080 */
#define ADC_AWD3CR_AWDCH_8       (0x100UL << ADC_AWD3CR_AWDCH_Pos)     /*!< 0x00000100 */
#define ADC_AWD3CR_AWDCH_9       (0x200UL << ADC_AWD3CR_AWDCH_Pos)     /*!< 0x00000200 */
#define ADC_AWD3CR_AWDCH_10      (0x400UL << ADC_AWD3CR_AWDCH_Pos)     /*!< 0x00000400 */
#define ADC_AWD3CR_AWDCH_11      (0x800UL << ADC_AWD3CR_AWDCH_Pos)     /*!< 0x00000800 */
#define ADC_AWD3CR_AWDCH_12      (0x1000UL << ADC_AWD3CR_AWDCH_Pos)    /*!< 0x00001000 */
#define ADC_AWD3CR_AWDCH_13      (0x2000UL << ADC_AWD3CR_AWDCH_Pos)    /*!< 0x00002000 */

/* ***********************************  Bit definition for ADC_AWD1LTR register  ************************************ */
#define ADC_AWD1LTR_LTR_Pos      (0U)
#define ADC_AWD1LTR_LTR_Msk      (0x7FFFFFUL << ADC_AWD1LTR_LTR_Pos)   /*!< 0x007FFFFF */
#define ADC_AWD1LTR_LTR          ADC_AWD1LTR_LTR_Msk                   /*!< Analog watchdog 1 lower threshold */
#define ADC_AWD1LTR_LTR_0        (0x1UL << ADC_AWD1LTR_LTR_Pos)        /*!< 0x00000001 */
#define ADC_AWD1LTR_LTR_1        (0x2UL << ADC_AWD1LTR_LTR_Pos)        /*!< 0x00000002 */
#define ADC_AWD1LTR_LTR_2        (0x4UL << ADC_AWD1LTR_LTR_Pos)        /*!< 0x00000004 */
#define ADC_AWD1LTR_LTR_3        (0x8UL << ADC_AWD1LTR_LTR_Pos)        /*!< 0x00000008 */
#define ADC_AWD1LTR_LTR_4        (0x10UL << ADC_AWD1LTR_LTR_Pos)       /*!< 0x00000010 */
#define ADC_AWD1LTR_LTR_5        (0x20UL << ADC_AWD1LTR_LTR_Pos)       /*!< 0x00000020 */
#define ADC_AWD1LTR_LTR_6        (0x40UL << ADC_AWD1LTR_LTR_Pos)       /*!< 0x00000040 */
#define ADC_AWD1LTR_LTR_7        (0x80UL << ADC_AWD1LTR_LTR_Pos)       /*!< 0x00000080 */
#define ADC_AWD1LTR_LTR_8        (0x100UL << ADC_AWD1LTR_LTR_Pos)      /*!< 0x00000100 */
#define ADC_AWD1LTR_LTR_9        (0x200UL << ADC_AWD1LTR_LTR_Pos)      /*!< 0x00000200 */
#define ADC_AWD1LTR_LTR_10       (0x400UL << ADC_AWD1LTR_LTR_Pos)      /*!< 0x00000400 */
#define ADC_AWD1LTR_LTR_11       (0x800UL << ADC_AWD1LTR_LTR_Pos)      /*!< 0x00000800 */
#define ADC_AWD1LTR_LTR_12       (0x1000UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00001000 */
#define ADC_AWD1LTR_LTR_13       (0x2000UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00002000 */
#define ADC_AWD1LTR_LTR_14       (0x4000UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00004000 */
#define ADC_AWD1LTR_LTR_15       (0x8000UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00008000 */
#define ADC_AWD1LTR_LTR_16       (0x10000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00010000 */
#define ADC_AWD1LTR_LTR_17       (0x20000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00020000 */
#define ADC_AWD1LTR_LTR_18       (0x40000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00040000 */
#define ADC_AWD1LTR_LTR_19       (0x80000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00080000 */
#define ADC_AWD1LTR_LTR_20       (0x100000UL << ADC_AWD1LTR_LTR_Pos)   /*!< 0x00100000 */
#define ADC_AWD1LTR_LTR_21       (0x200000UL << ADC_AWD1LTR_LTR_Pos)   /*!< 0x00200000 */
#define ADC_AWD1LTR_LTR_22       (0x400000UL << ADC_AWD1LTR_LTR_Pos)   /*!< 0x00400000 */

/* ***********************************  Bit definition for ADC_AWD1HTR register  ************************************ */
#define ADC_AWD1HTR_HTR_Pos      (0U)
#define ADC_AWD1HTR_HTR_Msk      (0x7FFFFFUL << ADC_AWD1HTR_HTR_Pos)   /*!< 0x007FFFFF */
#define ADC_AWD1HTR_HTR          ADC_AWD1HTR_HTR_Msk                   /*!< Analog watchdog 1 higher threshold */
#define ADC_AWD1HTR_HTR_0        (0x1UL << ADC_AWD1HTR_HTR_Pos)        /*!< 0x00000001 */
#define ADC_AWD1HTR_HTR_1        (0x2UL << ADC_AWD1HTR_HTR_Pos)        /*!< 0x00000002 */
#define ADC_AWD1HTR_HTR_2        (0x4UL << ADC_AWD1HTR_HTR_Pos)        /*!< 0x00000004 */
#define ADC_AWD1HTR_HTR_3        (0x8UL << ADC_AWD1HTR_HTR_Pos)        /*!< 0x00000008 */
#define ADC_AWD1HTR_HTR_4        (0x10UL << ADC_AWD1HTR_HTR_Pos)       /*!< 0x00000010 */
#define ADC_AWD1HTR_HTR_5        (0x20UL << ADC_AWD1HTR_HTR_Pos)       /*!< 0x00000020 */
#define ADC_AWD1HTR_HTR_6        (0x40UL << ADC_AWD1HTR_HTR_Pos)       /*!< 0x00000040 */
#define ADC_AWD1HTR_HTR_7        (0x80UL << ADC_AWD1HTR_HTR_Pos)       /*!< 0x00000080 */
#define ADC_AWD1HTR_HTR_8        (0x100UL << ADC_AWD1HTR_HTR_Pos)      /*!< 0x00000100 */
#define ADC_AWD1HTR_HTR_9        (0x200UL << ADC_AWD1HTR_HTR_Pos)      /*!< 0x00000200 */
#define ADC_AWD1HTR_HTR_10       (0x400UL << ADC_AWD1HTR_HTR_Pos)      /*!< 0x00000400 */
#define ADC_AWD1HTR_HTR_11       (0x800UL << ADC_AWD1HTR_HTR_Pos)      /*!< 0x00000800 */
#define ADC_AWD1HTR_HTR_12       (0x1000UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00001000 */
#define ADC_AWD1HTR_HTR_13       (0x2000UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00002000 */
#define ADC_AWD1HTR_HTR_14       (0x4000UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00004000 */
#define ADC_AWD1HTR_HTR_15       (0x8000UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00008000 */
#define ADC_AWD1HTR_HTR_16       (0x10000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00010000 */
#define ADC_AWD1HTR_HTR_17       (0x20000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00020000 */
#define ADC_AWD1HTR_HTR_18       (0x40000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00040000 */
#define ADC_AWD1HTR_HTR_19       (0x80000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00080000 */
#define ADC_AWD1HTR_HTR_20       (0x100000UL << ADC_AWD1HTR_HTR_Pos)   /*!< 0x00100000 */
#define ADC_AWD1HTR_HTR_21       (0x200000UL << ADC_AWD1HTR_HTR_Pos)   /*!< 0x00200000 */
#define ADC_AWD1HTR_HTR_22       (0x400000UL << ADC_AWD1HTR_HTR_Pos)   /*!< 0x00400000 */
#define ADC_AWD1HTR_AWDFILT_Pos  (29U)
#define ADC_AWD1HTR_AWDFILT_Msk  (0x7UL << ADC_AWD1HTR_AWDFILT_Pos)    /*!< 0xE0000000 */
#define ADC_AWD1HTR_AWDFILT      ADC_AWD1HTR_AWDFILT_Msk               /*!< Analog watchdog filtering parameter */
#define ADC_AWD1HTR_AWDFILT_0    (0x1UL << ADC_AWD1HTR_AWDFILT_Pos)    /*!< 0x20000000 */
#define ADC_AWD1HTR_AWDFILT_1    (0x2UL << ADC_AWD1HTR_AWDFILT_Pos)    /*!< 0x40000000 */
#define ADC_AWD1HTR_AWDFILT_2    (0x4UL << ADC_AWD1HTR_AWDFILT_Pos)    /*!< 0x80000000 */

/* ***********************************  Bit definition for ADC_AWD2LTR register  ************************************ */
#define ADC_AWD2LTR_LTR_Pos      (0U)
#define ADC_AWD2LTR_LTR_Msk      (0x7FFFFFUL << ADC_AWD2LTR_LTR_Pos)   /*!< 0x007FFFFF */
#define ADC_AWD2LTR_LTR          ADC_AWD2LTR_LTR_Msk                   /*!< Analog watchdog 2 lower threshold */
#define ADC_AWD2LTR_LTR_0        (0x1UL << ADC_AWD2LTR_LTR_Pos)        /*!< 0x00000001 */
#define ADC_AWD2LTR_LTR_1        (0x2UL << ADC_AWD2LTR_LTR_Pos)        /*!< 0x00000002 */
#define ADC_AWD2LTR_LTR_2        (0x4UL << ADC_AWD2LTR_LTR_Pos)        /*!< 0x00000004 */
#define ADC_AWD2LTR_LTR_3        (0x8UL << ADC_AWD2LTR_LTR_Pos)        /*!< 0x00000008 */
#define ADC_AWD2LTR_LTR_4        (0x10UL << ADC_AWD2LTR_LTR_Pos)       /*!< 0x00000010 */
#define ADC_AWD2LTR_LTR_5        (0x20UL << ADC_AWD2LTR_LTR_Pos)       /*!< 0x00000020 */
#define ADC_AWD2LTR_LTR_6        (0x40UL << ADC_AWD2LTR_LTR_Pos)       /*!< 0x00000040 */
#define ADC_AWD2LTR_LTR_7        (0x80UL << ADC_AWD2LTR_LTR_Pos)       /*!< 0x00000080 */
#define ADC_AWD2LTR_LTR_8        (0x100UL << ADC_AWD2LTR_LTR_Pos)      /*!< 0x00000100 */
#define ADC_AWD2LTR_LTR_9        (0x200UL << ADC_AWD2LTR_LTR_Pos)      /*!< 0x00000200 */
#define ADC_AWD2LTR_LTR_10       (0x400UL << ADC_AWD2LTR_LTR_Pos)      /*!< 0x00000400 */
#define ADC_AWD2LTR_LTR_11       (0x800UL << ADC_AWD2LTR_LTR_Pos)      /*!< 0x00000800 */
#define ADC_AWD2LTR_LTR_12       (0x1000UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00001000 */
#define ADC_AWD2LTR_LTR_13       (0x2000UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00002000 */
#define ADC_AWD2LTR_LTR_14       (0x4000UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00004000 */
#define ADC_AWD2LTR_LTR_15       (0x8000UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00008000 */
#define ADC_AWD2LTR_LTR_16       (0x10000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00010000 */
#define ADC_AWD2LTR_LTR_17       (0x20000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00020000 */
#define ADC_AWD2LTR_LTR_18       (0x40000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00040000 */
#define ADC_AWD2LTR_LTR_19       (0x80000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00080000 */
#define ADC_AWD2LTR_LTR_20       (0x100000UL << ADC_AWD2LTR_LTR_Pos)   /*!< 0x00100000 */
#define ADC_AWD2LTR_LTR_21       (0x200000UL << ADC_AWD2LTR_LTR_Pos)   /*!< 0x00200000 */
#define ADC_AWD2LTR_LTR_22       (0x400000UL << ADC_AWD2LTR_LTR_Pos)   /*!< 0x00400000 */

/* ***********************************  Bit definition for ADC_AWD2HTR register  ************************************ */
#define ADC_AWD2HTR_HTR_Pos      (0U)
#define ADC_AWD2HTR_HTR_Msk      (0x7FFFFFUL << ADC_AWD2HTR_HTR_Pos)   /*!< 0x007FFFFF */
#define ADC_AWD2HTR_HTR          ADC_AWD2HTR_HTR_Msk                   /*!< Analog watchdog 2 higher threshold */
#define ADC_AWD2HTR_HTR_0        (0x1UL << ADC_AWD2HTR_HTR_Pos)        /*!< 0x00000001 */
#define ADC_AWD2HTR_HTR_1        (0x2UL << ADC_AWD2HTR_HTR_Pos)        /*!< 0x00000002 */
#define ADC_AWD2HTR_HTR_2        (0x4UL << ADC_AWD2HTR_HTR_Pos)        /*!< 0x00000004 */
#define ADC_AWD2HTR_HTR_3        (0x8UL << ADC_AWD2HTR_HTR_Pos)        /*!< 0x00000008 */
#define ADC_AWD2HTR_HTR_4        (0x10UL << ADC_AWD2HTR_HTR_Pos)       /*!< 0x00000010 */
#define ADC_AWD2HTR_HTR_5        (0x20UL << ADC_AWD2HTR_HTR_Pos)       /*!< 0x00000020 */
#define ADC_AWD2HTR_HTR_6        (0x40UL << ADC_AWD2HTR_HTR_Pos)       /*!< 0x00000040 */
#define ADC_AWD2HTR_HTR_7        (0x80UL << ADC_AWD2HTR_HTR_Pos)       /*!< 0x00000080 */
#define ADC_AWD2HTR_HTR_8        (0x100UL << ADC_AWD2HTR_HTR_Pos)      /*!< 0x00000100 */
#define ADC_AWD2HTR_HTR_9        (0x200UL << ADC_AWD2HTR_HTR_Pos)      /*!< 0x00000200 */
#define ADC_AWD2HTR_HTR_10       (0x400UL << ADC_AWD2HTR_HTR_Pos)      /*!< 0x00000400 */
#define ADC_AWD2HTR_HTR_11       (0x800UL << ADC_AWD2HTR_HTR_Pos)      /*!< 0x00000800 */
#define ADC_AWD2HTR_HTR_12       (0x1000UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00001000 */
#define ADC_AWD2HTR_HTR_13       (0x2000UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00002000 */
#define ADC_AWD2HTR_HTR_14       (0x4000UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00004000 */
#define ADC_AWD2HTR_HTR_15       (0x8000UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00008000 */
#define ADC_AWD2HTR_HTR_16       (0x10000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00010000 */
#define ADC_AWD2HTR_HTR_17       (0x20000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00020000 */
#define ADC_AWD2HTR_HTR_18       (0x40000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00040000 */
#define ADC_AWD2HTR_HTR_19       (0x80000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00080000 */
#define ADC_AWD2HTR_HTR_20       (0x100000UL << ADC_AWD2HTR_HTR_Pos)   /*!< 0x00100000 */
#define ADC_AWD2HTR_HTR_21       (0x200000UL << ADC_AWD2HTR_HTR_Pos)   /*!< 0x00200000 */
#define ADC_AWD2HTR_HTR_22       (0x400000UL << ADC_AWD2HTR_HTR_Pos)   /*!< 0x00400000 */

/* ***********************************  Bit definition for ADC_AWD3LTR register  ************************************ */
#define ADC_AWD3LTR_LTR_Pos      (0U)
#define ADC_AWD3LTR_LTR_Msk      (0x7FFFFFUL << ADC_AWD3LTR_LTR_Pos)   /*!< 0x007FFFFF */
#define ADC_AWD3LTR_LTR          ADC_AWD3LTR_LTR_Msk                   /*!< Analog watchdog 3 lower threshold */
#define ADC_AWD3LTR_LTR_0        (0x1UL << ADC_AWD3LTR_LTR_Pos)        /*!< 0x00000001 */
#define ADC_AWD3LTR_LTR_1        (0x2UL << ADC_AWD3LTR_LTR_Pos)        /*!< 0x00000002 */
#define ADC_AWD3LTR_LTR_2        (0x4UL << ADC_AWD3LTR_LTR_Pos)        /*!< 0x00000004 */
#define ADC_AWD3LTR_LTR_3        (0x8UL << ADC_AWD3LTR_LTR_Pos)        /*!< 0x00000008 */
#define ADC_AWD3LTR_LTR_4        (0x10UL << ADC_AWD3LTR_LTR_Pos)       /*!< 0x00000010 */
#define ADC_AWD3LTR_LTR_5        (0x20UL << ADC_AWD3LTR_LTR_Pos)       /*!< 0x00000020 */
#define ADC_AWD3LTR_LTR_6        (0x40UL << ADC_AWD3LTR_LTR_Pos)       /*!< 0x00000040 */
#define ADC_AWD3LTR_LTR_7        (0x80UL << ADC_AWD3LTR_LTR_Pos)       /*!< 0x00000080 */
#define ADC_AWD3LTR_LTR_8        (0x100UL << ADC_AWD3LTR_LTR_Pos)      /*!< 0x00000100 */
#define ADC_AWD3LTR_LTR_9        (0x200UL << ADC_AWD3LTR_LTR_Pos)      /*!< 0x00000200 */
#define ADC_AWD3LTR_LTR_10       (0x400UL << ADC_AWD3LTR_LTR_Pos)      /*!< 0x00000400 */
#define ADC_AWD3LTR_LTR_11       (0x800UL << ADC_AWD3LTR_LTR_Pos)      /*!< 0x00000800 */
#define ADC_AWD3LTR_LTR_12       (0x1000UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00001000 */
#define ADC_AWD3LTR_LTR_13       (0x2000UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00002000 */
#define ADC_AWD3LTR_LTR_14       (0x4000UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00004000 */
#define ADC_AWD3LTR_LTR_15       (0x8000UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00008000 */
#define ADC_AWD3LTR_LTR_16       (0x10000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00010000 */
#define ADC_AWD3LTR_LTR_17       (0x20000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00020000 */
#define ADC_AWD3LTR_LTR_18       (0x40000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00040000 */
#define ADC_AWD3LTR_LTR_19       (0x80000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00080000 */
#define ADC_AWD3LTR_LTR_20       (0x100000UL << ADC_AWD3LTR_LTR_Pos)   /*!< 0x00100000 */
#define ADC_AWD3LTR_LTR_21       (0x200000UL << ADC_AWD3LTR_LTR_Pos)   /*!< 0x00200000 */
#define ADC_AWD3LTR_LTR_22       (0x400000UL << ADC_AWD3LTR_LTR_Pos)   /*!< 0x00400000 */

/* ***********************************  Bit definition for ADC_AWD3HTR register  ************************************ */
#define ADC_AWD3HTR_HTR_Pos      (0U)
#define ADC_AWD3HTR_HTR_Msk      (0x7FFFFFUL << ADC_AWD3HTR_HTR_Pos)   /*!< 0x007FFFFF */
#define ADC_AWD3HTR_HTR          ADC_AWD3HTR_HTR_Msk                   /*!< Analog watchdog 3 higher threshold */
#define ADC_AWD3HTR_HTR_0        (0x1UL << ADC_AWD3HTR_HTR_Pos)        /*!< 0x00000001 */
#define ADC_AWD3HTR_HTR_1        (0x2UL << ADC_AWD3HTR_HTR_Pos)        /*!< 0x00000002 */
#define ADC_AWD3HTR_HTR_2        (0x4UL << ADC_AWD3HTR_HTR_Pos)        /*!< 0x00000004 */
#define ADC_AWD3HTR_HTR_3        (0x8UL << ADC_AWD3HTR_HTR_Pos)        /*!< 0x00000008 */
#define ADC_AWD3HTR_HTR_4        (0x10UL << ADC_AWD3HTR_HTR_Pos)       /*!< 0x00000010 */
#define ADC_AWD3HTR_HTR_5        (0x20UL << ADC_AWD3HTR_HTR_Pos)       /*!< 0x00000020 */
#define ADC_AWD3HTR_HTR_6        (0x40UL << ADC_AWD3HTR_HTR_Pos)       /*!< 0x00000040 */
#define ADC_AWD3HTR_HTR_7        (0x80UL << ADC_AWD3HTR_HTR_Pos)       /*!< 0x00000080 */
#define ADC_AWD3HTR_HTR_8        (0x100UL << ADC_AWD3HTR_HTR_Pos)      /*!< 0x00000100 */
#define ADC_AWD3HTR_HTR_9        (0x200UL << ADC_AWD3HTR_HTR_Pos)      /*!< 0x00000200 */
#define ADC_AWD3HTR_HTR_10       (0x400UL << ADC_AWD3HTR_HTR_Pos)      /*!< 0x00000400 */
#define ADC_AWD3HTR_HTR_11       (0x800UL << ADC_AWD3HTR_HTR_Pos)      /*!< 0x00000800 */
#define ADC_AWD3HTR_HTR_12       (0x1000UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00001000 */
#define ADC_AWD3HTR_HTR_13       (0x2000UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00002000 */
#define ADC_AWD3HTR_HTR_14       (0x4000UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00004000 */
#define ADC_AWD3HTR_HTR_15       (0x8000UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00008000 */
#define ADC_AWD3HTR_HTR_16       (0x10000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00010000 */
#define ADC_AWD3HTR_HTR_17       (0x20000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00020000 */
#define ADC_AWD3HTR_HTR_18       (0x40000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00040000 */
#define ADC_AWD3HTR_HTR_19       (0x80000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00080000 */
#define ADC_AWD3HTR_HTR_20       (0x100000UL << ADC_AWD3HTR_HTR_Pos)   /*!< 0x00100000 */
#define ADC_AWD3HTR_HTR_21       (0x200000UL << ADC_AWD3HTR_HTR_Pos)   /*!< 0x00200000 */
#define ADC_AWD3HTR_HTR_22       (0x400000UL << ADC_AWD3HTR_HTR_Pos)   /*!< 0x00400000 */

/* ***********************************  Bit definition for ADC_CALFACT register  ************************************ */
#define ADC_CALFACT_CALFACT_Pos  (0U)
#define ADC_CALFACT_CALFACT_Msk  (0x7FUL << ADC_CALFACT_CALFACT_Pos)   /*!< 0x0000007F */
#define ADC_CALFACT_CALFACT      ADC_CALFACT_CALFACT_Msk               /*!< Calibration factors */
#define ADC_CALFACT_CALFACT_0    (0x1UL << ADC_CALFACT_CALFACT_Pos)    /*!< 0x00000001 */
#define ADC_CALFACT_CALFACT_1    (0x2UL << ADC_CALFACT_CALFACT_Pos)    /*!< 0x00000002 */
#define ADC_CALFACT_CALFACT_2    (0x4UL << ADC_CALFACT_CALFACT_Pos)    /*!< 0x00000004 */
#define ADC_CALFACT_CALFACT_3    (0x8UL << ADC_CALFACT_CALFACT_Pos)    /*!< 0x00000008 */
#define ADC_CALFACT_CALFACT_4    (0x10UL << ADC_CALFACT_CALFACT_Pos)   /*!< 0x00000010 */
#define ADC_CALFACT_CALFACT_5    (0x20UL << ADC_CALFACT_CALFACT_Pos)   /*!< 0x00000020 */
#define ADC_CALFACT_CALFACT_6    (0x40UL << ADC_CALFACT_CALFACT_Pos)   /*!< 0x00000040 */

/* *********************************************  ADC Common registers  ********************************************* */
/* *************************************  Bit definition for ADCC_CSR register  ************************************* */
#define ADCC_CSR_ADRDY_MST_Pos  (0U)
#define ADCC_CSR_ADRDY_MST_Msk  (0x1UL << ADCC_CSR_ADRDY_MST_Pos)    /*!< 0x00000001 */
#define ADCC_CSR_ADRDY_MST      ADCC_CSR_ADRDY_MST_Msk               /*!< Master ADC ready */
#define ADCC_CSR_EOSMP_MST_Pos  (1U)
#define ADCC_CSR_EOSMP_MST_Msk  (0x1UL << ADCC_CSR_EOSMP_MST_Pos)    /*!< 0x00000002 */
#define ADCC_CSR_EOSMP_MST      ADCC_CSR_EOSMP_MST_Msk               /*!< End of Sampling phase flag of the master ADC
                                                                          */
#define ADCC_CSR_EOC_MST_Pos    (2U)
#define ADCC_CSR_EOC_MST_Msk    (0x1UL << ADCC_CSR_EOC_MST_Pos)      /*!< 0x00000004 */
#define ADCC_CSR_EOC_MST        ADCC_CSR_EOC_MST_Msk                 /*!< End of regular conversion of the master ADC */
#define ADCC_CSR_EOS_MST_Pos    (3U)
#define ADCC_CSR_EOS_MST_Msk    (0x1UL << ADCC_CSR_EOS_MST_Pos)      /*!< 0x00000008 */
#define ADCC_CSR_EOS_MST        ADCC_CSR_EOS_MST_Msk                 /*!< End of regular sequence flag of the master ADC
                                                                          */
#define ADCC_CSR_OVR_MST_Pos    (4U)
#define ADCC_CSR_OVR_MST_Msk    (0x1UL << ADCC_CSR_OVR_MST_Pos)      /*!< 0x00000010 */
#define ADCC_CSR_OVR_MST        ADCC_CSR_OVR_MST_Msk                 /*!< Overrun flag of the master ADC */
#define ADCC_CSR_JEOC_MST_Pos   (5U)
#define ADCC_CSR_JEOC_MST_Msk   (0x1UL << ADCC_CSR_JEOC_MST_Pos)     /*!< 0x00000020 */
#define ADCC_CSR_JEOC_MST       ADCC_CSR_JEOC_MST_Msk                /*!< End of injected conversion flag of the master
                                                                          ADC */
#define ADCC_CSR_JEOS_MST_Pos   (6U)
#define ADCC_CSR_JEOS_MST_Msk   (0x1UL << ADCC_CSR_JEOS_MST_Pos)     /*!< 0x00000040 */
#define ADCC_CSR_JEOS_MST       ADCC_CSR_JEOS_MST_Msk                /*!< End of injected sequence flag of the master
                                                                          ADC */
#define ADCC_CSR_AWD1_MST_Pos   (7U)
#define ADCC_CSR_AWD1_MST_Msk   (0x1UL << ADCC_CSR_AWD1_MST_Pos)     /*!< 0x00000080 */
#define ADCC_CSR_AWD1_MST       ADCC_CSR_AWD1_MST_Msk                /*!< Analog watchdog 1 flag of the master ADC */
#define ADCC_CSR_AWD2_MST_Pos   (8U)
#define ADCC_CSR_AWD2_MST_Msk   (0x1UL << ADCC_CSR_AWD2_MST_Pos)     /*!< 0x00000100 */
#define ADCC_CSR_AWD2_MST       ADCC_CSR_AWD2_MST_Msk                /*!< Analog watchdog 2 flag of the master ADC */
#define ADCC_CSR_AWD3_MST_Pos   (9U)
#define ADCC_CSR_AWD3_MST_Msk   (0x1UL << ADCC_CSR_AWD3_MST_Pos)     /*!< 0x00000200 */
#define ADCC_CSR_AWD3_MST       ADCC_CSR_AWD3_MST_Msk                /*!< Analog watchdog 3 flag of the master ADC */
#define ADCC_CSR_LDORDY_MST_Pos (12U)
#define ADCC_CSR_LDORDY_MST_Msk (0x1UL << ADCC_CSR_LDORDY_MST_Pos)   /*!< 0x00001000 */
#define ADCC_CSR_LDORDY_MST     ADCC_CSR_LDORDY_MST_Msk              /*!< ADC internal voltage regulator flag of the
                                                                          master ADC */
#define ADCC_CSR_ADRDY_SLV_Pos  (16U)
#define ADCC_CSR_ADRDY_SLV_Msk  (0x1UL << ADCC_CSR_ADRDY_SLV_Pos)    /*!< 0x00010000 */
#define ADCC_CSR_ADRDY_SLV      ADCC_CSR_ADRDY_SLV_Msk               /*!< Slave ADC ready */
#define ADCC_CSR_EOSMP_SLV_Pos  (17U)
#define ADCC_CSR_EOSMP_SLV_Msk  (0x1UL << ADCC_CSR_EOSMP_SLV_Pos)    /*!< 0x00020000 */
#define ADCC_CSR_EOSMP_SLV      ADCC_CSR_EOSMP_SLV_Msk               /*!< End of sampling phase flag of the slave ADC */
#define ADCC_CSR_EOC_SLV_Pos    (18U)
#define ADCC_CSR_EOC_SLV_Msk    (0x1UL << ADCC_CSR_EOC_SLV_Pos)      /*!< 0x00040000 */
#define ADCC_CSR_EOC_SLV        ADCC_CSR_EOC_SLV_Msk                 /*!< End of regular conversion of the slave ADC */
#define ADCC_CSR_EOS_SLV_Pos    (19U)
#define ADCC_CSR_EOS_SLV_Msk    (0x1UL << ADCC_CSR_EOS_SLV_Pos)      /*!< 0x00080000 */
#define ADCC_CSR_EOS_SLV        ADCC_CSR_EOS_SLV_Msk                 /*!< End of regular sequence flag of the slave ADC
                                                                          */
#define ADCC_CSR_OVR_SLV_Pos    (20U)
#define ADCC_CSR_OVR_SLV_Msk    (0x1UL << ADCC_CSR_OVR_SLV_Pos)      /*!< 0x00100000 */
#define ADCC_CSR_OVR_SLV        ADCC_CSR_OVR_SLV_Msk                 /*!< Overrun flag of the slave ADC */
#define ADCC_CSR_JEOC_SLV_Pos   (21U)
#define ADCC_CSR_JEOC_SLV_Msk   (0x1UL << ADCC_CSR_JEOC_SLV_Pos)     /*!< 0x00200000 */
#define ADCC_CSR_JEOC_SLV       ADCC_CSR_JEOC_SLV_Msk                /*!< End of injected conversion flag of the slave
                                                                          ADC */
#define ADCC_CSR_JEOS_SLV_Pos   (22U)
#define ADCC_CSR_JEOS_SLV_Msk   (0x1UL << ADCC_CSR_JEOS_SLV_Pos)     /*!< 0x00400000 */
#define ADCC_CSR_JEOS_SLV       ADCC_CSR_JEOS_SLV_Msk                /*!< End of injected sequence flag of the slave ADC
                                                                          */
#define ADCC_CSR_AWD1_SLV_Pos   (23U)
#define ADCC_CSR_AWD1_SLV_Msk   (0x1UL << ADCC_CSR_AWD1_SLV_Pos)     /*!< 0x00800000 */
#define ADCC_CSR_AWD1_SLV       ADCC_CSR_AWD1_SLV_Msk                /*!< Analog watchdog 1 flag of the slave ADC */
#define ADCC_CSR_AWD2_SLV_Pos   (24U)
#define ADCC_CSR_AWD2_SLV_Msk   (0x1UL << ADCC_CSR_AWD2_SLV_Pos)     /*!< 0x01000000 */
#define ADCC_CSR_AWD2_SLV       ADCC_CSR_AWD2_SLV_Msk                /*!< Analog watchdog 2 flag of the slave ADC */
#define ADCC_CSR_AWD3_SLV_Pos   (25U)
#define ADCC_CSR_AWD3_SLV_Msk   (0x1UL << ADCC_CSR_AWD3_SLV_Pos)     /*!< 0x02000000 */
#define ADCC_CSR_AWD3_SLV       ADCC_CSR_AWD3_SLV_Msk                /*!< Analog watchdog 3 flag of the slave ADC */
#define ADCC_CSR_LDORDY_SLV_Pos (28U)
#define ADCC_CSR_LDORDY_SLV_Msk (0x1UL << ADCC_CSR_LDORDY_SLV_Pos)   /*!< 0x10000000 */
#define ADCC_CSR_LDORDY_SLV     ADCC_CSR_LDORDY_SLV_Msk              /*!< ADC internal voltage regulator flag of the
                                                                          slave ADC */

/* *************************************  Bit definition for ADCC_CCR register  ************************************* */
#define ADCC_CCR_DUAL_Pos       (0U)
#define ADCC_CCR_DUAL_Msk       (0x1FUL << ADCC_CCR_DUAL_Pos)        /*!< 0x0000001F */
#define ADCC_CCR_DUAL           ADCC_CCR_DUAL_Msk                    /*!< Dual ADC mode selection */
#define ADCC_CCR_DUAL_0         (0x1UL << ADCC_CCR_DUAL_Pos)         /*!< 0x00000001 */
#define ADCC_CCR_DUAL_1         (0x2UL << ADCC_CCR_DUAL_Pos)         /*!< 0x00000002 */
#define ADCC_CCR_DUAL_2         (0x4UL << ADCC_CCR_DUAL_Pos)         /*!< 0x00000004 */
#define ADCC_CCR_DUAL_3         (0x8UL << ADCC_CCR_DUAL_Pos)         /*!< 0x00000008 */
#define ADCC_CCR_DUAL_4         (0x10UL << ADCC_CCR_DUAL_Pos)        /*!< 0x00000010 */
#define ADCC_CCR_DELAY_Pos      (8U)
#define ADCC_CCR_DELAY_Msk      (0xFUL << ADCC_CCR_DELAY_Pos)        /*!< 0x00000F00 */
#define ADCC_CCR_DELAY          ADCC_CCR_DELAY_Msk                   /*!< Delay between two sampling phases */
#define ADCC_CCR_DELAY_0        (0x1UL << ADCC_CCR_DELAY_Pos)        /*!< 0x00000100 */
#define ADCC_CCR_DELAY_1        (0x2UL << ADCC_CCR_DELAY_Pos)        /*!< 0x00000200 */
#define ADCC_CCR_DELAY_2        (0x4UL << ADCC_CCR_DELAY_Pos)        /*!< 0x00000400 */
#define ADCC_CCR_DELAY_3        (0x8UL << ADCC_CCR_DELAY_Pos)        /*!< 0x00000800 */
#define ADCC_CCR_DAMDF_Pos      (14U)
#define ADCC_CCR_DAMDF_Msk      (0x3UL << ADCC_CCR_DAMDF_Pos)        /*!< 0x0000C000 */
#define ADCC_CCR_DAMDF          ADCC_CCR_DAMDF_Msk                   /*!< Dual ADC mode data format */
#define ADCC_CCR_DAMDF_0        (0x1UL << ADCC_CCR_DAMDF_Pos)        /*!< 0x00004000 */
#define ADCC_CCR_DAMDF_1        (0x2UL << ADCC_CCR_DAMDF_Pos)        /*!< 0x00008000 */
#define ADCC_CCR_VREFEN_Pos     (22U)
#define ADCC_CCR_VREFEN_Msk     (0x1UL << ADCC_CCR_VREFEN_Pos)       /*!< 0x00400000 */
#define ADCC_CCR_VREFEN         ADCC_CCR_VREFEN_Msk                  /*!< V<sub>REFINT</sub> enable */
#define ADCC_CCR_TSEN_Pos       (23U)
#define ADCC_CCR_TSEN_Msk       (0x1UL << ADCC_CCR_TSEN_Pos)         /*!< 0x00800000 */
#define ADCC_CCR_TSEN           ADCC_CCR_TSEN_Msk                    /*!< Temperature sensor voltage enable */

/* *************************************  Bit definition for ADCC_CDR register  ************************************* */
#define ADCC_CDR_RDATA_MST_Pos  (0U)
#define ADCC_CDR_RDATA_MST_Msk  (0xFFFFUL << ADCC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
#define ADCC_CDR_RDATA_MST      ADCC_CDR_RDATA_MST_Msk               /*!< Regular data of the master ADC. */
#define ADCC_CDR_RDATA_SLV_Pos  (16U)
#define ADCC_CDR_RDATA_SLV_Msk  (0xFFFFUL << ADCC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
#define ADCC_CDR_RDATA_SLV      ADCC_CDR_RDATA_SLV_Msk               /*!< Regular data of the slave ADC */

/* ************************************  Bit definition for ADCC_CDR2 register  ************************************* */
#define ADCC_CDR2_RDATA_ALT_Pos (0U)
#define ADCC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADCC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
#define ADCC_CDR2_RDATA_ALT     ADCC_CDR2_RDATA_ALT_Msk         /*!< Regular data of the master/slave alternated ADCs */

/* ****************************************************************************************************************** */
/*                                                                                                                    */
/*                                           AES hardware accelerator (AES)                                           */
/*                                                                                                                    */
/* ****************************************************************************************************************** */
/* **************************************  Bit definition for AES_CR register  ************************************** */
#define AES_CR_EN_Pos             (0U)
#define AES_CR_EN_Msk             (0x1UL << AES_CR_EN_Pos)                     /*!< 0x00000001 */
#define AES_CR_EN                 AES_CR_EN_Msk                                /*!< Enable */
#define AES_CR_DATATYPE_Pos       (1U)
#define AES_CR_DATATYPE_Msk       (0x3UL << AES_CR_DATATYPE_Pos)               /*!< 0x00000006 */
#define AES_CR_DATATYPE           AES_CR_DATATYPE_Msk                          /*!< Data type */
#define AES_CR_DATATYPE_0         (0x1UL << AES_CR_DATATYPE_Pos)               /*!< 0x00000002 */
#define AES_CR_DATATYPE_1         (0x2UL << AES_CR_DATATYPE_Pos)               /*!< 0x00000004 */
#define AES_CR_MODE_Pos           (3U)
#define AES_CR_MODE_Msk           (0x3UL << AES_CR_MODE_Pos)                   /*!< 0x00000018 */
#define AES_CR_MODE               AES_CR_MODE_Msk                              /*!< Operating mode */
#define AES_CR_MODE_0             (0x1UL << AES_CR_MODE_Pos)                   /*!< 0x00000008 */
#define AES_CR_MODE_1             (0x2UL << AES_CR_MODE_Pos)                   /*!< 0x00000010 */
#define AES_CR_CHMOD_Pos          (5U)
#define AES_CR_CHMOD_Msk          (0x803UL << AES_CR_CHMOD_Pos)                /*!< 0x00010060 */
#define AES_CR_CHMOD              AES_CR_CHMOD_Msk                             /*!< AES Chaining Mode */
#define AES_CR_CHMOD_0            (0x001UL << AES_CR_CHMOD_Pos)                /*!< 0x00000020 */
#define AES_CR_CHMOD_1            (0x002UL << AES_CR_CHMOD_Pos)                /*!< 0x00000040 */
#define AES_CR_CHMOD_2            (0x800UL << AES_CR_CHMOD_Pos)                /*!< 0x00010000 */
#define AES_CR_DMAINEN_Pos        (11U)
#define AES_CR_DMAINEN_Msk        (0x1UL << AES_CR_DMAINEN_Pos)                /*!< 0x00000800 */
#define AES_CR_DMAINEN            AES_CR_DMAINEN_Msk                           /*!< DMA input enable */
#define AES_CR_DMAOUTEN_Pos       (12U)
#define AES_CR_DMAOUTEN_Msk       (0x1UL << AES_CR_DMAOUTEN_Pos)               /*!< 0x00001000 */
#define AES_CR_DMAOUTEN           AES_CR_DMAOUTEN_Msk                          /*!< DMA output enable */
#define AES_CR_CPHASE_Pos         (13U)
#define AES_CR_CPHASE_Msk         (0x3UL << AES_CR_CPHASE_Pos)                 /*!< 0x00006000 */
#define AES_CR_CPHASE             AES_CR_CPHASE_Msk                            /*!< Chaining phase selection */
#define AES_CR_CPHASE_0           (0x1UL << AES_CR_CPHASE_Pos)                 /*!< 0x00002000 */
#define AES_CR_CPHASE_1           (0x2UL << AES_CR_CPHASE_Pos)                 /*!< 0x00004000 */
#define AES_CR_KEYSIZE_Pos        (18U)
#define AES_CR_KEYSIZE_Msk        (0x1UL << AES_CR_KEYSIZE_Pos)                /*!< 0x00040000 */
#define AES_CR_KEYSIZE            AES_CR_KEYSIZE_Msk                           /*!< Key size selection */
#define AES_CR_NPBLB_Pos          (20U)
#define AES_CR_NPBLB_Msk          (0xFUL << AES_CR_NPBLB_Pos)                  /*!< 0x00F00000 */
#define AES_CR_NPBLB              AES_CR_NPBLB_Msk                             /*!< Number of padding bytes in last
                                                                                    block */
#define AES_CR_NPBLB_0            (0x1UL << AES_CR_NPBLB_Pos)                  /*!< 0x00100000 */
#define AES_CR_NPBLB_1            (0x2UL << AES_CR_NPBLB_Pos)                  /*!< 0x00200000 */
#define AES_CR_NPBLB_2            (0x4UL << AES_CR_NPBLB_Pos)                  /*!< 0x00400000 */
#define AES_CR_NPBLB_3            (0x8UL << AES_CR_NPBLB_Pos)                  /*!< 0x00800000 */
#define AES_CR_KMOD_Pos           (24U)
#define AES_CR_KMOD_Msk           (0x3UL << AES_CR_KMOD_Pos)                   /*!< 0x03000000 */
#define AES_CR_KMOD               AES_CR_KMOD_Msk                              /*!< Key mode selection */
#define AES_CR_KMOD_0             (0x1UL << AES_CR_KMOD_Pos)                   /*!< 0x01000000 */
#define AES_CR_KMOD_1             (0x2UL << AES_CR_KMOD_Pos)                   /*!< 0x02000000 */
#define AES_CR_IPRST_Pos          (31U)
#define AES_CR_IPRST_Msk          (0x1UL << AES_CR_IPRST_Pos)                  /*!< 0x80000000 */
#define AES_CR_IPRST              AES_CR_IPRST_Msk                             /*!< AES peripheral software reset */

/* **************************************  Bit definition for AES_SR register  ************************************** */
#define AES_SR_RDERRF_Pos         (1U)
#define AES_SR_RDERRF_Msk         (0x1UL << AES_SR_RDERRF_Pos)                 /*!< 0x00000002 */
#define AES_SR_RDERRF             AES_SR_RDERRF_Msk                            /*!< Read error flag */
#define AES_SR_WRERRF_Pos         (2U)
#define AES_SR_WRERRF_Msk         (0x1UL << AES_SR_WRERRF_Pos)                 /*!< 0x00000004 */
#define AES_SR_WRERRF             AES_SR_WRERRF_Msk                            /*!< Write error flag */
#define AES_SR_BUSY_Pos           (3U)
#define AES_SR_BUSY_Msk           (0x1UL << AES_SR_BUSY_Pos)                   /*!< 0x00000008 */
#define AES_SR_BUSY               AES_SR_BUSY_Msk                              /*!< Busy Flag */
#define AES_SR_KEYVALID_Pos       (7U)
#define AES_SR_KEYVALID_Msk       (0x1UL << AES_SR_KEYVALID_Pos)               /*!< 0x00000080 */
#define AES_SR_KEYVALID           AES_SR_KEYVALID_Msk                          /*!< Key valid flag */

/* *************************************  Bit definition for AES_DINR register  ************************************* */
#define AES_DINR_DIN_Pos          (0U)
#define AES_DINR_DIN_Msk          (0xFFFFFFFFUL << AES_DINR_DIN_Pos)           /*!< 0xFFFFFFFF */
#define AES_DINR_DIN              AES_DINR_DIN_Msk                             /*!< Data input */

/* ************************************  Bit definition for AES_DOUTR register  ************************************* */
#define AES_DOUTR_DOUT_Pos        (0U)
#define AES_DOUTR_DOUT_Msk        (0xFFFFFFFFUL << AES_DOUTR_DOUT_Pos)         /*!< 0xFFFFFFFF */
#define AES_DOUTR_DOUT            AES_DOUTR_DOUT_Msk                           /*!< Data output */

/* ************************************  Bit definition for AES_KEYR0 register  ************************************* */
#define AES_KEYR0_KEY_Pos         (0U)
#define AES_KEYR0_KEY_Msk         (0xFFFFFFFFUL <<  AES_KEYR0_KEY_Pos)         /*!< 0xFFFFFFFF */
#define AES_KEYR0_KEY             AES_KEYR0_KEY_Msk                            /*!< Cryptographic key, bits [31:0] */

/* ************************************  Bit definition for AES_KEYR1 register  ************************************* */
#define AES_KEYR1_KEY_Pos         (0U)
#define AES_KEYR1_KEY_Msk         (0xFFFFFFFFUL << AES_KEYR1_KEY_Pos)          /*!< 0xFFFFFFFF */
#define AES_KEYR1_KEY             AES_KEYR1_KEY_Msk                            /*!< Cryptographic key, bits [63:32] */

/* ************************************  Bit definition for AES_KEYR2 register  ************************************* */
#define AES_KEYR2_KEY_Pos         (0U)
#define AES_KEYR2_KEY_Msk         (0xFFFFFFFFUL << AES_KEYR2_KEY_Pos)          /*!< 0xFFFFFFFF */
#define AES_KEYR2_KEY             AES_KEYR2_KEY_Msk                            /*!< Cryptographic key, bits [95:64] */

/* ************************************  Bit definition for AES_KEYR3 register  ************************************* */
#define AES_KEYR3_KEY_Pos         (0U)
#define AES_KEYR3_KEY_Msk         (0xFFFFFFFFUL << AES_KEYR3_KEY_Pos)          /*!< 0xFFFFFFFF */
#define AES_KEYR3_KEY             AES_KEYR3_KEY_Msk                            /*!< Cryptographic key, bits [127:96] */

/* ************************************  Bit definition for AES_KEYR4 register  ************************************* */
#define AES_KEYR4_KEY_Pos         (0U)
#define AES_KEYR4_KEY_Msk         (0xFFFFFFFFUL << AES_KEYR4_KEY_Pos)          /*!< 0xFFFFFFFF */
#define AES_KEYR4_KEY             AES_KEYR4_KEY_Msk                            /*!< Cryptographic key, bits [159:128] */

/* ************************************  Bit definition for AES_KEYR5 register  ************************************* */
#define AES_KEYR5_KEY_Pos         (0U)
#define AES_KEYR5_KEY_Msk         (0xFFFFFFFFUL << AES_KEYR5_KEY_Pos)          /*!< 0xFFFFFFFF */
#define AES_KEYR5_KEY             AES_KEYR5_KEY_Msk                            /*!< Cryptographic key, bits [191:160] */

/* ************************************  Bit definition for AES_KEYR6 register  ************************************* */
#define AES_KEYR6_KEY_Pos         (0U)
#define AES_KEYR6_KEY_Msk         (0xFFFFFFFFUL << AES_KEYR6_KEY_Pos)          /*!< 0xFFFFFFFF */
#define AES_KEYR6_KEY             AES_KEYR6_KEY_Msk                            /*!< Cryptographic key, bits [223:192] */

/* ************************************  Bit definition for AES_KEYR7 register  ************************************* */
#define AES_KEYR7_KEY_Pos         (0U)
#define AES_KEYR7_KEY_Msk         (0xFFFFFFFFUL << AES_KEYR7_KEY_Pos)          /*!< 0xFFFFFFFF */
#define AES_KEYR7_KEY             AES_KEYR7_KEY_Msk                            /*!< Cryptographic key, bits [255:224] */

/* *************************************  Bit definition for AES_IVR0 register  ************************************* */
#define AES_IVR0_IVI_Pos          (0U)
#define AES_IVR0_IVI_Msk          (0xFFFFFFFFUL << AES_IVR0_IVI_Pos)           /*!< 0xFFFFFFFF */
#define AES_IVR0_IVI              AES_IVR0_IVI_Msk                             /*!< Initialization vector input, bits
                                                                                    [31:0] */

/* *************************************  Bit definition for AES_IVR1 register  ************************************* */
#define AES_IVR1_IVI_Pos          (0U)
#define AES_IVR1_IVI_Msk          (0xFFFFFFFFUL << AES_IVR1_IVI_Pos)           /*!< 0xFFFFFFFF */
#define AES_IVR1_IVI              AES_IVR1_IVI_Msk                             /*!< Initialization vector input, bits
                                                                                    [63:32] */

/* *************************************  Bit definition for AES_IVR2 register  ************************************* */
#define AES_IVR2_IVI_Pos          (0U)
#define AES_IVR2_IVI_Msk          (0xFFFFFFFFUL << AES_IVR2_IVI_Pos)           /*!< 0xFFFFFFFF */
#define AES_IVR2_IVI              AES_IVR2_IVI_Msk                             /*!< Initialization vector input, bits
                                                                                    [95:64] */

/* *************************************  Bit definition for AES_IVR3 register  ************************************* */
#define AES_IVR3_IVI_Pos          (0U)
#define AES_IVR3_IVI_Msk          (0xFFFFFFFFUL << AES_IVR3_IVI_Pos)           /*!< 0xFFFFFFFF */
#define AES_IVR3_IVI              AES_IVR3_IVI_Msk                             /*!< Initialization vector input, bits
                                                                                    [127:96] */

/* ************************************  Bit definition for AES_SUSPR0 register  ************************************ */
#define AES_SUSPR0_SUSP_Pos       (0U)
#define AES_SUSPR0_SUSP_Msk       (0xFFFFFFFFUL << AES_SUSPR0_SUSP_Pos)        /*!< 0xFFFFFFFF */
#define AES_SUSPR0_SUSP           AES_SUSPR0_SUSP_Msk                          /*!< Suspend data */

/* ************************************  Bit definition for AES_SUSPR1 register  ************************************ */
#define AES_SUSPR1_SUSP_Pos       (0U)
#define AES_SUSPR1_SUSP_Msk       (0xFFFFFFFFUL << AES_SUSPR1_SUSP_Pos)        /*!< 0xFFFFFFFF */
#define AES_SUSPR1_SUSP           AES_SUSPR1_SUSP_Msk                          /*!< Suspend data */

/* ************************************  Bit definition for AES_SUSPR2 register  ************************************ */
#define AES_SUSPR2_SUSP_Pos       (0U)
#define AES_SUSPR2_SUSP_Msk       (0xFFFFFFFFUL << AES_SUSPR2_SUSP_Pos)        /*!< 0xFFFFFFFF */
#define AES_SUSPR2_SUSP           AES_SUSPR2_SUSP_Msk                          /*!< Suspend data */

/* ************************************  Bit definition for AES_SUSPR3 register  ************************************ */
#define AES_SUSPR3_SUSP_Pos       (0U)
#define AES_SUSPR3_SUSP_Msk       (0xFFFFFFFFUL << AES_SUSPR3_SUSP_Pos)        /*!< 0xFFFFFFFF */
#define AES_SUSPR3_SUSP           AES_SUSPR3_SUSP_Msk                          /*!< Suspend data */

/* ************************************  Bit definition for AES_SUSPR4 register  ************************************ */
#define AES_SUSPR4_SUSP_Pos       (0U)
#define AES_SUSPR4_SUSP_Msk       (0xFFFFFFFFUL << AES_SUSPR4_SUSP_Pos)        /*!< 0xFFFFFFFF */
#define AES_SUSPR4_SUSP           AES_SUSPR4_SUSP_Msk                          /*!< Suspend data */

/* ************************************  Bit definition for AES_SUSPR5 register  ************************************ */
#define AES_SUSPR5_SUSP_Pos       (0U)
#define AES_SUSPR5_SUSP_Msk       (0xFFFFFFFFUL << AES_SUSPR5_SUSP_Pos)        /*!< 0xFFFFFFFF */
#define AES_SUSPR5_SUSP           AES_SUSPR5_SUSP_Msk                          /*!< Suspend data */

/* ************************************  Bit definition for AES_SUSPR6 register  ************************************ */
#define AES_SUSPR6_SUSP_Pos       (0U)
#define AES_SUSPR6_SUSP_Msk       (0xFFFFFFFFUL << AES_SUSPR6_SUSP_Pos)        /*!< 0xFFFFFFFF */
#define AES_SUSPR6_SUSP           AES_SUSPR6_SUSP_Msk                          /*!< Suspend data */

/* ************************************  Bit definition for AES_SUSPR7 register  ************************************ */
#define AES_SUSPR7_SUSP_Pos       (0U)
#define AES_SUSPR7_SUSP_Msk       (0xFFFFFFFFUL << AES_SUSPR7_SUSP_Pos)        /*!< 0xFFFFFFFF */
#define AES_SUSPR7_SUSP           AES_SUSPR7_SUSP_Msk                          /*!< Suspend data */

/* *************************************  Bit definition for AES_IER register  ************************************** */
#define AES_IER_CCFIE_Pos         (0U)
#define AES_IER_CCFIE_Msk         (0x1UL << AES_IER_CCFIE_Pos)                 /*!< 0x00000001 */
#define AES_IER_CCFIE             AES_IER_CCFIE_Msk                            /*!< Computation complete flag interrupt
                                                                                    enable */
#define AES_IER_RWEIE_Pos         (1U)
#define AES_IER_RWEIE_Msk         (0x1UL << AES_IER_RWEIE_Pos)                 /*!< 0x00000002 */
#define AES_IER_RWEIE             AES_IER_RWEIE_Msk                            /*!< Read or write error interrupt
                                                                                    enable */
#define AES_IER_KEIE_Pos          (2U)
#define AES_IER_KEIE_Msk          (0x1UL << AES_IER_KEIE_Pos)                  /*!< 0x00000004 */
#define AES_IER_KEIE              AES_IER_KEIE_Msk                             /*!< Key error interrupt enable */

/* *************************************  Bit definition for AES_ISR register  ************************************** */
#define AES_ISR_CCF_Pos           (0U)
#define AES_ISR_CCF_Msk           (0x1UL << AES_ISR_CCF_Pos)                   /*!< 0x00000001 */
#define AES_ISR_CCF               AES_ISR_CCF_Msk                              /*!< Computation complete flag */
#define AES_ISR_RWEIF_Pos         (1U)
#define AES_ISR_RWEIF_Msk         (0x1UL << AES_ISR_RWEIF_Pos)                 /*!< 0x00000002 */
#define AES_ISR_RWEIF             AES_ISR_RWEIF_Msk                            /*!< Read or write error interrupt flag
                                                                                    */
#define AES_ISR_KEIF_Pos          (2U)
#define AES_ISR_KEIF_Msk          (0x1UL << AES_ISR_KEIF_Pos)                  /*!< 0x00000004 */
#define AES_ISR_KEIF              AES_ISR_KEIF_Msk                             /*!< Key error interrupt flag */

/* *************************************  Bit definition for AES_ICR register  ************************************** */
#define AES_ICR_CCF_Pos           (0U)
#define AES_ICR_CCF_Msk           (0x1UL << AES_ICR_CCF_Pos)                   /*!< 0x00000001 */
#define AES_ICR_CCF               AES_ICR_CCF_Msk                              /*!< Computation complete flag clear */
#define AES_ICR_RWEIF_Pos         (1U)
#define AES_ICR_RWEIF_Msk         (0x1UL << AES_ICR_RWEIF_Pos)                 /*!< 0x00000002 */
#define AES_ICR_RWEIF             AES_ICR_RWEIF_Msk                            /*!< Read or write error interrupt flag
                                                                                    clear */
#define AES_ICR_KEIF_Pos          (2U)
#define AES_ICR_KEIF_Msk          (0x1UL << AES_ICR_KEIF_Pos)                  /*!< 0x00000004 */
#define AES_ICR_KEIF              AES_ICR_KEIF_Msk                             /*!< Key error interrupt flag clear */

/******************************************************************************/
/*                                                                            */
/*                          CRC calculation unit                              */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for CRC_DR register  *********************/
#define CRC_DR_DR_Pos                       (0U)
#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)         /*!< 0xFFFFFFFF */
#define CRC_DR_DR                           CRC_DR_DR_Msk                           /*!< Data register bits */

/*******************  Bit definition for CRC_IDR register  ********************/
#define CRC_IDR_IDR_Pos                     (0U)
#define CRC_IDR_IDR_Msk                     (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)       /*!< 0xFFFFFFFF */
#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                         /*!< General-purpose 32-bits data register bits */

/********************  Bit definition for CRC_CR register  ********************/
#define CRC_CR_RESET_Pos           (0U)
#define CRC_CR_RESET_Msk           (0x1UL << CRC_CR_RESET_Pos)                 /*!< 0x00000001 */
#define CRC_CR_RESET               CRC_CR_RESET_Msk                            /*!< RESET the CRC computation unit bit */
#define CRC_CR_POLYSIZE_Pos        (3U)
#define CRC_CR_POLYSIZE_Msk        (0x3UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000018 */
#define CRC_CR_POLYSIZE            CRC_CR_POLYSIZE_Msk                         /*!< Polynomial size bits */
#define CRC_CR_POLYSIZE_0          (0x1UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000008 */
#define CRC_CR_POLYSIZE_1          (0x2UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000010 */
#define CRC_CR_REV_IN_Pos          (5U)
#define CRC_CR_REV_IN_Msk          (0x3UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000060 */
#define CRC_CR_REV_IN              CRC_CR_REV_IN_Msk                           /*!< REV_IN Reverse Input Data bits */
#define CRC_CR_REV_IN_0            (0x1UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000020 */
#define CRC_CR_REV_IN_1            (0x2UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000040 */
#define CRC_CR_REV_OUT_Pos         (7U)
#define CRC_CR_REV_OUT_Msk         (0x3UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000180 */
#define CRC_CR_REV_OUT             CRC_CR_REV_OUT_Msk                          /*!< REV_OUT Reverse Output Data bits */
#define CRC_CR_REV_OUT_0           (0x1UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000080 */
#define CRC_CR_REV_OUT_1           (0x2UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000100 */
#define CRC_CR_RTYPE_IN_Pos        (9U)
#define CRC_CR_RTYPE_IN_Msk        (0x1UL << CRC_CR_RTYPE_IN_Pos)              /*!< 0x00000200 */
#define CRC_CR_RTYPE_IN            CRC_CR_RTYPE_IN_Msk                         /*!< Reverse type input */
#define CRC_CR_RTYPE_OUT_Pos       (10U)
#define CRC_CR_RTYPE_OUT_Msk       (0x1UL << CRC_CR_RTYPE_OUT_Pos)             /*!< 0x00000400 */
#define CRC_CR_RTYPE_OUT           CRC_CR_RTYPE_OUT_Msk                        /*!< Reverse type output*/

/*******************  Bit definition for CRC_INIT register  *******************/
#define CRC_INIT_INIT_Pos                   (0U)
#define CRC_INIT_INIT_Msk                   (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)     /*!< 0xFFFFFFFF */
#define CRC_INIT_INIT                       CRC_INIT_INIT_Msk                       /*!< Initial CRC value bits */

/*******************  Bit definition for CRC_POL register  ********************/
#define CRC_POL_POL_Pos                     (0U)
#define CRC_POL_POL_Msk                     (0xFFFFFFFFUL << CRC_POL_POL_Pos)       /*!< 0xFFFFFFFF */
#define CRC_POL_POL                         CRC_POL_POL_Msk                         /*!< Coefficients of the polynomial */

/******************************************************************************/
/*                                                                            */
/*                         Analog comparators (COMP)                          */
/*                                                                            */
/******************************************************************************/

/********************  Bit definition for COMP_SR register  ******************/
#define COMP_SR_C1VAL_Pos                   (0U)
#define COMP_SR_C1VAL_Msk                   (0x1UL << COMP_SR_C1VAL_Pos)          /*!< 0x00000001 */
#define COMP_SR_C1VAL                       COMP_SR_C1VAL_Msk

#define COMP_SR_C1IF_Pos                    (16U)
#define COMP_SR_C1IF_Msk                    (0x1UL << COMP_SR_C1IF_Pos)           /*!< 0x00010000 */
#define COMP_SR_C1IF                        COMP_SR_C1IF_Msk

/********************  Bit definition for COMP_ICFR register ******************/
#define COMP_ICFR_CC1IF_Pos                 (16U)
#define COMP_ICFR_CC1IF_Msk                 (0x1UL << COMP_ICFR_CC1IF_Pos)        /*!< 0x00010000 */
#define COMP_ICFR_CC1IF                     COMP_ICFR_CC1IF_Msk

/********************  Bit definition for COMP_CFGR1 register  ******************/
#define COMP_CFGR1_EN_Pos                   (0U)
#define COMP_CFGR1_EN_Msk                   (0x1UL << COMP_CFGR1_EN_Pos)          /*!< 0x00000001 */
#define COMP_CFGR1_EN                       COMP_CFGR1_EN_Msk                     /*!< Comparator enable */

#define COMP_CFGR1_BRGEN_Pos                (1U)
#define COMP_CFGR1_BRGEN_Msk                (0x1UL << COMP_CFGR1_BRGEN_Pos)       /*!< 0x00000002 */
#define COMP_CFGR1_BRGEN                    COMP_CFGR1_BRGEN_Msk                  /*!< Comparator scaler bridge enable */

#define COMP_CFGR1_SCALEN_Pos               (2U)
#define COMP_CFGR1_SCALEN_Msk               (0x1UL << COMP_CFGR1_SCALEN_Pos)      /*!< 0x00000004 */
#define COMP_CFGR1_SCALEN                   COMP_CFGR1_SCALEN_Msk                 /*!< Comparator voltage scaler enable */

#define COMP_CFGR1_POLARITY_Pos             (3U)
#define COMP_CFGR1_POLARITY_Msk             (0x1UL << COMP_CFGR1_POLARITY_Pos)    /*!< 0x00000008 */
#define COMP_CFGR1_POLARITY                 COMP_CFGR1_POLARITY_Msk               /*!< Comparator polarity selection */

#define COMP_CFGR1_ITEN_Pos                 (6U)
#define COMP_CFGR1_ITEN_Msk                 (0x1UL << COMP_CFGR1_ITEN_Pos)        /*!< 0x00000040 */
#define COMP_CFGR1_ITEN                     COMP_CFGR1_ITEN_Msk                   /*!< Comparator interrupt enable */

#define COMP_CFGR1_HYST_Pos                 (8U)
#define COMP_CFGR1_HYST_Msk                 (0x3UL << COMP_CFGR1_HYST_Pos)        /*!< 0x00000300 */
#define COMP_CFGR1_HYST                     COMP_CFGR1_HYST_Msk                   /*!< Comparator hysteresis selection */
#define COMP_CFGR1_HYST_0                   (0x1UL << COMP_CFGR1_HYST_Pos)        /*!< 0x00000100 */
#define COMP_CFGR1_HYST_1                   (0x2UL << COMP_CFGR1_HYST_Pos)        /*!< 0x00000200 */

#define COMP_CFGR1_PWRMODE_Pos              (12U)
#define COMP_CFGR1_PWRMODE_Msk              (0x3UL << COMP_CFGR1_PWRMODE_Pos)     /*!< 0x00003000 */
#define COMP_CFGR1_PWRMODE                  COMP_CFGR1_PWRMODE_Msk                /*!< Comparator power mode selection */
#define COMP_CFGR1_PWRMODE_0                (0x1UL << COMP_CFGR1_PWRMODE_Pos)     /*!< 0x00001000 */
#define COMP_CFGR1_PWRMODE_1                (0x2UL << COMP_CFGR1_PWRMODE_Pos)     /*!< 0x00002000 */

#define COMP_CFGR1_INMSEL_Pos               (16U)
#define COMP_CFGR1_INMSEL_Msk               (0xFUL << COMP_CFGR1_INMSEL_Pos)      /*!< 0x000F0000 */
#define COMP_CFGR1_INMSEL                   COMP_CFGR1_INMSEL_Msk                 /*!< Comparator input minus selection */
#define COMP_CFGR1_INMSEL_0                 (0x1UL << COMP_CFGR1_INMSEL_Pos)      /*!< 0x00010000 */
#define COMP_CFGR1_INMSEL_1                 (0x2UL << COMP_CFGR1_INMSEL_Pos)      /*!< 0x00020000 */
#define COMP_CFGR1_INMSEL_2                 (0x4UL << COMP_CFGR1_INMSEL_Pos)      /*!< 0x00040000 */
#define COMP_CFGR1_INMSEL_3                 (0x8UL << COMP_CFGR1_INMSEL_Pos)      /*!< 0x00080000 */

#define COMP_CFGR1_INPSEL_Pos               (20U)
#define COMP_CFGR1_INPSEL_Msk               (0x3UL << COMP_CFGR1_INPSEL_Pos)      /*!< 0x00300000 */
#define COMP_CFGR1_INPSEL                   COMP_CFGR1_INPSEL_Msk                 /*!< Comparator input plus selection */
#define COMP_CFGR1_INPSEL_0                 (0x1UL << COMP_CFGR1_INPSEL_Pos)      /*!< 0x00100000 */
#define COMP_CFGR1_INPSEL_1                 (0x2UL << COMP_CFGR1_INPSEL_Pos)      /*!< 0x00200000 */

#define COMP_CFGR1_BLANKING_Pos             (24U)
#define COMP_CFGR1_BLANKING_Msk             (0xFUL << COMP_CFGR1_BLANKING_Pos)    /*!< 0x0F000000 */
#define COMP_CFGR1_BLANKING                 COMP_CFGR1_BLANKING_Msk               /*!< Comparator blanking source selection */
#define COMP_CFGR1_BLANKING_0               (0x1UL << COMP_CFGR1_BLANKING_Pos)    /*!< 0x01000000 */
#define COMP_CFGR1_BLANKING_1               (0x2UL << COMP_CFGR1_BLANKING_Pos)    /*!< 0x02000000 */
#define COMP_CFGR1_BLANKING_2               (0x4UL << COMP_CFGR1_BLANKING_Pos)    /*!< 0x04000000 */
#define COMP_CFGR1_BLANKING_3               (0x8UL << COMP_CFGR1_BLANKING_Pos)    /*!< 0x08000000 */

#define COMP_CFGR1_LOCK_Pos                 (31U)
#define COMP_CFGR1_LOCK_Msk                 (0x1UL << COMP_CFGR1_LOCK_Pos)        /*!< 0x80000000 */
#define COMP_CFGR1_LOCK                     COMP_CFGR1_LOCK_Msk                   /*!< Comparator lock */

/******************************************************************************/
/*                                                                            */
/*                          CORDIC calculation unit                           */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for CORDIC_CSR register  *****************/
#define CORDIC_CSR_FUNC_Pos                 (0U)
#define CORDIC_CSR_FUNC_Msk                 (0xFUL << CORDIC_CSR_FUNC_Pos)          /*!< 0x0000000F */
#define CORDIC_CSR_FUNC                     CORDIC_CSR_FUNC_Msk                     /*!< Function */
#define CORDIC_CSR_FUNC_0                   (0x1UL << CORDIC_CSR_FUNC_Pos)          /*!< 0x00000001 */
#define CORDIC_CSR_FUNC_1                   (0x2UL << CORDIC_CSR_FUNC_Pos)          /*!< 0x00000002 */
#define CORDIC_CSR_FUNC_2                   (0x4UL << CORDIC_CSR_FUNC_Pos)          /*!< 0x00000004 */
#define CORDIC_CSR_FUNC_3                   (0x8UL << CORDIC_CSR_FUNC_Pos)          /*!< 0x00000008 */
#define CORDIC_CSR_PRECISION_Pos            (4U)
#define CORDIC_CSR_PRECISION_Msk            (0xFUL << CORDIC_CSR_PRECISION_Pos)     /*!< 0x000000F0 */
#define CORDIC_CSR_PRECISION                CORDIC_CSR_PRECISION_Msk                /*!< Precision */
#define CORDIC_CSR_PRECISION_0              (0x1UL << CORDIC_CSR_PRECISION_Pos)     /*!< 0x00000010 */
#define CORDIC_CSR_PRECISION_1              (0x2UL << CORDIC_CSR_PRECISION_Pos)     /*!< 0x00000020 */
#define CORDIC_CSR_PRECISION_2              (0x4UL << CORDIC_CSR_PRECISION_Pos)     /*!< 0x00000040 */
#define CORDIC_CSR_PRECISION_3              (0x8UL << CORDIC_CSR_PRECISION_Pos)     /*!< 0x00000080 */
#define CORDIC_CSR_SCALE_Pos                (8U)
#define CORDIC_CSR_SCALE_Msk                (0x7UL << CORDIC_CSR_SCALE_Pos)         /*!< 0x00000700 */
#define CORDIC_CSR_SCALE                    CORDIC_CSR_SCALE_Msk                    /*!< Scaling factor */
#define CORDIC_CSR_SCALE_0                  (0x1UL << CORDIC_CSR_SCALE_Pos)         /*!< 0x00000100 */
#define CORDIC_CSR_SCALE_1                  (0x2UL << CORDIC_CSR_SCALE_Pos)         /*!< 0x00000200 */
#define CORDIC_CSR_SCALE_2                  (0x4UL << CORDIC_CSR_SCALE_Pos)         /*!< 0x00000400 */
#define CORDIC_CSR_IEN_Pos                  (16U)
#define CORDIC_CSR_IEN_Msk                  (0x1UL << CORDIC_CSR_IEN_Pos)           /*!< 0x00010000 */
#define CORDIC_CSR_IEN                      CORDIC_CSR_IEN_Msk                      /*!< Interrupt Enable */
#define CORDIC_CSR_DMAREN_Pos               (17U)
#define CORDIC_CSR_DMAREN_Msk               (0x1UL << CORDIC_CSR_DMAREN_Pos)        /*!< 0x00020000 */
#define CORDIC_CSR_DMAREN                   CORDIC_CSR_DMAREN_Msk                   /*!< DMA Read channel Enable */
#define CORDIC_CSR_DMAWEN_Pos               (18U)
#define CORDIC_CSR_DMAWEN_Msk               (0x1UL << CORDIC_CSR_DMAWEN_Pos)        /*!< 0x00040000 */
#define CORDIC_CSR_DMAWEN                   CORDIC_CSR_DMAWEN_Msk                   /*!< DMA Write channel Enable */
#define CORDIC_CSR_NRES_Pos                 (19U)
#define CORDIC_CSR_NRES_Msk                 (0x1UL << CORDIC_CSR_NRES_Pos)          /*!< 0x00080000 */
#define CORDIC_CSR_NRES                     CORDIC_CSR_NRES_Msk                     /*!< Number of results in WDATA register */
#define CORDIC_CSR_NARGS_Pos                (20U)
#define CORDIC_CSR_NARGS_Msk                (0x1UL << CORDIC_CSR_NARGS_Pos)         /*!< 0x00100000 */
#define CORDIC_CSR_NARGS                    CORDIC_CSR_NARGS_Msk                    /*!< Number of arguments in RDATA register */
#define CORDIC_CSR_RESSIZE_Pos              (21U)
#define CORDIC_CSR_RESSIZE_Msk              (0x1UL << CORDIC_CSR_RESSIZE_Pos)       /*!< 0x00200000 */
#define CORDIC_CSR_RESSIZE                  CORDIC_CSR_RESSIZE_Msk                  /*!< Width of output data */
#define CORDIC_CSR_ARGSIZE_Pos              (22U)
#define CORDIC_CSR_ARGSIZE_Msk              (0x1UL << CORDIC_CSR_ARGSIZE_Pos)       /*!< 0x00400000 */
#define CORDIC_CSR_ARGSIZE                  CORDIC_CSR_ARGSIZE_Msk                  /*!< Width of input data */
#define CORDIC_CSR_RRDY_Pos                 (31U)
#define CORDIC_CSR_RRDY_Msk                 (0x1UL << CORDIC_CSR_RRDY_Pos)          /*!< 0x80000000 */
#define CORDIC_CSR_RRDY                     CORDIC_CSR_RRDY_Msk                     /*!< Result Ready Flag */

/*******************  Bit definition for CORDIC_WDATA register  ***************/
#define CORDIC_WDATA_ARG_Pos                (0U)
#define CORDIC_WDATA_ARG_Msk                (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos)  /*!< 0xFFFFFFFF */
#define CORDIC_WDATA_ARG                    CORDIC_WDATA_ARG_Msk                    /*!< Input Argument */

/*******************  Bit definition for CORDIC_RDATA register  ***************/
#define CORDIC_RDATA_RES_Pos                (0U)
#define CORDIC_RDATA_RES_Msk                (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos)  /*!< 0xFFFFFFFF */
#define CORDIC_RDATA_RES                    CORDIC_RDATA_RES_Msk                    /*!< Output Result */

/******************************************************************************/
/*                                                                            */
/*                            CRC calculation unit                            */
/*                                                                            */
/******************************************************************************/

/******************************************************************************/
/*                                                                            */
/*                          CRS Clock Recovery System                         */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for CRS_CR register  *********************/
#define CRS_CR_SYNCOKIE_Pos                 (0U)
#define CRS_CR_SYNCOKIE_Msk                 (0x1UL << CRS_CR_SYNCOKIE_Pos)          /*!< 0x00000001 */
#define CRS_CR_SYNCOKIE                     CRS_CR_SYNCOKIE_Msk                     /*!< SYNC event OK interrupt enable */
#define CRS_CR_SYNCWARNIE_Pos               (1U)
#define CRS_CR_SYNCWARNIE_Msk               (0x1UL << CRS_CR_SYNCWARNIE_Pos)        /*!< 0x00000002 */
#define CRS_CR_SYNCWARNIE                   CRS_CR_SYNCWARNIE_Msk                   /*!< SYNC warning interrupt enable */
#define CRS_CR_ERRIE_Pos                    (2U)
#define CRS_CR_ERRIE_Msk                    (0x1UL << CRS_CR_ERRIE_Pos)             /*!< 0x00000004 */
#define CRS_CR_ERRIE                        CRS_CR_ERRIE_Msk                        /*!< SYNC error or trimming error interrupt enable */
#define CRS_CR_ESYNCIE_Pos                  (3U)
#define CRS_CR_ESYNCIE_Msk                  (0x1UL << CRS_CR_ESYNCIE_Pos)           /*!< 0x00000008 */
#define CRS_CR_ESYNCIE                      CRS_CR_ESYNCIE_Msk                      /*!< Expected SYNC interrupt enable */
#define CRS_CR_CEN_Pos                      (5U)
#define CRS_CR_CEN_Msk                      (0x1UL << CRS_CR_CEN_Pos)               /*!< 0x00000020 */
#define CRS_CR_CEN                          CRS_CR_CEN_Msk                          /*!< Frequency error counter enable */
#define CRS_CR_AUTOTRIMEN_Pos               (6U)
#define CRS_CR_AUTOTRIMEN_Msk               (0x1UL << CRS_CR_AUTOTRIMEN_Pos)        /*!< 0x00000040 */
#define CRS_CR_AUTOTRIMEN                   CRS_CR_AUTOTRIMEN_Msk                   /*!< Automatic trimming enable */
#define CRS_CR_SWSYNC_Pos                   (7U)
#define CRS_CR_SWSYNC_Msk                   (0x1UL << CRS_CR_SWSYNC_Pos)            /*!< 0x00000080 */
#define CRS_CR_SWSYNC                       CRS_CR_SWSYNC_Msk                       /*!< Generate software SYNC event */
#define CRS_CR_TRIM_Pos                     (8U)
#define CRS_CR_TRIM_Msk                     (0x7FUL << CRS_CR_TRIM_Pos)             /*!< 0x00007F00 */
#define CRS_CR_TRIM                         CRS_CR_TRIM_Msk                         /*!< HSI144 oscillator smooth trimming */

/*******************  Bit definition for CRS_CFGR register  *********************/
#define CRS_CFGR_RELOAD_Pos                 (0U)
#define CRS_CFGR_RELOAD_Msk                 (0xFFFFUL << CRS_CFGR_RELOAD_Pos)       /*!< 0x0000FFFF */
#define CRS_CFGR_RELOAD                     CRS_CFGR_RELOAD_Msk                     /*!< Counter reload value */
#define CRS_CFGR_FELIM_Pos                  (16U)
#define CRS_CFGR_FELIM_Msk                  (0xFFUL << CRS_CFGR_FELIM_Pos)          /*!< 0x00FF0000 */
#define CRS_CFGR_FELIM                      CRS_CFGR_FELIM_Msk                      /*!< Frequency error limit */
#define CRS_CFGR_SYNCDIV_Pos                (24U)
#define CRS_CFGR_SYNCDIV_Msk                (0x7UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x07000000 */
#define CRS_CFGR_SYNCDIV                    CRS_CFGR_SYNCDIV_Msk                    /*!< SYNC divider */
#define CRS_CFGR_SYNCDIV_0                  (0x1UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x01000000 */
#define CRS_CFGR_SYNCDIV_1                  (0x2UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x02000000 */
#define CRS_CFGR_SYNCDIV_2                  (0x4UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x04000000 */
#define CRS_CFGR_SYNCSRC_Pos                (28U)
#define CRS_CFGR_SYNCSRC_Msk                (0x3UL << CRS_CFGR_SYNCSRC_Pos)         /*!< 0x30000000 */
#define CRS_CFGR_SYNCSRC                    CRS_CFGR_SYNCSRC_Msk                    /*!< SYNC signal source selection */
#define CRS_CFGR_SYNCSRC_0                  (0x1UL << CRS_CFGR_SYNCSRC_Pos)         /*!< 0x10000000 */
#define CRS_CFGR_SYNCSRC_1                  (0x2UL << CRS_CFGR_SYNCSRC_Pos)         /*!< 0x20000000 */
#define CRS_CFGR_SYNCPOL_Pos                (31U)
#define CRS_CFGR_SYNCPOL_Msk                (0x1UL << CRS_CFGR_SYNCPOL_Pos)         /*!< 0x80000000 */
#define CRS_CFGR_SYNCPOL                    CRS_CFGR_SYNCPOL_Msk                    /*!< SYNC polarity selection */

/*******************  Bit definition for CRS_ISR register  *********************/
#define CRS_ISR_SYNCOKF_Pos                 (0U)
#define CRS_ISR_SYNCOKF_Msk                 (0x1UL << CRS_ISR_SYNCOKF_Pos)          /*!< 0x00000001 */
#define CRS_ISR_SYNCOKF                     CRS_ISR_SYNCOKF_Msk                     /*!< SYNC event OK flag */
#define CRS_ISR_SYNCWARNF_Pos               (1U)
#define CRS_ISR_SYNCWARNF_Msk               (0x1UL << CRS_ISR_SYNCWARNF_Pos)        /*!< 0x00000002 */
#define CRS_ISR_SYNCWARNF                   CRS_ISR_SYNCWARNF_Msk                   /*!< SYNC warning flag */
#define CRS_ISR_ERRF_Pos                    (2U)
#define CRS_ISR_ERRF_Msk                    (0x1UL << CRS_ISR_ERRF_Pos)             /*!< 0x00000004 */
#define CRS_ISR_ERRF                        CRS_ISR_ERRF_Msk                        /*!< Error flag */
#define CRS_ISR_ESYNCF_Pos                  (3U)
#define CRS_ISR_ESYNCF_Msk                  (0x1UL << CRS_ISR_ESYNCF_Pos)           /*!< 0x00000008 */
#define CRS_ISR_ESYNCF                      CRS_ISR_ESYNCF_Msk                      /*!< Expected SYNC flag */
#define CRS_ISR_SYNCERR_Pos                 (8U)
#define CRS_ISR_SYNCERR_Msk                 (0x1UL << CRS_ISR_SYNCERR_Pos)          /*!< 0x00000100 */
#define CRS_ISR_SYNCERR                     CRS_ISR_SYNCERR_Msk                     /*!< SYNC error */
#define CRS_ISR_SYNCMISS_Pos                (9U)
#define CRS_ISR_SYNCMISS_Msk                (0x1UL << CRS_ISR_SYNCMISS_Pos)         /*!< 0x00000200 */
#define CRS_ISR_SYNCMISS                    CRS_ISR_SYNCMISS_Msk                    /*!< SYNC missed */
#define CRS_ISR_TRIMOVF_Pos                 (10U)
#define CRS_ISR_TRIMOVF_Msk                 (0x1UL << CRS_ISR_TRIMOVF_Pos)          /*!< 0x00000400 */
#define CRS_ISR_TRIMOVF                     CRS_ISR_TRIMOVF_Msk                     /*!< Trimming overflow or underflow */
#define CRS_ISR_FEDIR_Pos                   (15U)
#define CRS_ISR_FEDIR_Msk                   (0x1UL << CRS_ISR_FEDIR_Pos)            /*!< 0x00008000 */
#define CRS_ISR_FEDIR                       CRS_ISR_FEDIR_Msk                       /*!< Frequency error direction */
#define CRS_ISR_FECAP_Pos                   (16U)
#define CRS_ISR_FECAP_Msk                   (0xFFFFUL << CRS_ISR_FECAP_Pos)         /*!< 0xFFFF0000 */
#define CRS_ISR_FECAP                       CRS_ISR_FECAP_Msk                       /*!< Frequency error capture */

/*******************  Bit definition for CRS_ICR register  *********************/
#define CRS_ICR_SYNCOKC_Pos                 (0U)
#define CRS_ICR_SYNCOKC_Msk                 (0x1UL << CRS_ICR_SYNCOKC_Pos)          /*!< 0x00000001 */
#define CRS_ICR_SYNCOKC                     CRS_ICR_SYNCOKC_Msk                     /*!< SYNC event OK clear flag */
#define CRS_ICR_SYNCWARNC_Pos               (1U)
#define CRS_ICR_SYNCWARNC_Msk               (0x1UL << CRS_ICR_SYNCWARNC_Pos)        /*!< 0x00000002 */
#define CRS_ICR_SYNCWARNC                   CRS_ICR_SYNCWARNC_Msk                   /*!< SYNC warning clear flag */
#define CRS_ICR_ERRC_Pos                    (2U)
#define CRS_ICR_ERRC_Msk                    (0x1UL << CRS_ICR_ERRC_Pos)             /*!< 0x00000004 */
#define CRS_ICR_ERRC                        CRS_ICR_ERRC_Msk                        /*!< Error clear flag */
#define CRS_ICR_ESYNCC_Pos                  (3U)
#define CRS_ICR_ESYNCC_Msk                  (0x1UL << CRS_ICR_ESYNCC_Pos)           /*!< 0x00000008 */
#define CRS_ICR_ESYNCC                      CRS_ICR_ESYNCC_Msk                      /*!< Expected SYNC clear flag */

/**********************************************************************************************************************/
/*                                                                                                                    */
/*                                           Digital to Analog Converter (DAC)                                        */
/*                                                                                                                    */
/**********************************************************************************************************************/
#define DAC_NB_OF_CHANNEL                 (1U)    /*!< one available channel for each DAC instance */

/* **************************************  Bit definition for DAC_CR register  ************************************** */
#define DAC_CR_EN1_Pos             (0U)
#define DAC_CR_EN1_Msk             (0x1UL << DAC_CR_EN1_Pos)               /*!< 0x00000001 */
#define DAC_CR_EN1                 DAC_CR_EN1_Msk                          /*!< DAC channel1 enable */
#define DAC_CR_TEN1_Pos            (1U)
#define DAC_CR_TEN1_Msk            (0x1UL << DAC_CR_TEN1_Pos)              /*!< 0x00000002 */
#define DAC_CR_TEN1                DAC_CR_TEN1_Msk                         /*!< DAC channel1 trigger enable */
#define DAC_CR_TSEL1_Pos           (2U)
#define DAC_CR_TSEL1_Msk           (0x200FUL << DAC_CR_TSEL1_Pos)          /*!< 0x0008003C */
#define DAC_CR_TSEL1               DAC_CR_TSEL1_Msk                        /*!< DAC channel1 trigger selection */
#define DAC_CR_TSEL1_0             (0x1UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000004 */
#define DAC_CR_TSEL1_1             (0x2UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000008 */
#define DAC_CR_TSEL1_2             (0x4UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000010 */
#define DAC_CR_TSEL1_3             (0x8UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000020 */
#define DAC_CR_WAVE1_Pos           (6U)
#define DAC_CR_WAVE1_Msk           (0x3UL << DAC_CR_WAVE1_Pos)             /*!< 0x000000C0 */
#define DAC_CR_WAVE1               DAC_CR_WAVE1_Msk                        /*!< DAC channel1 noise/triangle wave
                                                                                generation enable */
#define DAC_CR_WAVE1_0             (0x1UL << DAC_CR_WAVE1_Pos)             /*!< 0x00000040 */
#define DAC_CR_WAVE1_1             (0x2UL << DAC_CR_WAVE1_Pos)             /*!< 0x00000080 */
#define DAC_CR_MAMP1_Pos           (8U)
#define DAC_CR_MAMP1_Msk           (0xFUL << DAC_CR_MAMP1_Pos)             /*!< 0x00000F00 */
#define DAC_CR_MAMP1               DAC_CR_MAMP1_Msk                        /*!< DAC channel1 mask/amplitude selector */
#define DAC_CR_MAMP1_0             (0x1UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000100 */
#define DAC_CR_MAMP1_1             (0x2UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000200 */
#define DAC_CR_MAMP1_2             (0x4UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000400 */
#define DAC_CR_MAMP1_3             (0x8UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000800 */
#define DAC_CR_DMAEN1_Pos          (12U)
#define DAC_CR_DMAEN1_Msk          (0x1UL << DAC_CR_DMAEN1_Pos)            /*!< 0x00001000 */
#define DAC_CR_DMAEN1              DAC_CR_DMAEN1_Msk                       /*!< DAC channel1 DMA enable */
#define DAC_CR_DMAUDRIE1_Pos       (13U)
#define DAC_CR_DMAUDRIE1_Msk       (0x1UL << DAC_CR_DMAUDRIE1_Pos)         /*!< 0x00002000 */
#define DAC_CR_DMAUDRIE1           DAC_CR_DMAUDRIE1_Msk                    /*!< DAC channel1 DMA Underrun
                                                                                Interrupt enable */
#define DAC_CR_CEN1_Pos            (14U)
#define DAC_CR_CEN1_Msk            (0x1UL << DAC_CR_CEN1_Pos)              /*!< 0x00004000 */
#define DAC_CR_CEN1                DAC_CR_CEN1_Msk                         /*!< DAC channel1 calibration enable */

/* ************************************  Bit definition for DAC_SWTRGR register  ************************************ */
#define DAC_SWTRGR_SWTRIG1_Pos     (0U)
#define DAC_SWTRGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRGR_SWTRIG1_Pos)       /*!< 0x00000001 */
#define DAC_SWTRGR_SWTRIG1         DAC_SWTRGR_SWTRIG1_Msk                  /*!< SWTRG1 (DAC channel1 software trigger)
                                                                                */

/* ***********************************  Bit definition for DAC_DHR12R1 register  ************************************ */
#define DAC_DHR12R1_DACC1DHR_Pos   (0U)
#define DAC_DHR12R1_DACC1DHR_Msk   (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)   /*!< 0x00000FFF */
#define DAC_DHR12R1_DACC1DHR       DAC_DHR12R1_DACC1DHR_Msk                /*!< DAC channel1 12-bit right-aligned data
                                                                                */
#define DAC_DHR12R1_DACC1DHR_0     (0x1UL << DAC_DHR12R1_DACC1DHR_Pos)     /*!< 0x00000001 */
#define DAC_DHR12R1_DACC1DHR_1     (0x2UL << DAC_DHR12R1_DACC1DHR_Pos)     /*!< 0x00000002 */
#define DAC_DHR12R1_DACC1DHR_2     (0x4UL << DAC_DHR12R1_DACC1DHR_Pos)     /*!< 0x00000004 */
#define DAC_DHR12R1_DACC1DHR_3     (0x8UL << DAC_DHR12R1_DACC1DHR_Pos)     /*!< 0x00000008 */
#define DAC_DHR12R1_DACC1DHR_4     (0x10UL << DAC_DHR12R1_DACC1DHR_Pos)    /*!< 0x00000010 */
#define DAC_DHR12R1_DACC1DHR_5     (0x20UL << DAC_DHR12R1_DACC1DHR_Pos)    /*!< 0x00000020 */
#define DAC_DHR12R1_DACC1DHR_6     (0x40UL << DAC_DHR12R1_DACC1DHR_Pos)    /*!< 0x00000040 */
#define DAC_DHR12R1_DACC1DHR_7     (0x80UL << DAC_DHR12R1_DACC1DHR_Pos)    /*!< 0x00000080 */
#define DAC_DHR12R1_DACC1DHR_8     (0x100UL << DAC_DHR12R1_DACC1DHR_Pos)   /*!< 0x00000100 */
#define DAC_DHR12R1_DACC1DHR_9     (0x200UL << DAC_DHR12R1_DACC1DHR_Pos)   /*!< 0x00000200 */
#define DAC_DHR12R1_DACC1DHR_10    (0x400UL << DAC_DHR12R1_DACC1DHR_Pos)   /*!< 0x00000400 */
#define DAC_DHR12R1_DACC1DHR_11    (0x800UL << DAC_DHR12R1_DACC1DHR_Pos)   /*!< 0x00000800 */
#define DAC_DHR12R1_DACC1DHRB_Pos  (16U)
#define DAC_DHR12R1_DACC1DHRB_Msk  (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos)  /*!< 0x0FFF0000 */
#define DAC_DHR12R1_DACC1DHRB      DAC_DHR12R1_DACC1DHRB_Msk               /*!< DAC channel1 12-bit right-aligned data B
                                                                                */
#define DAC_DHR12R1_DACC1DHRB_0    (0x1UL << DAC_DHR12R1_DACC1DHRB_Pos)    /*!< 0x00010000 */
#define DAC_DHR12R1_DACC1DHRB_1    (0x2UL << DAC_DHR12R1_DACC1DHRB_Pos)    /*!< 0x00020000 */
#define DAC_DHR12R1_DACC1DHRB_2    (0x4UL << DAC_DHR12R1_DACC1DHRB_Pos)    /*!< 0x00040000 */
#define DAC_DHR12R1_DACC1DHRB_3    (0x8UL << DAC_DHR12R1_DACC1DHRB_Pos)    /*!< 0x00080000 */
#define DAC_DHR12R1_DACC1DHRB_4    (0x10UL << DAC_DHR12R1_DACC1DHRB_Pos)   /*!< 0x00100000 */
#define DAC_DHR12R1_DACC1DHRB_5    (0x20UL << DAC_DHR12R1_DACC1DHRB_Pos)   /*!< 0x00200000 */
#define DAC_DHR12R1_DACC1DHRB_6    (0x40UL << DAC_DHR12R1_DACC1DHRB_Pos)   /*!< 0x00400000 */
#define DAC_DHR12R1_DACC1DHRB_7    (0x80UL << DAC_DHR12R1_DACC1DHRB_Pos)   /*!< 0x00800000 */
#define DAC_DHR12R1_DACC1DHRB_8    (0x100UL << DAC_DHR12R1_DACC1DHRB_Pos)  /*!< 0x01000000 */
#define DAC_DHR12R1_DACC1DHRB_9    (0x200UL << DAC_DHR12R1_DACC1DHRB_Pos)  /*!< 0x02000000 */
#define DAC_DHR12R1_DACC1DHRB_10   (0x400UL << DAC_DHR12R1_DACC1DHRB_Pos)  /*!< 0x04000000 */
#define DAC_DHR12R1_DACC1DHRB_11   (0x800UL << DAC_DHR12R1_DACC1DHRB_Pos)  /*!< 0x08000000 */

/* ***********************************  Bit definition for DAC_DHR12L1 register  ************************************ */
#define DAC_DHR12L1_DACC1DHR_Pos   (4U)
#define DAC_DHR12L1_DACC1DHR_Msk   (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)   /*!< 0x0000FFF0 */
#define DAC_DHR12L1_DACC1DHR       DAC_DHR12L1_DACC1DHR_Msk                /*!< DAC channel1 12-bit left-aligned data */
#define DAC_DHR12L1_DACC1DHR_0     (0x1UL << DAC_DHR12L1_DACC1DHR_Pos)     /*!< 0x00000010 */
#define DAC_DHR12L1_DACC1DHR_1     (0x2UL << DAC_DHR12L1_DACC1DHR_Pos)     /*!< 0x00000020 */
#define DAC_DHR12L1_DACC1DHR_2     (0x4UL << DAC_DHR12L1_DACC1DHR_Pos)     /*!< 0x00000040 */
#define DAC_DHR12L1_DACC1DHR_3     (0x8UL << DAC_DHR12L1_DACC1DHR_Pos)     /*!< 0x00000080 */
#define DAC_DHR12L1_DACC1DHR_4     (0x10UL << DAC_DHR12L1_DACC1DHR_Pos)    /*!< 0x00000100 */
#define DAC_DHR12L1_DACC1DHR_5     (0x20UL << DAC_DHR12L1_DACC1DHR_Pos)    /*!< 0x00000200 */
#define DAC_DHR12L1_DACC1DHR_6     (0x40UL << DAC_DHR12L1_DACC1DHR_Pos)    /*!< 0x00000400 */
#define DAC_DHR12L1_DACC1DHR_7     (0x80UL << DAC_DHR12L1_DACC1DHR_Pos)    /*!< 0x00000800 */
#define DAC_DHR12L1_DACC1DHR_8     (0x100UL << DAC_DHR12L1_DACC1DHR_Pos)   /*!< 0x00001000 */
#define DAC_DHR12L1_DACC1DHR_9     (0x200UL << DAC_DHR12L1_DACC1DHR_Pos)   /*!< 0x00002000 */
#define DAC_DHR12L1_DACC1DHR_10    (0x400UL << DAC_DHR12L1_DACC1DHR_Pos)   /*!< 0x00004000 */
#define DAC_DHR12L1_DACC1DHR_11    (0x800UL << DAC_DHR12L1_DACC1DHR_Pos)   /*!< 0x00008000 */
#define DAC_DHR12L1_DACC1DHRB_Pos  (20U)
#define DAC_DHR12L1_DACC1DHRB_Msk  (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos)  /*!< 0xFFF00000 */
#define DAC_DHR12L1_DACC1DHRB      DAC_DHR12L1_DACC1DHRB_Msk               /*!< DAC channel1 12-bit left-aligned data B
                                                                                */
#define DAC_DHR12L1_DACC1DHRB_0    (0x1UL << DAC_DHR12L1_DACC1DHRB_Pos)    /*!< 0x00100000 */
#define DAC_DHR12L1_DACC1DHRB_1    (0x2UL << DAC_DHR12L1_DACC1DHRB_Pos)    /*!< 0x00200000 */
#define DAC_DHR12L1_DACC1DHRB_2    (0x4UL << DAC_DHR12L1_DACC1DHRB_Pos)    /*!< 0x00400000 */
#define DAC_DHR12L1_DACC1DHRB_3    (0x8UL << DAC_DHR12L1_DACC1DHRB_Pos)    /*!< 0x00800000 */
#define DAC_DHR12L1_DACC1DHRB_4    (0x10UL << DAC_DHR12L1_DACC1DHRB_Pos)   /*!< 0x01000000 */
#define DAC_DHR12L1_DACC1DHRB_5    (0x20UL << DAC_DHR12L1_DACC1DHRB_Pos)   /*!< 0x02000000 */
#define DAC_DHR12L1_DACC1DHRB_6    (0x40UL << DAC_DHR12L1_DACC1DHRB_Pos)   /*!< 0x04000000 */
#define DAC_DHR12L1_DACC1DHRB_7    (0x80UL << DAC_DHR12L1_DACC1DHRB_Pos)   /*!< 0x08000000 */
#define DAC_DHR12L1_DACC1DHRB_8    (0x100UL << DAC_DHR12L1_DACC1DHRB_Pos)  /*!< 0x10000000 */
#define DAC_DHR12L1_DACC1DHRB_9    (0x200UL << DAC_DHR12L1_DACC1DHRB_Pos)  /*!< 0x20000000 */
#define DAC_DHR12L1_DACC1DHRB_10   (0x400UL << DAC_DHR12L1_DACC1DHRB_Pos)  /*!< 0x40000000 */
#define DAC_DHR12L1_DACC1DHRB_11   (0x800UL << DAC_DHR12L1_DACC1DHRB_Pos)  /*!< 0x80000000 */

/* ************************************  Bit definition for DAC_DHR8R1 register  ************************************ */
#define DAC_DHR8R1_DACC1DHR_Pos    (0U)
#define DAC_DHR8R1_DACC1DHR_Msk    (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)     /*!< 0x000000FF */
#define DAC_DHR8R1_DACC1DHR        DAC_DHR8R1_DACC1DHR_Msk                 /*!< DAC channel1 8-bit right-aligned data */
#define DAC_DHR8R1_DACC1DHR_0      (0x1UL << DAC_DHR8R1_DACC1DHR_Pos)      /*!< 0x00000001 */
#define DAC_DHR8R1_DACC1DHR_1      (0x2UL << DAC_DHR8R1_DACC1DHR_Pos)      /*!< 0x00000002 */
#define DAC_DHR8R1_DACC1DHR_2      (0x4UL << DAC_DHR8R1_DACC1DHR_Pos)      /*!< 0x00000004 */
#define DAC_DHR8R1_DACC1DHR_3      (0x8UL << DAC_DHR8R1_DACC1DHR_Pos)      /*!< 0x00000008 */
#define DAC_DHR8R1_DACC1DHR_4      (0x10UL << DAC_DHR8R1_DACC1DHR_Pos)     /*!< 0x00000010 */
#define DAC_DHR8R1_DACC1DHR_5      (0x20UL << DAC_DHR8R1_DACC1DHR_Pos)     /*!< 0x00000020 */
#define DAC_DHR8R1_DACC1DHR_6      (0x40UL << DAC_DHR8R1_DACC1DHR_Pos)     /*!< 0x00000040 */
#define DAC_DHR8R1_DACC1DHR_7      (0x80UL << DAC_DHR8R1_DACC1DHR_Pos)     /*!< 0x00000080 */
#define DAC_DHR8R1_DACC1DHRB_Pos   (8U)
#define DAC_DHR8R1_DACC1DHRB_Msk   (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos)    /*!< 0x0000FF00 */
#define DAC_DHR8R1_DACC1DHRB       DAC_DHR8R1_DACC1DHRB_Msk                /*!< DAC channel1 8-bit right-aligned data */
#define DAC_DHR8R1_DACC1DHRB_0     (0x1UL << DAC_DHR8R1_DACC1DHRB_Pos)     /*!< 0x00000100 */
#define DAC_DHR8R1_DACC1DHRB_1     (0x2UL << DAC_DHR8R1_DACC1DHRB_Pos)     /*!< 0x00000200 */
#define DAC_DHR8R1_DACC1DHRB_2     (0x4UL << DAC_DHR8R1_DACC1DHRB_Pos)     /*!< 0x00000400 */
#define DAC_DHR8R1_DACC1DHRB_3     (0x8UL << DAC_DHR8R1_DACC1DHRB_Pos)     /*!< 0x00000800 */
#define DAC_DHR8R1_DACC1DHRB_4     (0x10UL << DAC_DHR8R1_DACC1DHRB_Pos)    /*!< 0x00001000 */
#define DAC_DHR8R1_DACC1DHRB_5     (0x20UL << DAC_DHR8R1_DACC1DHRB_Pos)    /*!< 0x00002000 */
#define DAC_DHR8R1_DACC1DHRB_6     (0x40UL << DAC_DHR8R1_DACC1DHRB_Pos)    /*!< 0x00004000 */
#define DAC_DHR8R1_DACC1DHRB_7     (0x80UL << DAC_DHR8R1_DACC1DHRB_Pos)    /*!< 0x00008000 */

/* *************************************  Bit definition for DAC_DOR1 register  ************************************* */
#define DAC_DOR1_DACC1DOR_Pos      (0U)
#define DAC_DOR1_DACC1DOR_Msk      (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)      /*!< 0x00000FFF */
#define DAC_DOR1_DACC1DOR          DAC_DOR1_DACC1DOR_Msk                   /*!< DAC channel1 data output */
#define DAC_DOR1_DACC1DOR_0        (0x1UL << DAC_DOR1_DACC1DOR_Pos)        /*!< 0x00000001 */
#define DAC_DOR1_DACC1DOR_1        (0x2UL << DAC_DOR1_DACC1DOR_Pos)        /*!< 0x00000002 */
#define DAC_DOR1_DACC1DOR_2        (0x4UL << DAC_DOR1_DACC1DOR_Pos)        /*!< 0x00000004 */
#define DAC_DOR1_DACC1DOR_3        (0x8UL << DAC_DOR1_DACC1DOR_Pos)        /*!< 0x00000008 */
#define DAC_DOR1_DACC1DOR_4        (0x10UL << DAC_DOR1_DACC1DOR_Pos)       /*!< 0x00000010 */
#define DAC_DOR1_DACC1DOR_5        (0x20UL << DAC_DOR1_DACC1DOR_Pos)       /*!< 0x00000020 */
#define DAC_DOR1_DACC1DOR_6        (0x40UL << DAC_DOR1_DACC1DOR_Pos)       /*!< 0x00000040 */
#define DAC_DOR1_DACC1DOR_7        (0x80UL << DAC_DOR1_DACC1DOR_Pos)       /*!< 0x00000080 */
#define DAC_DOR1_DACC1DOR_8        (0x100UL << DAC_DOR1_DACC1DOR_Pos)      /*!< 0x00000100 */
#define DAC_DOR1_DACC1DOR_9        (0x200UL << DAC_DOR1_DACC1DOR_Pos)      /*!< 0x00000200 */
#define DAC_DOR1_DACC1DOR_10       (0x400UL << DAC_DOR1_DACC1DOR_Pos)      /*!< 0x00000400 */
#define DAC_DOR1_DACC1DOR_11       (0x800UL << DAC_DOR1_DACC1DOR_Pos)      /*!< 0x00000800 */
#define DAC_DOR1_DACC1DORB_Pos     (16U)
#define DAC_DOR1_DACC1DORB_Msk     (0xFFFUL << DAC_DOR1_DACC1DORB_Pos)     /*!< 0x0FFF0000 */
#define DAC_DOR1_DACC1DORB         DAC_DOR1_DACC1DORB_Msk                  /*!< DAC channel1 data output */
#define DAC_DOR1_DACC1DORB_0       (0x1UL << DAC_DOR1_DACC1DORB_Pos)       /*!< 0x00010000 */
#define DAC_DOR1_DACC1DORB_1       (0x2UL << DAC_DOR1_DACC1DORB_Pos)       /*!< 0x00020000 */
#define DAC_DOR1_DACC1DORB_2       (0x4UL << DAC_DOR1_DACC1DORB_Pos)       /*!< 0x00040000 */
#define DAC_DOR1_DACC1DORB_3       (0x8UL << DAC_DOR1_DACC1DORB_Pos)       /*!< 0x00080000 */
#define DAC_DOR1_DACC1DORB_4       (0x10UL << DAC_DOR1_DACC1DORB_Pos)      /*!< 0x00100000 */
#define DAC_DOR1_DACC1DORB_5       (0x20UL << DAC_DOR1_DACC1DORB_Pos)      /*!< 0x00200000 */
#define DAC_DOR1_DACC1DORB_6       (0x40UL << DAC_DOR1_DACC1DORB_Pos)      /*!< 0x00400000 */
#define DAC_DOR1_DACC1DORB_7       (0x80UL << DAC_DOR1_DACC1DORB_Pos)      /*!< 0x00800000 */
#define DAC_DOR1_DACC1DORB_8       (0x100UL << DAC_DOR1_DACC1DORB_Pos)     /*!< 0x01000000 */
#define DAC_DOR1_DACC1DORB_9       (0x200UL << DAC_DOR1_DACC1DORB_Pos)     /*!< 0x02000000 */
#define DAC_DOR1_DACC1DORB_10      (0x400UL << DAC_DOR1_DACC1DORB_Pos)     /*!< 0x04000000 */
#define DAC_DOR1_DACC1DORB_11      (0x800UL << DAC_DOR1_DACC1DORB_Pos)     /*!< 0x08000000 */

/* **************************************  Bit definition for DAC_SR register  ************************************** */
#define DAC_SR_DAC1RDY_Pos         (11U)
#define DAC_SR_DAC1RDY_Msk         (0x1UL << DAC_SR_DAC1RDY_Pos)           /*!< 0x00000800 */
#define DAC_SR_DAC1RDY             DAC_SR_DAC1RDY_Msk                      /*!< DAC channel1 ready status bit */
#define DAC_SR_DORSTAT1_Pos        (12U)
#define DAC_SR_DORSTAT1_Msk        (0x1UL << DAC_SR_DORSTAT1_Pos)          /*!< 0x00001000 */
#define DAC_SR_DORSTAT1            DAC_SR_DORSTAT1_Msk                     /*!< DAC channel1 output register status bit
                                                                                */
#define DAC_SR_DMAUDR1_Pos         (13U)
#define DAC_SR_DMAUDR1_Msk         (0x1UL << DAC_SR_DMAUDR1_Pos)           /*!< 0x00002000 */
#define DAC_SR_DMAUDR1             DAC_SR_DMAUDR1_Msk                      /*!< DAC channel1 DMA underrun flag */
#define DAC_SR_CAL_FLAG1_Pos       (14U)
#define DAC_SR_CAL_FLAG1_Msk       (0x1UL << DAC_SR_CAL_FLAG1_Pos)         /*!< 0x00004000 */
#define DAC_SR_CAL_FLAG1           DAC_SR_CAL_FLAG1_Msk                    /*!< DAC channel1 calibration offset status
                                                                                */
#define DAC_SR_BWST1_Pos           (15U)
#define DAC_SR_BWST1_Msk           (0x1UL << DAC_SR_BWST1_Pos)             /*!< 0x00008000 */
#define DAC_SR_BWST1               DAC_SR_BWST1_Msk                        /*!< DAC channel1 busy writing sample time
                                                                                flag */

/* *************************************  Bit definition for DAC_CCR register  ************************************** */
#define DAC_CCR_OTRIM1_Pos         (0U)
#define DAC_CCR_OTRIM1_Msk         (0x1FUL << DAC_CCR_OTRIM1_Pos)          /*!< 0x0000001F */
#define DAC_CCR_OTRIM1             DAC_CCR_OTRIM1_Msk                      /*!< DAC channel1 offset trimming value */
#define DAC_CCR_OTRIM1_0           (0x1UL << DAC_CCR_OTRIM1_Pos)           /*!< 0x00000001 */
#define DAC_CCR_OTRIM1_1           (0x2UL << DAC_CCR_OTRIM1_Pos)           /*!< 0x00000002 */
#define DAC_CCR_OTRIM1_2           (0x4UL << DAC_CCR_OTRIM1_Pos)           /*!< 0x00000004 */
#define DAC_CCR_OTRIM1_3           (0x8UL << DAC_CCR_OTRIM1_Pos)           /*!< 0x00000008 */
#define DAC_CCR_OTRIM1_4           (0x10UL << DAC_CCR_OTRIM1_Pos)          /*!< 0x00000010 */

/* *************************************  Bit definition for DAC_MCR register  ************************************** */
#define DAC_MCR_MODE1_Pos          (0U)
#define DAC_MCR_MODE1_Msk          (0x7UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000007 */
#define DAC_MCR_MODE1              DAC_MCR_MODE1_Msk                       /*!< DAC channel1 mode */
#define DAC_MCR_MODE1_0            (0x1UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000001 */
#define DAC_MCR_MODE1_1            (0x2UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000002 */
#define DAC_MCR_MODE1_2            (0x4UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000004 */
#define DAC_MCR_DMADOUBLE1_Pos     (8U)
#define DAC_MCR_DMADOUBLE1_Msk     (0x1UL << DAC_MCR_DMADOUBLE1_Pos)       /*!< 0x00000100 */
#define DAC_MCR_DMADOUBLE1         DAC_MCR_DMADOUBLE1_Msk                  /*!< DAC channel1 DMA double data mode */
#define DAC_MCR_SINFORMAT1_Pos     (9U)
#define DAC_MCR_SINFORMAT1_Msk     (0x1UL << DAC_MCR_SINFORMAT1_Pos)       /*!< 0x00000200 */
#define DAC_MCR_SINFORMAT1         DAC_MCR_SINFORMAT1_Msk                  /*!< Enable signed format for DAC channel1 */
#define DAC_MCR_HFSEL_Pos          (13U)
#define DAC_MCR_HFSEL_Msk          (0x7UL << DAC_MCR_HFSEL_Pos)            /*!< 0x0000E000 */
#define DAC_MCR_HFSEL              DAC_MCR_HFSEL_Msk                       /*!< High frequency interface mode selection
                                                                                */
#define DAC_MCR_HFSEL_0            (0x1UL << DAC_MCR_HFSEL_Pos)            /*!< 0x00002000 */
#define DAC_MCR_HFSEL_1            (0x2UL << DAC_MCR_HFSEL_Pos)            /*!< 0x00004000 */
#define DAC_MCR_HFSEL_2            (0x4UL << DAC_MCR_HFSEL_Pos)            /*!< 0x00008000 */

/* ************************************  Bit definition for DAC_SHSR1 register  ************************************* */
#define DAC_SHSR1_TSAMPLE1_Pos     (0U)
#define DAC_SHSR1_TSAMPLE1_Msk     (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)     /*!< 0x000003FF */
#define DAC_SHSR1_TSAMPLE1         DAC_SHSR1_TSAMPLE1_Msk                  /*!< DAC channel1 sample time
                                                                                (only valid in sample and hold mode) */
#define DAC_SHSR1_TSAMPLE1_0       (0x1UL << DAC_SHSR1_TSAMPLE1_Pos)       /*!< 0x00000001 */
#define DAC_SHSR1_TSAMPLE1_1       (0x2UL << DAC_SHSR1_TSAMPLE1_Pos)       /*!< 0x00000002 */
#define DAC_SHSR1_TSAMPLE1_2       (0x4UL << DAC_SHSR1_TSAMPLE1_Pos)       /*!< 0x00000004 */
#define DAC_SHSR1_TSAMPLE1_3       (0x8UL << DAC_SHSR1_TSAMPLE1_Pos)       /*!< 0x00000008 */
#define DAC_SHSR1_TSAMPLE1_4       (0x10UL << DAC_SHSR1_TSAMPLE1_Pos)      /*!< 0x00000010 */
#define DAC_SHSR1_TSAMPLE1_5       (0x20UL << DAC_SHSR1_TSAMPLE1_Pos)      /*!< 0x00000020 */
#define DAC_SHSR1_TSAMPLE1_6       (0x40UL << DAC_SHSR1_TSAMPLE1_Pos)      /*!< 0x00000040 */
#define DAC_SHSR1_TSAMPLE1_7       (0x80UL << DAC_SHSR1_TSAMPLE1_Pos)      /*!< 0x00000080 */
#define DAC_SHSR1_TSAMPLE1_8       (0x100UL << DAC_SHSR1_TSAMPLE1_Pos)     /*!< 0x00000100 */
#define DAC_SHSR1_TSAMPLE1_9       (0x200UL << DAC_SHSR1_TSAMPLE1_Pos)     /*!< 0x00000200 */

/* *************************************  Bit definition for DAC_SHHR register  ************************************* */
#define DAC_SHHR_THOLD1_Pos        (0U)
#define DAC_SHHR_THOLD1_Msk        (0x3FFUL << DAC_SHHR_THOLD1_Pos)        /*!< 0x000003FF */
#define DAC_SHHR_THOLD1            DAC_SHHR_THOLD1_Msk                     /*!< DAC channel1 hold time
                                                                                (only valid in Sample and hold mode) */
#define DAC_SHHR_THOLD1_0          (0x1UL << DAC_SHHR_THOLD1_Pos)          /*!< 0x00000001 */
#define DAC_SHHR_THOLD1_1          (0x2UL << DAC_SHHR_THOLD1_Pos)          /*!< 0x00000002 */
#define DAC_SHHR_THOLD1_2          (0x4UL << DAC_SHHR_THOLD1_Pos)          /*!< 0x00000004 */
#define DAC_SHHR_THOLD1_3          (0x8UL << DAC_SHHR_THOLD1_Pos)          /*!< 0x00000008 */
#define DAC_SHHR_THOLD1_4          (0x10UL << DAC_SHHR_THOLD1_Pos)         /*!< 0x00000010 */
#define DAC_SHHR_THOLD1_5          (0x20UL << DAC_SHHR_THOLD1_Pos)         /*!< 0x00000020 */
#define DAC_SHHR_THOLD1_6          (0x40UL << DAC_SHHR_THOLD1_Pos)         /*!< 0x00000040 */
#define DAC_SHHR_THOLD1_7          (0x080UL << DAC_SHHR_THOLD1_Pos)        /*!< 0x00000080 */
#define DAC_SHHR_THOLD1_8          (0x100UL << DAC_SHHR_THOLD1_Pos)        /*!< 0x00000100 */
#define DAC_SHHR_THOLD1_9          (0x200UL << DAC_SHHR_THOLD1_Pos)        /*!< 0x00000200 */

/* *************************************  Bit definition for DAC_SHRR register  ************************************* */
#define DAC_SHRR_TREFRESH1_Pos     (0U)
#define DAC_SHRR_TREFRESH1_Msk     (0xFFUL << DAC_SHRR_TREFRESH1_Pos)      /*!< 0x000000FF */
#define DAC_SHRR_TREFRESH1         DAC_SHRR_TREFRESH1_Msk                  /*!< DAC channel1 refresh time
                                                                                (only valid in sample and hold mode) */
#define DAC_SHRR_TREFRESH1_0       (0x1UL << DAC_SHRR_TREFRESH1_Pos)       /*!< 0x00000001 */
#define DAC_SHRR_TREFRESH1_1       (0x2UL << DAC_SHRR_TREFRESH1_Pos)       /*!< 0x00000002 */
#define DAC_SHRR_TREFRESH1_2       (0x4UL << DAC_SHRR_TREFRESH1_Pos)       /*!< 0x00000004 */
#define DAC_SHRR_TREFRESH1_3       (0x8UL << DAC_SHRR_TREFRESH1_Pos)       /*!< 0x00000008 */
#define DAC_SHRR_TREFRESH1_4       (0x10UL << DAC_SHRR_TREFRESH1_Pos)      /*!< 0x00000010 */
#define DAC_SHRR_TREFRESH1_5       (0x20UL << DAC_SHRR_TREFRESH1_Pos)      /*!< 0x00000020 */
#define DAC_SHRR_TREFRESH1_6       (0x40UL << DAC_SHRR_TREFRESH1_Pos)      /*!< 0x00000040 */
#define DAC_SHRR_TREFRESH1_7       (0x80UL << DAC_SHRR_TREFRESH1_Pos)      /*!< 0x00000080 */

/**********************************************************************************************************************/
/*                                                                                                                    */
/*                                            Debug MCU (DBGMCU)                                                      */
/*                                                                                                                    */
/**********************************************************************************************************************/
/* **********************************  Bit definition for DBGMCU_IDCODE register  *********************************** */
#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)
#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)               /*!< 0x00000FFF */
#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk                            /*!< Device
                                                                                                        identification
                                                                                                        */
#define DBGMCU_IDCODE_REV_ID_Pos               (16U)
#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)              /*!< 0xFFFF0000 */
#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk                            /*!< Revision of the
                                                                                                        device */

/* ************************************  Bit definition for DBGMCU_CR register  ************************************* */
#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)
#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)                  /*!< 0x00000001 */
#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk                             /*!< Debug in Sleep
                                                                                                        mode */
#define DBGMCU_CR_DBG_STOP_Pos                 (1U)
#define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos)                   /*!< 0x00000002 */
#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk                              /*!< Debug in Stop
                                                                                                        mode */
#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)
#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)                /*!< 0x00000004 */
#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk                           /*!< Debug in Standby
                                                                                                        mode */
#define DBGMCU_CR_TRACE_IOEN_Pos               (4U)
#define DBGMCU_CR_TRACE_IOEN_Msk               (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)                 /*!< 0x00000010 */
#define DBGMCU_CR_TRACE_IOEN                   DBGMCU_CR_TRACE_IOEN_Msk                            /*!< Trace pin enable
                                                                                                        */
#define DBGMCU_CR_TRACE_EN_Pos                 (5U)
#define DBGMCU_CR_TRACE_EN_Msk                 (0x1UL << DBGMCU_CR_TRACE_EN_Pos)                   /*!< 0x00000020 */
#define DBGMCU_CR_TRACE_EN                     DBGMCU_CR_TRACE_EN_Msk                              /*!< Trace port and
                                                                                                        clock enable. */
#define DBGMCU_CR_TRACE_MODE_Pos               (6U)
#define DBGMCU_CR_TRACE_MODE_Msk               (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)                 /*!< 0x000000C0 */
#define DBGMCU_CR_TRACE_MODE                   DBGMCU_CR_TRACE_MODE_Msk                            /*!< Trace pin
                                                                                                        assignment */
#define DBGMCU_CR_TRACE_MODE_0                (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)                  /*!< 0x00000040 */
#define DBGMCU_CR_TRACE_MODE_1                (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)                  /*!< 0x00000080 */

/* *********************************  Bit definition for DBGMCU_APB1LFZR register  ********************************** */
#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos      (0U)
#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk      (0x1UL << DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos)        /*!< 0x00000001 */
#define DBGMCU_APB1LFZR_DBG_TIM2_STOP          DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk                   /*!< TIM2 stop in
                                                                                                        debug */
#define DBGMCU_APB1LFZR_DBG_TIM5_STOP_Pos      (3U)
#define DBGMCU_APB1LFZR_DBG_TIM5_STOP_Msk      (0x1UL << DBGMCU_APB1LFZR_DBG_TIM5_STOP_Pos)        /*!< 0x00000008 */
#define DBGMCU_APB1LFZR_DBG_TIM5_STOP          DBGMCU_APB1LFZR_DBG_TIM5_STOP_Msk                   /*!< TIM5 stop in
                                                                                                        debug */
#define DBGMCU_APB1LFZR_DBG_TIM6_STOP_Pos      (4U)
#define DBGMCU_APB1LFZR_DBG_TIM6_STOP_Msk      (0x1UL << DBGMCU_APB1LFZR_DBG_TIM6_STOP_Pos)        /*!< 0x00000010 */
#define DBGMCU_APB1LFZR_DBG_TIM6_STOP          DBGMCU_APB1LFZR_DBG_TIM6_STOP_Msk                   /*!< TIM6 stop in
                                                                                                        debug */
#define DBGMCU_APB1LFZR_DBG_TIM7_STOP_Pos      (5U)
#define DBGMCU_APB1LFZR_DBG_TIM7_STOP_Msk      (0x1UL << DBGMCU_APB1LFZR_DBG_TIM7_STOP_Pos)        /*!< 0x00000020 */
#define DBGMCU_APB1LFZR_DBG_TIM7_STOP          DBGMCU_APB1LFZR_DBG_TIM7_STOP_Msk                   /*!< TIM7 stop in
                                                                                                        debug */
#define DBGMCU_APB1LFZR_DBG_TIM12_STOP_Pos     (6U)
#define DBGMCU_APB1LFZR_DBG_TIM12_STOP_Msk     (0x1UL << DBGMCU_APB1LFZR_DBG_TIM12_STOP_Pos)       /*!< 0x00000040 */
#define DBGMCU_APB1LFZR_DBG_TIM12_STOP         DBGMCU_APB1LFZR_DBG_TIM12_STOP_Msk                  /*!< TIM12 stop in
                                                                                                        debug */
#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos      (11U)
#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk      (0x1UL << DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos)        /*!< 0x00000800 */
#define DBGMCU_APB1LFZR_DBG_WWDG_STOP          DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk                   /*!< WWDG stop in
                                                                                                        debug */
#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos      (12U)
#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk      (0x1UL << DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos)        /*!< 0x00001000 */
#define DBGMCU_APB1LFZR_DBG_IWDG_STOP          DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk                   /*!< IWDG stop in
                                                                                                        debug */
#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos      (21U)
#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk      (0x1UL << DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos)        /*!< 0x00200000 */
#define DBGMCU_APB1LFZR_DBG_I2C1_STOP          DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk                   /*!< I2C1 SMBUS
                                                                                                        timeout stop in
                                                                                                        debug */
#define DBGMCU_APB1LFZR_DBG_I2C2_STOP_Pos      (22U)
#define DBGMCU_APB1LFZR_DBG_I2C2_STOP_Msk      (0x1UL << DBGMCU_APB1LFZR_DBG_I2C2_STOP_Pos)        /*!< 0x00400000 */
#define DBGMCU_APB1LFZR_DBG_I2C2_STOP          DBGMCU_APB1LFZR_DBG_I2C2_STOP_Msk                   /*!< I2C2 SMBUS
                                                                                                        timeout stop in
                                                                                                        debug */
#define DBGMCU_APB1LFZR_DBG_I3C1_STOP_Pos      (23U)
#define DBGMCU_APB1LFZR_DBG_I3C1_STOP_Msk      (0x1UL << DBGMCU_APB1LFZR_DBG_I3C1_STOP_Pos)        /*!< 0x00800000 */
#define DBGMCU_APB1LFZR_DBG_I3C1_STOP          DBGMCU_APB1LFZR_DBG_I3C1_STOP_Msk                   /*!< I3C1 SCL stall
                                                                                                        counter stop in
                                                                                                        debug */

/* **********************************  Bit definition for DBGMCU_APB2FZR register  ********************************** */
#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos       (11U)
#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk       (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos)         /*!< 0x00000800 */
#define DBGMCU_APB2FZR_DBG_TIM1_STOP           DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk                    /*!< TIM1 stop in
                                                                                                        debug */
#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos       (13U)
#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk       (0x1UL << DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos)         /*!< 0x00002000 */
#define DBGMCU_APB2FZR_DBG_TIM8_STOP           DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk                    /*!< TIM8 stop in
                                                                                                        debug */
#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos      (16U)
#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk      (0x1UL << DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos)        /*!< 0x00010000 */
#define DBGMCU_APB2FZR_DBG_TIM15_STOP          DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk                   /*!< TIM15 stop in
                                                                                                        debug */
#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos      (17U)
#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk      (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos)        /*!< 0x00020000 */
#define DBGMCU_APB2FZR_DBG_TIM16_STOP          DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk                   /*!< TIM16 stop in
                                                                                                        debug */
#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos      (18U)
#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk      (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos)        /*!< 0x00040000 */
#define DBGMCU_APB2FZR_DBG_TIM17_STOP          DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk                   /*!< TIM17 stop in
                                                                                                        debug */

/* **********************************  Bit definition for DBGMCU_APB3FZR register  ********************************** */
#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos     (17U)
#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk     (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos)       /*!< 0x00020000 */
#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP         DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk                  /*!< LPTIM1 stop
                                                                                                        in debug */
#define DBGMCU_APB3FZR_DBG_RTC_STOP_Pos        (30U)
#define DBGMCU_APB3FZR_DBG_RTC_STOP_Msk        (0x1UL << DBGMCU_APB3FZR_DBG_RTC_STOP_Pos)          /*!< 0x40000000 */
#define DBGMCU_APB3FZR_DBG_RTC_STOP            DBGMCU_APB3FZR_DBG_RTC_STOP_Msk                     /*!< RTC stop in
                                                                                                        debug */

/* **********************************  Bit definition for DBGMCU_AHB1FZR register  ********************************** */
#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Pos   (0U)
#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Msk   (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Pos)     /*!< 0x00000001 */
#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP       DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Msk                /*!< LPDMA1 channel 0
                                                                                                        stop in debug */
#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Pos   (1U)
#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Msk   (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Pos)     /*!< 0x00000002 */
#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP       DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Msk                /*!< LPDMA1 channel 1
                                                                                                        stop in debug */
#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Pos   (2U)
#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Msk   (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Pos)     /*!< 0x00000004 */
#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP       DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Msk                /*!< LPDMA1 channel 2
                                                                                                        stop in debug */
#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Pos   (3U)
#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Msk   (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Pos)     /*!< 0x00000008 */
#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP       DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Msk                /*!< LPDMA1 channel 3
                                                                                                        stop in debug */
#define DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Pos   (4U)
#define DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Msk   (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Pos)     /*!< 0x00000010 */
#define DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP       DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Msk                /*!< LPDMA1 channel 4
                                                                                                        stop in debug */
#define DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Pos   (5U)
#define DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Msk   (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Pos)     /*!< 0x00000020 */
#define DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP       DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Msk                /*!< LPDMA1 channel 5
                                                                                                        stop in debug */
#define DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Pos   (6U)
#define DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Msk   (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Pos)     /*!< 0x00000040 */
#define DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP       DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Msk                /*!< LPDMA1 channel 6
                                                                                                        stop in debug */
#define DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Pos   (7U)
#define DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Msk   (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Pos)     /*!< 0x00000080 */
#define DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP       DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Msk                /*!< LPDMA1 channel 7
                                                                                                        stop in debug */
#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Pos   (16U)
#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Msk   (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Pos)     /*!< 0x00010000 */
#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP       DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Msk                /*!< LPDMA2 channel 0
                                                                                                        stop in debug */
#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Pos   (17U)
#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Msk   (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Pos)     /*!< 0x00020000 */
#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP       DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Msk                /*!< LPDMA2 channel 1
                                                                                                        stop in debug */
#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Pos   (18U)
#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Msk   (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Pos)     /*!< 0x00040000 */
#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP       DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Msk                /*!< LPDMA2 channel 2
                                                                                                        stop in debug */
#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Pos   (19U)
#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Msk   (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Pos)     /*!< 0x00080000 */
#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP       DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Msk                /*!< LPDMA2 channel 3
                                                                                                        stop in debug */

/* ************************************  Bit definition for DBGMCU_SR register  ************************************* */
#define DBGMCU_SR_AP_PRESENT_Pos               (0U)
#define DBGMCU_SR_AP_PRESENT_Msk               (0xFFFFUL << DBGMCU_SR_AP_PRESENT_Pos)              /*!< 0x0000FFFF */
#define DBGMCU_SR_AP_PRESENT                   DBGMCU_SR_AP_PRESENT_Msk                            /*!< Access port
                                                                                                        present */
#define DBGMCU_SR_AP_ENABLED_Pos               (16U)
#define DBGMCU_SR_AP_ENABLED_Msk               (0xFFFFUL << DBGMCU_SR_AP_ENABLED_Pos)              /*!< 0xFFFF0000 */
#define DBGMCU_SR_AP_ENABLED                   DBGMCU_SR_AP_ENABLED_Msk                            /*!< Access port
                                                                                                        enable */

/* *******************************  Bit definition for DBGMCU_DBG_AUTH_HOST register  ******************************* */
#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Pos      (0U)
#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Msk      (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Pos) /*!< 0xFFFFFFFF */
#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY          DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Msk                   /*!< Device
                                                                                                        authentication
                                                                                                        key */

/* ******************************  Bit definition for DBGMCU_DBG_AUTH_DEVICE register  ****************************** */
#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Pos     (0U)
#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Msk     (0xFFFFFFFFUL << \
                                               DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Pos)                 /*!< 0xFFFFFFFF */
#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID         DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Msk                  /*!< Device specific
                                                                                                        ID */

/* *******************************  Bit definition for DBGMCU_DBG_BSKEY_PWD register  ******************************* */
#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Pos (0U)
#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Msk (0xFFFFFFFFUL << \
                                               DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Pos)             /*!< 0xFFFFFFFF */
#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD     DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Msk              /*!< Boundary-scan
                                                                                                        key (BS key) */

/* *********************************  Bit definition for DBGMCU_DBG_VALR register  ********************************** */
#define DBGMCU_DBG_VALR_VAL_RDY_Pos            (0U)
#define DBGMCU_DBG_VALR_VAL_RDY_Msk            (0x1UL << DBGMCU_DBG_VALR_VAL_RDY_Pos)              /*!< 0x00000001 */
#define DBGMCU_DBG_VALR_VAL_RDY                DBGMCU_DBG_VALR_VAL_RDY_Msk                         /*!< Validation ready
                                                                                                        */
#define DBGMCU_DBG_VALR_VAL_OEMKEY_Pos         (1U)
#define DBGMCU_DBG_VALR_VAL_OEMKEY_Msk         (0x1UL << DBGMCU_DBG_VALR_VAL_OEMKEY_Pos)           /*!< 0x00000002 */
#define DBGMCU_DBG_VALR_VAL_OEMKEY             DBGMCU_DBG_VALR_VAL_OEMKEY_Msk                      /*!< OEMKEY
                                                                                                        validation. */

/* ***********************************  Bit definition for DBGMCU_PIDR4 register  *********************************** */
#define DBGMCU_PIDR4_JEP106CON_Pos             (0U)
#define DBGMCU_PIDR4_JEP106CON_Msk             (0xFUL << DBGMCU_PIDR4_JEP106CON_Pos)               /*!< 0x0000000F */
#define DBGMCU_PIDR4_JEP106CON                 DBGMCU_PIDR4_JEP106CON_Msk                          /*!< JEP106
                                                                                                        continuation
                                                                                                        code */
#define DBGMCU_PIDR4_SIZE_Pos                  (4U)
#define DBGMCU_PIDR4_SIZE_Msk                  (0xFUL << DBGMCU_PIDR4_SIZE_Pos)                    /*!< 0x000000F0 */
#define DBGMCU_PIDR4_SIZE                      DBGMCU_PIDR4_SIZE_Msk                               /*!< Register file
                                                                                                        size */

/* ***********************************  Bit definition for DBGMCU_PIDR0 register  *********************************** */
#define DBGMCU_PIDR0_PARTNUM_Pos               (0U)
#define DBGMCU_PIDR0_PARTNUM_Msk               (0xFFUL << DBGMCU_PIDR0_PARTNUM_Pos)                /*!< 0x000000FF */
#define DBGMCU_PIDR0_PARTNUM                   DBGMCU_PIDR0_PARTNUM_Msk                            /*!< Part number bits
                                                                                                        [7:0] */

/* ***********************************  Bit definition for DBGMCU_PIDR1 register  *********************************** */
#define DBGMCU_PIDR1_PARTNUM_Pos               (0U)
#define DBGMCU_PIDR1_PARTNUM_Msk               (0xFUL << DBGMCU_PIDR1_PARTNUM_Pos)                 /*!< 0x0000000F */
#define DBGMCU_PIDR1_PARTNUM                   DBGMCU_PIDR1_PARTNUM_Msk                            /*!< Part number bits
                                                                                                        [11:8] */
#define DBGMCU_PIDR1_JEP106ID_Pos              (4U)
#define DBGMCU_PIDR1_JEP106ID_Msk              (0xFUL << DBGMCU_PIDR1_JEP106ID_Pos)                /*!< 0x000000F0 */
#define DBGMCU_PIDR1_JEP106ID                  DBGMCU_PIDR1_JEP106ID_Msk                           /*!< JEP106 identity
                                                                                                        code bits [3:0]
                                                                                                        */

/* ***********************************  Bit definition for DBGMCU_PIDR2 register  *********************************** */
#define DBGMCU_PIDR2_JEP106ID_Pos              (0U)
#define DBGMCU_PIDR2_JEP106ID_Msk              (0x7UL << DBGMCU_PIDR2_JEP106ID_Pos)                /*!< 0x00000007 */
#define DBGMCU_PIDR2_JEP106ID                  DBGMCU_PIDR2_JEP106ID_Msk                           /*!< JEP106 identity
                                                                                                        code bits [6:4]
                                                                                                        */
#define DBGMCU_PIDR2_JEDEC_Pos                 (3U)
#define DBGMCU_PIDR2_JEDEC_Msk                 (0x1UL << DBGMCU_PIDR2_JEDEC_Pos)                   /*!< 0x00000008 */
#define DBGMCU_PIDR2_JEDEC                     DBGMCU_PIDR2_JEDEC_Msk                              /*!< JEDEC assigned
                                                                                                        value */
#define DBGMCU_PIDR2_REVISION_Pos              (4U)
#define DBGMCU_PIDR2_REVISION_Msk              (0xFUL << DBGMCU_PIDR2_REVISION_Pos)                /*!< 0x000000F0 */
#define DBGMCU_PIDR2_REVISION                  DBGMCU_PIDR2_REVISION_Msk                           /*!< Component
                                                                                                        revision number
                                                                                                        */

/* ***********************************  Bit definition for DBGMCU_PIDR3 register  *********************************** */
#define DBGMCU_PIDR3_CMOD_Pos                  (0U)
#define DBGMCU_PIDR3_CMOD_Msk                  (0xFUL << DBGMCU_PIDR3_CMOD_Pos)                    /*!< 0x0000000F */
#define DBGMCU_PIDR3_CMOD                      DBGMCU_PIDR3_CMOD_Msk                               /*!< Customer
                                                                                                        modified */
#define DBGMCU_PIDR3_REVAND_Pos                (4U)
#define DBGMCU_PIDR3_REVAND_Msk                (0xFUL << DBGMCU_PIDR3_REVAND_Pos)                  /*!< 0x000000F0 */
#define DBGMCU_PIDR3_REVAND                    DBGMCU_PIDR3_REVAND_Msk                             /*!< Metal fix
                                                                                                        version */

/* ***********************************  Bit definition for DBGMCU_CIDR0 register  *********************************** */
#define DBGMCU_CIDR0_PREAMBLE_Pos              (0U)
#define DBGMCU_CIDR0_PREAMBLE_Msk              (0xFFUL << DBGMCU_CIDR0_PREAMBLE_Pos)               /*!< 0x000000FF */
#define DBGMCU_CIDR0_PREAMBLE                  DBGMCU_CIDR0_PREAMBLE_Msk                           /*!< Component
                                                                                                        identification
                                                                                                        bits [7:0] */

/* ***********************************  Bit definition for DBGMCU_CIDR1 register  *********************************** */
#define DBGMCU_CIDR1_PREAMBLE_Pos              (0U)
#define DBGMCU_CIDR1_PREAMBLE_Msk              (0xFUL << DBGMCU_CIDR1_PREAMBLE_Pos)                /*!< 0x0000000F */
#define DBGMCU_CIDR1_PREAMBLE                  DBGMCU_CIDR1_PREAMBLE_Msk                           /*!< Component
                                                                                                        identification
                                                                                                        bits [11:8] */
#define DBGMCU_CIDR1_CLASS_Pos                 (4U)
#define DBGMCU_CIDR1_CLASS_Msk                 (0xFUL << DBGMCU_CIDR1_CLASS_Pos)                   /*!< 0x000000F0 */
#define DBGMCU_CIDR1_CLASS                     DBGMCU_CIDR1_CLASS_Msk                              /*!< Component
                                                                                                        identification
                                                                                                        bits [15:12] -
                                                                                                        component class
                                                                                                        */

/* ***********************************  Bit definition for DBGMCU_CIDR2 register  *********************************** */
#define DBGMCU_CIDR2_PREAMBLE_Pos              (0U)
#define DBGMCU_CIDR2_PREAMBLE_Msk              (0xFFUL << DBGMCU_CIDR2_PREAMBLE_Pos)               /*!< 0x000000FF */
#define DBGMCU_CIDR2_PREAMBLE                  DBGMCU_CIDR2_PREAMBLE_Msk                           /*!< Component
                                                                                                        identification
                                                                                                        bits [23:16] */

/* ***********************************  Bit definition for DBGMCU_CIDR3 register  *********************************** */
#define DBGMCU_CIDR3_PREAMBLE_Pos              (0U)
#define DBGMCU_CIDR3_PREAMBLE_Msk              (0xFFUL << DBGMCU_CIDR3_PREAMBLE_Pos)               /*!< 0x000000FF */
#define DBGMCU_CIDR3_PREAMBLE                  DBGMCU_CIDR3_PREAMBLE_Msk                           /*!< Component
                                                                                                        identification
                                                                                                        bits [31:24] */

/**********************************************************************************************************************/
/*                                                                                                                    */
/*                                         DMA Controller (DMA)                                                       */
/*                                                                                                                    */
/**********************************************************************************************************************/
/* ***********************************  Bit definition for DMA_PRIVCFGR register  *********************************** */
#define DMA_PRIVCFGR_PRIV0_Pos              (0U)
#define DMA_PRIVCFGR_PRIV0_Msk              (0x1UL << DMA_PRIVCFGR_PRIV0_Pos)       /*!< 0x00000001 */
#define DMA_PRIVCFGR_PRIV0                  DMA_PRIVCFGR_PRIV0_Msk                  /*!< Privileged State of
                                                                                           Channel 0 */
#define DMA_PRIVCFGR_PRIV1_Pos              (1U)
#define DMA_PRIVCFGR_PRIV1_Msk              (0x1UL << DMA_PRIVCFGR_PRIV1_Pos)       /*!< 0x00000002 */
#define DMA_PRIVCFGR_PRIV1                  DMA_PRIVCFGR_PRIV1_Msk                  /*!< Privileged State of
                                                                                           Channel 1  */
#define DMA_PRIVCFGR_PRIV2_Pos              (2U)
#define DMA_PRIVCFGR_PRIV2_Msk              (0x1UL << DMA_PRIVCFGR_PRIV2_Pos)       /*!< 0x00000004 */
#define DMA_PRIVCFGR_PRIV2                  DMA_PRIVCFGR_PRIV2_Msk                  /*!< Privileged State of
                                                                                           Channel 2  */
#define DMA_PRIVCFGR_PRIV3_Pos              (3U)
#define DMA_PRIVCFGR_PRIV3_Msk              (0x1UL << DMA_PRIVCFGR_PRIV3_Pos)       /*!< 0x00000008 */
#define DMA_PRIVCFGR_PRIV3                  DMA_PRIVCFGR_PRIV3_Msk                  /*!< Privileged State of
                                                                                           Channel 3  */
#define DMA_PRIVCFGR_PRIV4_Pos              (4U)
#define DMA_PRIVCFGR_PRIV4_Msk              (0x1UL << DMA_PRIVCFGR_PRIV4_Pos)       /*!< 0x00000010 */
#define DMA_PRIVCFGR_PRIV4                  DMA_PRIVCFGR_PRIV4_Msk                  /*!< Privileged State of
                                                                                           Channel 4  */
#define DMA_PRIVCFGR_PRIV5_Pos              (5U)
#define DMA_PRIVCFGR_PRIV5_Msk              (0x1UL << DMA_PRIVCFGR_PRIV5_Pos)       /*!< 0x00000020 */
#define DMA_PRIVCFGR_PRIV5                  DMA_PRIVCFGR_PRIV5_Msk                  /*!< Privileged State of
                                                                                           Channel 5  */
#define DMA_PRIVCFGR_PRIV6_Pos              (6U)
#define DMA_PRIVCFGR_PRIV6_Msk              (0x1UL << DMA_PRIVCFGR_PRIV6_Pos)       /*!< 0x00000040 */
#define DMA_PRIVCFGR_PRIV6                  DMA_PRIVCFGR_PRIV6_Msk                  /*!< Privileged State of
                                                                                           Channel 6  */
#define DMA_PRIVCFGR_PRIV7_Pos              (7U)
#define DMA_PRIVCFGR_PRIV7_Msk              (0x1UL << DMA_PRIVCFGR_PRIV7_Pos)       /*!< 0x00000080 */
#define DMA_PRIVCFGR_PRIV7                  DMA_PRIVCFGR_PRIV7_Msk                  /*!< Privileged State of
                                                                                           Channel 7  */

/* **********************************  Bit definition for DMA_RCFGLOCKR register  *********************************** */
#define DMA_RCFGLOCKR_LOCK0_Pos              (0U)
#define DMA_RCFGLOCKR_LOCK0_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos)       /*!< 0x00000001 */
#define DMA_RCFGLOCKR_LOCK0                  DMA_RCFGLOCKR_LOCK0_Msk                  /*!< Lock the configuration
                                                                                           of Channel 0  */
#define DMA_RCFGLOCKR_LOCK1_Pos              (1U)
#define DMA_RCFGLOCKR_LOCK1_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos)       /*!< 0x00000002 */
#define DMA_RCFGLOCKR_LOCK1                  DMA_RCFGLOCKR_LOCK1_Msk                  /*!< Lock the configuration
                                                                                           of Channel 1  */
#define DMA_RCFGLOCKR_LOCK2_Pos              (2U)
#define DMA_RCFGLOCKR_LOCK2_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos)       /*!< 0x00000004 */
#define DMA_RCFGLOCKR_LOCK2                  DMA_RCFGLOCKR_LOCK2_Msk                  /*!< Lock the configuration
                                                                                           of Channel 2  */
#define DMA_RCFGLOCKR_LOCK3_Pos              (3U)
#define DMA_RCFGLOCKR_LOCK3_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos)       /*!< 0x00000008 */
#define DMA_RCFGLOCKR_LOCK3                  DMA_RCFGLOCKR_LOCK3_Msk                  /*!< Lock the configuration
                                                                                           of Channel 3  */
#define DMA_RCFGLOCKR_LOCK4_Pos              (4U)
#define DMA_RCFGLOCKR_LOCK4_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos)       /*!< 0x00000010 */
#define DMA_RCFGLOCKR_LOCK4                  DMA_RCFGLOCKR_LOCK4_Msk                  /*!< Lock the configuration
                                                                                           of Channel 4  */
#define DMA_RCFGLOCKR_LOCK5_Pos              (5U)
#define DMA_RCFGLOCKR_LOCK5_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos)       /*!< 0x00000020 */
#define DMA_RCFGLOCKR_LOCK5                  DMA_RCFGLOCKR_LOCK5_Msk                  /*!< Lock the configuration
                                                                                           of Channel 5  */
#define DMA_RCFGLOCKR_LOCK6_Pos              (6U)
#define DMA_RCFGLOCKR_LOCK6_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos)       /*!< 0x00000040 */
#define DMA_RCFGLOCKR_LOCK6                  DMA_RCFGLOCKR_LOCK6_Msk                  /*!< Lock the configuration
                                                                                           of Channel 6  */
#define DMA_RCFGLOCKR_LOCK7_Pos              (7U)
#define DMA_RCFGLOCKR_LOCK7_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos)       /*!< 0x00000080 */
#define DMA_RCFGLOCKR_LOCK7                  DMA_RCFGLOCKR_LOCK7_Msk                  /*!< Lock the configuration
                                                                                           of Channel 7  */

/* *************************************  Bit definition for DMA_MISR register  ************************************* */
#define DMA_MISR_MIS0_Pos                   (0U)
#define DMA_MISR_MIS0_Msk                   (0x1UL << DMA_MISR_MIS0_Pos)            /*!< 0x00000001 */
#define DMA_MISR_MIS0                       DMA_MISR_MIS0_Msk                       /*!< Masked Interrupt State of
                                                                                         Channel 0  */
#define DMA_MISR_MIS1_Pos                   (1U)
#define DMA_MISR_MIS1_Msk                   (0x1UL << DMA_MISR_MIS1_Pos)            /*!< 0x00000002 */
#define DMA_MISR_MIS1                       DMA_MISR_MIS1_Msk                       /*!< Masked Interrupt State of
                                                                                         Channel 1  */
#define DMA_MISR_MIS2_Pos                   (2U)
#define DMA_MISR_MIS2_Msk                   (0x1UL << DMA_MISR_MIS2_Pos)            /*!< 0x00000004 */
#define DMA_MISR_MIS2                       DMA_MISR_MIS2_Msk                       /*!< Masked Interrupt State of
                                                                                         Channel 2  */
#define DMA_MISR_MIS3_Pos                   (3U)
#define DMA_MISR_MIS3_Msk                   (0x1UL << DMA_MISR_MIS3_Pos)            /*!< 0x00000008 */
#define DMA_MISR_MIS3                       DMA_MISR_MIS3_Msk                       /*!< Masked Interrupt State of
                                                                                         Channel 3  */
#define DMA_MISR_MIS4_Pos                   (4U)
#define DMA_MISR_MIS4_Msk                   (0x1UL << DMA_MISR_MIS4_Pos)            /*!< 0x00000010 */
#define DMA_MISR_MIS4                       DMA_MISR_MIS4_Msk                       /*!< Masked Interrupt State of
                                                                                         Channel 4  */
#define DMA_MISR_MIS5_Pos                   (5U)
#define DMA_MISR_MIS5_Msk                   (0x1UL << DMA_MISR_MIS5_Pos)            /*!< 0x00000020 */
#define DMA_MISR_MIS5                       DMA_MISR_MIS5_Msk                       /*!< Masked Interrupt State of
                                                                                         Channel 5  */
#define DMA_MISR_MIS6_Pos                   (6U)
#define DMA_MISR_MIS6_Msk                   (0x1UL << DMA_MISR_MIS6_Pos)            /*!< 0x00000040 */
#define DMA_MISR_MIS6                       DMA_MISR_MIS6_Msk                       /*!< Masked Interrupt State of
                                                                                         Channel 6  */
#define DMA_MISR_MIS7_Pos                   (7U)
#define DMA_MISR_MIS7_Msk                   (0x1UL << DMA_MISR_MIS7_Pos)            /*!< 0x00000080 */
#define DMA_MISR_MIS7                       DMA_MISR_MIS7_Msk                       /*!< Masked Interrupt State of
                                                                                         Channel 7  */

/* ************************************  Bit definition for DMA_CLBAR register  ************************************* */
#define DMA_CLBAR_LBA_Pos                   (16U)
#define DMA_CLBAR_LBA_Msk                   (0xFFFFUL << DMA_CLBAR_LBA_Pos)         /*!< 0xFFFF0000 */
#define DMA_CLBAR_LBA                       DMA_CLBAR_LBA_Msk                       /*!< Linked-list Base Address
                                                                                         of DMA channel x */

/* ************************************  Bit definition for DMA_CFCR register  ************************************** */
#define DMA_CFCR_TCF_Pos                    (8U)
#define DMA_CFCR_TCF_Msk                    (0x1UL << DMA_CFCR_TCF_Pos)             /*!< 0x00000100 */
#define DMA_CFCR_TCF                        DMA_CFCR_TCF_Msk                        /*!< Transfer complete
                                                                                          flag clear */
#define DMA_CFCR_HTF_Pos                    (9U)
#define DMA_CFCR_HTF_Msk                    (0x1UL << DMA_CFCR_HTF_Pos)             /*!< 0x00000200 */
#define DMA_CFCR_HTF                        DMA_CFCR_HTF_Msk                        /*!< Half transfer complete
                                                                                          flag clear */
#define DMA_CFCR_DTEF_Pos                   (10U)
#define DMA_CFCR_DTEF_Msk                   (0x1UL << DMA_CFCR_DTEF_Pos)            /*!< 0x00000400 */
#define DMA_CFCR_DTEF                       DMA_CFCR_DTEF_Msk                       /*!< Data transfer error
                                                                                          flag clear */
#define DMA_CFCR_ULEF_Pos                   (11U)
#define DMA_CFCR_ULEF_Msk                   (0x1UL << DMA_CFCR_ULEF_Pos)            /*!< 0x00000800 */
#define DMA_CFCR_ULEF                       DMA_CFCR_ULEF_Msk                       /*!< Update linked-list item
                                                                                          error flag clear  */
#define DMA_CFCR_USEF_Pos                   (12U)
#define DMA_CFCR_USEF_Msk                   (0x1UL << DMA_CFCR_USEF_Pos)            /*!< 0x00001000 */
#define DMA_CFCR_USEF                       DMA_CFCR_USEF_Msk                       /*!< User setting error
                                                                                          flag clear */
#define DMA_CFCR_SUSPF_Pos                  (13U)
#define DMA_CFCR_SUSPF_Msk                  (0x1UL << DMA_CFCR_SUSPF_Pos)           /*!< 0x00002000 */
#define DMA_CFCR_SUSPF                      DMA_CFCR_SUSPF_Msk                      /*!< Completed suspension
                                                                                          flag clear */
#define DMA_CFCR_TOF_Pos                    (14U)
#define DMA_CFCR_TOF_Msk                    (0x1UL << DMA_CFCR_TOF_Pos)             /*!< 0x00004000 */
#define DMA_CFCR_TOF                        DMA_CFCR_TOF_Msk                        /*!< Trigger overrun
                                                                                          flag clear  */

/* *************************************  Bit definition for DMA_CSR register  ************************************** */
#define DMA_CSR_IDLEF_Pos                   (0U)
#define DMA_CSR_IDLEF_Msk                   (0x1UL << DMA_CSR_IDLEF_Pos)            /*!< 0x00000001 */
#define DMA_CSR_IDLEF                       DMA_CSR_IDLEF_Msk                       /*!< Idle flag */
#define DMA_CSR_TCF_Pos                     (8U)
#define DMA_CSR_TCF_Msk                     (0x1UL << DMA_CSR_TCF_Pos)              /*!< 0x00000100 */
#define DMA_CSR_TCF                         DMA_CSR_TCF_Msk                         /*!< Transfer complete flag */
#define DMA_CSR_HTF_Pos                     (9U)
#define DMA_CSR_HTF_Msk                     (0x1UL << DMA_CSR_HTF_Pos)              /*!< 0x00000200 */
#define DMA_CSR_HTF                         DMA_CSR_HTF_Msk                         /*!< Half transfer complete flag */
#define DMA_CSR_DTEF_Pos                    (10U)
#define DMA_CSR_DTEF_Msk                    (0x1UL << DMA_CSR_DTEF_Pos)             /*!< 0x00000400 */
#define DMA_CSR_DTEF                        DMA_CSR_DTEF_Msk                        /*!< Data transfer error flag */
#define DMA_CSR_ULEF_Pos                    (11U)
#define DMA_CSR_ULEF_Msk                    (0x1UL << DMA_CSR_ULEF_Pos)             /*!< 0x00000800 */
#define DMA_CSR_ULEF                        DMA_CSR_ULEF_Msk                        /*!< Update linked-list
                                                                                         item error flag */
#define DMA_CSR_USEF_Pos                    (12U)
#define DMA_CSR_USEF_Msk                    (0x1UL << DMA_CSR_USEF_Pos)             /*!< 0x00001000 */
#define DMA_CSR_USEF                        DMA_CSR_USEF_Msk                        /*!< User setting error flag */
#define DMA_CSR_SUSPF_Pos                   (13U)
#define DMA_CSR_SUSPF_Msk                   (0x1UL << DMA_CSR_SUSPF_Pos)            /*!< 0x00002000 */
#define DMA_CSR_SUSPF                       DMA_CSR_SUSPF_Msk                       /*!< Completed suspension flag */
#define DMA_CSR_TOF_Pos                     (14U)
#define DMA_CSR_TOF_Msk                     (0x1UL << DMA_CSR_TOF_Pos)              /*!< 0x00004000 */
#define DMA_CSR_TOF                         DMA_CSR_TOF_Msk                         /*!< Trigger overrun flag */

/* *************************************  Bit definition for DMA_CCR register  ************************************** */
#define DMA_CCR_EN_Pos                      (0U)
#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)               /*!< 0x00000001 */
#define DMA_CCR_EN                          DMA_CCR_EN_Msk                          /*!< Channel enable */
#define DMA_CCR_RESET_Pos                   (1U)
#define DMA_CCR_RESET_Msk                   (0x1UL << DMA_CCR_RESET_Pos)            /*!< 0x00000002 */
#define DMA_CCR_RESET                       DMA_CCR_RESET_Msk                       /*!< Channel reset  */
#define DMA_CCR_SUSP_Pos                    (2U)
#define DMA_CCR_SUSP_Msk                    (0x1UL << DMA_CCR_SUSP_Pos)             /*!< 0x00000004 */
#define DMA_CCR_SUSP                        DMA_CCR_SUSP_Msk                        /*!< Channel suspend */
#define DMA_CCR_TCIE_Pos                    (8U)
#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)             /*!< 0x00000100 */
#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                        /*!< Transfer complete interrupt
                                                                                          enable */
#define DMA_CCR_HTIE_Pos                    (9U)
#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)             /*!< 0x00000200 */
#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                        /*!< Half transfer complete
                                                                                         interrupt enable */
#define DMA_CCR_DTEIE_Pos                   (10U)
#define DMA_CCR_DTEIE_Msk                   (0x1UL << DMA_CCR_DTEIE_Pos)            /*!< 0x00000400 */
#define DMA_CCR_DTEIE                       DMA_CCR_DTEIE_Msk                       /*!< Data transfer error interrupt
                                                                                          enable */
#define DMA_CCR_ULEIE_Pos                   (11U)
#define DMA_CCR_ULEIE_Msk                   (0x1UL << DMA_CCR_ULEIE_Pos)            /*!< 0x00000800 */
#define DMA_CCR_ULEIE                       DMA_CCR_ULEIE_Msk                       /*!< Update linked-list item
                                                                                         error interrupt enable */
#define DMA_CCR_USEIE_Pos                   (12U)
#define DMA_CCR_USEIE_Msk                   (0x1UL << DMA_CCR_USEIE_Pos)            /*!< 0x00001000 */
#define DMA_CCR_USEIE                       DMA_CCR_USEIE_Msk                       /*!< User setting error
                                                                                         interrupt enable */
#define DMA_CCR_SUSPIE_Pos                  (13U)
#define DMA_CCR_SUSPIE_Msk                  (0x1UL << DMA_CCR_SUSPIE_Pos)           /*!< 0x00002000 */
#define DMA_CCR_SUSPIE                      DMA_CCR_SUSPIE_Msk                      /*!< Completed suspension
                                                                                         interrupt enable */
#define DMA_CCR_TOIE_Pos                    (14U)
#define DMA_CCR_TOIE_Msk                    (0x1UL << DMA_CCR_TOIE_Pos)             /*!< 0x00004000 */
#define DMA_CCR_TOIE                        DMA_CCR_TOIE_Msk                        /*!< Trigger overrun
                                                                                         interrupt enable */
#define DMA_CCR_LSM_Pos                     (16U)
#define DMA_CCR_LSM_Msk                     (0x1UL << DMA_CCR_LSM_Pos)              /*!< 0x00010000 */
#define DMA_CCR_LSM                         DMA_CCR_LSM_Msk                         /*!< Link step mode */
#define DMA_CCR_PRIO_Pos                    (22U)
#define DMA_CCR_PRIO_Msk                    (0x3UL << DMA_CCR_PRIO_Pos)             /*!< 0x00C00000 */
#define DMA_CCR_PRIO                        DMA_CCR_PRIO_Msk                        /*!< Priority level  */
#define DMA_CCR_PRIO_0                      (0x1UL << DMA_CCR_PRIO_Pos)             /*!< 0x00400000 */
#define DMA_CCR_PRIO_1                      (0x2UL << DMA_CCR_PRIO_Pos)             /*!< 0x00800000 */

/* ************************************  Bit definition for DMA_CTR1 register  ************************************** */
#define DMA_CTR1_SDW_LOG2_Pos               (0U)
#define DMA_CTR1_SDW_LOG2_Msk               (0x3UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< 0x00000003 */
#define DMA_CTR1_SDW_LOG2                   DMA_CTR1_SDW_LOG2_Msk                   /*!< Binary logarithm of the
                                                                                         source data width of a burst */
#define DMA_CTR1_SDW_LOG2_0                 (0x1UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 0 */
#define DMA_CTR1_SDW_LOG2_1                 (0x2UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 1 */
#define DMA_CTR1_SINC_Pos                   (3U)
#define DMA_CTR1_SINC_Msk                   (0x1UL << DMA_CTR1_SINC_Pos)            /*!< 0x00000008 */
#define DMA_CTR1_SINC                       DMA_CTR1_SINC_Msk                       /*!< Source incrementing burst */
#define DMA_CTR1_PAM_Pos                    (11U)
#define DMA_CTR1_PAM_Msk                    (0x1UL << DMA_CTR1_PAM_Pos)             /*!< 0x00000800 */
#define DMA_CTR1_PAM                        DMA_CTR1_PAM_Msk                        /*!< Padding / alignment mode */
#define DMA_CTR1_PAM_0                      DMA_CTR1_PAM                            /*!< Bit 0 */
#define DMA_CTR1_DDW_LOG2_Pos               (16U)
#define DMA_CTR1_DDW_LOG2_Msk               (0x3UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< 0x00030000 */
#define DMA_CTR1_DDW_LOG2                   DMA_CTR1_DDW_LOG2_Msk                   /*!< Binary logarithm of the
                                                                                         destination data width
                                                                                         of a burst */
#define DMA_CTR1_DDW_LOG2_0                 (0x1UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 0 */
#define DMA_CTR1_DDW_LOG2_1                 (0x2UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 1 */
#define DMA_CTR1_DINC_Pos                   (19U)
#define DMA_CTR1_DINC_Msk                   (0x1UL << DMA_CTR1_DINC_Pos)            /*!< 0x00080000 */
#define DMA_CTR1_DINC                       DMA_CTR1_DINC_Msk                       /*!< Destination incrementing
                                                                                        burst */

/* ************************************  Bit definition for DMA_CTR2 register  ************************************** */
#define DMA_CTR2_REQSEL_Pos                 (0U)
#define DMA_CTR2_REQSEL_Msk                 (0x7FUL << DMA_CTR2_REQSEL_Pos)         /*!< 0x0000007F */
#define DMA_CTR2_REQSEL                     DMA_CTR2_REQSEL_Msk                     /*!< DMA hardware request
                                                                                         selection */
#define DMA_CTR2_SWREQ_Pos                  (9U)
#define DMA_CTR2_SWREQ_Msk                  (0x1UL << DMA_CTR2_SWREQ_Pos)           /*!< 0x00000200 */
#define DMA_CTR2_SWREQ                      DMA_CTR2_SWREQ_Msk                      /*!< Software request */
#define DMA_CTR2_BREQ_Pos                   (11U)
#define DMA_CTR2_BREQ_Msk                   (0x1UL << DMA_CTR2_BREQ_Pos)            /*!< 0x00000800 */
#define DMA_CTR2_BREQ                       DMA_CTR2_BREQ_Msk                       /*!< Block hardware request */
#define DMA_CTR2_PFREQ_Pos                  (12U)
#define DMA_CTR2_PFREQ_Msk                  (0x1UL << DMA_CTR2_PFREQ_Pos)            /*!< 0x00001000 */
#define DMA_CTR2_PFREQ                      DMA_CTR2_PFREQ_Msk                       /*!< Hardware request in peripheral
                                                                                          flow control mode */
#define DMA_CTR2_TRIGM_Pos                  (14U)
#define DMA_CTR2_TRIGM_Msk                  (0x3UL << DMA_CTR2_TRIGM_Pos)           /*!< 0x0000C000 */
#define DMA_CTR2_TRIGM                      DMA_CTR2_TRIGM_Msk                      /*!< Trigger mode */
#define DMA_CTR2_TRIGM_0                    (0x1UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 0 */
#define DMA_CTR2_TRIGM_1                    (0x2UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 1 */
#define DMA_CTR2_TRIGSEL_Pos                (16U)
#define DMA_CTR2_TRIGSEL_Msk                (0x1FUL << DMA_CTR2_TRIGSEL_Pos)        /*!< 0x001F0000 */
#define DMA_CTR2_TRIGSEL                    DMA_CTR2_TRIGSEL_Msk                    /*!< Trigger event
                                                                                         input selection */
#define DMA_CTR2_TRIGPOL_Pos                (24U)
#define DMA_CTR2_TRIGPOL_Msk                (0x3UL << DMA_CTR2_TRIGPOL_Pos)         /*!< 0x03000000 */
#define DMA_CTR2_TRIGPOL                    DMA_CTR2_TRIGPOL_Msk                    /*!< Trigger event
                                                                                         polarity         */
#define DMA_CTR2_TRIGPOL_0                  (0x1UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 0 */
#define DMA_CTR2_TRIGPOL_1                  (0x2UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 1 */
#define DMA_CTR2_TCEM_Pos                   (30U)
#define DMA_CTR2_TCEM_Msk                   (0x3UL << DMA_CTR2_TCEM_Pos)            /*!< 0xC0000000 */
#define DMA_CTR2_TCEM                       DMA_CTR2_TCEM_Msk                       /*!< Transfer complete
                                                                                         event mode   */
#define DMA_CTR2_TCEM_0                     (0x1UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 0 */
#define DMA_CTR2_TCEM_1                     (0x2UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 1 */

/* ************************************  Bit definition for DMA_CBR1 register  ************************************** */
#define DMA_CBR1_BNDT_Pos                   (0U)
#define DMA_CBR1_BNDT_Msk                   (0xFFFFUL << DMA_CBR1_BNDT_Pos)         /*!< 0x0000FFFF */
#define DMA_CBR1_BNDT                       DMA_CBR1_BNDT_Msk                       /*!< Block number of data bytes
                                                                                         to transfer from the source */

/* ************************************  Bit definition for DMA_CSAR register  ************************************** */
#define DMA_CSAR_SA_Pos                     (0U)
#define DMA_CSAR_SA_Msk                     (0xFFFFFFFFUL << DMA_CSAR_SA_Pos)       /*!< 0xFFFFFFFF */
#define DMA_CSAR_SA                         DMA_CSAR_SA_Msk                         /*!< Source Address */

/* ************************************  Bit definition for DMA_CDAR register  ************************************** */
#define DMA_CDAR_DA_Pos                     (0U)
#define DMA_CDAR_DA_Msk                     (0xFFFFFFFFUL << DMA_CDAR_DA_Pos)       /*!< 0xFFFFFFFF */
#define DMA_CDAR_DA                         DMA_CDAR_DA_Msk                         /*!< Destination address */

/* ************************************  Bit definition for DMA_CLLR register  ************************************** */
#define DMA_CLLR_LA_Pos                     (2U)
#define DMA_CLLR_LA_Msk                     (0x3FFFUL << DMA_CLLR_LA_Pos)           /*!< 0x0000FFFC */
#define DMA_CLLR_LA                         DMA_CLLR_LA_Msk                         /*!< Pointer to the next
                                                                                         linked-list data structure */
#define DMA_CLLR_ULL_Pos                    (16U)
#define DMA_CLLR_ULL_Msk                    (0x1UL << DMA_CLLR_ULL_Pos)             /*!< 0x00010000 */
#define DMA_CLLR_ULL                        DMA_CLLR_ULL_Msk                        /*!< Update link address
                                                                                         register from memory */
#define DMA_CLLR_UDA_Pos                    (27U)
#define DMA_CLLR_UDA_Msk                    (0x1UL << DMA_CLLR_UDA_Pos)             /*!< 0x08000000 */
#define DMA_CLLR_UDA                        DMA_CLLR_UDA_Msk                        /*!< Update destination address
                                                                                         register from SRAM  */
#define DMA_CLLR_USA_Pos                    (28U)
#define DMA_CLLR_USA_Msk                    (0x1UL << DMA_CLLR_USA_Pos)             /*!< 0x10000000 */
#define DMA_CLLR_USA                        DMA_CLLR_USA_Msk                        /*!< Update source address
                                                                                         register from SRAM */
#define DMA_CLLR_UB1_Pos                    (29U)
#define DMA_CLLR_UB1_Msk                    (0x1UL << DMA_CLLR_UB1_Pos)             /*!< 0x20000000 */
#define DMA_CLLR_UB1                        DMA_CLLR_UB1_Msk                        /*!< Update block register 1
                                                                                         from SRAM */
#define DMA_CLLR_UT2_Pos                    (30U)
#define DMA_CLLR_UT2_Msk                    (0x1UL << DMA_CLLR_UT2_Pos)             /*!< 0x40000000 */
#define DMA_CLLR_UT2                        DMA_CLLR_UT2_Msk                        /*!< Update transfer register 2
                                                                                         from SRAM */
#define DMA_CLLR_UT1_Pos                    (31U)
#define DMA_CLLR_UT1_Msk                    (0x1UL << DMA_CLLR_UT1_Pos)             /*!< 0x80000000 */
#define DMA_CLLR_UT1                        DMA_CLLR_UT1_Msk                        /*!< Update transfer register 1
                                                                                         from SRAM  */

/**********************************************************************************************************************/
/*                                                                                                                    */
/*                               Extended interrupts and event controller (EXTI)                                      */
/*                                                                                                                    */
/**********************************************************************************************************************/
/* ************************************  Bit definition for EXTI_RTSR1 register  ************************************ */
#define EXTI_RTSR1_RT0_Pos        (0U)
#define EXTI_RTSR1_RT0_Msk        (0x1UL << EXTI_RTSR1_RT0_Pos)          /*!< 0x00000001 */
#define EXTI_RTSR1_RT0            EXTI_RTSR1_RT0_Msk                     /*!< Rising trigger event configuration bit of
                                                                              configurable event input 0 */
#define EXTI_RTSR1_RT1_Pos        (1U)
#define EXTI_RTSR1_RT1_Msk        (0x1UL << EXTI_RTSR1_RT1_Pos)          /*!< 0x00000002 */
#define EXTI_RTSR1_RT1            EXTI_RTSR1_RT1_Msk                     /*!< Rising trigger event configuration bit of
                                                                              configurable event input 1 */
#define EXTI_RTSR1_RT2_Pos        (2U)
#define EXTI_RTSR1_RT2_Msk        (0x1UL << EXTI_RTSR1_RT2_Pos)          /*!< 0x00000004 */
#define EXTI_RTSR1_RT2            EXTI_RTSR1_RT2_Msk                     /*!< Rising trigger event configuration bit of
                                                                              configurable event input 2 */
#define EXTI_RTSR1_RT3_Pos        (3U)
#define EXTI_RTSR1_RT3_Msk        (0x1UL << EXTI_RTSR1_RT3_Pos)          /*!< 0x00000008 */
#define EXTI_RTSR1_RT3            EXTI_RTSR1_RT3_Msk                     /*!< Rising trigger event configuration bit of
                                                                              configurable event input 3 */
#define EXTI_RTSR1_RT4_Pos        (4U)
#define EXTI_RTSR1_RT4_Msk        (0x1UL << EXTI_RTSR1_RT4_Pos)          /*!< 0x00000010 */
#define EXTI_RTSR1_RT4            EXTI_RTSR1_RT4_Msk                     /*!< Rising trigger event configuration bit of
                                                                              configurable event input 4 */
#define EXTI_RTSR1_RT5_Pos        (5U)
#define EXTI_RTSR1_RT5_Msk        (0x1UL << EXTI_RTSR1_RT5_Pos)          /*!< 0x00000020 */
#define EXTI_RTSR1_RT5            EXTI_RTSR1_RT5_Msk                     /*!< Rising trigger event configuration bit of
                                                                              configurable event input 5 */
#define EXTI_RTSR1_RT6_Pos        (6U)
#define EXTI_RTSR1_RT6_Msk        (0x1UL << EXTI_RTSR1_RT6_Pos)          /*!< 0x00000040 */
#define EXTI_RTSR1_RT6            EXTI_RTSR1_RT6_Msk                     /*!< Rising trigger event configuration bit of
                                                                              configurable event input 6 */
#define EXTI_RTSR1_RT7_Pos        (7U)
#define EXTI_RTSR1_RT7_Msk        (0x1UL << EXTI_RTSR1_RT7_Pos)          /*!< 0x00000080 */
#define EXTI_RTSR1_RT7            EXTI_RTSR1_RT7_Msk                     /*!< Rising trigger event configuration bit of
                                                                              configurable event input 7 */
#define EXTI_RTSR1_RT8_Pos        (8U)
#define EXTI_RTSR1_RT8_Msk        (0x1UL << EXTI_RTSR1_RT8_Pos)          /*!< 0x00000100 */
#define EXTI_RTSR1_RT8            EXTI_RTSR1_RT8_Msk                     /*!< Rising trigger event configuration bit of
                                                                              configurable event input 8 */
#define EXTI_RTSR1_RT9_Pos        (9U)
#define EXTI_RTSR1_RT9_Msk        (0x1UL << EXTI_RTSR1_RT9_Pos)          /*!< 0x00000200 */
#define EXTI_RTSR1_RT9            EXTI_RTSR1_RT9_Msk                     /*!< Rising trigger event configuration bit of
                                                                              configurable event input 9 */
#define EXTI_RTSR1_RT10_Pos       (10U)
#define EXTI_RTSR1_RT10_Msk       (0x1UL << EXTI_RTSR1_RT10_Pos)         /*!< 0x00000400 */
#define EXTI_RTSR1_RT10           EXTI_RTSR1_RT10_Msk                    /*!< Rising trigger event configuration bit of
                                                                              configurable event input 10 */
#define EXTI_RTSR1_RT11_Pos       (11U)
#define EXTI_RTSR1_RT11_Msk       (0x1UL << EXTI_RTSR1_RT11_Pos)         /*!< 0x00000800 */
#define EXTI_RTSR1_RT11           EXTI_RTSR1_RT11_Msk                    /*!< Rising trigger event configuration bit of
                                                                              configurable event input 11 */
#define EXTI_RTSR1_RT12_Pos       (12U)
#define EXTI_RTSR1_RT12_Msk       (0x1UL << EXTI_RTSR1_RT12_Pos)         /*!< 0x00001000 */
#define EXTI_RTSR1_RT12           EXTI_RTSR1_RT12_Msk                    /*!< Rising trigger event configuration bit of
                                                                              configurable event input 12 */
#define EXTI_RTSR1_RT13_Pos       (13U)
#define EXTI_RTSR1_RT13_Msk       (0x1UL << EXTI_RTSR1_RT13_Pos)         /*!< 0x00002000 */
#define EXTI_RTSR1_RT13           EXTI_RTSR1_RT13_Msk                    /*!< Rising trigger event configuration bit of
                                                                              configurable event input 13 */
#define EXTI_RTSR1_RT14_Pos       (14U)
#define EXTI_RTSR1_RT14_Msk       (0x1UL << EXTI_RTSR1_RT14_Pos)         /*!< 0x00004000 */
#define EXTI_RTSR1_RT14           EXTI_RTSR1_RT14_Msk                    /*!< Rising trigger event configuration bit of
                                                                              configurable event input 14 */
#define EXTI_RTSR1_RT15_Pos       (15U)
#define EXTI_RTSR1_RT15_Msk       (0x1UL << EXTI_RTSR1_RT15_Pos)         /*!< 0x00008000 */
#define EXTI_RTSR1_RT15           EXTI_RTSR1_RT15_Msk                    /*!< Rising trigger event configuration bit of
                                                                              configurable event input 15 */
#define EXTI_RTSR1_RT16_Pos       (16U)
#define EXTI_RTSR1_RT16_Msk       (0x1UL << EXTI_RTSR1_RT16_Pos)         /*!< 0x00010000 */
#define EXTI_RTSR1_RT16           EXTI_RTSR1_RT16_Msk                    /*!< Rising trigger event configuration bit of
                                                                              configurable event input 16 */

/* ************************************  Bit definition for EXTI_FTSR1 register  ************************************ */
#define EXTI_FTSR1_FT0_Pos        (0U)
#define EXTI_FTSR1_FT0_Msk        (0x1UL << EXTI_FTSR1_FT0_Pos)          /*!< 0x00000001 */
#define EXTI_FTSR1_FT0            EXTI_FTSR1_FT0_Msk                     /*!< Falling trigger event configuration bit of
                                                                              configurable event input 0 */
#define EXTI_FTSR1_FT1_Pos        (1U)
#define EXTI_FTSR1_FT1_Msk        (0x1UL << EXTI_FTSR1_FT1_Pos)          /*!< 0x00000002 */
#define EXTI_FTSR1_FT1            EXTI_FTSR1_FT1_Msk                     /*!< Falling trigger event configuration bit of
                                                                              configurable event input 1 */
#define EXTI_FTSR1_FT2_Pos        (2U)
#define EXTI_FTSR1_FT2_Msk        (0x1UL << EXTI_FTSR1_FT2_Pos)          /*!< 0x00000004 */
#define EXTI_FTSR1_FT2            EXTI_FTSR1_FT2_Msk                     /*!< Falling trigger event configuration bit of
                                                                              configurable event input 2 */
#define EXTI_FTSR1_FT3_Pos        (3U)
#define EXTI_FTSR1_FT3_Msk        (0x1UL << EXTI_FTSR1_FT3_Pos)          /*!< 0x00000008 */
#define EXTI_FTSR1_FT3            EXTI_FTSR1_FT3_Msk                     /*!< Falling trigger event configuration bit of
                                                                              configurable event input 3 */
#define EXTI_FTSR1_FT4_Pos        (4U)
#define EXTI_FTSR1_FT4_Msk        (0x1UL << EXTI_FTSR1_FT4_Pos)          /*!< 0x00000010 */
#define EXTI_FTSR1_FT4            EXTI_FTSR1_FT4_Msk                     /*!< Falling trigger event configuration bit of
                                                                              configurable event input 4 */
#define EXTI_FTSR1_FT5_Pos        (5U)
#define EXTI_FTSR1_FT5_Msk        (0x1UL << EXTI_FTSR1_FT5_Pos)          /*!< 0x00000020 */
#define EXTI_FTSR1_FT5            EXTI_FTSR1_FT5_Msk                     /*!< Falling trigger event configuration bit of
                                                                              configurable event input 5 */
#define EXTI_FTSR1_FT6_Pos        (6U)
#define EXTI_FTSR1_FT6_Msk        (0x1UL << EXTI_FTSR1_FT6_Pos)          /*!< 0x00000040 */
#define EXTI_FTSR1_FT6            EXTI_FTSR1_FT6_Msk                     /*!< Falling trigger event configuration bit of
                                                                              configurable event input 6 */
#define EXTI_FTSR1_FT7_Pos        (7U)
#define EXTI_FTSR1_FT7_Msk        (0x1UL << EXTI_FTSR1_FT7_Pos)          /*!< 0x00000080 */
#define EXTI_FTSR1_FT7            EXTI_FTSR1_FT7_Msk                     /*!< Falling trigger event configuration bit of
                                                                              configurable event input 7 */
#define EXTI_FTSR1_FT8_Pos        (8U)
#define EXTI_FTSR1_FT8_Msk        (0x1UL << EXTI_FTSR1_FT8_Pos)          /*!< 0x00000100 */
#define EXTI_FTSR1_FT8            EXTI_FTSR1_FT8_Msk                     /*!< Falling trigger event configuration bit of
                                                                              configurable event input 8 */
#define EXTI_FTSR1_FT9_Pos        (9U)
#define EXTI_FTSR1_FT9_Msk        (0x1UL << EXTI_FTSR1_FT9_Pos)          /*!< 0x00000200 */
#define EXTI_FTSR1_FT9            EXTI_FTSR1_FT9_Msk                     /*!< Falling trigger event configuration bit of
                                                                              configurable event input 9 */
#define EXTI_FTSR1_FT10_Pos       (10U)
#define EXTI_FTSR1_FT10_Msk       (0x1UL << EXTI_FTSR1_FT10_Pos)         /*!< 0x00000400 */
#define EXTI_FTSR1_FT10           EXTI_FTSR1_FT10_Msk                    /*!< Falling trigger event configuration bit of
                                                                              configurable event input 10 */
#define EXTI_FTSR1_FT11_Pos       (11U)
#define EXTI_FTSR1_FT11_Msk       (0x1UL << EXTI_FTSR1_FT11_Pos)         /*!< 0x00000800 */
#define EXTI_FTSR1_FT11           EXTI_FTSR1_FT11_Msk                    /*!< Falling trigger event configuration bit of
                                                                              configurable event input 11 */
#define EXTI_FTSR1_FT12_Pos       (12U)
#define EXTI_FTSR1_FT12_Msk       (0x1UL << EXTI_FTSR1_FT12_Pos)         /*!< 0x00001000 */
#define EXTI_FTSR1_FT12           EXTI_FTSR1_FT12_Msk                    /*!< Falling trigger event configuration bit of
                                                                              configurable event input 12 */
#define EXTI_FTSR1_FT13_Pos       (13U)
#define EXTI_FTSR1_FT13_Msk       (0x1UL << EXTI_FTSR1_FT13_Pos)         /*!< 0x00002000 */
#define EXTI_FTSR1_FT13           EXTI_FTSR1_FT13_Msk                    /*!< Falling trigger event configuration bit of
                                                                              configurable event input 13 */
#define EXTI_FTSR1_FT14_Pos       (14U)
#define EXTI_FTSR1_FT14_Msk       (0x1UL << EXTI_FTSR1_FT14_Pos)         /*!< 0x00004000 */
#define EXTI_FTSR1_FT14           EXTI_FTSR1_FT14_Msk                    /*!< Falling trigger event configuration bit of
                                                                              configurable event input 14 */
#define EXTI_FTSR1_FT15_Pos       (15U)
#define EXTI_FTSR1_FT15_Msk       (0x1UL << EXTI_FTSR1_FT15_Pos)         /*!< 0x00008000 */
#define EXTI_FTSR1_FT15           EXTI_FTSR1_FT15_Msk                    /*!< Falling trigger event configuration bit of
                                                                              configurable event input 15 */
#define EXTI_FTSR1_FT16_Pos       (16U)
#define EXTI_FTSR1_FT16_Msk       (0x1UL << EXTI_FTSR1_FT16_Pos)         /*!< 0x00010000 */
#define EXTI_FTSR1_FT16           EXTI_FTSR1_FT16_Msk                    /*!< Falling trigger event configuration bit of
                                                                              configurable event input 16 */

/* ***********************************  Bit definition for EXTI_SWIER1 register  ************************************ */
#define EXTI_SWIER1_SWI0_Pos      (0U)
#define EXTI_SWIER1_SWI0_Msk      (0x1UL << EXTI_SWIER1_SWI0_Pos)        /*!< 0x00000001 */
#define EXTI_SWIER1_SWI0          EXTI_SWIER1_SWI0_Msk                   /*!< Software interrupt on event 0 */
#define EXTI_SWIER1_SWI1_Pos      (1U)
#define EXTI_SWIER1_SWI1_Msk      (0x1UL << EXTI_SWIER1_SWI1_Pos)        /*!< 0x00000002 */
#define EXTI_SWIER1_SWI1          EXTI_SWIER1_SWI1_Msk                   /*!< Software interrupt on event 1 */
#define EXTI_SWIER1_SWI2_Pos      (2U)
#define EXTI_SWIER1_SWI2_Msk      (0x1UL << EXTI_SWIER1_SWI2_Pos)        /*!< 0x00000004 */
#define EXTI_SWIER1_SWI2          EXTI_SWIER1_SWI2_Msk                   /*!< Software interrupt on event 2 */
#define EXTI_SWIER1_SWI3_Pos      (3U)
#define EXTI_SWIER1_SWI3_Msk      (0x1UL << EXTI_SWIER1_SWI3_Pos)        /*!< 0x00000008 */
#define EXTI_SWIER1_SWI3          EXTI_SWIER1_SWI3_Msk                   /*!< Software interrupt on event 3 */
#define EXTI_SWIER1_SWI4_Pos      (4U)
#define EXTI_SWIER1_SWI4_Msk      (0x1UL << EXTI_SWIER1_SWI4_Pos)        /*!< 0x00000010 */
#define EXTI_SWIER1_SWI4          EXTI_SWIER1_SWI4_Msk                   /*!< Software interrupt on event 4 */
#define EXTI_SWIER1_SWI5_Pos      (5U)
#define EXTI_SWIER1_SWI5_Msk      (0x1UL << EXTI_SWIER1_SWI5_Pos)        /*!< 0x00000020 */
#define EXTI_SWIER1_SWI5          EXTI_SWIER1_SWI5_Msk                   /*!< Software interrupt on event 5 */
#define EXTI_SWIER1_SWI6_Pos      (6U)
#define EXTI_SWIER1_SWI6_Msk      (0x1UL << EXTI_SWIER1_SWI6_Pos)        /*!< 0x00000040 */
#define EXTI_SWIER1_SWI6          EXTI_SWIER1_SWI6_Msk                   /*!< Software interrupt on event 6 */
#define EXTI_SWIER1_SWI7_Pos      (7U)
#define EXTI_SWIER1_SWI7_Msk      (0x1UL << EXTI_SWIER1_SWI7_Pos)        /*!< 0x00000080 */
#define EXTI_SWIER1_SWI7          EXTI_SWIER1_SWI7_Msk                   /*!< Software interrupt on event 7 */
#define EXTI_SWIER1_SWI8_Pos      (8U)
#define EXTI_SWIER1_SWI8_Msk      (0x1UL << EXTI_SWIER1_SWI8_Pos)        /*!< 0x00000100 */
#define EXTI_SWIER1_SWI8          EXTI_SWIER1_SWI8_Msk                   /*!< Software interrupt on event 8 */
#define EXTI_SWIER1_SWI9_Pos      (9U)
#define EXTI_SWIER1_SWI9_Msk      (0x1UL << EXTI_SWIER1_SWI9_Pos)        /*!< 0x00000200 */
#define EXTI_SWIER1_SWI9          EXTI_SWIER1_SWI9_Msk                   /*!< Software interrupt on event 9 */
#define EXTI_SWIER1_SWI10_Pos     (10U)
#define EXTI_SWIER1_SWI10_Msk     (0x1UL << EXTI_SWIER1_SWI10_Pos)       /*!< 0x00000400 */
#define EXTI_SWIER1_SWI10         EXTI_SWIER1_SWI10_Msk                  /*!< Software interrupt on event 10 */
#define EXTI_SWIER1_SWI11_Pos     (11U)
#define EXTI_SWIER1_SWI11_Msk     (0x1UL << EXTI_SWIER1_SWI11_Pos)       /*!< 0x00000800 */
#define EXTI_SWIER1_SWI11         EXTI_SWIER1_SWI11_Msk                  /*!< Software interrupt on event 11 */
#define EXTI_SWIER1_SWI12_Pos     (12U)
#define EXTI_SWIER1_SWI12_Msk     (0x1UL << EXTI_SWIER1_SWI12_Pos)       /*!< 0x00001000 */
#define EXTI_SWIER1_SWI12         EXTI_SWIER1_SWI12_Msk                  /*!< Software interrupt on event 12 */
#define EXTI_SWIER1_SWI13_Pos     (13U)
#define EXTI_SWIER1_SWI13_Msk     (0x1UL << EXTI_SWIER1_SWI13_Pos)       /*!< 0x00002000 */
#define EXTI_SWIER1_SWI13         EXTI_SWIER1_SWI13_Msk                  /*!< Software interrupt on event 13 */
#define EXTI_SWIER1_SWI14_Pos     (14U)
#define EXTI_SWIER1_SWI14_Msk     (0x1UL << EXTI_SWIER1_SWI14_Pos)       /*!< 0x00004000 */
#define EXTI_SWIER1_SWI14         EXTI_SWIER1_SWI14_Msk                  /*!< Software interrupt on event 14 */
#define EXTI_SWIER1_SWI15_Pos     (15U)
#define EXTI_SWIER1_SWI15_Msk     (0x1UL << EXTI_SWIER1_SWI15_Pos)       /*!< 0x00008000 */
#define EXTI_SWIER1_SWI15         EXTI_SWIER1_SWI15_Msk                  /*!< Software interrupt on event 15 */
#define EXTI_SWIER1_SWI16_Pos     (16U)
#define EXTI_SWIER1_SWI16_Msk     (0x1UL << EXTI_SWIER1_SWI16_Pos)       /*!< 0x00010000 */
#define EXTI_SWIER1_SWI16         EXTI_SWIER1_SWI16_Msk                  /*!< Software interrupt on event 16 */

/* ************************************  Bit definition for EXTI_RPR1 register  ************************************* */
#define EXTI_RPR1_RPIF0_Pos       (0U)
#define EXTI_RPR1_RPIF0_Msk       (0x1UL << EXTI_RPR1_RPIF0_Pos)         /*!< 0x00000001 */
#define EXTI_RPR1_RPIF0           EXTI_RPR1_RPIF0_Msk                    /*!< configurable event input 0 rising edge
                                                                              pending bit */
#define EXTI_RPR1_RPIF1_Pos       (1U)
#define EXTI_RPR1_RPIF1_Msk       (0x1UL << EXTI_RPR1_RPIF1_Pos)         /*!< 0x00000002 */
#define EXTI_RPR1_RPIF1           EXTI_RPR1_RPIF1_Msk                    /*!< configurable event input 1 rising edge
                                                                              pending bit */
#define EXTI_RPR1_RPIF2_Pos       (2U)
#define EXTI_RPR1_RPIF2_Msk       (0x1UL << EXTI_RPR1_RPIF2_Pos)         /*!< 0x00000004 */
#define EXTI_RPR1_RPIF2           EXTI_RPR1_RPIF2_Msk                    /*!< configurable event input 2 rising edge
                                                                              pending bit */
#define EXTI_RPR1_RPIF3_Pos       (3U)
#define EXTI_RPR1_RPIF3_Msk       (0x1UL << EXTI_RPR1_RPIF3_Pos)         /*!< 0x00000008 */
#define EXTI_RPR1_RPIF3           EXTI_RPR1_RPIF3_Msk                    /*!< configurable event input 3 rising edge
                                                                              pending bit */
#define EXTI_RPR1_RPIF4_Pos       (4U)
#define EXTI_RPR1_RPIF4_Msk       (0x1UL << EXTI_RPR1_RPIF4_Pos)         /*!< 0x00000010 */
#define EXTI_RPR1_RPIF4           EXTI_RPR1_RPIF4_Msk                    /*!< configurable event input 4 rising edge
                                                                              pending bit */
#define EXTI_RPR1_RPIF5_Pos       (5U)
#define EXTI_RPR1_RPIF5_Msk       (0x1UL << EXTI_RPR1_RPIF5_Pos)         /*!< 0x00000020 */
#define EXTI_RPR1_RPIF5           EXTI_RPR1_RPIF5_Msk                    /*!< configurable event input 5 rising edge
                                                                              pending bit */
#define EXTI_RPR1_RPIF6_Pos       (6U)
#define EXTI_RPR1_RPIF6_Msk       (0x1UL << EXTI_RPR1_RPIF6_Pos)         /*!< 0x00000040 */
#define EXTI_RPR1_RPIF6           EXTI_RPR1_RPIF6_Msk                    /*!< configurable event input 6 rising edge
                                                                              pending bit */
#define EXTI_RPR1_RPIF7_Pos       (7U)
#define EXTI_RPR1_RPIF7_Msk       (0x1UL << EXTI_RPR1_RPIF7_Pos)         /*!< 0x00000080 */
#define EXTI_RPR1_RPIF7           EXTI_RPR1_RPIF7_Msk                    /*!< configurable event input 7 rising edge
                                                                              pending bit */
#define EXTI_RPR1_RPIF8_Pos       (8U)
#define EXTI_RPR1_RPIF8_Msk       (0x1UL << EXTI_RPR1_RPIF8_Pos)         /*!< 0x00000100 */
#define EXTI_RPR1_RPIF8           EXTI_RPR1_RPIF8_Msk                    /*!< configurable event input 8 rising edge
                                                                              pending bit */
#define EXTI_RPR1_RPIF9_Pos       (9U)
#define EXTI_RPR1_RPIF9_Msk       (0x1UL << EXTI_RPR1_RPIF9_Pos)         /*!< 0x00000200 */
#define EXTI_RPR1_RPIF9           EXTI_RPR1_RPIF9_Msk                    /*!< configurable event input 9 rising edge
                                                                              pending bit */
#define EXTI_RPR1_RPIF10_Pos      (10U)
#define EXTI_RPR1_RPIF10_Msk      (0x1UL << EXTI_RPR1_RPIF10_Pos)        /*!< 0x00000400 */
#define EXTI_RPR1_RPIF10          EXTI_RPR1_RPIF10_Msk                   /*!< configurable event input 10 rising edge
                                                                              pending bit */
#define EXTI_RPR1_RPIF11_Pos      (11U)
#define EXTI_RPR1_RPIF11_Msk      (0x1UL << EXTI_RPR1_RPIF11_Pos)        /*!< 0x00000800 */
#define EXTI_RPR1_RPIF11          EXTI_RPR1_RPIF11_Msk                   /*!< configurable event input 11 rising edge
                                                                              pending bit */
#define EXTI_RPR1_RPIF12_Pos      (12U)
#define EXTI_RPR1_RPIF12_Msk      (0x1UL << EXTI_RPR1_RPIF12_Pos)        /*!< 0x00001000 */
#define EXTI_RPR1_RPIF12          EXTI_RPR1_RPIF12_Msk                   /*!< configurable event input 12 rising edge
                                                                              pending bit */
#define EXTI_RPR1_RPIF13_Pos      (13U)
#define EXTI_RPR1_RPIF13_Msk      (0x1UL << EXTI_RPR1_RPIF13_Pos)        /*!< 0x00002000 */
#define EXTI_RPR1_RPIF13          EXTI_RPR1_RPIF13_Msk                   /*!< configurable event input 13 rising edge
                                                                              pending bit */
#define EXTI_RPR1_RPIF14_Pos      (14U)
#define EXTI_RPR1_RPIF14_Msk      (0x1UL << EXTI_RPR1_RPIF14_Pos)        /*!< 0x00004000 */
#define EXTI_RPR1_RPIF14          EXTI_RPR1_RPIF14_Msk                   /*!< configurable event input 14 rising edge
                                                                              pending bit */
#define EXTI_RPR1_RPIF15_Pos      (15U)
#define EXTI_RPR1_RPIF15_Msk      (0x1UL << EXTI_RPR1_RPIF15_Pos)        /*!< 0x00008000 */
#define EXTI_RPR1_RPIF15          EXTI_RPR1_RPIF15_Msk                   /*!< configurable event input 15 rising edge
                                                                              pending bit */
#define EXTI_RPR1_RPIF16_Pos      (16U)
#define EXTI_RPR1_RPIF16_Msk      (0x1UL << EXTI_RPR1_RPIF16_Pos)        /*!< 0x00010000 */
#define EXTI_RPR1_RPIF16          EXTI_RPR1_RPIF16_Msk                   /*!< configurable event input 16 rising edge
                                                                              pending bit */

/* ************************************  Bit definition for EXTI_FPR1 register  ************************************* */
#define EXTI_FPR1_FPIF0_Pos       (0U)
#define EXTI_FPR1_FPIF0_Msk       (0x1UL << EXTI_FPR1_FPIF0_Pos)         /*!< 0x00000001 */
#define EXTI_FPR1_FPIF0           EXTI_FPR1_FPIF0_Msk                    /*!< configurable event input 0 falling edge
                                                                              pending bit */
#define EXTI_FPR1_FPIF1_Pos       (1U)
#define EXTI_FPR1_FPIF1_Msk       (0x1UL << EXTI_FPR1_FPIF1_Pos)         /*!< 0x00000002 */
#define EXTI_FPR1_FPIF1           EXTI_FPR1_FPIF1_Msk                    /*!< configurable event input 1 falling edge
                                                                              pending bit */
#define EXTI_FPR1_FPIF2_Pos       (2U)
#define EXTI_FPR1_FPIF2_Msk       (0x1UL << EXTI_FPR1_FPIF2_Pos)         /*!< 0x00000004 */
#define EXTI_FPR1_FPIF2           EXTI_FPR1_FPIF2_Msk                    /*!< configurable event input 2 falling edge
                                                                              pending bit */
#define EXTI_FPR1_FPIF3_Pos       (3U)
#define EXTI_FPR1_FPIF3_Msk       (0x1UL << EXTI_FPR1_FPIF3_Pos)         /*!< 0x00000008 */
#define EXTI_FPR1_FPIF3           EXTI_FPR1_FPIF3_Msk                    /*!< configurable event input 3 falling edge
                                                                              pending bit */
#define EXTI_FPR1_FPIF4_Pos       (4U)
#define EXTI_FPR1_FPIF4_Msk       (0x1UL << EXTI_FPR1_FPIF4_Pos)         /*!< 0x00000010 */
#define EXTI_FPR1_FPIF4           EXTI_FPR1_FPIF4_Msk                    /*!< configurable event input 4 falling edge
                                                                              pending bit */
#define EXTI_FPR1_FPIF5_Pos       (5U)
#define EXTI_FPR1_FPIF5_Msk       (0x1UL << EXTI_FPR1_FPIF5_Pos)         /*!< 0x00000020 */
#define EXTI_FPR1_FPIF5           EXTI_FPR1_FPIF5_Msk                    /*!< configurable event input 5 falling edge
                                                                              pending bit */
#define EXTI_FPR1_FPIF6_Pos       (6U)
#define EXTI_FPR1_FPIF6_Msk       (0x1UL << EXTI_FPR1_FPIF6_Pos)         /*!< 0x00000040 */
#define EXTI_FPR1_FPIF6           EXTI_FPR1_FPIF6_Msk                    /*!< configurable event input 6 falling edge
                                                                              pending bit */
#define EXTI_FPR1_FPIF7_Pos       (7U)
#define EXTI_FPR1_FPIF7_Msk       (0x1UL << EXTI_FPR1_FPIF7_Pos)         /*!< 0x00000080 */
#define EXTI_FPR1_FPIF7           EXTI_FPR1_FPIF7_Msk                    /*!< configurable event input 7 falling edge
                                                                              pending bit */
#define EXTI_FPR1_FPIF8_Pos       (8U)
#define EXTI_FPR1_FPIF8_Msk       (0x1UL << EXTI_FPR1_FPIF8_Pos)         /*!< 0x00000100 */
#define EXTI_FPR1_FPIF8           EXTI_FPR1_FPIF8_Msk                    /*!< configurable event input 8 falling edge
                                                                              pending bit */
#define EXTI_FPR1_FPIF9_Pos       (9U)
#define EXTI_FPR1_FPIF9_Msk       (0x1UL << EXTI_FPR1_FPIF9_Pos)         /*!< 0x00000200 */
#define EXTI_FPR1_FPIF9           EXTI_FPR1_FPIF9_Msk                    /*!< configurable event input 9 falling edge
                                                                              pending bit */
#define EXTI_FPR1_FPIF10_Pos      (10U)
#define EXTI_FPR1_FPIF10_Msk      (0x1UL << EXTI_FPR1_FPIF10_Pos)        /*!< 0x00000400 */
#define EXTI_FPR1_FPIF10          EXTI_FPR1_FPIF10_Msk                   /*!< configurable event input 10 falling edge
                                                                              pending bit */
#define EXTI_FPR1_FPIF11_Pos      (11U)
#define EXTI_FPR1_FPIF11_Msk      (0x1UL << EXTI_FPR1_FPIF11_Pos)        /*!< 0x00000800 */
#define EXTI_FPR1_FPIF11          EXTI_FPR1_FPIF11_Msk                   /*!< configurable event input 11 falling edge
                                                                              pending bit */
#define EXTI_FPR1_FPIF12_Pos      (12U)
#define EXTI_FPR1_FPIF12_Msk      (0x1UL << EXTI_FPR1_FPIF12_Pos)        /*!< 0x00001000 */
#define EXTI_FPR1_FPIF12          EXTI_FPR1_FPIF12_Msk                   /*!< configurable event input 12 falling edge
                                                                              pending bit */
#define EXTI_FPR1_FPIF13_Pos      (13U)
#define EXTI_FPR1_FPIF13_Msk      (0x1UL << EXTI_FPR1_FPIF13_Pos)        /*!< 0x00002000 */
#define EXTI_FPR1_FPIF13          EXTI_FPR1_FPIF13_Msk                   /*!< configurable event input 13 falling edge
                                                                              pending bit */
#define EXTI_FPR1_FPIF14_Pos      (14U)
#define EXTI_FPR1_FPIF14_Msk      (0x1UL << EXTI_FPR1_FPIF14_Pos)        /*!< 0x00004000 */
#define EXTI_FPR1_FPIF14          EXTI_FPR1_FPIF14_Msk                   /*!< configurable event input 14 falling edge
                                                                              pending bit */
#define EXTI_FPR1_FPIF15_Pos      (15U)
#define EXTI_FPR1_FPIF15_Msk      (0x1UL << EXTI_FPR1_FPIF15_Pos)        /*!< 0x00008000 */
#define EXTI_FPR1_FPIF15          EXTI_FPR1_FPIF15_Msk                   /*!< configurable event input 15 falling edge
                                                                              pending bit */
#define EXTI_FPR1_FPIF16_Pos      (16U)
#define EXTI_FPR1_FPIF16_Msk      (0x1UL << EXTI_FPR1_FPIF16_Pos)        /*!< 0x00010000 */
#define EXTI_FPR1_FPIF16          EXTI_FPR1_FPIF16_Msk                   /*!< configurable event input 16 falling edge
                                                                              pending bit */

/* **********************************  Bit definition for EXTI_PRIVCFGR1 register  ********************************** */
#define EXTI_PRIVCFGR1_PRIV0_Pos  (0U)
#define EXTI_PRIVCFGR1_PRIV0_Msk  (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos)    /*!< 0x00000001 */
#define EXTI_PRIVCFGR1_PRIV0      EXTI_PRIVCFGR1_PRIV0_Msk               /*!< Privilege enable on event input 0 */
#define EXTI_PRIVCFGR1_PRIV1_Pos  (1U)
#define EXTI_PRIVCFGR1_PRIV1_Msk  (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos)    /*!< 0x00000002 */
#define EXTI_PRIVCFGR1_PRIV1      EXTI_PRIVCFGR1_PRIV1_Msk               /*!< Privilege enable on event input 1 */
#define EXTI_PRIVCFGR1_PRIV2_Pos  (2U)
#define EXTI_PRIVCFGR1_PRIV2_Msk  (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos)    /*!< 0x00000004 */
#define EXTI_PRIVCFGR1_PRIV2      EXTI_PRIVCFGR1_PRIV2_Msk               /*!< Privilege enable on event input 2 */
#define EXTI_PRIVCFGR1_PRIV3_Pos  (3U)
#define EXTI_PRIVCFGR1_PRIV3_Msk  (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos)    /*!< 0x00000008 */
#define EXTI_PRIVCFGR1_PRIV3      EXTI_PRIVCFGR1_PRIV3_Msk               /*!< Privilege enable on event input 3 */
#define EXTI_PRIVCFGR1_PRIV4_Pos  (4U)
#define EXTI_PRIVCFGR1_PRIV4_Msk  (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos)    /*!< 0x00000010 */
#define EXTI_PRIVCFGR1_PRIV4      EXTI_PRIVCFGR1_PRIV4_Msk               /*!< Privilege enable on event input 4 */
#define EXTI_PRIVCFGR1_PRIV5_Pos  (5U)
#define EXTI_PRIVCFGR1_PRIV5_Msk  (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos)    /*!< 0x00000020 */
#define EXTI_PRIVCFGR1_PRIV5      EXTI_PRIVCFGR1_PRIV5_Msk               /*!< Privilege enable on event input 5 */
#define EXTI_PRIVCFGR1_PRIV6_Pos  (6U)
#define EXTI_PRIVCFGR1_PRIV6_Msk  (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos)    /*!< 0x00000040 */
#define EXTI_PRIVCFGR1_PRIV6      EXTI_PRIVCFGR1_PRIV6_Msk               /*!< Privilege enable on event input 6 */
#define EXTI_PRIVCFGR1_PRIV7_Pos  (7U)
#define EXTI_PRIVCFGR1_PRIV7_Msk  (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos)    /*!< 0x00000080 */
#define EXTI_PRIVCFGR1_PRIV7      EXTI_PRIVCFGR1_PRIV7_Msk               /*!< Privilege enable on event input 7 */
#define EXTI_PRIVCFGR1_PRIV8_Pos  (8U)
#define EXTI_PRIVCFGR1_PRIV8_Msk  (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos)    /*!< 0x00000100 */
#define EXTI_PRIVCFGR1_PRIV8      EXTI_PRIVCFGR1_PRIV8_Msk               /*!< Privilege enable on event input 8 */
#define EXTI_PRIVCFGR1_PRIV9_Pos  (9U)
#define EXTI_PRIVCFGR1_PRIV9_Msk  (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos)    /*!< 0x00000200 */
#define EXTI_PRIVCFGR1_PRIV9      EXTI_PRIVCFGR1_PRIV9_Msk               /*!< Privilege enable on event input 9 */
#define EXTI_PRIVCFGR1_PRIV10_Pos (10U)
#define EXTI_PRIVCFGR1_PRIV10_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos)   /*!< 0x00000400 */
#define EXTI_PRIVCFGR1_PRIV10     EXTI_PRIVCFGR1_PRIV10_Msk              /*!< Privilege enable on event input 10 */
#define EXTI_PRIVCFGR1_PRIV11_Pos (11U)
#define EXTI_PRIVCFGR1_PRIV11_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos)   /*!< 0x00000800 */
#define EXTI_PRIVCFGR1_PRIV11     EXTI_PRIVCFGR1_PRIV11_Msk              /*!< Privilege enable on event input 11 */
#define EXTI_PRIVCFGR1_PRIV12_Pos (12U)
#define EXTI_PRIVCFGR1_PRIV12_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos)   /*!< 0x00001000 */
#define EXTI_PRIVCFGR1_PRIV12     EXTI_PRIVCFGR1_PRIV12_Msk              /*!< Privilege enable on event input 12 */
#define EXTI_PRIVCFGR1_PRIV13_Pos (13U)
#define EXTI_PRIVCFGR1_PRIV13_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos)   /*!< 0x00002000 */
#define EXTI_PRIVCFGR1_PRIV13     EXTI_PRIVCFGR1_PRIV13_Msk              /*!< Privilege enable on event input 13 */
#define EXTI_PRIVCFGR1_PRIV14_Pos (14U)
#define EXTI_PRIVCFGR1_PRIV14_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos)   /*!< 0x00004000 */
#define EXTI_PRIVCFGR1_PRIV14     EXTI_PRIVCFGR1_PRIV14_Msk              /*!< Privilege enable on event input 14 */
#define EXTI_PRIVCFGR1_PRIV15_Pos (15U)
#define EXTI_PRIVCFGR1_PRIV15_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos)   /*!< 0x00008000 */
#define EXTI_PRIVCFGR1_PRIV15     EXTI_PRIVCFGR1_PRIV15_Msk              /*!< Privilege enable on event input 15 */
#define EXTI_PRIVCFGR1_PRIV16_Pos (16U)
#define EXTI_PRIVCFGR1_PRIV16_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV16_Pos)   /*!< 0x00010000 */
#define EXTI_PRIVCFGR1_PRIV16     EXTI_PRIVCFGR1_PRIV16_Msk              /*!< Privilege enable on event input 16 */
#define EXTI_PRIVCFGR1_PRIV17_Pos (17U)
#define EXTI_PRIVCFGR1_PRIV17_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos)   /*!< 0x00020000 */
#define EXTI_PRIVCFGR1_PRIV17     EXTI_PRIVCFGR1_PRIV17_Msk              /*!< Privilege enable on event input 17 */
#define EXTI_PRIVCFGR1_PRIV18_Pos (18U)
#define EXTI_PRIVCFGR1_PRIV18_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos)   /*!< 0x00040000 */
#define EXTI_PRIVCFGR1_PRIV18     EXTI_PRIVCFGR1_PRIV18_Msk              /*!< Privilege enable on event input 18 */
#define EXTI_PRIVCFGR1_PRIV19_Pos (19U)
#define EXTI_PRIVCFGR1_PRIV19_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV19_Pos)   /*!< 0x00080000 */
#define EXTI_PRIVCFGR1_PRIV19     EXTI_PRIVCFGR1_PRIV19_Msk              /*!< Privilege enable on event input 19 */
#define EXTI_PRIVCFGR1_PRIV20_Pos (20U)
#define EXTI_PRIVCFGR1_PRIV20_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV20_Pos)   /*!< 0x00100000 */
#define EXTI_PRIVCFGR1_PRIV20     EXTI_PRIVCFGR1_PRIV20_Msk              /*!< Privilege enable on event input 20 */
#define EXTI_PRIVCFGR1_PRIV21_Pos (21U)
#define EXTI_PRIVCFGR1_PRIV21_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV21_Pos)   /*!< 0x00200000 */
#define EXTI_PRIVCFGR1_PRIV21     EXTI_PRIVCFGR1_PRIV21_Msk              /*!< Privilege enable on event input 21 */
#define EXTI_PRIVCFGR1_PRIV22_Pos (22U)
#define EXTI_PRIVCFGR1_PRIV22_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV22_Pos)   /*!< 0x00400000 */
#define EXTI_PRIVCFGR1_PRIV22     EXTI_PRIVCFGR1_PRIV22_Msk              /*!< Privilege enable on event input 22 */
#define EXTI_PRIVCFGR1_PRIV23_Pos (23U)
#define EXTI_PRIVCFGR1_PRIV23_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV23_Pos)   /*!< 0x00800000 */
#define EXTI_PRIVCFGR1_PRIV23     EXTI_PRIVCFGR1_PRIV23_Msk              /*!< Privilege enable on event input 23 */
#define EXTI_PRIVCFGR1_PRIV24_Pos (24U)
#define EXTI_PRIVCFGR1_PRIV24_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV24_Pos)   /*!< 0x01000000 */
#define EXTI_PRIVCFGR1_PRIV24     EXTI_PRIVCFGR1_PRIV24_Msk              /*!< Privilege enable on event input 24 */
#define EXTI_PRIVCFGR1_PRIV25_Pos (25U)
#define EXTI_PRIVCFGR1_PRIV25_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV25_Pos)   /*!< 0x02000000 */
#define EXTI_PRIVCFGR1_PRIV25     EXTI_PRIVCFGR1_PRIV25_Msk              /*!< Privilege enable on event input 25 */
#define EXTI_PRIVCFGR1_PRIV26_Pos (26U)
#define EXTI_PRIVCFGR1_PRIV26_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV26_Pos)   /*!< 0x04000000 */
#define EXTI_PRIVCFGR1_PRIV26     EXTI_PRIVCFGR1_PRIV26_Msk              /*!< Privilege enable on event input 26 */
#define EXTI_PRIVCFGR1_PRIV27_Pos (27U)
#define EXTI_PRIVCFGR1_PRIV27_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV27_Pos)   /*!< 0x08000000 */
#define EXTI_PRIVCFGR1_PRIV27     EXTI_PRIVCFGR1_PRIV27_Msk              /*!< Privilege enable on event input 27 */
#define EXTI_PRIVCFGR1_PRIV28_Pos (28U)
#define EXTI_PRIVCFGR1_PRIV28_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV28_Pos)   /*!< 0x10000000 */
#define EXTI_PRIVCFGR1_PRIV28     EXTI_PRIVCFGR1_PRIV28_Msk              /*!< Privilege enable on event input 28 */
#define EXTI_PRIVCFGR1_PRIV29_Pos (29U)
#define EXTI_PRIVCFGR1_PRIV29_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV29_Pos)   /*!< 0x20000000 */
#define EXTI_PRIVCFGR1_PRIV29     EXTI_PRIVCFGR1_PRIV29_Msk              /*!< Privilege enable on event input 29 */
#define EXTI_PRIVCFGR1_PRIV30_Pos (30U)
#define EXTI_PRIVCFGR1_PRIV30_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV30_Pos)   /*!< 0x40000000 */
#define EXTI_PRIVCFGR1_PRIV30     EXTI_PRIVCFGR1_PRIV30_Msk              /*!< Privilege enable on event input 30 */
#define EXTI_PRIVCFGR1_PRIV31_Pos (31U)
#define EXTI_PRIVCFGR1_PRIV31_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV31_Pos)   /*!< 0x80000000 */
#define EXTI_PRIVCFGR1_PRIV31     EXTI_PRIVCFGR1_PRIV31_Msk              /*!< Privilege enable on event input 31 */

/* ************************************  Bit definition for EXTI_RTSR2 register  ************************************ */
#define EXTI_RTSR2_RT34_Pos       (2U)
#define EXTI_RTSR2_RT34_Msk       (0x1UL << EXTI_RTSR2_RT34_Pos)         /*!< 0x00000004 */
#define EXTI_RTSR2_RT34           EXTI_RTSR2_RT34_Msk                    /*!< Rising trigger event configuration bit of
                                                                              configurable event input 34 */

/* ************************************  Bit definition for EXTI_FTSR2 register  ************************************ */
#define EXTI_FTSR2_FT34_Pos       (2U)
#define EXTI_FTSR2_FT34_Msk       (0x1UL << EXTI_FTSR2_FT34_Pos)         /*!< 0x00000004 */
#define EXTI_FTSR2_FT34           EXTI_FTSR2_FT34_Msk                    /*!< Falling trigger event configuration bit of
                                                                              configurable event input 34 */

/* ***********************************  Bit definition for EXTI_SWIER2 register  ************************************ */
#define EXTI_SWIER2_SWI34_Pos     (2U)
#define EXTI_SWIER2_SWI34_Msk     (0x1UL << EXTI_SWIER2_SWI34_Pos)       /*!< 0x00000004 */
#define EXTI_SWIER2_SWI34         EXTI_SWIER2_SWI34_Msk                  /*!< Software Interrupt on event 34 */

/* ************************************  Bit definition for EXTI_RPR2 register  ************************************* */
#define EXTI_RPR2_RPIF34_Pos      (2U)
#define EXTI_RPR2_RPIF34_Msk      (0x1UL << EXTI_RPR2_RPIF34_Pos)        /*!< 0x00000004 */
#define EXTI_RPR2_RPIF34          EXTI_RPR2_RPIF34_Msk                   /*!< configurable event inputs 34 rising edge
                                                                              pending bit */

/* ************************************  Bit definition for EXTI_FPR2 register  ************************************* */
#define EXTI_FPR2_FPIF34_Pos      (2U)
#define EXTI_FPR2_FPIF34_Msk      (0x1UL << EXTI_FPR2_FPIF34_Pos)        /*!< 0x00000004 */
#define EXTI_FPR2_FPIF34          EXTI_FPR2_FPIF34_Msk                   /*!< configurable event inputs 34 falling edge
                                                                              pending bit */

/* **********************************  Bit definition for EXTI_PRIVCFGR2 register  ********************************** */
#define EXTI_PRIVCFGR2_PRIV32_Pos (0U)
#define EXTI_PRIVCFGR2_PRIV32_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV32_Pos)   /*!< 0x00000001 */
#define EXTI_PRIVCFGR2_PRIV32     EXTI_PRIVCFGR2_PRIV32_Msk              /*!< Privilege enable on event input 32 */
#define EXTI_PRIVCFGR2_PRIV33_Pos (1U)
#define EXTI_PRIVCFGR2_PRIV33_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV33_Pos)   /*!< 0x00000002 */
#define EXTI_PRIVCFGR2_PRIV33     EXTI_PRIVCFGR2_PRIV33_Msk              /*!< Privilege enable on event input 33 */
#define EXTI_PRIVCFGR2_PRIV34_Pos (2U)
#define EXTI_PRIVCFGR2_PRIV34_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV34_Pos)   /*!< 0x00000004 */
#define EXTI_PRIVCFGR2_PRIV34     EXTI_PRIVCFGR2_PRIV34_Msk              /*!< Privilege enable on event input 34 */
#define EXTI_PRIVCFGR2_PRIV35_Pos (3U)
#define EXTI_PRIVCFGR2_PRIV35_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV35_Pos)   /*!< 0x00000008 */
#define EXTI_PRIVCFGR2_PRIV35     EXTI_PRIVCFGR2_PRIV35_Msk              /*!< Privilege enable on event input 35 */

/* ***********************************  Bit definition for EXTI_EXTICR1 register  *********************************** */
#define EXTI_EXTICR1_EXTI0_Pos    (0U)
#define EXTI_EXTICR1_EXTI0_Msk    (0xFFUL << EXTI_EXTICR1_EXTI0_Pos)     /*!< 0x000000FF */
#define EXTI_EXTICR1_EXTI0        EXTI_EXTICR1_EXTI0_Msk                 /*!< EXTI0 GPIO port selection */
#define EXTI_EXTICR1_EXTI0_0      (0x1UL << EXTI_EXTICR1_EXTI0_Pos)      /*!< 0x00000001 */
#define EXTI_EXTICR1_EXTI0_1      (0x2UL << EXTI_EXTICR1_EXTI0_Pos)      /*!< 0x00000002 */
#define EXTI_EXTICR1_EXTI0_2      (0x4UL << EXTI_EXTICR1_EXTI0_Pos)      /*!< 0x00000004 */
#define EXTI_EXTICR1_EXTI0_3      (0x8UL << EXTI_EXTICR1_EXTI0_Pos)      /*!< 0x00000008 */
#define EXTI_EXTICR1_EXTI1_Pos    (8U)
#define EXTI_EXTICR1_EXTI1_Msk    (0xFFUL << EXTI_EXTICR1_EXTI1_Pos)     /*!< 0x0000FF00 */
#define EXTI_EXTICR1_EXTI1        EXTI_EXTICR1_EXTI1_Msk                 /*!< EXTI1 GPIO port selection */
#define EXTI_EXTICR1_EXTI1_0      (0x1UL << EXTI_EXTICR1_EXTI1_Pos)      /*!< 0x00000100 */
#define EXTI_EXTICR1_EXTI1_1      (0x2UL << EXTI_EXTICR1_EXTI1_Pos)      /*!< 0x00000200 */
#define EXTI_EXTICR1_EXTI1_2      (0x4UL << EXTI_EXTICR1_EXTI1_Pos)      /*!< 0x00000400 */
#define EXTI_EXTICR1_EXTI1_3      (0x8UL << EXTI_EXTICR1_EXTI1_Pos)      /*!< 0x00000800 */
#define EXTI_EXTICR1_EXTI2_Pos    (16U)
#define EXTI_EXTICR1_EXTI2_Msk    (0xFFUL << EXTI_EXTICR1_EXTI2_Pos)     /*!< 0x00FF0000 */
#define EXTI_EXTICR1_EXTI2        EXTI_EXTICR1_EXTI2_Msk                 /*!< EXTI2 GPIO port selection */
#define EXTI_EXTICR1_EXTI2_0      (0x1UL << EXTI_EXTICR1_EXTI2_Pos)      /*!< 0x00010000 */
#define EXTI_EXTICR1_EXTI2_1      (0x2UL << EXTI_EXTICR1_EXTI2_Pos)      /*!< 0x00020000 */
#define EXTI_EXTICR1_EXTI2_2      (0x4UL << EXTI_EXTICR1_EXTI2_Pos)      /*!< 0x00040000 */
#define EXTI_EXTICR1_EXTI2_3      (0x8UL << EXTI_EXTICR1_EXTI2_Pos)      /*!< 0x00080000 */
#define EXTI_EXTICR1_EXTI3_Pos    (24U)
#define EXTI_EXTICR1_EXTI3_Msk    (0xFFUL << EXTI_EXTICR1_EXTI3_Pos)     /*!< 0xFF000000 */
#define EXTI_EXTICR1_EXTI3        EXTI_EXTICR1_EXTI3_Msk                 /*!< EXTI3 GPIO port selection */
#define EXTI_EXTICR1_EXTI3_0      (0x1UL << EXTI_EXTICR1_EXTI3_Pos)      /*!< 0x01000000 */
#define EXTI_EXTICR1_EXTI3_1      (0x2UL << EXTI_EXTICR1_EXTI3_Pos)      /*!< 0x02000000 */
#define EXTI_EXTICR1_EXTI3_2      (0x4UL << EXTI_EXTICR1_EXTI3_Pos)      /*!< 0x04000000 */
#define EXTI_EXTICR1_EXTI3_3      (0x8UL << EXTI_EXTICR1_EXTI3_Pos)      /*!< 0x08000000 */

/* ***********************************  Bit definition for EXTI_EXTICR2 register  *********************************** */
#define EXTI_EXTICR2_EXTI4_Pos    (0U)
#define EXTI_EXTICR2_EXTI4_Msk    (0xFFUL << EXTI_EXTICR2_EXTI4_Pos)     /*!< 0x000000FF */
#define EXTI_EXTICR2_EXTI4        EXTI_EXTICR2_EXTI4_Msk                 /*!< EXTI4 GPIO port selection */
#define EXTI_EXTICR2_EXTI4_0      (0x1UL << EXTI_EXTICR2_EXTI4_Pos)      /*!< 0x00000001 */
#define EXTI_EXTICR2_EXTI4_1      (0x2UL << EXTI_EXTICR2_EXTI4_Pos)      /*!< 0x00000002 */
#define EXTI_EXTICR2_EXTI4_2      (0x4UL << EXTI_EXTICR2_EXTI4_Pos)      /*!< 0x00000004 */
#define EXTI_EXTICR2_EXTI4_3      (0x8UL << EXTI_EXTICR2_EXTI4_Pos)      /*!< 0x00000008 */
#define EXTI_EXTICR2_EXTI5_Pos    (8U)
#define EXTI_EXTICR2_EXTI5_Msk    (0xFFUL << EXTI_EXTICR2_EXTI5_Pos)     /*!< 0x0000FF00 */
#define EXTI_EXTICR2_EXTI5        EXTI_EXTICR2_EXTI5_Msk                 /*!< EXTI5 GPIO port selection */
#define EXTI_EXTICR2_EXTI5_0      (0x1UL << EXTI_EXTICR2_EXTI5_Pos)      /*!< 0x00000100 */
#define EXTI_EXTICR2_EXTI5_1      (0x2UL << EXTI_EXTICR2_EXTI5_Pos)      /*!< 0x00000200 */
#define EXTI_EXTICR2_EXTI5_2      (0x4UL << EXTI_EXTICR2_EXTI5_Pos)      /*!< 0x00000400 */
#define EXTI_EXTICR2_EXTI5_3      (0x8UL << EXTI_EXTICR2_EXTI5_Pos)      /*!< 0x00000800 */
#define EXTI_EXTICR2_EXTI6_Pos    (16U)
#define EXTI_EXTICR2_EXTI6_Msk    (0xFFUL << EXTI_EXTICR2_EXTI6_Pos)     /*!< 0x00FF0000 */
#define EXTI_EXTICR2_EXTI6        EXTI_EXTICR2_EXTI6_Msk                 /*!< EXTI6 GPIO port selection */
#define EXTI_EXTICR2_EXTI6_0      (0x1UL << EXTI_EXTICR2_EXTI6_Pos)      /*!< 0x00010000 */
#define EXTI_EXTICR2_EXTI6_1      (0x2UL << EXTI_EXTICR2_EXTI6_Pos)      /*!< 0x00020000 */
#define EXTI_EXTICR2_EXTI6_2      (0x4UL << EXTI_EXTICR2_EXTI6_Pos)      /*!< 0x00040000 */
#define EXTI_EXTICR2_EXTI6_3      (0x8UL << EXTI_EXTICR2_EXTI6_Pos)      /*!< 0x00080000 */
#define EXTI_EXTICR2_EXTI7_Pos    (24U)
#define EXTI_EXTICR2_EXTI7_Msk    (0xFFUL << EXTI_EXTICR2_EXTI7_Pos)     /*!< 0xFF000000 */
#define EXTI_EXTICR2_EXTI7        EXTI_EXTICR2_EXTI7_Msk                 /*!< EXTI7 GPIO port selection */
#define EXTI_EXTICR2_EXTI7_0      (0x1UL << EXTI_EXTICR2_EXTI7_Pos)      /*!< 0x01000000 */
#define EXTI_EXTICR2_EXTI7_1      (0x2UL << EXTI_EXTICR2_EXTI7_Pos)      /*!< 0x02000000 */
#define EXTI_EXTICR2_EXTI7_2      (0x4UL << EXTI_EXTICR2_EXTI7_Pos)      /*!< 0x04000000 */
#define EXTI_EXTICR2_EXTI7_3      (0x8UL << EXTI_EXTICR2_EXTI7_Pos)      /*!< 0x08000000 */

/* ***********************************  Bit definition for EXTI_EXTICR3 register  *********************************** */
#define EXTI_EXTICR3_EXTI8_Pos    (0U)
#define EXTI_EXTICR3_EXTI8_Msk    (0xFFUL << EXTI_EXTICR3_EXTI8_Pos)     /*!< 0x000000FF */
#define EXTI_EXTICR3_EXTI8        EXTI_EXTICR3_EXTI8_Msk                 /*!< EXTI8 GPIO port selection */
#define EXTI_EXTICR3_EXTI8_0      (0x1UL << EXTI_EXTICR3_EXTI8_Pos)      /*!< 0x00000001 */
#define EXTI_EXTICR3_EXTI8_1      (0x2UL << EXTI_EXTICR3_EXTI8_Pos)      /*!< 0x00000002 */
#define EXTI_EXTICR3_EXTI8_2      (0x4UL << EXTI_EXTICR3_EXTI8_Pos)      /*!< 0x00000004 */
#define EXTI_EXTICR3_EXTI8_3      (0x8UL << EXTI_EXTICR3_EXTI8_Pos)      /*!< 0x00000008 */
#define EXTI_EXTICR3_EXTI9_Pos    (8U)
#define EXTI_EXTICR3_EXTI9_Msk    (0xFFUL << EXTI_EXTICR3_EXTI9_Pos)     /*!< 0x0000FF00 */
#define EXTI_EXTICR3_EXTI9        EXTI_EXTICR3_EXTI9_Msk                 /*!< EXTI9 GPIO port selection */
#define EXTI_EXTICR3_EXTI9_0      (0x1UL << EXTI_EXTICR3_EXTI9_Pos)      /*!< 0x00000100 */
#define EXTI_EXTICR3_EXTI9_1      (0x2UL << EXTI_EXTICR3_EXTI9_Pos)      /*!< 0x00000200 */
#define EXTI_EXTICR3_EXTI9_2      (0x4UL << EXTI_EXTICR3_EXTI9_Pos)      /*!< 0x00000400 */
#define EXTI_EXTICR3_EXTI9_3      (0x8UL << EXTI_EXTICR3_EXTI9_Pos)      /*!< 0x00000800 */
#define EXTI_EXTICR3_EXTI10_Pos   (16U)
#define EXTI_EXTICR3_EXTI10_Msk   (0xFFUL << EXTI_EXTICR3_EXTI10_Pos)    /*!< 0x00FF0000 */
#define EXTI_EXTICR3_EXTI10       EXTI_EXTICR3_EXTI10_Msk                /*!< EXTI10 GPIO port selection */
#define EXTI_EXTICR3_EXTI10_0     (0x1UL << EXTI_EXTICR3_EXTI10_Pos)     /*!< 0x00010000 */
#define EXTI_EXTICR3_EXTI10_1     (0x2UL << EXTI_EXTICR3_EXTI10_Pos)     /*!< 0x00020000 */
#define EXTI_EXTICR3_EXTI10_2     (0x4UL << EXTI_EXTICR3_EXTI10_Pos)     /*!< 0x00040000 */
#define EXTI_EXTICR3_EXTI10_3     (0x8UL << EXTI_EXTICR3_EXTI10_Pos)     /*!< 0x00080000 */
#define EXTI_EXTICR3_EXTI11_Pos   (24U)
#define EXTI_EXTICR3_EXTI11_Msk   (0xFFUL << EXTI_EXTICR3_EXTI11_Pos)    /*!< 0xFF000000 */
#define EXTI_EXTICR3_EXTI11       EXTI_EXTICR3_EXTI11_Msk                /*!< EXTI11 GPIO port selection */
#define EXTI_EXTICR3_EXTI11_0     (0x1UL << EXTI_EXTICR3_EXTI11_Pos)     /*!< 0x01000000 */
#define EXTI_EXTICR3_EXTI11_1     (0x2UL << EXTI_EXTICR3_EXTI11_Pos)     /*!< 0x02000000 */
#define EXTI_EXTICR3_EXTI11_2     (0x4UL << EXTI_EXTICR3_EXTI11_Pos)     /*!< 0x04000000 */
#define EXTI_EXTICR3_EXTI11_3     (0x8UL << EXTI_EXTICR3_EXTI11_Pos)     /*!< 0x08000000 */

/* ***********************************  Bit definition for EXTI_EXTICR4 register  *********************************** */
#define EXTI_EXTICR4_EXTI12_Pos   (0U)
#define EXTI_EXTICR4_EXTI12_Msk   (0xFFUL << EXTI_EXTICR4_EXTI12_Pos)    /*!< 0x000000FF */
#define EXTI_EXTICR4_EXTI12       EXTI_EXTICR4_EXTI12_Msk                /*!< EXTI12 GPIO port selection */
#define EXTI_EXTICR4_EXTI12_0     (0x1UL << EXTI_EXTICR4_EXTI12_Pos)     /*!< 0x00000001 */
#define EXTI_EXTICR4_EXTI12_1     (0x2UL << EXTI_EXTICR4_EXTI12_Pos)     /*!< 0x00000002 */
#define EXTI_EXTICR4_EXTI12_2     (0x4UL << EXTI_EXTICR4_EXTI12_Pos)     /*!< 0x00000004 */
#define EXTI_EXTICR4_EXTI12_3     (0x8UL << EXTI_EXTICR4_EXTI12_Pos)     /*!< 0x00000008 */
#define EXTI_EXTICR4_EXTI13_Pos   (8U)
#define EXTI_EXTICR4_EXTI13_Msk   (0xFFUL << EXTI_EXTICR4_EXTI13_Pos)    /*!< 0x0000FF00 */
#define EXTI_EXTICR4_EXTI13       EXTI_EXTICR4_EXTI13_Msk                /*!< EXTI13 GPIO port selection */
#define EXTI_EXTICR4_EXTI13_0     (0x1UL << EXTI_EXTICR4_EXTI13_Pos)     /*!< 0x00000100 */
#define EXTI_EXTICR4_EXTI13_1     (0x2UL << EXTI_EXTICR4_EXTI13_Pos)     /*!< 0x00000200 */
#define EXTI_EXTICR4_EXTI13_2     (0x4UL << EXTI_EXTICR4_EXTI13_Pos)     /*!< 0x00000400 */
#define EXTI_EXTICR4_EXTI13_3     (0x8UL << EXTI_EXTICR4_EXTI13_Pos)     /*!< 0x00000800 */
#define EXTI_EXTICR4_EXTI14_Pos   (16U)
#define EXTI_EXTICR4_EXTI14_Msk   (0xFFUL << EXTI_EXTICR4_EXTI14_Pos)    /*!< 0x00FF0000 */
#define EXTI_EXTICR4_EXTI14       EXTI_EXTICR4_EXTI14_Msk                /*!< EXTI14 GPIO port selection */
#define EXTI_EXTICR4_EXTI14_0     (0x1UL << EXTI_EXTICR4_EXTI14_Pos)     /*!< 0x00010000 */
#define EXTI_EXTICR4_EXTI14_1     (0x2UL << EXTI_EXTICR4_EXTI14_Pos)     /*!< 0x00020000 */
#define EXTI_EXTICR4_EXTI14_2     (0x4UL << EXTI_EXTICR4_EXTI14_Pos)     /*!< 0x00040000 */
#define EXTI_EXTICR4_EXTI14_3     (0x8UL << EXTI_EXTICR4_EXTI14_Pos)     /*!< 0x00080000 */
#define EXTI_EXTICR4_EXTI15_Pos   (24U)
#define EXTI_EXTICR4_EXTI15_Msk   (0xFFUL << EXTI_EXTICR4_EXTI15_Pos)    /*!< 0xFF000000 */
#define EXTI_EXTICR4_EXTI15       EXTI_EXTICR4_EXTI15_Msk                /*!< EXTI15 GPIO port selection */
#define EXTI_EXTICR4_EXTI15_0     (0x1UL << EXTI_EXTICR4_EXTI15_Pos)     /*!< 0x01000000 */
#define EXTI_EXTICR4_EXTI15_1     (0x2UL << EXTI_EXTICR4_EXTI15_Pos)     /*!< 0x02000000 */
#define EXTI_EXTICR4_EXTI15_2     (0x4UL << EXTI_EXTICR4_EXTI15_Pos)     /*!< 0x04000000 */
#define EXTI_EXTICR4_EXTI15_3     (0x8UL << EXTI_EXTICR4_EXTI15_Pos)     /*!< 0x08000000 */

/* ************************************  Bit definition for EXTI_IMR1 register  ************************************* */
#define EXTI_IMR1_IM0_Pos         (0U)
#define EXTI_IMR1_IM0_Msk         (0x1UL << EXTI_IMR1_IM0_Pos)           /*!< 0x00000001 */
#define EXTI_IMR1_IM0             EXTI_IMR1_IM0_Msk                      /*!< CPU wake-up with interrupt mask on event
                                                                              input 0 */
#define EXTI_IMR1_IM1_Pos         (1U)
#define EXTI_IMR1_IM1_Msk         (0x1UL << EXTI_IMR1_IM1_Pos)           /*!< 0x00000002 */
#define EXTI_IMR1_IM1             EXTI_IMR1_IM1_Msk                      /*!< CPU wake-up with interrupt mask on event
                                                                              input 1 */
#define EXTI_IMR1_IM2_Pos         (2U)
#define EXTI_IMR1_IM2_Msk         (0x1UL << EXTI_IMR1_IM2_Pos)           /*!< 0x00000004 */
#define EXTI_IMR1_IM2             EXTI_IMR1_IM2_Msk                      /*!< CPU wake-up with interrupt mask on event
                                                                              input 2 */
#define EXTI_IMR1_IM3_Pos         (3U)
#define EXTI_IMR1_IM3_Msk         (0x1UL << EXTI_IMR1_IM3_Pos)           /*!< 0x00000008 */
#define EXTI_IMR1_IM3             EXTI_IMR1_IM3_Msk                      /*!< CPU wake-up with interrupt mask on event
                                                                              input 3 */
#define EXTI_IMR1_IM4_Pos         (4U)
#define EXTI_IMR1_IM4_Msk         (0x1UL << EXTI_IMR1_IM4_Pos)           /*!< 0x00000010 */
#define EXTI_IMR1_IM4             EXTI_IMR1_IM4_Msk                      /*!< CPU wake-up with interrupt mask on event
                                                                              input 4 */
#define EXTI_IMR1_IM5_Pos         (5U)
#define EXTI_IMR1_IM5_Msk         (0x1UL << EXTI_IMR1_IM5_Pos)           /*!< 0x00000020 */
#define EXTI_IMR1_IM5             EXTI_IMR1_IM5_Msk                      /*!< CPU wake-up with interrupt mask on event
                                                                              input 5 */
#define EXTI_IMR1_IM6_Pos         (6U)
#define EXTI_IMR1_IM6_Msk         (0x1UL << EXTI_IMR1_IM6_Pos)           /*!< 0x00000040 */
#define EXTI_IMR1_IM6             EXTI_IMR1_IM6_Msk                      /*!< CPU wake-up with interrupt mask on event
                                                                              input 6 */
#define EXTI_IMR1_IM7_Pos         (7U)
#define EXTI_IMR1_IM7_Msk         (0x1UL << EXTI_IMR1_IM7_Pos)           /*!< 0x00000080 */
#define EXTI_IMR1_IM7             EXTI_IMR1_IM7_Msk                      /*!< CPU wake-up with interrupt mask on event
                                                                              input 7 */
#define EXTI_IMR1_IM8_Pos         (8U)
#define EXTI_IMR1_IM8_Msk         (0x1UL << EXTI_IMR1_IM8_Pos)           /*!< 0x00000100 */
#define EXTI_IMR1_IM8             EXTI_IMR1_IM8_Msk                      /*!< CPU wake-up with interrupt mask on event
                                                                              input 8 */
#define EXTI_IMR1_IM9_Pos         (9U)
#define EXTI_IMR1_IM9_Msk         (0x1UL << EXTI_IMR1_IM9_Pos)           /*!< 0x00000200 */
#define EXTI_IMR1_IM9             EXTI_IMR1_IM9_Msk                      /*!< CPU wake-up with interrupt mask on event
                                                                              input 9 */
#define EXTI_IMR1_IM10_Pos        (10U)
#define EXTI_IMR1_IM10_Msk        (0x1UL << EXTI_IMR1_IM10_Pos)          /*!< 0x00000400 */
#define EXTI_IMR1_IM10            EXTI_IMR1_IM10_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 10 */
#define EXTI_IMR1_IM11_Pos        (11U)
#define EXTI_IMR1_IM11_Msk        (0x1UL << EXTI_IMR1_IM11_Pos)          /*!< 0x00000800 */
#define EXTI_IMR1_IM11            EXTI_IMR1_IM11_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 11 */
#define EXTI_IMR1_IM12_Pos        (12U)
#define EXTI_IMR1_IM12_Msk        (0x1UL << EXTI_IMR1_IM12_Pos)          /*!< 0x00001000 */
#define EXTI_IMR1_IM12            EXTI_IMR1_IM12_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 12 */
#define EXTI_IMR1_IM13_Pos        (13U)
#define EXTI_IMR1_IM13_Msk        (0x1UL << EXTI_IMR1_IM13_Pos)          /*!< 0x00002000 */
#define EXTI_IMR1_IM13            EXTI_IMR1_IM13_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 13 */
#define EXTI_IMR1_IM14_Pos        (14U)
#define EXTI_IMR1_IM14_Msk        (0x1UL << EXTI_IMR1_IM14_Pos)          /*!< 0x00004000 */
#define EXTI_IMR1_IM14            EXTI_IMR1_IM14_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 14 */
#define EXTI_IMR1_IM15_Pos        (15U)
#define EXTI_IMR1_IM15_Msk        (0x1UL << EXTI_IMR1_IM15_Pos)          /*!< 0x00008000 */
#define EXTI_IMR1_IM15            EXTI_IMR1_IM15_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 15 */
#define EXTI_IMR1_IM16_Pos        (16U)
#define EXTI_IMR1_IM16_Msk        (0x1UL << EXTI_IMR1_IM16_Pos)          /*!< 0x00010000 */
#define EXTI_IMR1_IM16            EXTI_IMR1_IM16_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 16 */
#define EXTI_IMR1_IM17_Pos        (17U)
#define EXTI_IMR1_IM17_Msk        (0x1UL << EXTI_IMR1_IM17_Pos)          /*!< 0x00020000 */
#define EXTI_IMR1_IM17            EXTI_IMR1_IM17_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 17 */
#define EXTI_IMR1_IM18_Pos        (18U)
#define EXTI_IMR1_IM18_Msk        (0x1UL << EXTI_IMR1_IM18_Pos)          /*!< 0x00040000 */
#define EXTI_IMR1_IM18            EXTI_IMR1_IM18_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 18 */
#define EXTI_IMR1_IM19_Pos        (19U)
#define EXTI_IMR1_IM19_Msk        (0x1UL << EXTI_IMR1_IM19_Pos)          /*!< 0x00080000 */
#define EXTI_IMR1_IM19            EXTI_IMR1_IM19_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 19 */
#define EXTI_IMR1_IM20_Pos        (20U)
#define EXTI_IMR1_IM20_Msk        (0x1UL << EXTI_IMR1_IM20_Pos)          /*!< 0x00100000 */
#define EXTI_IMR1_IM20            EXTI_IMR1_IM20_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 20 */
#define EXTI_IMR1_IM21_Pos        (21U)
#define EXTI_IMR1_IM21_Msk        (0x1UL << EXTI_IMR1_IM21_Pos)          /*!< 0x00200000 */
#define EXTI_IMR1_IM21            EXTI_IMR1_IM21_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 21 */
#define EXTI_IMR1_IM22_Pos        (22U)
#define EXTI_IMR1_IM22_Msk        (0x1UL << EXTI_IMR1_IM22_Pos)          /*!< 0x00400000 */
#define EXTI_IMR1_IM22            EXTI_IMR1_IM22_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 22 */
#define EXTI_IMR1_IM23_Pos        (23U)
#define EXTI_IMR1_IM23_Msk        (0x1UL << EXTI_IMR1_IM23_Pos)          /*!< 0x00800000 */
#define EXTI_IMR1_IM23            EXTI_IMR1_IM23_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 23 */
#define EXTI_IMR1_IM24_Pos        (24U)
#define EXTI_IMR1_IM24_Msk        (0x1UL << EXTI_IMR1_IM24_Pos)          /*!< 0x01000000 */
#define EXTI_IMR1_IM24            EXTI_IMR1_IM24_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 24 */
#define EXTI_IMR1_IM25_Pos        (25U)
#define EXTI_IMR1_IM25_Msk        (0x1UL << EXTI_IMR1_IM25_Pos)          /*!< 0x02000000 */
#define EXTI_IMR1_IM25            EXTI_IMR1_IM25_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 25 */
#define EXTI_IMR1_IM26_Pos        (26U)
#define EXTI_IMR1_IM26_Msk        (0x1UL << EXTI_IMR1_IM26_Pos)          /*!< 0x04000000 */
#define EXTI_IMR1_IM26            EXTI_IMR1_IM26_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 26 */
#define EXTI_IMR1_IM27_Pos        (27U)
#define EXTI_IMR1_IM27_Msk        (0x1UL << EXTI_IMR1_IM27_Pos)          /*!< 0x08000000 */
#define EXTI_IMR1_IM27            EXTI_IMR1_IM27_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 27 */
#define EXTI_IMR1_IM28_Pos        (28U)
#define EXTI_IMR1_IM28_Msk        (0x1UL << EXTI_IMR1_IM28_Pos)          /*!< 0x10000000 */
#define EXTI_IMR1_IM28            EXTI_IMR1_IM28_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 28 */
#define EXTI_IMR1_IM29_Pos        (29U)
#define EXTI_IMR1_IM29_Msk        (0x1UL << EXTI_IMR1_IM29_Pos)          /*!< 0x20000000 */
#define EXTI_IMR1_IM29            EXTI_IMR1_IM29_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 29 */
#define EXTI_IMR1_IM30_Pos        (30U)
#define EXTI_IMR1_IM30_Msk        (0x1UL << EXTI_IMR1_IM30_Pos)          /*!< 0x40000000 */
#define EXTI_IMR1_IM30            EXTI_IMR1_IM30_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 30 */
#define EXTI_IMR1_IM31_Pos        (31U)
#define EXTI_IMR1_IM31_Msk        (0x1UL << EXTI_IMR1_IM31_Pos)          /*!< 0x80000000 */
#define EXTI_IMR1_IM31            EXTI_IMR1_IM31_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 31 */

/* ************************************  Bit definition for EXTI_EMR1 register  ************************************* */
#define EXTI_EMR1_EM0_Pos         (0U)
#define EXTI_EMR1_EM0_Msk         (0x1UL << EXTI_EMR1_EM0_Pos)           /*!< 0x00000001 */
#define EXTI_EMR1_EM0             EXTI_EMR1_EM0_Msk                      /*!< CPU wake-up with event generation mask on
                                                                              event input 0 */
#define EXTI_EMR1_EM1_Pos         (1U)
#define EXTI_EMR1_EM1_Msk         (0x1UL << EXTI_EMR1_EM1_Pos)           /*!< 0x00000002 */
#define EXTI_EMR1_EM1             EXTI_EMR1_EM1_Msk                      /*!< CPU wake-up with event generation mask on
                                                                              event input 1 */
#define EXTI_EMR1_EM2_Pos         (2U)
#define EXTI_EMR1_EM2_Msk         (0x1UL << EXTI_EMR1_EM2_Pos)           /*!< 0x00000004 */
#define EXTI_EMR1_EM2             EXTI_EMR1_EM2_Msk                      /*!< CPU wake-up with event generation mask on
                                                                              event input 2 */
#define EXTI_EMR1_EM3_Pos         (3U)
#define EXTI_EMR1_EM3_Msk         (0x1UL << EXTI_EMR1_EM3_Pos)           /*!< 0x00000008 */
#define EXTI_EMR1_EM3             EXTI_EMR1_EM3_Msk                      /*!< CPU wake-up with event generation mask on
                                                                              event input 3 */
#define EXTI_EMR1_EM4_Pos         (4U)
#define EXTI_EMR1_EM4_Msk         (0x1UL << EXTI_EMR1_EM4_Pos)           /*!< 0x00000010 */
#define EXTI_EMR1_EM4             EXTI_EMR1_EM4_Msk                      /*!< CPU wake-up with event generation mask on
                                                                              event input 4 */
#define EXTI_EMR1_EM5_Pos         (5U)
#define EXTI_EMR1_EM5_Msk         (0x1UL << EXTI_EMR1_EM5_Pos)           /*!< 0x00000020 */
#define EXTI_EMR1_EM5             EXTI_EMR1_EM5_Msk                      /*!< CPU wake-up with event generation mask on
                                                                              event input 5 */
#define EXTI_EMR1_EM6_Pos         (6U)
#define EXTI_EMR1_EM6_Msk         (0x1UL << EXTI_EMR1_EM6_Pos)           /*!< 0x00000040 */
#define EXTI_EMR1_EM6             EXTI_EMR1_EM6_Msk                      /*!< CPU wake-up with event generation mask on
                                                                              event input 6 */
#define EXTI_EMR1_EM7_Pos         (7U)
#define EXTI_EMR1_EM7_Msk         (0x1UL << EXTI_EMR1_EM7_Pos)           /*!< 0x00000080 */
#define EXTI_EMR1_EM7             EXTI_EMR1_EM7_Msk                      /*!< CPU wake-up with event generation mask on
                                                                              event input 7 */
#define EXTI_EMR1_EM8_Pos         (8U)
#define EXTI_EMR1_EM8_Msk         (0x1UL << EXTI_EMR1_EM8_Pos)           /*!< 0x00000100 */
#define EXTI_EMR1_EM8             EXTI_EMR1_EM8_Msk                      /*!< CPU wake-up with event generation mask on
                                                                              event input 8 */
#define EXTI_EMR1_EM9_Pos         (9U)
#define EXTI_EMR1_EM9_Msk         (0x1UL << EXTI_EMR1_EM9_Pos)           /*!< 0x00000200 */
#define EXTI_EMR1_EM9             EXTI_EMR1_EM9_Msk                      /*!< CPU wake-up with event generation mask on
                                                                              event input 9 */
#define EXTI_EMR1_EM10_Pos        (10U)
#define EXTI_EMR1_EM10_Msk        (0x1UL << EXTI_EMR1_EM10_Pos)          /*!< 0x00000400 */
#define EXTI_EMR1_EM10            EXTI_EMR1_EM10_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 10 */
#define EXTI_EMR1_EM11_Pos        (11U)
#define EXTI_EMR1_EM11_Msk        (0x1UL << EXTI_EMR1_EM11_Pos)          /*!< 0x00000800 */
#define EXTI_EMR1_EM11            EXTI_EMR1_EM11_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 11 */
#define EXTI_EMR1_EM12_Pos        (12U)
#define EXTI_EMR1_EM12_Msk        (0x1UL << EXTI_EMR1_EM12_Pos)          /*!< 0x00001000 */
#define EXTI_EMR1_EM12            EXTI_EMR1_EM12_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 12 */
#define EXTI_EMR1_EM13_Pos        (13U)
#define EXTI_EMR1_EM13_Msk        (0x1UL << EXTI_EMR1_EM13_Pos)          /*!< 0x00002000 */
#define EXTI_EMR1_EM13            EXTI_EMR1_EM13_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 13 */
#define EXTI_EMR1_EM14_Pos        (14U)
#define EXTI_EMR1_EM14_Msk        (0x1UL << EXTI_EMR1_EM14_Pos)          /*!< 0x00004000 */
#define EXTI_EMR1_EM14            EXTI_EMR1_EM14_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 14 */
#define EXTI_EMR1_EM15_Pos        (15U)
#define EXTI_EMR1_EM15_Msk        (0x1UL << EXTI_EMR1_EM15_Pos)          /*!< 0x00008000 */
#define EXTI_EMR1_EM15            EXTI_EMR1_EM15_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 15 */
#define EXTI_EMR1_EM16_Pos        (16U)
#define EXTI_EMR1_EM16_Msk        (0x1UL << EXTI_EMR1_EM16_Pos)          /*!< 0x00010000 */
#define EXTI_EMR1_EM16            EXTI_EMR1_EM16_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 16 */
#define EXTI_EMR1_EM17_Pos        (17U)
#define EXTI_EMR1_EM17_Msk        (0x1UL << EXTI_EMR1_EM17_Pos)          /*!< 0x00020000 */
#define EXTI_EMR1_EM17            EXTI_EMR1_EM17_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 17 */
#define EXTI_EMR1_EM18_Pos        (18U)
#define EXTI_EMR1_EM18_Msk        (0x1UL << EXTI_EMR1_EM18_Pos)          /*!< 0x00040000 */
#define EXTI_EMR1_EM18            EXTI_EMR1_EM18_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 18 */
#define EXTI_EMR1_EM19_Pos        (19U)
#define EXTI_EMR1_EM19_Msk        (0x1UL << EXTI_EMR1_EM19_Pos)          /*!< 0x00080000 */
#define EXTI_EMR1_EM19            EXTI_EMR1_EM19_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 19 */
#define EXTI_EMR1_EM20_Pos        (20U)
#define EXTI_EMR1_EM20_Msk        (0x1UL << EXTI_EMR1_EM20_Pos)          /*!< 0x00100000 */
#define EXTI_EMR1_EM20            EXTI_EMR1_EM20_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 20 */
#define EXTI_EMR1_EM21_Pos        (21U)
#define EXTI_EMR1_EM21_Msk        (0x1UL << EXTI_EMR1_EM21_Pos)          /*!< 0x00200000 */
#define EXTI_EMR1_EM21            EXTI_EMR1_EM21_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 21 */
#define EXTI_EMR1_EM22_Pos        (22U)
#define EXTI_EMR1_EM22_Msk        (0x1UL << EXTI_EMR1_EM22_Pos)          /*!< 0x00400000 */
#define EXTI_EMR1_EM22            EXTI_EMR1_EM22_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 22 */
#define EXTI_EMR1_EM23_Pos        (23U)
#define EXTI_EMR1_EM23_Msk        (0x1UL << EXTI_EMR1_EM23_Pos)          /*!< 0x00800000 */
#define EXTI_EMR1_EM23            EXTI_EMR1_EM23_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 23 */
#define EXTI_EMR1_EM24_Pos        (24U)
#define EXTI_EMR1_EM24_Msk        (0x1UL << EXTI_EMR1_EM24_Pos)          /*!< 0x01000000 */
#define EXTI_EMR1_EM24            EXTI_EMR1_EM24_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 24 */
#define EXTI_EMR1_EM25_Pos        (25U)
#define EXTI_EMR1_EM25_Msk        (0x1UL << EXTI_EMR1_EM25_Pos)          /*!< 0x02000000 */
#define EXTI_EMR1_EM25            EXTI_EMR1_EM25_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 25 */
#define EXTI_EMR1_EM26_Pos        (26U)
#define EXTI_EMR1_EM26_Msk        (0x1UL << EXTI_EMR1_EM26_Pos)          /*!< 0x04000000 */
#define EXTI_EMR1_EM26            EXTI_EMR1_EM26_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 26 */
#define EXTI_EMR1_EM27_Pos        (27U)
#define EXTI_EMR1_EM27_Msk        (0x1UL << EXTI_EMR1_EM27_Pos)          /*!< 0x08000000 */
#define EXTI_EMR1_EM27            EXTI_EMR1_EM27_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 27 */
#define EXTI_EMR1_EM28_Pos        (28U)
#define EXTI_EMR1_EM28_Msk        (0x1UL << EXTI_EMR1_EM28_Pos)          /*!< 0x10000000 */
#define EXTI_EMR1_EM28            EXTI_EMR1_EM28_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 28 */
#define EXTI_EMR1_EM29_Pos        (29U)
#define EXTI_EMR1_EM29_Msk        (0x1UL << EXTI_EMR1_EM29_Pos)          /*!< 0x20000000 */
#define EXTI_EMR1_EM29            EXTI_EMR1_EM29_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 29 */
#define EXTI_EMR1_EM30_Pos        (30U)
#define EXTI_EMR1_EM30_Msk        (0x1UL << EXTI_EMR1_EM30_Pos)          /*!< 0x40000000 */
#define EXTI_EMR1_EM30            EXTI_EMR1_EM30_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 30 */
#define EXTI_EMR1_EM31_Pos        (31U)
#define EXTI_EMR1_EM31_Msk        (0x1UL << EXTI_EMR1_EM31_Pos)          /*!< 0x80000000 */
#define EXTI_EMR1_EM31            EXTI_EMR1_EM31_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 31 */

/* ************************************  Bit definition for EXTI_IMR2 register  ************************************* */
#define EXTI_IMR2_IM32_Pos        (0U)
#define EXTI_IMR2_IM32_Msk        (0x1UL << EXTI_IMR2_IM32_Pos)           /*!< 0x00000001 */
#define EXTI_IMR2_IM32            EXTI_IMR2_IM32_Msk                      /*!< CPU wake-up with interrupt mask on event
                                                                               input 32 */
#define EXTI_IMR2_IM33_Pos        (1U)
#define EXTI_IMR2_IM33_Msk        (0x1UL << EXTI_IMR2_IM33_Pos)          /*!< 0x00000002 */
#define EXTI_IMR2_IM33            EXTI_IMR2_IM33_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 33*/
#define EXTI_IMR2_IM34_Pos        (2U)
#define EXTI_IMR2_IM34_Msk        (0x1UL << EXTI_IMR2_IM34_Pos)          /*!< 0x00000004 */
#define EXTI_IMR2_IM34            EXTI_IMR2_IM34_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 34 */
#define EXTI_IMR2_IM35_Pos        (3U)
#define EXTI_IMR2_IM35_Msk        (0x1UL << EXTI_IMR2_IM35_Pos)          /*!< 0x00000008 */
#define EXTI_IMR2_IM35            EXTI_IMR2_IM35_Msk                     /*!< CPU wake-up with interrupt mask on event
                                                                              input 35 */

/* ************************************  Bit definition for EXTI_EMR2 register  ************************************* */
#define EXTI_EMR2_EM32_Pos        (0U)
#define EXTI_EMR2_EM32_Msk        (0x1UL << EXTI_EMR2_EM32_Pos)          /*!< 0x00000001 */
#define EXTI_EMR2_EM32            EXTI_EMR2_EM32_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 32 */
#define EXTI_EMR2_EM33_Pos        (1U)
#define EXTI_EMR2_EM33_Msk        (0x1UL << EXTI_EMR2_EM33_Pos)          /*!< 0x00000002 */
#define EXTI_EMR2_EM33            EXTI_EMR2_EM33_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 33 */
#define EXTI_EMR2_EM34_Pos        (2U)
#define EXTI_EMR2_EM34_Msk        (0x1UL << EXTI_EMR2_EM34_Pos)          /*!< 0x00000004 */
#define EXTI_EMR2_EM34            EXTI_EMR2_EM34_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 34 */
#define EXTI_EMR2_EM35_Pos        (3U)
#define EXTI_EMR2_EM35_Msk        (0x1UL << EXTI_EMR2_EM35_Pos)          /*!< 0x00000008 */
#define EXTI_EMR2_EM35            EXTI_EMR2_EM35_Msk                     /*!< CPU wake-up with event generation mask on
                                                                              event input 35 */

/******************************************************************************/
/*                                                                            */
/*                 Flexible Datarate Controller Area Network                  */
/*                                                                            */
/******************************************************************************/
/*!<FDCAN control and status registers */
/*****************  Bit definition for FDCAN_CREL register  *******************/
#define FDCAN_CREL_DAY_Pos                  (0U)
#define FDCAN_CREL_DAY_Msk                  (0xFFUL << FDCAN_CREL_DAY_Pos)          /*!< 0x000000FF */
#define FDCAN_CREL_DAY                      FDCAN_CREL_DAY_Msk                      /*!<Timestamp Day                           */
#define FDCAN_CREL_MON_Pos                  (8U)
#define FDCAN_CREL_MON_Msk                  (0xFFUL << FDCAN_CREL_MON_Pos)          /*!< 0x0000FF00 */
#define FDCAN_CREL_MON                      FDCAN_CREL_MON_Msk                      /*!<Timestamp Month                         */
#define FDCAN_CREL_YEAR_Pos                 (16U)
#define FDCAN_CREL_YEAR_Msk                 (0xFUL << FDCAN_CREL_YEAR_Pos)          /*!< 0x000F0000 */
#define FDCAN_CREL_YEAR                     FDCAN_CREL_YEAR_Msk                     /*!<Timestamp Year                          */
#define FDCAN_CREL_SUBSTEP_Pos              (20U)
#define FDCAN_CREL_SUBSTEP_Msk              (0xFUL << FDCAN_CREL_SUBSTEP_Pos)       /*!< 0x00F00000 */
#define FDCAN_CREL_SUBSTEP                  FDCAN_CREL_SUBSTEP_Msk                  /*!<Sub-step of Core release                */
#define FDCAN_CREL_STEP_Pos                 (24U)
#define FDCAN_CREL_STEP_Msk                 (0xFUL << FDCAN_CREL_STEP_Pos)          /*!< 0x0F000000 */
#define FDCAN_CREL_STEP                     FDCAN_CREL_STEP_Msk                     /*!<Step of Core release                    */
#define FDCAN_CREL_REL_Pos                  (28U)
#define FDCAN_CREL_REL_Msk                  (0xFUL << FDCAN_CREL_REL_Pos)           /*!< 0xF0000000 */
#define FDCAN_CREL_REL                      FDCAN_CREL_REL_Msk                      /*!<Core release                            */

/*****************  Bit definition for FDCAN_ENDN register  *******************/
#define FDCAN_ENDN_ETV_Pos                  (0U)
#define FDCAN_ENDN_ETV_Msk                  (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)    /*!< 0xFFFFFFFF */
#define FDCAN_ENDN_ETV                      FDCAN_ENDN_ETV_Msk                      /*!<Endianness Test Value                    */

/*****************  Bit definition for FDCAN_DBTP register  *******************/
#define FDCAN_DBTP_DSJW_Pos                 (0U)
#define FDCAN_DBTP_DSJW_Msk                 (0xFUL << FDCAN_DBTP_DSJW_Pos)          /*!< 0x0000000F */
#define FDCAN_DBTP_DSJW                     FDCAN_DBTP_DSJW_Msk                     /*!<Synchronization Jump Width              */
#define FDCAN_DBTP_DTSEG2_Pos               (4U)
#define FDCAN_DBTP_DTSEG2_Msk               (0xFUL << FDCAN_DBTP_DTSEG2_Pos)        /*!< 0x000000F0 */
#define FDCAN_DBTP_DTSEG2                   FDCAN_DBTP_DTSEG2_Msk                   /*!<Data time segment after sample point    */
#define FDCAN_DBTP_DTSEG1_Pos               (8U)
#define FDCAN_DBTP_DTSEG1_Msk               (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)       /*!< 0x00001F00 */
#define FDCAN_DBTP_DTSEG1                   FDCAN_DBTP_DTSEG1_Msk                   /*!<Data time segment before sample point   */
#define FDCAN_DBTP_DBRP_Pos                 (16U)
#define FDCAN_DBTP_DBRP_Msk                 (0x1FUL << FDCAN_DBTP_DBRP_Pos)         /*!< 0x001F0000 */
#define FDCAN_DBTP_DBRP                     FDCAN_DBTP_DBRP_Msk                     /*!<Data BIt Rate Prescaler                 */
#define FDCAN_DBTP_TDC_Pos                  (23U)
#define FDCAN_DBTP_TDC_Msk                  (0x1UL << FDCAN_DBTP_TDC_Pos)           /*!< 0x00800000 */
#define FDCAN_DBTP_TDC                      FDCAN_DBTP_TDC_Msk                      /*!<Transceiver Delay Compensation          */

/*****************  Bit definition for FDCAN_TEST register  *******************/
#define FDCAN_TEST_LBCK_Pos                 (4U)
#define FDCAN_TEST_LBCK_Msk                 (0x1UL << FDCAN_TEST_LBCK_Pos)          /*!< 0x00000010 */
#define FDCAN_TEST_LBCK                     FDCAN_TEST_LBCK_Msk                     /*!<Loop Back mode                           */
#define FDCAN_TEST_TX_Pos                   (5U)
#define FDCAN_TEST_TX_Msk                   (0x3UL << FDCAN_TEST_TX_Pos)            /*!< 0x00000060 */
#define FDCAN_TEST_TX                       FDCAN_TEST_TX_Msk                       /*!<Control of Transmit Pin                  */
#define FDCAN_TEST_RX_Pos                   (7U)
#define FDCAN_TEST_RX_Msk                   (0x1UL << FDCAN_TEST_RX_Pos)            /*!< 0x00000080 */
#define FDCAN_TEST_RX                       FDCAN_TEST_RX_Msk                       /*!<Receive Pin                              */

/*****************  Bit definition for FDCAN_RWD register  ********************/
#define FDCAN_RWD_WDC_Pos                   (0U)
#define FDCAN_RWD_WDC_Msk                   (0xFFUL << FDCAN_RWD_WDC_Pos)           /*!< 0x000000FF */
#define FDCAN_RWD_WDC                       FDCAN_RWD_WDC_Msk                       /*!<Watchdog configuration                   */
#define FDCAN_RWD_WDV_Pos                   (8U)
#define FDCAN_RWD_WDV_Msk                   (0xFFUL << FDCAN_RWD_WDV_Pos)           /*!< 0x0000FF00 */
#define FDCAN_RWD_WDV                       FDCAN_RWD_WDV_Msk                       /*!<Watchdog value                           */

/*****************  Bit definition for FDCAN_CCCR register  ********************/
#define FDCAN_CCCR_INIT_Pos                 (0U)
#define FDCAN_CCCR_INIT_Msk                 (0x1UL << FDCAN_CCCR_INIT_Pos)          /*!< 0x00000001 */
#define FDCAN_CCCR_INIT                     FDCAN_CCCR_INIT_Msk                     /*!<Initialization                           */
#define FDCAN_CCCR_CCE_Pos                  (1U)
#define FDCAN_CCCR_CCE_Msk                  (0x1UL << FDCAN_CCCR_CCE_Pos)           /*!< 0x00000002 */
#define FDCAN_CCCR_CCE                      FDCAN_CCCR_CCE_Msk                      /*!<Configuration Change Enable              */
#define FDCAN_CCCR_ASM_Pos                  (2U)
#define FDCAN_CCCR_ASM_Msk                  (0x1UL << FDCAN_CCCR_ASM_Pos)           /*!< 0x00000004 */
#define FDCAN_CCCR_ASM                      FDCAN_CCCR_ASM_Msk                      /*!<ASM Restricted Operation Mode            */
#define FDCAN_CCCR_CSA_Pos                  (3U)
#define FDCAN_CCCR_CSA_Msk                  (0x1UL << FDCAN_CCCR_CSA_Pos)           /*!< 0x00000008 */
#define FDCAN_CCCR_CSA                      FDCAN_CCCR_CSA_Msk                      /*!<Clock Stop Acknowledge                   */
#define FDCAN_CCCR_CSR_Pos                  (4U)
#define FDCAN_CCCR_CSR_Msk                  (0x1UL << FDCAN_CCCR_CSR_Pos)           /*!< 0x00000010 */
#define FDCAN_CCCR_CSR                      FDCAN_CCCR_CSR_Msk                      /*!<Clock Stop Request                       */
#define FDCAN_CCCR_MON_Pos                  (5U)
#define FDCAN_CCCR_MON_Msk                  (0x1UL << FDCAN_CCCR_MON_Pos)           /*!< 0x00000020 */
#define FDCAN_CCCR_MON                      FDCAN_CCCR_MON_Msk                      /*!<Bus Monitoring Mode                      */
#define FDCAN_CCCR_DAR_Pos                  (6U)
#define FDCAN_CCCR_DAR_Msk                  (0x1UL << FDCAN_CCCR_DAR_Pos)           /*!< 0x00000040 */
#define FDCAN_CCCR_DAR                      FDCAN_CCCR_DAR_Msk                      /*!<Disable Automatic Retransmission         */
#define FDCAN_CCCR_TEST_Pos                 (7U)
#define FDCAN_CCCR_TEST_Msk                 (0x1UL << FDCAN_CCCR_TEST_Pos)          /*!< 0x00000080 */
#define FDCAN_CCCR_TEST                     FDCAN_CCCR_TEST_Msk                     /*!<Test Mode Enable                         */
#define FDCAN_CCCR_FDOE_Pos                 (8U)
#define FDCAN_CCCR_FDOE_Msk                 (0x1UL << FDCAN_CCCR_FDOE_Pos)          /*!< 0x00000100 */
#define FDCAN_CCCR_FDOE                     FDCAN_CCCR_FDOE_Msk                     /*!<FD Operation Enable                      */
#define FDCAN_CCCR_BRSE_Pos                 (9U)
#define FDCAN_CCCR_BRSE_Msk                 (0x1UL << FDCAN_CCCR_BRSE_Pos)          /*!< 0x00000200 */
#define FDCAN_CCCR_BRSE                     FDCAN_CCCR_BRSE_Msk                     /*!<FDCAN Bit Rate Switching                 */
#define FDCAN_CCCR_PXHD_Pos                 (12U)
#define FDCAN_CCCR_PXHD_Msk                 (0x1UL << FDCAN_CCCR_PXHD_Pos)          /*!< 0x00001000 */
#define FDCAN_CCCR_PXHD                     FDCAN_CCCR_PXHD_Msk                     /*!<Protocol Exception Handling Disable      */
#define FDCAN_CCCR_EFBI_Pos                 (13U)
#define FDCAN_CCCR_EFBI_Msk                 (0x1UL << FDCAN_CCCR_EFBI_Pos)          /*!< 0x00002000 */
#define FDCAN_CCCR_EFBI                     FDCAN_CCCR_EFBI_Msk                     /*!<Edge Filtering during Bus Integration    */
#define FDCAN_CCCR_TXP_Pos                  (14U)
#define FDCAN_CCCR_TXP_Msk                  (0x1UL << FDCAN_CCCR_TXP_Pos)           /*!< 0x00004000 */
#define FDCAN_CCCR_TXP                      FDCAN_CCCR_TXP_Msk                      /*!<Two CAN bit times Pause                  */
#define FDCAN_CCCR_NISO_Pos                 (15U)
#define FDCAN_CCCR_NISO_Msk                 (0x1UL << FDCAN_CCCR_NISO_Pos)          /*!< 0x00008000 */
#define FDCAN_CCCR_NISO                     FDCAN_CCCR_NISO_Msk                     /*!<Non ISO Operation                        */

/*****************  Bit definition for FDCAN_NBTP register  ******************* */
#define FDCAN_NBTP_NTSEG2_Pos               (0U)
#define FDCAN_NBTP_NTSEG2_Msk               (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)       /*!< 0x0000007F */
#define FDCAN_NBTP_NTSEG2                   FDCAN_NBTP_NTSEG2_Msk                   /*!<Nominal Time segment after sample point  */
#define FDCAN_NBTP_NTSEG1_Pos               (8U)
#define FDCAN_NBTP_NTSEG1_Msk               (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)       /*!< 0x0000FF00 */
#define FDCAN_NBTP_NTSEG1                   FDCAN_NBTP_NTSEG1_Msk                   /*!<Nominal Time segment before sample point */
#define FDCAN_NBTP_NBRP_Pos                 (16U)
#define FDCAN_NBTP_NBRP_Msk                 (0x1FFUL << FDCAN_NBTP_NBRP_Pos)        /*!< 0x01FF0000 */
#define FDCAN_NBTP_NBRP                     FDCAN_NBTP_NBRP_Msk                     /*!<Bit Rate Prescaler                       */
#define FDCAN_NBTP_NSJW_Pos                 (25U)
#define FDCAN_NBTP_NSJW_Msk                 (0x7FUL << FDCAN_NBTP_NSJW_Pos)         /*!< 0xFE000000 */
#define FDCAN_NBTP_NSJW                     FDCAN_NBTP_NSJW_Msk                     /*!<Nominal (Re)Synchronization Jump Width   */

/*****************  Bit definition for FDCAN_TSCC register  ********************/
#define FDCAN_TSCC_TSS_Pos                  (0U)
#define FDCAN_TSCC_TSS_Msk                  (0x3UL << FDCAN_TSCC_TSS_Pos)           /*!< 0x00000003 */
#define FDCAN_TSCC_TSS                      FDCAN_TSCC_TSS_Msk                      /*!<Timestamp Select                         */
#define FDCAN_TSCC_TCP_Pos                  (16U)
#define FDCAN_TSCC_TCP_Msk                  (0xFUL << FDCAN_TSCC_TCP_Pos)           /*!< 0x000F0000 */
#define FDCAN_TSCC_TCP                      FDCAN_TSCC_TCP_Msk                      /*!<Timestamp Counter Prescaler              */

/*****************  Bit definition for FDCAN_TSCV register  ********************/
#define FDCAN_TSCV_TSC_Pos                  (0U)
#define FDCAN_TSCV_TSC_Msk                  (0xFFFFUL << FDCAN_TSCV_TSC_Pos)        /*!< 0x0000FFFF */
#define FDCAN_TSCV_TSC                      FDCAN_TSCV_TSC_Msk                      /*!<Timestamp Counter                        */

/*****************  Bit definition for FDCAN_TOCC register  ********************/
#define FDCAN_TOCC_ETOC_Pos                 (0U)
#define FDCAN_TOCC_ETOC_Msk                 (0x1UL << FDCAN_TOCC_ETOC_Pos)          /*!< 0x00000001 */
#define FDCAN_TOCC_ETOC                     FDCAN_TOCC_ETOC_Msk                     /*!<Enable Timeout Counter                   */
#define FDCAN_TOCC_TOS_Pos                  (1U)
#define FDCAN_TOCC_TOS_Msk                  (0x3UL << FDCAN_TOCC_TOS_Pos)           /*!< 0x00000006 */
#define FDCAN_TOCC_TOS                      FDCAN_TOCC_TOS_Msk                      /*!<Timeout Select                           */
#define FDCAN_TOCC_TOP_Pos                  (16U)
#define FDCAN_TOCC_TOP_Msk                  (0xFFFFUL << FDCAN_TOCC_TOP_Pos)        /*!< 0xFFFF0000 */
#define FDCAN_TOCC_TOP                      FDCAN_TOCC_TOP_Msk                      /*!<Timeout Period                           */

/*****************  Bit definition for FDCAN_TOCV register  ******************* */
#define FDCAN_TOCV_TOC_Pos                  (0U)
#define FDCAN_TOCV_TOC_Msk                  (0xFFFFUL << FDCAN_TOCV_TOC_Pos)        /*!< 0x0000FFFF */
#define FDCAN_TOCV_TOC                      FDCAN_TOCV_TOC_Msk                      /*!<Timeout Counter                          */

/*****************  Bit definition for FDCAN_ECR register  ******************** */
#define FDCAN_ECR_TEC_Pos                   (0U)
#define FDCAN_ECR_TEC_Msk                   (0xFFUL << FDCAN_ECR_TEC_Pos)           /*!< 0x000000FF */
#define FDCAN_ECR_TEC                       FDCAN_ECR_TEC_Msk                       /*!<Transmit Error Counter                   */
#define FDCAN_ECR_REC_Pos                   (8U)
#define FDCAN_ECR_REC_Msk                   (0x7FUL << FDCAN_ECR_REC_Pos)           /*!< 0x00007F00 */
#define FDCAN_ECR_REC                       FDCAN_ECR_REC_Msk                       /*!<Receive Error Counter                    */
#define FDCAN_ECR_RP_Pos                    (15U)
#define FDCAN_ECR_RP_Msk                    (0x1UL << FDCAN_ECR_RP_Pos)             /*!< 0x00008000 */
#define FDCAN_ECR_RP                        FDCAN_ECR_RP_Msk                        /*!<Receive Error Passive                    */
#define FDCAN_ECR_CEL_Pos                   (16U)
#define FDCAN_ECR_CEL_Msk                   (0xFFUL << FDCAN_ECR_CEL_Pos)           /*!< 0x00FF0000 */
#define FDCAN_ECR_CEL                       FDCAN_ECR_CEL_Msk                       /*!<CAN Error Logging                        */

/*****************  Bit definition for FDCAN_PSR register  ******************** */
#define FDCAN_PSR_LEC_Pos                   (0U)
#define FDCAN_PSR_LEC_Msk                   (0x7UL << FDCAN_PSR_LEC_Pos)            /*!< 0x00000007 */
#define FDCAN_PSR_LEC                       FDCAN_PSR_LEC_Msk                       /*!<Last Error Code                          */
#define FDCAN_PSR_ACT_Pos                   (3U)
#define FDCAN_PSR_ACT_Msk                   (0x3UL << FDCAN_PSR_ACT_Pos)            /*!< 0x00000018 */
#define FDCAN_PSR_ACT                       FDCAN_PSR_ACT_Msk                       /*!<Activity                                 */
#define FDCAN_PSR_EP_Pos                    (5U)
#define FDCAN_PSR_EP_Msk                    (0x1UL << FDCAN_PSR_EP_Pos)             /*!< 0x00000020 */
#define FDCAN_PSR_EP                        FDCAN_PSR_EP_Msk                        /*!<Error Passive                            */
#define FDCAN_PSR_EW_Pos                    (6U)
#define FDCAN_PSR_EW_Msk                    (0x1UL << FDCAN_PSR_EW_Pos)             /*!< 0x00000040 */
#define FDCAN_PSR_EW                        FDCAN_PSR_EW_Msk                        /*!<Warning Status                           */
#define FDCAN_PSR_BO_Pos                    (7U)
#define FDCAN_PSR_BO_Msk                    (0x1UL << FDCAN_PSR_BO_Pos)             /*!< 0x00000080 */
#define FDCAN_PSR_BO                        FDCAN_PSR_BO_Msk                        /*!<Bus_Off Status                           */
#define FDCAN_PSR_DLEC_Pos                  (8U)
#define FDCAN_PSR_DLEC_Msk                  (0x7UL << FDCAN_PSR_DLEC_Pos)           /*!< 0x00000700 */
#define FDCAN_PSR_DLEC                      FDCAN_PSR_DLEC_Msk                      /*!<Data Last Error Code                     */
#define FDCAN_PSR_RESI_Pos                  (11U)
#define FDCAN_PSR_RESI_Msk                  (0x1UL << FDCAN_PSR_RESI_Pos)           /*!< 0x00000800 */
#define FDCAN_PSR_RESI                      FDCAN_PSR_RESI_Msk                      /*!<ESI flag of last received FDCAN Message  */
#define FDCAN_PSR_RBRS_Pos                  (12U)
#define FDCAN_PSR_RBRS_Msk                  (0x1UL << FDCAN_PSR_RBRS_Pos)           /*!< 0x00001000 */
#define FDCAN_PSR_RBRS                      FDCAN_PSR_RBRS_Msk                      /*!<BRS flag of last received FDCAN Message  */
#define FDCAN_PSR_REDL_Pos                  (13U)
#define FDCAN_PSR_REDL_Msk                  (0x1UL << FDCAN_PSR_REDL_Pos)           /*!< 0x00002000 */
#define FDCAN_PSR_REDL                      FDCAN_PSR_REDL_Msk                      /*!<Received FDCAN Message                   */
#define FDCAN_PSR_PXE_Pos                   (14U)
#define FDCAN_PSR_PXE_Msk                   (0x1UL << FDCAN_PSR_PXE_Pos)            /*!< 0x00004000 */
#define FDCAN_PSR_PXE                       FDCAN_PSR_PXE_Msk                       /*!<Protocol Exception Event                 */
#define FDCAN_PSR_TDCV_Pos                  (16U)
#define FDCAN_PSR_TDCV_Msk                  (0x7FUL << FDCAN_PSR_TDCV_Pos)          /*!< 0x007F0000 */
#define FDCAN_PSR_TDCV                      FDCAN_PSR_TDCV_Msk                      /*!<Transmitter Delay Compensation Value     */

/*****************  Bit definition for FDCAN_TDCR register  ******************* */
#define FDCAN_TDCR_TDCF_Pos                 (0U)
#define FDCAN_TDCR_TDCF_Msk                 (0x7FUL << FDCAN_TDCR_TDCF_Pos)         /*!< 0x0000007F */
#define FDCAN_TDCR_TDCF                     FDCAN_TDCR_TDCF_Msk                     /*!<Transmitter Delay Compensation Filter    */
#define FDCAN_TDCR_TDCO_Pos                 (8U)
#define FDCAN_TDCR_TDCO_Msk                 (0x7FUL << FDCAN_TDCR_TDCO_Pos)         /*!< 0x00007F00 */
#define FDCAN_TDCR_TDCO                     FDCAN_TDCR_TDCO_Msk                     /*!<Transmitter Delay Compensation Offset    */

/*****************  Bit definition for FDCAN_IR register  ********************* */
#define FDCAN_IR_RF0N_Pos                   (0U)
#define FDCAN_IR_RF0N_Msk                   (0x1UL << FDCAN_IR_RF0N_Pos)            /*!< 0x00000001 */
#define FDCAN_IR_RF0N                       FDCAN_IR_RF0N_Msk                       /*!<Rx FIFO 0 New Message                    */
#define FDCAN_IR_RF0F_Pos                   (1U)
#define FDCAN_IR_RF0F_Msk                   (0x1UL << FDCAN_IR_RF0F_Pos)            /*!< 0x00000002 */
#define FDCAN_IR_RF0F                       FDCAN_IR_RF0F_Msk                       /*!<Rx FIFO 0 Full                           */
#define FDCAN_IR_RF0L_Pos                   (2U)
#define FDCAN_IR_RF0L_Msk                   (0x1UL << FDCAN_IR_RF0L_Pos)            /*!< 0x00000004 */
#define FDCAN_IR_RF0L                       FDCAN_IR_RF0L_Msk                       /*!<Rx FIFO 0 Message Lost                   */
#define FDCAN_IR_RF1N_Pos                   (3U)
#define FDCAN_IR_RF1N_Msk                   (0x1UL << FDCAN_IR_RF1N_Pos)            /*!< 0x00000008 */
#define FDCAN_IR_RF1N                       FDCAN_IR_RF1N_Msk                       /*!<Rx FIFO 1 New Message                    */
#define FDCAN_IR_RF1F_Pos                   (4U)
#define FDCAN_IR_RF1F_Msk                   (0x1UL << FDCAN_IR_RF1F_Pos)            /*!< 0x00000010 */
#define FDCAN_IR_RF1F                       FDCAN_IR_RF1F_Msk                       /*!<Rx FIFO 1 Full                           */
#define FDCAN_IR_RF1L_Pos                   (5U)
#define FDCAN_IR_RF1L_Msk                   (0x1UL << FDCAN_IR_RF1L_Pos)            /*!< 0x00000020 */
#define FDCAN_IR_RF1L                       FDCAN_IR_RF1L_Msk                       /*!<Rx FIFO 1 Message Lost                   */
#define FDCAN_IR_HPM_Pos                    (6U)
#define FDCAN_IR_HPM_Msk                    (0x1UL << FDCAN_IR_HPM_Pos)             /*!< 0x00000040 */
#define FDCAN_IR_HPM                        FDCAN_IR_HPM_Msk                        /*!<High Priority Message                    */
#define FDCAN_IR_TC_Pos                     (7U)
#define FDCAN_IR_TC_Msk                     (0x1UL << FDCAN_IR_TC_Pos)              /*!< 0x00000080 */
#define FDCAN_IR_TC                         FDCAN_IR_TC_Msk                         /*!<Transmission Completed                   */
#define FDCAN_IR_TCF_Pos                    (8U)
#define FDCAN_IR_TCF_Msk                    (0x1UL << FDCAN_IR_TCF_Pos)             /*!< 0x00000100 */
#define FDCAN_IR_TCF                        FDCAN_IR_TCF_Msk                        /*!<Transmission Cancellation Finished       */
#define FDCAN_IR_TFE_Pos                    (9U)
#define FDCAN_IR_TFE_Msk                    (0x1UL << FDCAN_IR_TFE_Pos)             /*!< 0x00000200 */
#define FDCAN_IR_TFE                        FDCAN_IR_TFE_Msk                        /*!<Tx FIFO Empty                            */
#define FDCAN_IR_TEFN_Pos                   (10U)
#define FDCAN_IR_TEFN_Msk                   (0x1UL << FDCAN_IR_TEFN_Pos)            /*!< 0x00000400 */
#define FDCAN_IR_TEFN                       FDCAN_IR_TEFN_Msk                       /*!<Tx Event FIFO New Entry                  */
#define FDCAN_IR_TEFF_Pos                   (11U)
#define FDCAN_IR_TEFF_Msk                   (0x1UL << FDCAN_IR_TEFF_Pos)            /*!< 0x00000800 */
#define FDCAN_IR_TEFF                       FDCAN_IR_TEFF_Msk                       /*!<Tx Event FIFO Full                       */
#define FDCAN_IR_TEFL_Pos                   (12U)
#define FDCAN_IR_TEFL_Msk                   (0x1UL << FDCAN_IR_TEFL_Pos)            /*!< 0x00001000 */
#define FDCAN_IR_TEFL                       FDCAN_IR_TEFL_Msk                       /*!<Tx Event FIFO Element Lost               */
#define FDCAN_IR_TSW_Pos                    (13U)
#define FDCAN_IR_TSW_Msk                    (0x1UL << FDCAN_IR_TSW_Pos)             /*!< 0x00002000 */
#define FDCAN_IR_TSW                        FDCAN_IR_TSW_Msk                        /*!<Timestamp Wraparound                     */
#define FDCAN_IR_MRAF_Pos                   (14U)
#define FDCAN_IR_MRAF_Msk                   (0x1UL << FDCAN_IR_MRAF_Pos)            /*!< 0x00004000 */
#define FDCAN_IR_MRAF                       FDCAN_IR_MRAF_Msk                       /*!<Message RAM Access Failure               */
#define FDCAN_IR_TOO_Pos                    (15U)
#define FDCAN_IR_TOO_Msk                    (0x1UL << FDCAN_IR_TOO_Pos)             /*!< 0x00008000 */
#define FDCAN_IR_TOO                        FDCAN_IR_TOO_Msk                        /*!<Timeout Occurred                         */
#define FDCAN_IR_ELO_Pos                    (16U)
#define FDCAN_IR_ELO_Msk                    (0x1UL << FDCAN_IR_ELO_Pos)             /*!< 0x00010000 */
#define FDCAN_IR_ELO                        FDCAN_IR_ELO_Msk                        /*!<Error Logging Overflow                   */
#define FDCAN_IR_EP_Pos                     (17U)
#define FDCAN_IR_EP_Msk                     (0x1UL << FDCAN_IR_EP_Pos)              /*!< 0x00020000 */
#define FDCAN_IR_EP                         FDCAN_IR_EP_Msk                         /*!<Error Passive                            */
#define FDCAN_IR_EW_Pos                     (18U)
#define FDCAN_IR_EW_Msk                     (0x1UL << FDCAN_IR_EW_Pos)              /*!< 0x00040000 */
#define FDCAN_IR_EW                         FDCAN_IR_EW_Msk                         /*!<Warning Status                           */
#define FDCAN_IR_BO_Pos                     (19U)
#define FDCAN_IR_BO_Msk                     (0x1UL << FDCAN_IR_BO_Pos)              /*!< 0x00080000 */
#define FDCAN_IR_BO                         FDCAN_IR_BO_Msk                         /*!<Bus_Off Status                           */
#define FDCAN_IR_WDI_Pos                    (20U)
#define FDCAN_IR_WDI_Msk                    (0x1UL << FDCAN_IR_WDI_Pos)             /*!< 0x00100000 */
#define FDCAN_IR_WDI                        FDCAN_IR_WDI_Msk                        /*!<Watchdog Interrupt                       */
#define FDCAN_IR_PEA_Pos                    (21U)
#define FDCAN_IR_PEA_Msk                    (0x1UL << FDCAN_IR_PEA_Pos)             /*!< 0x00200000 */
#define FDCAN_IR_PEA                        FDCAN_IR_PEA_Msk                        /*!<Protocol Error in Arbitration Phase      */
#define FDCAN_IR_PED_Pos                    (22U)
#define FDCAN_IR_PED_Msk                    (0x1UL << FDCAN_IR_PED_Pos)             /*!< 0x00400000 */
#define FDCAN_IR_PED                        FDCAN_IR_PED_Msk                        /*!<Protocol Error in Data Phase             */
#define FDCAN_IR_ARA_Pos                    (23U)
#define FDCAN_IR_ARA_Msk                    (0x1UL << FDCAN_IR_ARA_Pos)             /*!< 0x00800000 */
#define FDCAN_IR_ARA                        FDCAN_IR_ARA_Msk                        /*!<Access to Reserved Address               */

/*****************  Bit definition for FDCAN_IE register  ********************* */
#define FDCAN_IE_RF0NE_Pos                  (0U)
#define FDCAN_IE_RF0NE_Msk                  (0x1UL << FDCAN_IE_RF0NE_Pos)           /*!< 0x00000001 */
#define FDCAN_IE_RF0NE                      FDCAN_IE_RF0NE_Msk                      /*!<Rx FIFO 0 New Message Enable             */
#define FDCAN_IE_RF0FE_Pos                  (1U)
#define FDCAN_IE_RF0FE_Msk                  (0x1UL << FDCAN_IE_RF0FE_Pos)           /*!< 0x00000002 */
#define FDCAN_IE_RF0FE                      FDCAN_IE_RF0FE_Msk                      /*!<Rx FIFO 0 Full Enable                    */
#define FDCAN_IE_RF0LE_Pos                  (2U)
#define FDCAN_IE_RF0LE_Msk                  (0x1UL << FDCAN_IE_RF0LE_Pos)           /*!< 0x00000004 */
#define FDCAN_IE_RF0LE                      FDCAN_IE_RF0LE_Msk                      /*!<Rx FIFO 0 Message Lost Enable            */
#define FDCAN_IE_RF1NE_Pos                  (3U)
#define FDCAN_IE_RF1NE_Msk                  (0x1UL << FDCAN_IE_RF1NE_Pos)           /*!< 0x00000008 */
#define FDCAN_IE_RF1NE                      FDCAN_IE_RF1NE_Msk                      /*!<Rx FIFO 1 New Message Enable             */
#define FDCAN_IE_RF1FE_Pos                  (4U)
#define FDCAN_IE_RF1FE_Msk                  (0x1UL << FDCAN_IE_RF1FE_Pos)           /*!< 0x00000010 */
#define FDCAN_IE_RF1FE                      FDCAN_IE_RF1FE_Msk                      /*!<Rx FIFO 1 Full Enable                    */
#define FDCAN_IE_RF1LE_Pos                  (5U)
#define FDCAN_IE_RF1LE_Msk                  (0x1UL << FDCAN_IE_RF1LE_Pos)           /*!< 0x00000020 */
#define FDCAN_IE_RF1LE                      FDCAN_IE_RF1LE_Msk                      /*!<Rx FIFO 1 Message Lost Enable            */
#define FDCAN_IE_HPME_Pos                   (6U)
#define FDCAN_IE_HPME_Msk                   (0x1UL << FDCAN_IE_HPME_Pos)            /*!< 0x00000040 */
#define FDCAN_IE_HPME                       FDCAN_IE_HPME_Msk                       /*!<High Priority Message Enable             */
#define FDCAN_IE_TCE_Pos                    (7U)
#define FDCAN_IE_TCE_Msk                    (0x1UL << FDCAN_IE_TCE_Pos)             /*!< 0x00000080 */
#define FDCAN_IE_TCE                        FDCAN_IE_TCE_Msk                        /*!<Transmission Completed Enable            */
#define FDCAN_IE_TCFE_Pos                   (8U)
#define FDCAN_IE_TCFE_Msk                   (0x1UL << FDCAN_IE_TCFE_Pos)            /*!< 0x00000100 */
#define FDCAN_IE_TCFE                       FDCAN_IE_TCFE_Msk                       /*!<Transmission Cancellation Finished Enable*/
#define FDCAN_IE_TFEE_Pos                   (9U)
#define FDCAN_IE_TFEE_Msk                   (0x1UL << FDCAN_IE_TFEE_Pos)            /*!< 0x00000200 */
#define FDCAN_IE_TFEE                       FDCAN_IE_TFEE_Msk                       /*!<Tx FIFO Empty Enable                     */
#define FDCAN_IE_TEFNE_Pos                  (10U)
#define FDCAN_IE_TEFNE_Msk                  (0x1UL << FDCAN_IE_TEFNE_Pos)           /*!< 0x00000400 */
#define FDCAN_IE_TEFNE                      FDCAN_IE_TEFNE_Msk                      /*!<Tx Event FIFO New Entry Enable           */
#define FDCAN_IE_TEFFE_Pos                  (11U)
#define FDCAN_IE_TEFFE_Msk                  (0x1UL << FDCAN_IE_TEFFE_Pos)           /*!< 0x00000800 */
#define FDCAN_IE_TEFFE                      FDCAN_IE_TEFFE_Msk                      /*!<Tx Event FIFO Full Enable                */
#define FDCAN_IE_TEFLE_Pos                  (12U)
#define FDCAN_IE_TEFLE_Msk                  (0x1UL << FDCAN_IE_TEFLE_Pos)           /*!< 0x00001000 */
#define FDCAN_IE_TEFLE                      FDCAN_IE_TEFLE_Msk                      /*!<Tx Event FIFO Element Lost Enable        */
#define FDCAN_IE_TSWE_Pos                   (13U)
#define FDCAN_IE_TSWE_Msk                   (0x1UL << FDCAN_IE_TSWE_Pos)            /*!< 0x00002000 */
#define FDCAN_IE_TSWE                       FDCAN_IE_TSWE_Msk                       /*!<Timestamp Wraparound Enable              */
#define FDCAN_IE_MRAFE_Pos                  (14U)
#define FDCAN_IE_MRAFE_Msk                  (0x1UL << FDCAN_IE_MRAFE_Pos)           /*!< 0x00004000 */
#define FDCAN_IE_MRAFE                      FDCAN_IE_MRAFE_Msk                      /*!<Message RAM Access Failure Enable        */
#define FDCAN_IE_TOOE_Pos                   (15U)
#define FDCAN_IE_TOOE_Msk                   (0x1UL << FDCAN_IE_TOOE_Pos)            /*!< 0x00008000 */
#define FDCAN_IE_TOOE                       FDCAN_IE_TOOE_Msk                       /*!<Timeout Occurred Enable                  */
#define FDCAN_IE_ELOE_Pos                   (16U)
#define FDCAN_IE_ELOE_Msk                   (0x1UL << FDCAN_IE_ELOE_Pos)            /*!< 0x00010000 */
#define FDCAN_IE_ELOE                       FDCAN_IE_ELOE_Msk                       /*!<Error Logging Overflow Enable            */
#define FDCAN_IE_EPE_Pos                    (17U)
#define FDCAN_IE_EPE_Msk                    (0x1UL << FDCAN_IE_EPE_Pos)             /*!< 0x00020000 */
#define FDCAN_IE_EPE                        FDCAN_IE_EPE_Msk                        /*!<Error Passive Enable                     */
#define FDCAN_IE_EWE_Pos                    (18U)
#define FDCAN_IE_EWE_Msk                    (0x1UL << FDCAN_IE_EWE_Pos)             /*!< 0x00040000 */
#define FDCAN_IE_EWE                        FDCAN_IE_EWE_Msk                        /*!<Warning Status Enable                    */
#define FDCAN_IE_BOE_Pos                    (19U)
#define FDCAN_IE_BOE_Msk                    (0x1UL << FDCAN_IE_BOE_Pos)             /*!< 0x00080000 */
#define FDCAN_IE_BOE                        FDCAN_IE_BOE_Msk                        /*!<Bus_Off Status Enable                    */
#define FDCAN_IE_WDIE_Pos                   (20U)
#define FDCAN_IE_WDIE_Msk                   (0x1UL << FDCAN_IE_WDIE_Pos)            /*!< 0x00100000 */
#define FDCAN_IE_WDIE                       FDCAN_IE_WDIE_Msk                       /*!<Watchdog Interrupt Enable                */
#define FDCAN_IE_PEAE_Pos                   (21U)
#define FDCAN_IE_PEAE_Msk                   (0x1UL << FDCAN_IE_PEAE_Pos)            /*!< 0x00200000 */
#define FDCAN_IE_PEAE                       FDCAN_IE_PEAE_Msk                       /*!<Protocol Error in Arbitration Phase Enable*/
#define FDCAN_IE_PEDE_Pos                   (22U)
#define FDCAN_IE_PEDE_Msk                   (0x1UL << FDCAN_IE_PEDE_Pos)            /*!< 0x00400000 */
#define FDCAN_IE_PEDE                       FDCAN_IE_PEDE_Msk                       /*!<Protocol Error in Data Phase Enable      */
#define FDCAN_IE_ARAE_Pos                   (23U)
#define FDCAN_IE_ARAE_Msk                   (0x1UL << FDCAN_IE_ARAE_Pos)            /*!< 0x00800000 */
#define FDCAN_IE_ARAE                       FDCAN_IE_ARAE_Msk                       /*!<Access to Reserved Address Enable        */

/*****************  Bit definition for FDCAN_ILS register  ******************** **/
#define FDCAN_ILS_RXFIFO0_Pos               (0U)
#define FDCAN_ILS_RXFIFO0_Msk               (0x1UL << FDCAN_ILS_RXFIFO0_Pos)        /*!< 0x00000001 */
#define FDCAN_ILS_RXFIFO0                   FDCAN_ILS_RXFIFO0_Msk                   /*!<Rx FIFO 0 Message Lost
                                                                                        Rx FIFO 0 is Full
                                                                                        Rx FIFO 0 Has New Message */
#define FDCAN_ILS_RXFIFO1_Pos               (1U)
#define FDCAN_ILS_RXFIFO1_Msk               (0x1UL << FDCAN_ILS_RXFIFO1_Pos)        /*!< 0x00000002 */
#define FDCAN_ILS_RXFIFO1                   FDCAN_ILS_RXFIFO1_Msk                   /*!<Rx FIFO 1 Message Lost
                                                                                        Rx FIFO 1 is Full
                                                                                        Rx FIFO 1 Has New Message */
#define FDCAN_ILS_SMSG_Pos                  (2U)
#define FDCAN_ILS_SMSG_Msk                  (0x1UL << FDCAN_ILS_SMSG_Pos)           /*!< 0x00000004 */
#define FDCAN_ILS_SMSG                      FDCAN_ILS_SMSG_Msk                      /*!<Transmission Cancellation Finished
                                                                                        Transmission Completed
                                                                                        High Priority Message */
#define FDCAN_ILS_TFERR_Pos                 (3U)
#define FDCAN_ILS_TFERR_Msk                 (0x1UL << FDCAN_ILS_TFERR_Pos)          /*!< 0x00000008 */
#define FDCAN_ILS_TFERR                     FDCAN_ILS_TFERR_Msk                     /*!<Tx Event FIFO Element Lost
                                                                                        Tx Event FIFO Full
                                                                                        Tx Event FIFO New Entry
                                                                                        Tx FIFO Empty Interrupt Line */
#define FDCAN_ILS_MISC_Pos                  (4U)
#define FDCAN_ILS_MISC_Msk                  (0x1UL << FDCAN_ILS_MISC_Pos)           /*!< 0x00000010 */
#define FDCAN_ILS_MISC                      FDCAN_ILS_MISC_Msk                      /*!<Timeout Occurred
                                                                                        Message RAM Access Failure
                                                                                        Timestamp Wraparound */
#define FDCAN_ILS_BERR_Pos                  (5U)
#define FDCAN_ILS_BERR_Msk                  (0x1UL << FDCAN_ILS_BERR_Pos)           /*!< 0x00000020 */
#define FDCAN_ILS_BERR                      FDCAN_ILS_BERR_Msk                      /*!<Error Passive
                                                                                        Error Logging Overflow */
#define FDCAN_ILS_PERR_Pos                  (6U)
#define FDCAN_ILS_PERR_Msk                  (0x1UL << FDCAN_ILS_PERR_Pos)           /*!< 0x00000040 */
#define FDCAN_ILS_PERR                      FDCAN_ILS_PERR_Msk                      /*!<Access to Reserved Address Line
                                                                                        Protocol Error in Data Phase
                                                                                        Line Phase Line Protocol Error
                                                                                        in Arbitration Watchdog
                                                                                        Interrupt Line Bus_Off Status
                                                                                        Warning Status */

/*****************  Bit definition for FDCAN_ILE register  ******************** **/
#define FDCAN_ILE_EINT0_Pos                 (0U)
#define FDCAN_ILE_EINT0_Msk                 (0x1UL << FDCAN_ILE_EINT0_Pos)          /*!< 0x00000001 */
#define FDCAN_ILE_EINT0                     FDCAN_ILE_EINT0_Msk                     /*!<Enable Interrupt Line 0 */
#define FDCAN_ILE_EINT1_Pos                 (1U)
#define FDCAN_ILE_EINT1_Msk                 (0x1UL << FDCAN_ILE_EINT1_Pos)          /*!< 0x00000002 */
#define FDCAN_ILE_EINT1                     FDCAN_ILE_EINT1_Msk                     /*!<Enable Interrupt Line 1 */

/*****************  Bit definition for FDCAN_RXGFC register  ****************** **/
#define FDCAN_RXGFC_RRFE_Pos                (0U)
#define FDCAN_RXGFC_RRFE_Msk                (0x1UL << FDCAN_RXGFC_RRFE_Pos)         /*!< 0x00000001 */
#define FDCAN_RXGFC_RRFE                    FDCAN_RXGFC_RRFE_Msk                    /*!<Reject Remote Frames Extended */
#define FDCAN_RXGFC_RRFS_Pos                (1U)
#define FDCAN_RXGFC_RRFS_Msk                (0x1UL << FDCAN_RXGFC_RRFS_Pos)         /*!< 0x00000002 */
#define FDCAN_RXGFC_RRFS                    FDCAN_RXGFC_RRFS_Msk                    /*!<Reject Remote Frames Standard */
#define FDCAN_RXGFC_ANFE_Pos                (2U)
#define FDCAN_RXGFC_ANFE_Msk                (0x3UL << FDCAN_RXGFC_ANFE_Pos)         /*!< 0x0000000C */
#define FDCAN_RXGFC_ANFE                    FDCAN_RXGFC_ANFE_Msk                    /*!<Accept Non-matching Frames Extended      */
#define FDCAN_RXGFC_ANFS_Pos                (4U)
#define FDCAN_RXGFC_ANFS_Msk                (0x3UL << FDCAN_RXGFC_ANFS_Pos)         /*!< 0x00000030 */
#define FDCAN_RXGFC_ANFS                    FDCAN_RXGFC_ANFS_Msk                    /*!<Accept Non-matching Frames Standard      */
#define FDCAN_RXGFC_F1OM_Pos                (8U)
#define FDCAN_RXGFC_F1OM_Msk                (0x1UL << FDCAN_RXGFC_F1OM_Pos)         /*!< 0x00000100 */
#define FDCAN_RXGFC_F1OM                    FDCAN_RXGFC_F1OM_Msk                    /*!<FIFO 1 operation mode                    */
#define FDCAN_RXGFC_F0OM_Pos                (9U)
#define FDCAN_RXGFC_F0OM_Msk                (0x1UL << FDCAN_RXGFC_F0OM_Pos)         /*!< 0x00000200 */
#define FDCAN_RXGFC_F0OM                    FDCAN_RXGFC_F0OM_Msk                    /*!<FIFO 0 operation mode                    */
#define FDCAN_RXGFC_LSS_Pos                 (16U)
#define FDCAN_RXGFC_LSS_Msk                 (0x1FUL << FDCAN_RXGFC_LSS_Pos)         /*!< 0x001F0000 */
#define FDCAN_RXGFC_LSS                     FDCAN_RXGFC_LSS_Msk                     /*!<List Size Standard                       */
#define FDCAN_RXGFC_LSE_Pos                 (24U)
#define FDCAN_RXGFC_LSE_Msk                 (0xFUL << FDCAN_RXGFC_LSE_Pos)          /*!< 0x0F000000 */
#define FDCAN_RXGFC_LSE                     FDCAN_RXGFC_LSE_Msk                     /*!<List Size Extended                       */

/*****************  Bit definition for FDCAN_XIDAM register  ****************** **/
#define FDCAN_XIDAM_EIDM_Pos                (0U)
#define FDCAN_XIDAM_EIDM_Msk                (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)  /*!< 0x1FFFFFFF */
#define FDCAN_XIDAM_EIDM                    FDCAN_XIDAM_EIDM_Msk                    /*!<Extended ID Mask                         */

/*****************  Bit definition for FDCAN_HPMS register  ******************* **/
#define FDCAN_HPMS_BIDX_Pos                 (0U)
#define FDCAN_HPMS_BIDX_Msk                 (0x7UL << FDCAN_HPMS_BIDX_Pos)          /*!< 0x00000007 */
#define FDCAN_HPMS_BIDX                     FDCAN_HPMS_BIDX_Msk                     /*!<Buffer Index                             */
#define FDCAN_HPMS_MSI_Pos                  (6U)
#define FDCAN_HPMS_MSI_Msk                  (0x3UL << FDCAN_HPMS_MSI_Pos)           /*!< 0x000000C0 */
#define FDCAN_HPMS_MSI                      FDCAN_HPMS_MSI_Msk                      /*!<Message Storage Indicator                */
#define FDCAN_HPMS_FIDX_Pos                 (8U)
#define FDCAN_HPMS_FIDX_Msk                 (0x1FUL << FDCAN_HPMS_FIDX_Pos)         /*!< 0x00001F00 */
#define FDCAN_HPMS_FIDX                     FDCAN_HPMS_FIDX_Msk                     /*!<Filter Index                             */
#define FDCAN_HPMS_FLST_Pos                 (15U)
#define FDCAN_HPMS_FLST_Msk                 (0x1UL << FDCAN_HPMS_FLST_Pos)          /*!< 0x00008000 */
#define FDCAN_HPMS_FLST                     FDCAN_HPMS_FLST_Msk                     /*!<Filter List                              */

/*****************  Bit definition for FDCAN_RXF0S register  ****************** **/
#define FDCAN_RXF0S_F0FL_Pos                (0U)
#define FDCAN_RXF0S_F0FL_Msk                (0xFUL << FDCAN_RXF0S_F0FL_Pos)         /*!< 0x0000000F */
#define FDCAN_RXF0S_F0FL                    FDCAN_RXF0S_F0FL_Msk                    /*!<Rx FIFO 0 Fill Level                     */
#define FDCAN_RXF0S_F0GI_Pos                (8U)
#define FDCAN_RXF0S_F0GI_Msk                (0x3UL << FDCAN_RXF0S_F0GI_Pos)         /*!< 0x00000300 */
#define FDCAN_RXF0S_F0GI                    FDCAN_RXF0S_F0GI_Msk                    /*!<Rx FIFO 0 Get Index                      */
#define FDCAN_RXF0S_F0PI_Pos                (16U)
#define FDCAN_RXF0S_F0PI_Msk                (0x3UL << FDCAN_RXF0S_F0PI_Pos)         /*!< 0x00030000 */
#define FDCAN_RXF0S_F0PI                    FDCAN_RXF0S_F0PI_Msk                    /*!<Rx FIFO 0 Put Index                      */
#define FDCAN_RXF0S_F0F_Pos                 (24U)
#define FDCAN_RXF0S_F0F_Msk                 (0x1UL << FDCAN_RXF0S_F0F_Pos)          /*!< 0x01000000 */
#define FDCAN_RXF0S_F0F                     FDCAN_RXF0S_F0F_Msk                     /*!<Rx FIFO 0 Full                           */
#define FDCAN_RXF0S_RF0L_Pos                (25U)
#define FDCAN_RXF0S_RF0L_Msk                (0x1UL << FDCAN_RXF0S_RF0L_Pos)         /*!< 0x02000000 */
#define FDCAN_RXF0S_RF0L                    FDCAN_RXF0S_RF0L_Msk                    /*!<Rx FIFO 0 Message Lost                   */

/*****************  Bit definition for FDCAN_RXF0A register  ****************** **/
#define FDCAN_RXF0A_F0AI_Pos                (0U)
#define FDCAN_RXF0A_F0AI_Msk                (0x7UL << FDCAN_RXF0A_F0AI_Pos)         /*!< 0x00000007 */
#define FDCAN_RXF0A_F0AI                    FDCAN_RXF0A_F0AI_Msk                    /*!<Rx FIFO 0 Acknowledge Index              */

/*****************  Bit definition for FDCAN_RXF1S register  ****************** **/
#define FDCAN_RXF1S_F1FL_Pos                (0U)
#define FDCAN_RXF1S_F1FL_Msk                (0xFUL << FDCAN_RXF1S_F1FL_Pos)         /*!< 0x0000000F */
#define FDCAN_RXF1S_F1FL                    FDCAN_RXF1S_F1FL_Msk                    /*!<Rx FIFO 1 Fill Level                     */
#define FDCAN_RXF1S_F1GI_Pos                (8U)
#define FDCAN_RXF1S_F1GI_Msk                (0x3UL << FDCAN_RXF1S_F1GI_Pos)         /*!< 0x00000300 */
#define FDCAN_RXF1S_F1GI                    FDCAN_RXF1S_F1GI_Msk                    /*!<Rx FIFO 1 Get Index                      */
#define FDCAN_RXF1S_F1PI_Pos                (16U)
#define FDCAN_RXF1S_F1PI_Msk                (0x3UL << FDCAN_RXF1S_F1PI_Pos)         /*!< 0x00030000 */
#define FDCAN_RXF1S_F1PI                    FDCAN_RXF1S_F1PI_Msk                    /*!<Rx FIFO 1 Put Index                      */
#define FDCAN_RXF1S_F1F_Pos                 (24U)
#define FDCAN_RXF1S_F1F_Msk                 (0x1UL << FDCAN_RXF1S_F1F_Pos)          /*!< 0x01000000 */
#define FDCAN_RXF1S_F1F                     FDCAN_RXF1S_F1F_Msk                     /*!<Rx FIFO 1 Full                           */
#define FDCAN_RXF1S_RF1L_Pos                (25U)
#define FDCAN_RXF1S_RF1L_Msk                (0x1UL << FDCAN_RXF1S_RF1L_Pos)         /*!< 0x02000000 */
#define FDCAN_RXF1S_RF1L                    FDCAN_RXF1S_RF1L_Msk                    /*!<Rx FIFO 1 Message Lost                   */

/*****************  Bit definition for FDCAN_RXF1A register  ****************** **/
#define FDCAN_RXF1A_F1AI_Pos                (0U)
#define FDCAN_RXF1A_F1AI_Msk                (0x7UL << FDCAN_RXF1A_F1AI_Pos)         /*!< 0x00000007 */
#define FDCAN_RXF1A_F1AI                    FDCAN_RXF1A_F1AI_Msk                    /*!<Rx FIFO 1 Acknowledge Index              */

/*****************  Bit definition for FDCAN_TXBC register  ******************* **/
#define FDCAN_TXBC_TFQM_Pos                 (24U)
#define FDCAN_TXBC_TFQM_Msk                 (0x1UL << FDCAN_TXBC_TFQM_Pos)          /*!< 0x01000000 */
#define FDCAN_TXBC_TFQM                     FDCAN_TXBC_TFQM_Msk                     /*!<Tx FIFO/Queue Mode                       */

/*****************  Bit definition for FDCAN_TXFQS register  ****************** ***/
#define FDCAN_TXFQS_TFFL_Pos                (0U)
#define FDCAN_TXFQS_TFFL_Msk                (0x7UL << FDCAN_TXFQS_TFFL_Pos)         /*!< 0x00000007 */
#define FDCAN_TXFQS_TFFL                    FDCAN_TXFQS_TFFL_Msk                    /*!<Tx FIFO Free Level                       */
#define FDCAN_TXFQS_TFGI_Pos                (8U)
#define FDCAN_TXFQS_TFGI_Msk                (0x3UL << FDCAN_TXFQS_TFGI_Pos)         /*!< 0x00000300 */
#define FDCAN_TXFQS_TFGI                    FDCAN_TXFQS_TFGI_Msk                    /*!<Tx FIFO Get Index                        */
#define FDCAN_TXFQS_TFQPI_Pos               (16U)
#define FDCAN_TXFQS_TFQPI_Msk               (0x3UL << FDCAN_TXFQS_TFQPI_Pos)        /*!< 0x00030000 */
#define FDCAN_TXFQS_TFQPI                   FDCAN_TXFQS_TFQPI_Msk                   /*!<Tx FIFO/Queue Put Index                  */
#define FDCAN_TXFQS_TFQF_Pos                (21U)
#define FDCAN_TXFQS_TFQF_Msk                (0x1UL << FDCAN_TXFQS_TFQF_Pos)         /*!< 0x00200000 */
#define FDCAN_TXFQS_TFQF                    FDCAN_TXFQS_TFQF_Msk                    /*!<Tx FIFO/Queue Full                       */

/*****************  Bit definition for FDCAN_TXBRP register  ****************** ***/
#define FDCAN_TXBRP_TRP_Pos                 (0U)
#define FDCAN_TXBRP_TRP_Msk                 (0x7UL << FDCAN_TXBRP_TRP_Pos)          /*!< 0x00000007 */
#define FDCAN_TXBRP_TRP                     FDCAN_TXBRP_TRP_Msk                     /*!<Transmission Request Pending             */

/*****************  Bit definition for FDCAN_TXBAR register  ****************** ***/
#define FDCAN_TXBAR_AR_Pos                  (0U)
#define FDCAN_TXBAR_AR_Msk                  (0x7UL << FDCAN_TXBAR_AR_Pos)           /*!< 0x00000007 */
#define FDCAN_TXBAR_AR                      FDCAN_TXBAR_AR_Msk                      /*!<Add Request                              */

/*****************  Bit definition for FDCAN_TXBCR register  ****************** ***/
#define FDCAN_TXBCR_CR_Pos                  (0U)
#define FDCAN_TXBCR_CR_Msk                  (0x7UL << FDCAN_TXBCR_CR_Pos)           /*!< 0x00000007 */
#define FDCAN_TXBCR_CR                      FDCAN_TXBCR_CR_Msk                      /*!<Cancellation Request                     */

/*****************  Bit definition for FDCAN_TXBTO register  ****************** ***/
#define FDCAN_TXBTO_TO_Pos                  (0U)
#define FDCAN_TXBTO_TO_Msk                  (0x7UL << FDCAN_TXBTO_TO_Pos)           /*!< 0x00000007 */
#define FDCAN_TXBTO_TO                      FDCAN_TXBTO_TO_Msk                      /*!<Transmission Occurred                    */

/*****************  Bit definition for FDCAN_TXBCF register  ****************** ***/
#define FDCAN_TXBCF_CF_Pos                  (0U)
#define FDCAN_TXBCF_CF_Msk                  (0x7UL << FDCAN_TXBCF_CF_Pos)           /*!< 0x00000007 */
#define FDCAN_TXBCF_CF                      FDCAN_TXBCF_CF_Msk                      /*!<Cancellation Finished                    */

/*****************  Bit definition for FDCAN_TXBTIE register  ***************** ***/
#define FDCAN_TXBTIE_TIE_Pos                (0U)
#define FDCAN_TXBTIE_TIE_Msk                (0x7UL << FDCAN_TXBTIE_TIE_Pos)         /*!< 0x00000007 */
#define FDCAN_TXBTIE_TIE                    FDCAN_TXBTIE_TIE_Msk                    /*!<Transmission Interrupt Enable            */

/*****************  Bit definition for FDCAN_ TXBCIE register  **************** ***/
#define FDCAN_TXBCIE_CFIE_Pos               (0U)
#define FDCAN_TXBCIE_CFIE_Msk               (0x7UL << FDCAN_TXBCIE_CFIE_Pos)        /*!< 0x00000007 */
#define FDCAN_TXBCIE_CFIE                   FDCAN_TXBCIE_CFIE_Msk                   /*!<Cancellation Finished Interrupt Enable   */

/*****************  Bit definition for FDCAN_TXEFS register  ****************** ***/
#define FDCAN_TXEFS_EFFL_Pos                (0U)
#define FDCAN_TXEFS_EFFL_Msk                (0x7UL << FDCAN_TXEFS_EFFL_Pos)         /*!< 0x00000007 */
#define FDCAN_TXEFS_EFFL                    FDCAN_TXEFS_EFFL_Msk                    /*!<Event FIFO Fill Level                    */
#define FDCAN_TXEFS_EFGI_Pos                (8U)
#define FDCAN_TXEFS_EFGI_Msk                (0x3UL << FDCAN_TXEFS_EFGI_Pos)         /*!< 0x00000300 */
#define FDCAN_TXEFS_EFGI                    FDCAN_TXEFS_EFGI_Msk                    /*!<Event FIFO Get Index                     */
#define FDCAN_TXEFS_EFPI_Pos                (16U)
#define FDCAN_TXEFS_EFPI_Msk                (0x3UL << FDCAN_TXEFS_EFPI_Pos)         /*!< 0x00030000 */
#define FDCAN_TXEFS_EFPI                    FDCAN_TXEFS_EFPI_Msk                    /*!<Event FIFO Put Index                     */
#define FDCAN_TXEFS_EFF_Pos                 (24U)
#define FDCAN_TXEFS_EFF_Msk                 (0x1UL << FDCAN_TXEFS_EFF_Pos)          /*!< 0x01000000 */
#define FDCAN_TXEFS_EFF                     FDCAN_TXEFS_EFF_Msk                     /*!<Event FIFO Full                          */
#define FDCAN_TXEFS_TEFL_Pos                (25U)
#define FDCAN_TXEFS_TEFL_Msk                (0x1UL << FDCAN_TXEFS_TEFL_Pos)         /*!< 0x02000000 */
#define FDCAN_TXEFS_TEFL                    FDCAN_TXEFS_TEFL_Msk                    /*!<Tx Event FIFO Element Lost               */

/*****************  Bit definition for FDCAN_TXEFA register  ****************** ***/
#define FDCAN_TXEFA_EFAI_Pos                (0U)
#define FDCAN_TXEFA_EFAI_Msk                (0x3UL << FDCAN_TXEFA_EFAI_Pos)         /*!< 0x00000003 */
#define FDCAN_TXEFA_EFAI                    FDCAN_TXEFA_EFAI_Msk                    /*!<Event FIFO Acknowledge Index             */

/*!<FDCAN config registers */
/*****************  Bit definition for FDCAN_CKDIV register  ****************** ***/
#define FDCAN_CKDIV_PDIV_Pos                (0U)
#define FDCAN_CKDIV_PDIV_Msk                (0xFUL << FDCAN_CKDIV_PDIV_Pos)         /*!< 0x0000000F */
#define FDCAN_CKDIV_PDIV                    FDCAN_CKDIV_PDIV_Msk                    /*!<Input Clock Divider                      */

/**********************************************************************************************************************/
/*                                                                                                                    */
/*                                            Code FLASH registers (FLASH)                                            */
/*                                                                                                                    */
/**********************************************************************************************************************/
#define FLASH_LATENCY_DEFAULT        FLASH_ACR_LATENCY_3WS                               /* FLASH Three
                                                                                            Latency cycles   */
#define FLASH_BLOCKBASED_NB_REG      (1U)                                                /* 1 Block-based
                                                                                            registers for
                                                                                            each Flash bank */

#define FLASH_SIZE_MAX               (0x00080000UL)                                      /* 512 Kbytes user flash */
#define FLASH_PAGE_NB_MAX            (0x20U)                                             /* Page number in bank */
#define FLASH_SIZE                   ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? FLASH_SIZE_MAX : \
                                     ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? FLASH_SIZE_MAX : \
                                     (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U)))
#define FLASH_OTP_SIZE               (0x1200U)                                           /* 2 Kbytes OTP
                                                                                            (one-time programmable)
                                                                                            */
#define FLASH_EXT_USER_SIZE          (0x10000UL)                                         /* 64 Kbytes of Flash
                                                                                            extended memory
                                                                                            if configured
                                                                                            as user flash */
#define FLASH_EDATA_SIZE             (0xC000U)                                           /* 48 Kbytes of Flash
                                                                                            data memory
                                                                                            if configured
                                                                                            as data flash */
#define FLASH_BANK_SIZE              (FLASH_SIZE >> 1U)                                  /* 256 Kbytes per bank
                                                                                             */
#define FLASH_PAGE_SIZE              0x2000U                                             /* 8 Kbytes pages
                                                                                            */
#define FLASH_EXT_USER_BANK_SIZE     (FLASH_EXT_USER_SIZE >> 1U)
#define FLASH_EXT_USER_PAGE_SIZE     0x0800U                                             /* 2 Kbytes pages
                                                                                            in additional
                                                                                            Extended USER area */
#define FLASH_EDATA_BANK_SIZE        (FLASH_EDATA_SIZE >> 1U)
#define FLASH_EDATA_PAGE_SIZE        0x0600U                                             /* 1.5 Kbytes pages
                                                                                            in additional
                                                                                            EDATA area */
#define FLASH_BANK_NB                (2U)                                                /* Number of
                                                                                             FLASH memory
                                                                                             banks */
#define FLASH_PAGE_NB                (FLASH_BANK_SIZE/FLASH_PAGE_SIZE)                   /* Number of
                                                                                             USER pages
                                                                                             per bank */
#define FLASH_EXT_USER_PAGE_NB       (FLASH_EXT_USER_BANK_SIZE/FLASH_EXT_USER_PAGE_SIZE) /* Number of
                                                                                             EDATA pages
                                                                                             per bank */
#define FLASH_EDATA_PAGE_NB          (FLASH_EDATA_BANK_SIZE/FLASH_EDATA_PAGE_SIZE)       /* Number of
                                                                                             Extended USER
                                                                                             pages per bank */
#define FLASH_WRP_GROUP_WIDTH        (1U)

/* ************************************  Bit definition for FLASH_ACR register  ************************************* */
#define FLASH_ACR_LATENCY_Pos               (0U)
#define FLASH_ACR_LATENCY_Msk               (0xFUL << FLASH_ACR_LATENCY_Pos)                 /*!< 0x0000000F */
#define FLASH_ACR_LATENCY                   FLASH_ACR_LATENCY_Msk                            /*!< Read latency */
#define FLASH_ACR_LATENCY_0                 (0x1UL << FLASH_ACR_LATENCY_Pos)
#define FLASH_ACR_LATENCY_1                 (0x2UL << FLASH_ACR_LATENCY_Pos)
#define FLASH_ACR_LATENCY_2                 (0x3UL << FLASH_ACR_LATENCY_Pos)
#define FLASH_ACR_LATENCY_3                 (0x4UL << FLASH_ACR_LATENCY_Pos)
#define FLASH_ACR_LATENCY_4                 (0x5UL << FLASH_ACR_LATENCY_Pos)
#define FLASH_ACR_LATENCY_5                 (0x6UL << FLASH_ACR_LATENCY_Pos)
#define FLASH_ACR_LATENCY_6                 (0x7UL << FLASH_ACR_LATENCY_Pos)
#define FLASH_ACR_LATENCY_7                 (0x8UL << FLASH_ACR_LATENCY_Pos)
#define FLASH_ACR_LATENCY_8                 (0x9UL << FLASH_ACR_LATENCY_Pos)
#define FLASH_ACR_LATENCY_9                 (0xAUL << FLASH_ACR_LATENCY_Pos)
#define FLASH_ACR_LATENCY_10                (0xBUL << FLASH_ACR_LATENCY_Pos)
#define FLASH_ACR_LATENCY_11                (0xCUL << FLASH_ACR_LATENCY_Pos)
#define FLASH_ACR_LATENCY_12                (0xDUL << FLASH_ACR_LATENCY_Pos)
#define FLASH_ACR_LATENCY_13                (0xEUL << FLASH_ACR_LATENCY_Pos)
#define FLASH_ACR_LATENCY_14                (0xFUL << FLASH_ACR_LATENCY_Pos)
#define FLASH_ACR_WRHIGHFREQ_Pos            (4U)
#define FLASH_ACR_WRHIGHFREQ_Msk            (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)              /*!< 0x00000030 */
#define FLASH_ACR_WRHIGHFREQ                FLASH_ACR_WRHIGHFREQ_Msk                         /*!< FLASH signal delay */
#define FLASH_ACR_WRHIGHFREQ_0              (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)              /*!< 0x00000010 */
#define FLASH_ACR_WRHIGHFREQ_1              (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)              /*!< 0x00000020 */
#define FLASH_ACR_PRFTEN_Pos                (8U)
#define FLASH_ACR_PRFTEN_Msk                (0x1UL << FLASH_ACR_PRFTEN_Pos)                  /*!< 0x00000100 */
#define FLASH_ACR_PRFTEN                    FLASH_ACR_PRFTEN_Msk                             /*!< Prefetch enable */
#define FLASH_ACR_EMPTY_Pos                 (16U)
#define FLASH_ACR_EMPTY_Msk                 (0x1UL << FLASH_ACR_EMPTY_Pos)                   /*!< 0x00010000 */
#define FLASH_ACR_EMPTY                     FLASH_ACR_EMPTY_Msk                              /*!< Main Flash memory area
                                                                                                  empty (not reset by
                                                                                                  system reset) */

/* ************************************  Bit definition for FLASH_KEYR register  ************************************ */
#define FLASH_KEYR_KEY_Pos                  (0U)
#define FLASH_KEYR_KEY_Msk                  (0xFFFFFFFFUL << FLASH_KEYR_KEY_Pos)             /*!< 0xFFFFFFFF */
#define FLASH_KEYR_KEY                      FLASH_KEYR_KEY_Msk                               /*!< Non-volatile
                                                                                                  memoryconfiguration
                                                                                                  access unlock key */

/* **********************************  Bit definition for FLASH_OPTKEYR register  *********************************** */
#define FLASH_OPTKEYR_OPTKEY_Pos            (0U)
#define FLASH_OPTKEYR_OPTKEY_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEY_Pos)       /*!< 0xFFFFFFFF */
#define FLASH_OPTKEYR_OPTKEY                FLASH_OPTKEYR_OPTKEY_Msk                         /*!< FLASH option-byte
                                                                                                  control access unlock
                                                                                                  key */

/* ************************************  Bit definition for FLASH_OPSR register  ************************************ */
#define FLASH_OPSR_ADDR_OP_Pos              (0U)
#define FLASH_OPSR_ADDR_OP_Msk              (0xFFFFUL << FLASH_OPSR_ADDR_OP_Pos)             /*!< 0x0000FFFF */
#define FLASH_OPSR_ADDR_OP                  FLASH_OPSR_ADDR_OP_Msk                           /*!< Interrupted operation
                                                                                                  address */
#define FLASH_OPSR_DATA_OP_Pos              (21U)
#define FLASH_OPSR_DATA_OP_Msk              (0x1UL << FLASH_OPSR_DATA_OP_Pos)                /*!< 0x00200000 */
#define FLASH_OPSR_DATA_OP                  FLASH_OPSR_DATA_OP_Msk                           /*!< Flash data area
                                                                                                  operation interrupted
                                                                                                  */
#define FLASH_OPSR_BK_OP_Pos                (22U)
#define FLASH_OPSR_BK_OP_Msk                (0x1UL << FLASH_OPSR_BK_OP_Pos)                  /*!< 0x00400000 */
#define FLASH_OPSR_BK_OP                    FLASH_OPSR_BK_OP_Msk                             /*!< Interrupted operation
                                                                                                  bank */
#define FLASH_OPSR_OTP_OP_Pos               (24U)
#define FLASH_OPSR_OTP_OP_Msk               (0x1UL << FLASH_OPSR_OTP_OP_Pos)                 /*!< 0x01000000 */
#define FLASH_OPSR_OTP_OP                   FLASH_OPSR_OTP_OP_Msk                            /*!< OTP operation
                                                                                                  interrupted */
#define FLASH_OPSR_CODE_OP_Pos              (29U)
#define FLASH_OPSR_CODE_OP_Msk              (0x7UL << FLASH_OPSR_CODE_OP_Pos)                /*!< 0xE0000000 */
#define FLASH_OPSR_CODE_OP                  FLASH_OPSR_CODE_OP_Msk                           /*!< Flash memory operation
                                                                                                  code */
#define FLASH_OPSR_CODE_OP_0                (0x1UL << FLASH_OPSR_CODE_OP_Pos)                /*!< 0x20000000 */
#define FLASH_OPSR_CODE_OP_1                (0x2UL << FLASH_OPSR_CODE_OP_Pos)                /*!< 0x40000000 */
#define FLASH_OPSR_CODE_OP_2                (0x4UL << FLASH_OPSR_CODE_OP_Pos)                /*!< 0x80000000 */

/* ***********************************  Bit definition for FLASH_OPTCR register  ************************************ */
#define FLASH_OPTCR_OPTLOCK_Pos             (0U)
#define FLASH_OPTCR_OPTLOCK_Msk             (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)               /*!< 0x00000001 */
#define FLASH_OPTCR_OPTLOCK                 FLASH_OPTCR_OPTLOCK_Msk                          /*!< FLASH_OPTCR lock
                                                                                                  option configuration
                                                                                                  bit */
#define FLASH_OPTCR_OPTSTRT_Pos             (1U)
#define FLASH_OPTCR_OPTSTRT_Msk             (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)               /*!< 0x00000002 */
#define FLASH_OPTCR_OPTSTRT                 FLASH_OPTCR_OPTSTRT_Msk                          /*!< Option-byte start
                                                                                                  change option
                                                                                                  configuration bit */
#define FLASH_OPTCR_SWAP_BANK_Pos           (31U)
#define FLASH_OPTCR_SWAP_BANK_Msk           (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos)             /*!< 0x80000000 */
#define FLASH_OPTCR_SWAP_BANK               FLASH_OPTCR_SWAP_BANK_Msk                        /*!< Bank swapping option
                                                                                                  configuration bit */

/* *************************************  Bit definition for FLASH_SR register  ************************************* */
#define FLASH_SR_BSY_Pos                    (0U)
#define FLASH_SR_BSY_Msk                    (0x1UL << FLASH_SR_BSY_Pos)                      /*!< 0x00000001 */
#define FLASH_SR_BSY                        FLASH_SR_BSY_Msk                                 /*!< busy flag */
#define FLASH_SR_WBNE_Pos                   (1U)
#define FLASH_SR_WBNE_Msk                   (0x1UL << FLASH_SR_WBNE_Pos)                     /*!< 0x00000002 */
#define FLASH_SR_WBNE                       FLASH_SR_WBNE_Msk                                /*!< write buffer not empty
                                                                                                  flag */
#define FLASH_SR_DBNE_Pos                   (3U)
#define FLASH_SR_DBNE_Msk                   (0x1UL << FLASH_SR_DBNE_Pos)                     /*!< 0x00000008 */
#define FLASH_SR_DBNE                       FLASH_SR_DBNE_Msk                                /*!< data buffer not empty
                                                                                                  flag */
#define FLASH_SR_OEMLOCK_Pos                (8U)
#define FLASH_SR_OEMLOCK_Msk                (0x1UL << FLASH_SR_OEMLOCK_Pos)                  /*!< 0x00000100 */
#define FLASH_SR_OEMLOCK                    FLASH_SR_OEMLOCK_Msk                             /*!< OEM lock */
#define FLASH_SR_BSLOCK_Pos                 (9U)
#define FLASH_SR_BSLOCK_Msk                 (0x1UL << FLASH_SR_BSLOCK_Pos)                   /*!< 0x00000200 */
#define FLASH_SR_BSLOCK                     FLASH_SR_BSLOCK_Msk                              /*!< BS lock */
#define FLASH_SR_EOP_Pos                    (16U)
#define FLASH_SR_EOP_Msk                    (0x1UL << FLASH_SR_EOP_Pos)                      /*!< 0x00010000 */
#define FLASH_SR_EOP                        FLASH_SR_EOP_Msk                                 /*!< end of operation flag
                                                                                                  */
#define FLASH_SR_WRPERR_Pos                 (17U)
#define FLASH_SR_WRPERR_Msk                 (0x1UL << FLASH_SR_WRPERR_Pos)                   /*!< 0x00020000 */
#define FLASH_SR_WRPERR                     FLASH_SR_WRPERR_Msk                              /*!< write protection error
                                                                                                  flag */
#define FLASH_SR_PGSERR_Pos                 (18U)
#define FLASH_SR_PGSERR_Msk                 (0x1UL << FLASH_SR_PGSERR_Pos)                   /*!< 0x00040000 */
#define FLASH_SR_PGSERR                     FLASH_SR_PGSERR_Msk                              /*!< programming sequence
                                                                                                  error flag */
#define FLASH_SR_STRBERR_Pos                (19U)
#define FLASH_SR_STRBERR_Msk                (0x1UL << FLASH_SR_STRBERR_Pos)                  /*!< 0x00080000 */
#define FLASH_SR_STRBERR                    FLASH_SR_STRBERR_Msk                             /*!< strobe error flag */
#define FLASH_SR_INCERR_Pos                 (20U)
#define FLASH_SR_INCERR_Msk                 (0x1UL << FLASH_SR_INCERR_Pos)                   /*!< 0x00100000 */
#define FLASH_SR_INCERR                     FLASH_SR_INCERR_Msk                              /*!< Inconsistency error
                                                                                                  flag */
#define FLASH_SR_OPTCHANGEERR_Pos           (23U)
#define FLASH_SR_OPTCHANGEERR_Msk           (0x1UL << FLASH_SR_OPTCHANGEERR_Pos)             /*!< 0x00800000 */
#define FLASH_SR_OPTCHANGEERR               FLASH_SR_OPTCHANGEERR_Msk                        /*!< Option-byte change
                                                                                                  error flag */

/* *************************************  Bit definition for FLASH_CR register  ************************************* */
#define FLASH_CR_LOCK_Pos                   (0U)
#define FLASH_CR_LOCK_Msk                   (0x1UL << FLASH_CR_LOCK_Pos)                     /*!< 0x00000001 */
#define FLASH_CR_LOCK                       FLASH_CR_LOCK_Msk                                /*!< configuration lock bit
                                                                                                  */
#define FLASH_CR_PG_Pos                     (1U)
#define FLASH_CR_PG_Msk                     (0x1UL << FLASH_CR_PG_Pos)                       /*!< 0x00000002 */
#define FLASH_CR_PG                         FLASH_CR_PG_Msk                                  /*!< programming control
                                                                                                  bit */
#define FLASH_CR_PER_Pos                    (2U)
#define FLASH_CR_PER_Msk                    (0x1UL << FLASH_CR_PER_Pos)                      /*!< 0x00000004 */
#define FLASH_CR_PER                        FLASH_CR_PER_Msk                                 /*!< page erase request */
#define FLASH_CR_BER_Pos                    (3U)
#define FLASH_CR_BER_Msk                    (0x1UL << FLASH_CR_BER_Pos)                      /*!< 0x00000008 */
#define FLASH_CR_BER                        FLASH_CR_BER_Msk                                 /*!< Bank erase request */
#define FLASH_CR_FW_Pos                     (4U)
#define FLASH_CR_FW_Msk                     (0x1UL << FLASH_CR_FW_Pos)                       /*!< 0x00000010 */
#define FLASH_CR_FW                         FLASH_CR_FW_Msk                                  /*!< write forcing control
                                                                                                  bit */
#define FLASH_CR_STRT_Pos                   (5U)
#define FLASH_CR_STRT_Msk                   (0x1UL << FLASH_CR_STRT_Pos)                     /*!< 0x00000020 */
#define FLASH_CR_STRT                       FLASH_CR_STRT_Msk                                /*!< erase start control
                                                                                                  bit */
#define FLASH_CR_PNB_Pos                    (6U)
#define FLASH_CR_PNB_Msk                    (0x3FUL << FLASH_CR_PNB_Pos)                     /*!< 0x00000FC0 */
#define FLASH_CR_PNB                        FLASH_CR_PNB_Msk                                 /*!< Page erase selection
                                                                                                  number */
#define FLASH_CR_MER_Pos                    (15U)
#define FLASH_CR_MER_Msk                    (0x1UL << FLASH_CR_MER_Pos)                      /*!< 0x00008000 */
#define FLASH_CR_MER                        FLASH_CR_MER_Msk                                 /*!< Mass erase request */
#define FLASH_CR_EOPIE_Pos                  (16U)
#define FLASH_CR_EOPIE_Msk                  (0x1UL << FLASH_CR_EOPIE_Pos)                    /*!< 0x00010000 */
#define FLASH_CR_EOPIE                      FLASH_CR_EOPIE_Msk                               /*!< end of operation
                                                                                                  interrupt control bit
                                                                                                  */
#define FLASH_CR_WRPERRIE_Pos               (17U)
#define FLASH_CR_WRPERRIE_Msk               (0x1UL << FLASH_CR_WRPERRIE_Pos)                 /*!< 0x00020000 */
#define FLASH_CR_WRPERRIE                   FLASH_CR_WRPERRIE_Msk                            /*!< write protection error
                                                                                                  interrupt enable bit
                                                                                                  */
#define FLASH_CR_PGSERRIE_Pos               (18U)
#define FLASH_CR_PGSERRIE_Msk               (0x1UL << FLASH_CR_PGSERRIE_Pos)                 /*!< 0x00040000 */
#define FLASH_CR_PGSERRIE                   FLASH_CR_PGSERRIE_Msk                            /*!< programming sequence
                                                                                                  error interrupt enable
                                                                                                  bit */
#define FLASH_CR_STRBERRIE_Pos              (19U)
#define FLASH_CR_STRBERRIE_Msk              (0x1UL << FLASH_CR_STRBERRIE_Pos)                /*!< 0x00080000 */
#define FLASH_CR_STRBERRIE                  FLASH_CR_STRBERRIE_Msk                           /*!< strobe error interrupt
                                                                                                  enable bit */
#define FLASH_CR_INCERRIE_Pos               (20U)
#define FLASH_CR_INCERRIE_Msk               (0x1UL << FLASH_CR_INCERRIE_Pos)                 /*!< 0x00100000 */
#define FLASH_CR_INCERRIE                   FLASH_CR_INCERRIE_Msk                            /*!< inconsistency error
                                                                                                  interrupt enable bit
                                                                                                  */
#define FLASH_CR_OPTCHANGEERRIE_Pos         (23U)
#define FLASH_CR_OPTCHANGEERRIE_Msk         (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos)           /*!< 0x00800000 */
#define FLASH_CR_OPTCHANGEERRIE             FLASH_CR_OPTCHANGEERRIE_Msk                      /*!< Option-byte change
                                                                                                  error interrupt enable
                                                                                                  bit */
#define FLASH_CR_EDATASEL_Pos               (29U)
#define FLASH_CR_EDATASEL_Msk               (0x1UL << FLASH_CR_EDATASEL_Pos)                 /*!< 0x20000000 */
#define FLASH_CR_EDATASEL                   FLASH_CR_EDATASEL_Msk                            /*!< EDATA erase selector
                                                                                                  bit */
#define FLASH_CR_BKSEL_Pos                  (31U)
#define FLASH_CR_BKSEL_Msk                  (0x1UL << FLASH_CR_BKSEL_Pos)                    /*!< 0x80000000 */
#define FLASH_CR_BKSEL                      FLASH_CR_BKSEL_Msk                               /*!< Bank selector bit */

/* ************************************  Bit definition for FLASH_CCR register  ************************************* */
#define FLASH_CCR_CLR_EOP_Pos               (16U)
#define FLASH_CCR_CLR_EOP_Msk               (0x1UL << FLASH_CCR_CLR_EOP_Pos)                 /*!< 0x00010000 */
#define FLASH_CCR_CLR_EOP                   FLASH_CCR_CLR_EOP_Msk                            /*!< EOP flag clear bit */
#define FLASH_CCR_CLR_WRPERR_Pos            (17U)
#define FLASH_CCR_CLR_WRPERR_Msk            (0x1UL << FLASH_CCR_CLR_WRPERR_Pos)              /*!< 0x00020000 */
#define FLASH_CCR_CLR_WRPERR                FLASH_CCR_CLR_WRPERR_Msk                         /*!< WRPERR flag clear bit
                                                                                                  */
#define FLASH_CCR_CLR_PGSERR_Pos            (18U)
#define FLASH_CCR_CLR_PGSERR_Msk            (0x1UL << FLASH_CCR_CLR_PGSERR_Pos)              /*!< 0x00040000 */
#define FLASH_CCR_CLR_PGSERR                FLASH_CCR_CLR_PGSERR_Msk                         /*!< PGSERR flag clear bit
                                                                                                  */
#define FLASH_CCR_CLR_STRBERR_Pos           (19U)
#define FLASH_CCR_CLR_STRBERR_Msk           (0x1UL << FLASH_CCR_CLR_STRBERR_Pos)             /*!< 0x00080000 */
#define FLASH_CCR_CLR_STRBERR               FLASH_CCR_CLR_STRBERR_Msk                        /*!< STRBERR flag clear bit
                                                                                                  */
#define FLASH_CCR_CLR_INCERR_Pos            (20U)
#define FLASH_CCR_CLR_INCERR_Msk            (0x1UL << FLASH_CCR_CLR_INCERR_Pos)              /*!< 0x00100000 */
#define FLASH_CCR_CLR_INCERR                FLASH_CCR_CLR_INCERR_Msk                         /*!< INCERR flag clear bit
                                                                                                  */
#define FLASH_CCR_CLR_OPTCHANGEERR_Pos      (23U)
#define FLASH_CCR_CLR_OPTCHANGEERR_Msk      (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos)        /*!< 0x00800000 */
#define FLASH_CCR_CLR_OPTCHANGEERR          FLASH_CCR_CLR_OPTCHANGEERR_Msk                   /*!< Clear the flag
                                                                                                  corresponding flag in
                                                                                                  FLASH_SR by writing
                                                                                                  this bit. */

/* **********************************  Bit definition for FLASH_PRIVCFGR register  ********************************** */
#define FLASH_PRIVCFGR_PRIV_Pos             (1U)
#define FLASH_PRIVCFGR_PRIV_Msk             (0x1UL << FLASH_PRIVCFGR_PRIV_Pos)               /*!< 0x00000002 */
#define FLASH_PRIVCFGR_PRIV                 FLASH_PRIVCFGR_PRIV_Msk                          /*!< privilege attribute */

/* **********************************  Bit definition for FLASH_HDPEXTR register  *********************************** */
#define FLASH_HDPEXTR_HDP1_EXT_Pos          (0U)
#define FLASH_HDPEXTR_HDP1_EXT_Msk          (0x3FUL << FLASH_HDPEXTR_HDP1_EXT_Pos)           /*!< 0x0000003F */
#define FLASH_HDPEXTR_HDP1_EXT              FLASH_HDPEXTR_HDP1_EXT_Msk                       /*!< HDP area extension in
                                                                                                  8kB pages in bank 1 */
#define FLASH_HDPEXTR_HDP2_EXT_Pos          (16U)
#define FLASH_HDPEXTR_HDP2_EXT_Msk          (0x3FUL << FLASH_HDPEXTR_HDP2_EXT_Pos)           /*!< 0x003F0000 */
#define FLASH_HDPEXTR_HDP2_EXT              FLASH_HDPEXTR_HDP2_EXT_Msk                       /*!< HDP area extension in
                                                                                                  8kB pages in bank 2 */

/* *********************************  Bit definition for FLASH_OPTSR_CUR register  ********************************** */
#define FLASH_OPTSR_CUR_IWDG_SW_Pos         (3U)
#define FLASH_OPTSR_CUR_IWDG_SW_Msk         (0x1UL << FLASH_OPTSR_CUR_IWDG_SW_Pos)           /*!< 0x00000008 */
#define FLASH_OPTSR_CUR_IWDG_SW             FLASH_OPTSR_CUR_IWDG_SW_Msk                      /*!< IWDG control mode
                                                                                                  option status bit */
#define FLASH_OPTSR_CUR_WWDG_SW_Pos         (4U)
#define FLASH_OPTSR_CUR_WWDG_SW_Msk         (0x1UL << FLASH_OPTSR_CUR_WWDG_SW_Pos)           /*!< 0x00000010 */
#define FLASH_OPTSR_CUR_WWDG_SW             FLASH_OPTSR_CUR_WWDG_SW_Msk                      /*!< WWDG control mode
                                                                                                  option status bit */
#define FLASH_OPTSR_CUR_NRST_STOP_Pos       (6U)
#define FLASH_OPTSR_CUR_NRST_STOP_Msk       (0x1UL << FLASH_OPTSR_CUR_NRST_STOP_Pos)         /*!< 0x00000040 */
#define FLASH_OPTSR_CUR_NRST_STOP           FLASH_OPTSR_CUR_NRST_STOP_Msk                    /*!< Core domain Stop entry
                                                                                                  reset option status
                                                                                                  bit */
#define FLASH_OPTSR_CUR_NRST_STDBY_Pos      (7U)
#define FLASH_OPTSR_CUR_NRST_STDBY_Msk      (0x1UL << FLASH_OPTSR_CUR_NRST_STDBY_Pos)        /*!< 0x00000080 */
#define FLASH_OPTSR_CUR_NRST_STDBY          FLASH_OPTSR_CUR_NRST_STDBY_Msk                   /*!< Core domain Standby
                                                                                                  entry reset option
                                                                                                  status bit */
#define FLASH_OPTSR_CUR_RDP_LEVEL_Pos       (8U)
#define FLASH_OPTSR_CUR_RDP_LEVEL_Msk       (0xFFUL << FLASH_OPTSR_CUR_RDP_LEVEL_Pos)        /*!< 0x0000FF00 */
#define FLASH_OPTSR_CUR_RDP_LEVEL           FLASH_OPTSR_CUR_RDP_LEVEL_Msk                    /*!< RDP level code (based
                                                                                                  on Hamming 8,4) */
#define FLASH_OPTSR_CUR_IWDG_STOP_Pos       (20U)
#define FLASH_OPTSR_CUR_IWDG_STOP_Msk       (0x1UL << FLASH_OPTSR_CUR_IWDG_STOP_Pos)         /*!< 0x00100000 */
#define FLASH_OPTSR_CUR_IWDG_STOP           FLASH_OPTSR_CUR_IWDG_STOP_Msk                    /*!< IWDG Stop mode freeze
                                                                                                  option status bit */
#define FLASH_OPTSR_CUR_IWDG_STDBY_Pos      (21U)
#define FLASH_OPTSR_CUR_IWDG_STDBY_Msk      (0x1UL << FLASH_OPTSR_CUR_IWDG_STDBY_Pos)        /*!< 0x00200000 */
#define FLASH_OPTSR_CUR_IWDG_STDBY          FLASH_OPTSR_CUR_IWDG_STDBY_Msk                   /*!< IWDG Standby mode
                                                                                                  freeze option status
                                                                                                  bit */
#define FLASH_OPTSR_CUR_BOOT_SEL_Pos        (22U)
#define FLASH_OPTSR_CUR_BOOT_SEL_Msk        (0x1UL << FLASH_OPTSR_CUR_BOOT_SEL_Pos)          /*!< 0x00400000 */
#define FLASH_OPTSR_CUR_BOOT_SEL            FLASH_OPTSR_CUR_BOOT_SEL_Msk                     /*!< Boot 0 source
                                                                                                  selection */
#define FLASH_OPTSR_CUR_BOOT0_Pos           (23U)
#define FLASH_OPTSR_CUR_BOOT0_Msk           (0x1UL << FLASH_OPTSR_CUR_BOOT0_Pos)             /*!< 0x00800000 */
#define FLASH_OPTSR_CUR_BOOT0               FLASH_OPTSR_CUR_BOOT0_Msk                        /*!< Boot 0 option bit */
#define FLASH_OPTSR_CUR_EDATA_EN_Pos        (29U)
#define FLASH_OPTSR_CUR_EDATA_EN_Msk        (0x1UL << FLASH_OPTSR_CUR_EDATA_EN_Pos)          /*!< 0x20000000 */
#define FLASH_OPTSR_CUR_EDATA_EN            FLASH_OPTSR_CUR_EDATA_EN_Msk                     /*!< Flash data area enable
                                                                                                  */
#define FLASH_OPTSR_CUR_SINGLE_BANK_Pos     (30U)
#define FLASH_OPTSR_CUR_SINGLE_BANK_Msk     (0x1UL << FLASH_OPTSR_CUR_SINGLE_BANK_Pos)       /*!< 0x40000000 */
#define FLASH_OPTSR_CUR_SINGLE_BANK         FLASH_OPTSR_CUR_SINGLE_BANK_Msk                  /*!< Dual bank selection
                                                                                                  option status bit */
#define FLASH_OPTSR_CUR_SWAP_BANK_Pos       (31U)
#define FLASH_OPTSR_CUR_SWAP_BANK_Msk       (0x1UL << FLASH_OPTSR_CUR_SWAP_BANK_Pos)         /*!< 0x80000000 */
#define FLASH_OPTSR_CUR_SWAP_BANK           FLASH_OPTSR_CUR_SWAP_BANK_Msk                    /*!< Bank swapping option
                                                                                                  status bit */

/* *********************************  Bit definition for FLASH_OPTSR_PRG register  ********************************** */
#define FLASH_OPTSR_PRG_IWDG_SW_Pos         (3U)
#define FLASH_OPTSR_PRG_IWDG_SW_Msk         (0x1UL << FLASH_OPTSR_PRG_IWDG_SW_Pos)           /*!< 0x00000008 */
#define FLASH_OPTSR_PRG_IWDG_SW             FLASH_OPTSR_PRG_IWDG_SW_Msk                      /*!< IWDG control mode
                                                                                                  option configuration
                                                                                                  bit */
#define FLASH_OPTSR_PRG_WWDG_SW_Pos         (4U)
#define FLASH_OPTSR_PRG_WWDG_SW_Msk         (0x1UL << FLASH_OPTSR_PRG_WWDG_SW_Pos)           /*!< 0x00000010 */
#define FLASH_OPTSR_PRG_WWDG_SW             FLASH_OPTSR_PRG_WWDG_SW_Msk                      /*!< WWDG control mode
                                                                                                  option configuration
                                                                                                  bit */
#define FLASH_OPTSR_PRG_NRST_STOP_Pos       (6U)
#define FLASH_OPTSR_PRG_NRST_STOP_Msk       (0x1UL << FLASH_OPTSR_PRG_NRST_STOP_Pos)         /*!< 0x00000040 */
#define FLASH_OPTSR_PRG_NRST_STOP           FLASH_OPTSR_PRG_NRST_STOP_Msk                    /*!< Core domain Stop entry
                                                                                                  reset option
                                                                                                  configuration bit */
#define FLASH_OPTSR_PRG_NRST_STDBY_Pos      (7U)
#define FLASH_OPTSR_PRG_NRST_STDBY_Msk      (0x1UL << FLASH_OPTSR_PRG_NRST_STDBY_Pos)        /*!< 0x00000080 */
#define FLASH_OPTSR_PRG_NRST_STDBY          FLASH_OPTSR_PRG_NRST_STDBY_Msk                   /*!< Core domain Standby
                                                                                                  entry reset option
                                                                                                  configuration bit */
#define FLASH_OPTSR_PRG_RDP_LEVEL_Pos       (8U)
#define FLASH_OPTSR_PRG_RDP_LEVEL_Msk       (0xFFUL << FLASH_OPTSR_PRG_RDP_LEVEL_Pos)        /*!< 0x0000FF00 */
#define FLASH_OPTSR_PRG_RDP_LEVEL           FLASH_OPTSR_PRG_RDP_LEVEL_Msk                    /*!< RDP level code (based
                                                                                                  on Hamming 8,4) */
#define FLASH_OPTSR_PRG_IWDG_STOP_Pos       (20U)
#define FLASH_OPTSR_PRG_IWDG_STOP_Msk       (0x1UL << FLASH_OPTSR_PRG_IWDG_STOP_Pos)         /*!< 0x00100000 */
#define FLASH_OPTSR_PRG_IWDG_STOP           FLASH_OPTSR_PRG_IWDG_STOP_Msk                    /*!< IWDG Stop mode freeze
                                                                                                  option configuration
                                                                                                  bit */
#define FLASH_OPTSR_PRG_IWDG_STDBY_Pos      (21U)
#define FLASH_OPTSR_PRG_IWDG_STDBY_Msk      (0x1UL << FLASH_OPTSR_PRG_IWDG_STDBY_Pos)        /*!< 0x00200000 */
#define FLASH_OPTSR_PRG_IWDG_STDBY          FLASH_OPTSR_PRG_IWDG_STDBY_Msk                   /*!< IWDG Standby mode
                                                                                                  freeze option
                                                                                                  configuration bit */
#define FLASH_OPTSR_PRG_BOOT_SEL_Pos        (22U)
#define FLASH_OPTSR_PRG_BOOT_SEL_Msk        (0x1UL << FLASH_OPTSR_PRG_BOOT_SEL_Pos)          /*!< 0x00400000 */
#define FLASH_OPTSR_PRG_BOOT_SEL            FLASH_OPTSR_PRG_BOOT_SEL_Msk                     /*!< Boot 0 source
                                                                                                  configuration */
#define FLASH_OPTSR_PRG_BOOT0_Pos           (23U)
#define FLASH_OPTSR_PRG_BOOT0_Msk           (0x1UL << FLASH_OPTSR_PRG_BOOT0_Pos)             /*!< 0x00800000 */
#define FLASH_OPTSR_PRG_BOOT0               FLASH_OPTSR_PRG_BOOT0_Msk                        /*!< Boot 0 option bit */
#define FLASH_OPTSR_PRG_EDATA_EN_Pos        (29U)
#define FLASH_OPTSR_PRG_EDATA_EN_Msk        (0x1UL << FLASH_OPTSR_PRG_EDATA_EN_Pos)          /*!< 0x20000000 */
#define FLASH_OPTSR_PRG_EDATA_EN            FLASH_OPTSR_PRG_EDATA_EN_Msk                     /*!< Flash data area enable
                                                                                                  */
#define FLASH_OPTSR_PRG_SINGLE_BANK_Pos     (30U)
#define FLASH_OPTSR_PRG_SINGLE_BANK_Msk     (0x1UL << FLASH_OPTSR_PRG_SINGLE_BANK_Pos)       /*!< 0x40000000 */
#define FLASH_OPTSR_PRG_SINGLE_BANK         FLASH_OPTSR_PRG_SINGLE_BANK_Msk                  /*!< Dual bank option
                                                                                                  configuration bit */
#define FLASH_OPTSR_PRG_SWAP_BANK_Pos       (31U)
#define FLASH_OPTSR_PRG_SWAP_BANK_Msk       (0x1UL << FLASH_OPTSR_PRG_SWAP_BANK_Pos)         /*!< 0x80000000 */
#define FLASH_OPTSR_PRG_SWAP_BANK           FLASH_OPTSR_PRG_SWAP_BANK_Msk                    /*!< Bank swapping option
                                                                                                  configuration bit */

/* *********************************  Bit definition for FLASH_OPTSR2_CUR register  ********************************* */
#define FLASH_OPTSR2_CUR_SRAM1_RST_Pos      (0U)
#define FLASH_OPTSR2_CUR_SRAM1_RST_Msk      (0x1UL << FLASH_OPTSR2_CUR_SRAM1_RST_Pos)        /*!< 0x00000001 */
#define FLASH_OPTSR2_CUR_SRAM1_RST          FLASH_OPTSR2_CUR_SRAM1_RST_Msk                   /*!< SRAM1 erase upon
                                                                                                  system reset */
#define FLASH_OPTSR2_CUR_SRAM2_RST_Pos      (1U)
#define FLASH_OPTSR2_CUR_SRAM2_RST_Msk      (0x1UL << FLASH_OPTSR2_CUR_SRAM2_RST_Pos)        /*!< 0x00000002 */
#define FLASH_OPTSR2_CUR_SRAM2_RST          FLASH_OPTSR2_CUR_SRAM2_RST_Msk                   /*!< SRAM2 erase when
                                                                                                  system reset */
#define FLASH_OPTSR2_CUR_SRAM2_ECC_Pos      (4U)
#define FLASH_OPTSR2_CUR_SRAM2_ECC_Msk      (0x1UL << FLASH_OPTSR2_CUR_SRAM2_ECC_Pos)        /*!< 0x00000010 */
#define FLASH_OPTSR2_CUR_SRAM2_ECC          FLASH_OPTSR2_CUR_SRAM2_ECC_Msk                   /*!< SRAM2 ECC detection
                                                                                                  and correction disable
                                                                                                  */

/* *********************************  Bit definition for FLASH_OPTSR2_PRG register  ********************************* */
#define FLASH_OPTSR2_PRG_SRAM1_RST_Pos      (0U)
#define FLASH_OPTSR2_PRG_SRAM1_RST_Msk      (0x1UL << FLASH_OPTSR2_PRG_SRAM1_RST_Pos)        /*!< 0x00000001 */
#define FLASH_OPTSR2_PRG_SRAM1_RST          FLASH_OPTSR2_PRG_SRAM1_RST_Msk                   /*!< SRAM1 erase upon
                                                                                                  system reset */
#define FLASH_OPTSR2_PRG_SRAM2_RST_Pos      (1U)
#define FLASH_OPTSR2_PRG_SRAM2_RST_Msk      (0x1UL << FLASH_OPTSR2_PRG_SRAM2_RST_Pos)        /*!< 0x00000002 */
#define FLASH_OPTSR2_PRG_SRAM2_RST          FLASH_OPTSR2_PRG_SRAM2_RST_Msk                   /*!< SRAM2 erase when
                                                                                                  system reset */
#define FLASH_OPTSR2_PRG_SRAM2_ECC_Pos      (4U)
#define FLASH_OPTSR2_PRG_SRAM2_ECC_Msk      (0x1UL << FLASH_OPTSR2_PRG_SRAM2_ECC_Pos)        /*!< 0x00000010 */
#define FLASH_OPTSR2_PRG_SRAM2_ECC          FLASH_OPTSR2_PRG_SRAM2_ECC_Msk                   /*!< SRAM2 ECC detection
                                                                                                  and correction disable
                                                                                                  */

/* *********************************  Bit definition for FLASH_BOOTR_CUR register  ********************************** */
#define FLASH_BOOTR_CUR_BOOT_LOCK_Pos       (0U)
#define FLASH_BOOTR_CUR_BOOT_LOCK_Msk       (0xFFUL << FLASH_BOOTR_CUR_BOOT_LOCK_Pos)        /*!< 0x000000FF */
#define FLASH_BOOTR_CUR_BOOT_LOCK           FLASH_BOOTR_CUR_BOOT_LOCK_Msk                    /*!< A field locking the
                                                                                                  values of BOOT0,
                                                                                                  BOOT_SEL, SWAP_BANK,
                                                                                                  and BOOTADD option
                                                                                                  settings. */
#define FLASH_BOOTR_CUR_BOOTADD_Pos         (8U)
#define FLASH_BOOTR_CUR_BOOTADD_Msk         (0xFFFFFFUL << FLASH_BOOTR_CUR_BOOTADD_Pos)      /*!< 0xFFFFFF00 */
#define FLASH_BOOTR_CUR_BOOTADD             FLASH_BOOTR_CUR_BOOTADD_Msk                      /*!< unique boot entry
                                                                                                  address */

/* *********************************  Bit definition for FLASH_BOOTR_PRG register  ********************************** */
#define FLASH_BOOTR_PRG_BOOT_LOCK_Pos       (0U)
#define FLASH_BOOTR_PRG_BOOT_LOCK_Msk       (0xFFUL << FLASH_BOOTR_PRG_BOOT_LOCK_Pos)        /*!< 0x000000FF */
#define FLASH_BOOTR_PRG_BOOT_LOCK           FLASH_BOOTR_PRG_BOOT_LOCK_Msk                    /*!< A field locking the
                                                                                                  values of BOOT0,
                                                                                                  BOOT_SEL, SWAP_BANK,
                                                                                                  and BOOTADD option
                                                                                                  settings. */
#define FLASH_BOOTR_PRG_BOOTADD_Pos         (8U)
#define FLASH_BOOTR_PRG_BOOTADD_Msk         (0xFFFFFFUL << FLASH_BOOTR_PRG_BOOTADD_Pos)      /*!< 0xFFFFFF00 */
#define FLASH_BOOTR_PRG_BOOTADD             FLASH_BOOTR_PRG_BOOTADD_Msk                      /*!< unique boot entry
                                                                                                  address */

/* *********************************  Bit definition for FLASH_OTPBLR_CUR register  ********************************* */
#define FLASH_OTPBLR_CUR_LOCKBL_Pos         (0U)
#define FLASH_OTPBLR_CUR_LOCKBL_Msk         (0xFFFFFFUL << FLASH_OTPBLR_CUR_LOCKBL_Pos)      /*!< 0x00FFFFFF */
#define FLASH_OTPBLR_CUR_LOCKBL             FLASH_OTPBLR_CUR_LOCKBL_Msk                      /*!< OTP block lock */

/* *********************************  Bit definition for FLASH_OTPBLR_PRG register  ********************************* */
#define FLASH_OTPBLR_PRG_LOCKBL_Pos         (0U)
#define FLASH_OTPBLR_PRG_LOCKBL_Msk         (0xFFFFFFUL << FLASH_OTPBLR_PRG_LOCKBL_Pos)      /*!< 0x00FFFFFF */
#define FLASH_OTPBLR_PRG_LOCKBL             FLASH_OTPBLR_PRG_LOCKBL_Msk                      /*!< OTP block lock */

/* *******************************  Bit definition for FLASH_BL_COM_CFG_CUR register  ******************************* */
#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Pos (0U)
#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Msk (0xFFFFFFFFUL << \
                                            FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Pos)             /*!< 0xFFFFFFFF */
#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG     FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Msk              /*!< Bootloader interface
                                                                                                  selection/configuratio
                                                                                                  n */

/* *******************************  Bit definition for FLASH_BL_COM_CFG_PRG register  ******************************* */
#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Pos (0U)
#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Msk (0xFFFFFFFFUL << \
                                            FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Pos)             /*!< 0xFFFFFFFF */
#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG     FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Msk              /*!< Bootloader interface
                                                                                                  selection/configuratio
                                                                                                  n */

/* ********************************  Bit definition for FLASH_OEMKEYR1_PRG register  ******************************** */
#define FLASH_OEMKEYR1_PRG_OEMKEY_Pos       (0U)
#define FLASH_OEMKEYR1_PRG_OEMKEY_Msk       (0xFFFFFFFFUL << FLASH_OEMKEYR1_PRG_OEMKEY_Pos)  /*!< 0xFFFFFFFF */
#define FLASH_OEMKEYR1_PRG_OEMKEY           FLASH_OEMKEYR1_PRG_OEMKEY_Msk                    /*!< Least significants
                                                                                                  bytes of OEMKEY */

/* ********************************  Bit definition for FLASH_OEMKEYR2_PRG register  ******************************** */
#define FLASH_OEMKEYR2_PRG_OEMKEY_Pos       (0U)
#define FLASH_OEMKEYR2_PRG_OEMKEY_Msk       (0xFFFFFFFFUL << FLASH_OEMKEYR2_PRG_OEMKEY_Pos)  /*!< 0xFFFFFFFF */
#define FLASH_OEMKEYR2_PRG_OEMKEY           FLASH_OEMKEYR2_PRG_OEMKEY_Msk                    /*!< Mid-least significants
                                                                                                  bytes of OEMKEY */

/* ********************************  Bit definition for FLASH_OEMKEYR3_PRG register  ******************************** */
#define FLASH_OEMKEYR3_PRG_OEMKEY_Pos       (0U)
#define FLASH_OEMKEYR3_PRG_OEMKEY_Msk       (0xFFFFFFFFUL << FLASH_OEMKEYR3_PRG_OEMKEY_Pos)  /*!< 0xFFFFFFFF */
#define FLASH_OEMKEYR3_PRG_OEMKEY           FLASH_OEMKEYR3_PRG_OEMKEY_Msk                    /*!< Mid-most significants
                                                                                                  bytes of OEMKEY */

/* ********************************  Bit definition for FLASH_OEMKEYR4_PRG register  ******************************** */
#define FLASH_OEMKEYR4_PRG_OEMKEY_Pos       (0U)
#define FLASH_OEMKEYR4_PRG_OEMKEY_Msk       (0xFFFFFFFFUL << FLASH_OEMKEYR4_PRG_OEMKEY_Pos)  /*!< 0xFFFFFFFF */
#define FLASH_OEMKEYR4_PRG_OEMKEY           FLASH_OEMKEYR4_PRG_OEMKEY_Msk                    /*!< Most significants
                                                                                                  bytes of OEMKEY */

/* *********************************  Bit definition for FLASH_BSKEYR_PRG register  ********************************* */
#define FLASH_BSKEYR_PRG_BSKEY_Pos          (0U)
#define FLASH_BSKEYR_PRG_BSKEY_Msk          (0xFFFFFFFFUL << FLASH_BSKEYR_PRG_BSKEY_Pos)     /*!< 0xFFFFFFFF */
#define FLASH_BSKEYR_PRG_BSKEY              FLASH_BSKEYR_PRG_BSKEY_Msk                       /*!< Boundary Scan KEY */

/* *********************************  Bit definition for FLASH_WRP1R_CUR register  ********************************** */
#define FLASH_WRP1R_CUR_WRPSG1_Pos          (0U)
#define FLASH_WRP1R_CUR_WRPSG1_Msk          (0xFFFFFFFFUL << FLASH_WRP1R_CUR_WRPSG1_Pos)     /*!< 0xFFFFFFFF */
#define FLASH_WRP1R_CUR_WRPSG1              FLASH_WRP1R_CUR_WRPSG1_Msk                       /*!< Bank1 page protection
                                                                                                  option status byte */

/* *********************************  Bit definition for FLASH_WRP1R_PRG register  ********************************** */
#define FLASH_WRP1R_PRG_WRPSG1_Pos          (0U)
#define FLASH_WRP1R_PRG_WRPSG1_Msk          (0xFFFFFFFFUL << FLASH_WRP1R_PRG_WRPSG1_Pos)     /*!< 0xFFFFFFFF */
#define FLASH_WRP1R_PRG_WRPSG1              FLASH_WRP1R_PRG_WRPSG1_Msk                       /*!< Bank1 page protection
                                                                                                  option status byte */

/* *********************************  Bit definition for FLASH_HDP1R_CUR register  ********************************** */
#define FLASH_HDP1R_CUR_HDP1_STRT_Pos       (0U)
#define FLASH_HDP1R_CUR_HDP1_STRT_Msk       (0x3FUL << FLASH_HDP1R_CUR_HDP1_STRT_Pos)        /*!< 0x0000003F */
#define FLASH_HDP1R_CUR_HDP1_STRT           FLASH_HDP1R_CUR_HDP1_STRT_Msk                    /*!< HDPL barrier
                                                                                                  start set in
                                                                                                  number of 8
                                                                                                  Kbytes pages */
#define FLASH_HDP1R_CUR_HDP1_END_Pos        (16U)
#define FLASH_HDP1R_CUR_HDP1_END_Msk        (0x3FUL << FLASH_HDP1R_CUR_HDP1_END_Pos)         /*!< 0x003F0000 */
#define FLASH_HDP1R_CUR_HDP1_END            FLASH_HDP1R_CUR_HDP1_END_Msk                     /*!< HDPL barrier
                                                                                                   end set in
                                                                                                   number of 8
                                                                                                   Kbytes pages */

/* *********************************  Bit definition for FLASH_HDP1R_PRG register  ********************************** */
#define FLASH_HDP1R_PRG_HDP1_STRT_Pos       (0U)
#define FLASH_HDP1R_PRG_HDP1_STRT_Msk       (0x3FUL << FLASH_HDP1R_PRG_HDP1_STRT_Pos)        /*!< 0x0000003F */
#define FLASH_HDP1R_PRG_HDP1_STRT           FLASH_HDP1R_PRG_HDP1_STRT_Msk                    /*!< Bank 1 HDPL barrier
                                                                                                  start set in number of
                                                                                                  8 Kbytes pages */
#define FLASH_HDP1R_PRG_HDP1_END_Pos        (16U)
#define FLASH_HDP1R_PRG_HDP1_END_Msk        (0x3FUL << FLASH_HDP1R_PRG_HDP1_END_Pos)         /*!< 0x003F0000 */
#define FLASH_HDP1R_PRG_HDP1_END            FLASH_HDP1R_PRG_HDP1_END_Msk                     /*!< Bank 1 HDPL barrier
                                                                                                  end set in number of
                                                                                                  8 Kbytes pages */

/* **********************************  Bit definition for FLASH_ECCCORR register  *********************************** */
#define FLASH_ECCCORR_ADDR_ECC_Pos          (0U)
#define FLASH_ECCCORR_ADDR_ECC_Msk          (0x3FFFUL << FLASH_ECCCORR_ADDR_ECC_Pos)         /*!< 0x00003FFF */
#define FLASH_ECCCORR_ADDR_ECC              FLASH_ECCCORR_ADDR_ECC_Msk                       /*!< ECC error address */
#define FLASH_ECCCORR_EDATA_ECC_Pos         (21U)
#define FLASH_ECCCORR_EDATA_ECC_Msk         (0x1UL << FLASH_ECCCORR_EDATA_ECC_Pos)           /*!< 0x00200000 */
#define FLASH_ECCCORR_EDATA_ECC             FLASH_ECCCORR_EDATA_ECC_Msk                      /*!< ECC fail for corrected
                                                                                                  ECC error in flash
                                                                                                  data area */
#define FLASH_ECCCORR_BK_ECC_Pos            (22U)
#define FLASH_ECCCORR_BK_ECC_Msk            (0x1UL << FLASH_ECCCORR_BK_ECC_Pos)              /*!< 0x00400000 */
#define FLASH_ECCCORR_BK_ECC                FLASH_ECCCORR_BK_ECC_Msk                         /*!< ECC bank flag for
                                                                                                  corrected ECC error */
#define FLASH_ECCCORR_SYSF_ECC_Pos          (23U)
#define FLASH_ECCCORR_SYSF_ECC_Msk          (0x1UL << FLASH_ECCCORR_SYSF_ECC_Pos)            /*!< 0x00800000 */
#define FLASH_ECCCORR_SYSF_ECC              FLASH_ECCCORR_SYSF_ECC_Msk                       /*!< ECC flag for corrected
                                                                                                  ECC error in system
                                                                                                  FLASH */
#define FLASH_ECCCORR_OTP_ECC_Pos           (24U)
#define FLASH_ECCCORR_OTP_ECC_Msk           (0x1UL << FLASH_ECCCORR_OTP_ECC_Pos)             /*!< 0x01000000 */
#define FLASH_ECCCORR_OTP_ECC               FLASH_ECCCORR_OTP_ECC_Msk                        /*!< OTP ECC error bit */
#define FLASH_ECCCORR_ECCCIE_Pos            (25U)
#define FLASH_ECCCORR_ECCCIE_Msk            (0x1UL << FLASH_ECCCORR_ECCCIE_Pos)              /*!< 0x02000000 */
#define FLASH_ECCCORR_ECCCIE                FLASH_ECCCORR_ECCCIE_Msk                         /*!< ECC single correction
                                                                                                  error interrupt enable
                                                                                                  bit When ECCCIE bit is
                                                                                                  set to 1, an interrupt
                                                                                                  is generated when an
                                                                                                  ECC single correction
                                                                                                  error occurs during a
                                                                                                  read operation. */
#define FLASH_ECCCORR_ECCC_Pos              (30U)
#define FLASH_ECCCORR_ECCC_Msk              (0x1UL << FLASH_ECCCORR_ECCC_Pos)                /*!< 0x40000000 */
#define FLASH_ECCCORR_ECCC                  FLASH_ECCCORR_ECCC_Msk                           /*!< ECC correction */

/* **********************************  Bit definition for FLASH_ECCDETR register  *********************************** */
#define FLASH_ECCDETR_ADDR_ECC_Pos          (0U)
#define FLASH_ECCDETR_ADDR_ECC_Msk          (0x3FFFUL << FLASH_ECCDETR_ADDR_ECC_Pos)         /*!< 0x00003FFF */
#define FLASH_ECCDETR_ADDR_ECC              FLASH_ECCDETR_ADDR_ECC_Msk                       /*!< ECC error address */
#define FLASH_ECCDETR_EDATA_ECC_Pos         (21U)
#define FLASH_ECCDETR_EDATA_ECC_Msk         (0x1UL << FLASH_ECCDETR_EDATA_ECC_Pos)           /*!< 0x00200000 */
#define FLASH_ECCDETR_EDATA_ECC             FLASH_ECCDETR_EDATA_ECC_Msk                      /*!< ECC fail for double
                                                                                                  ECC error in flash
                                                                                                  data area */
#define FLASH_ECCDETR_BK_ECC_Pos            (22U)
#define FLASH_ECCDETR_BK_ECC_Msk            (0x1UL << FLASH_ECCDETR_BK_ECC_Pos)              /*!< 0x00400000 */
#define FLASH_ECCDETR_BK_ECC                FLASH_ECCDETR_BK_ECC_Msk                         /*!< ECC fail bank for
                                                                                                  double ECC Error */
#define FLASH_ECCDETR_SYSF_ECC_Pos          (23U)
#define FLASH_ECCDETR_SYSF_ECC_Msk          (0x1UL << FLASH_ECCDETR_SYSF_ECC_Pos)            /*!< 0x00800000 */
#define FLASH_ECCDETR_SYSF_ECC              FLASH_ECCDETR_SYSF_ECC_Msk                       /*!< ECC fail for double
                                                                                                  ECC error in system
                                                                                                  flash memory */
#define FLASH_ECCDETR_OTP_ECC_Pos           (24U)
#define FLASH_ECCDETR_OTP_ECC_Msk           (0x1UL << FLASH_ECCDETR_OTP_ECC_Pos)             /*!< 0x01000000 */
#define FLASH_ECCDETR_OTP_ECC               FLASH_ECCDETR_OTP_ECC_Msk                        /*!< OTP ECC error bit */
#define FLASH_ECCDETR_ECCD_Pos              (31U)
#define FLASH_ECCDETR_ECCD_Msk              (0x1UL << FLASH_ECCDETR_ECCD_Pos)                /*!< 0x80000000 */
#define FLASH_ECCDETR_ECCD                  FLASH_ECCDETR_ECCD_Msk                           /*!< ECC detection set by
                                                                                                  hardware when two ECC
                                                                                                  error has been
                                                                                                  detected. */

/* ***********************************  Bit definition for FLASH_ECCDR register  ************************************ */
#define FLASH_ECCDR_DATA_ECC_Pos            (0U)
#define FLASH_ECCDR_DATA_ECC_Msk            (0xFFFFUL << FLASH_ECCDR_DATA_ECC_Pos)           /*!< 0x0000FFFF */
#define FLASH_ECCDR_DATA_ECC                FLASH_ECCDR_DATA_ECC_Msk                         /*!< ECC error data */
#define FLASH_ECCDR_DATA_ADDR_ECC_Pos       (16U)
#define FLASH_ECCDR_DATA_ADDR_ECC_Msk       (0x7UL << FLASH_ECCDR_DATA_ADDR_ECC_Pos)         /*!< 0x00070000 */
#define FLASH_ECCDR_DATA_ADDR_ECC           FLASH_ECCDR_DATA_ADDR_ECC_Msk                    /*!< DATA ECC error address
                                                                                                  */

/* *********************************  Bit definition for FLASH_WRP2R_CUR register  ********************************** */
#define FLASH_WRP2R_CUR_WRPSG2_Pos          (0U)
#define FLASH_WRP2R_CUR_WRPSG2_Msk          (0xFFFFFFFFUL << FLASH_WRP2R_CUR_WRPSG2_Pos)     /*!< 0xFFFFFFFF */
#define FLASH_WRP2R_CUR_WRPSG2              FLASH_WRP2R_CUR_WRPSG2_Msk                       /*!< Bank2 page protection
                                                                                                  option status byte */

/* *********************************  Bit definition for FLASH_WRP2R_PRG register  ********************************** */
#define FLASH_WRP2R_PRG_WRPSG2_Pos          (0U)
#define FLASH_WRP2R_PRG_WRPSG2_Msk          (0xFFFFFFFFUL << FLASH_WRP2R_PRG_WRPSG2_Pos)     /*!< 0xFFFFFFFF */
#define FLASH_WRP2R_PRG_WRPSG2              FLASH_WRP2R_PRG_WRPSG2_Msk                       /*!< Bank2 page protection
                                                                                                  option status byte */

/* *********************************  Bit definition for FLASH_HDP2R_CUR register  ********************************** */
#define FLASH_HDP2R_CUR_HDP2_STRT_Pos       (0U)
#define FLASH_HDP2R_CUR_HDP2_STRT_Msk       (0x3FUL << FLASH_HDP2R_CUR_HDP2_STRT_Pos)        /*!< 0x0000003F */
#define FLASH_HDP2R_CUR_HDP2_STRT           FLASH_HDP2R_CUR_HDP2_STRT_Msk                    /*!< Bank 2 HDPL barrier
                                                                                                 start set in number of
                                                                                                 8 Kbytes pages */
#define FLASH_HDP2R_CUR_HDP2_END_Pos        (16U)
#define FLASH_HDP2R_CUR_HDP2_END_Msk        (0x3FUL << FLASH_HDP2R_CUR_HDP2_END_Pos)         /*!< 0x003F0000 */
#define FLASH_HDP2R_CUR_HDP2_END            FLASH_HDP2R_CUR_HDP2_END_Msk                     /*!< Bank 2 HDPL barrier
                                                                                                 end set in number of
                                                                                                 8 Kbytes pages */

/* *********************************  Bit definition for FLASH_HDP2R_PRG register  ********************************** */
#define FLASH_HDP2R_PRG_HDP2_STRT_Pos       (0U)
#define FLASH_HDP2R_PRG_HDP2_STRT_Msk       (0x3FUL << FLASH_HDP2R_PRG_HDP2_STRT_Pos)        /*!< 0x0000003F */
#define FLASH_HDP2R_PRG_HDP2_STRT           FLASH_HDP2R_PRG_HDP2_STRT_Msk                    /*!< Bank 2 HDPL barrier
                                                                                                  start set in number of
                                                                                                  8 Kbytes pages */
#define FLASH_HDP2R_PRG_HDP2_END_Pos        (16U)
#define FLASH_HDP2R_PRG_HDP2_END_Msk        (0x3FUL << FLASH_HDP2R_PRG_HDP2_END_Pos)         /*!< 0x003F0000 */
#define FLASH_HDP2R_PRG_HDP2_END            FLASH_HDP2R_PRG_HDP2_END_Msk                     /*!< Bank 2 HDPL barrier
                                                                                                   end set in number of
                                                                                                   8 Kbytes pages */

/**********************************************************************************************************************/
/*                                                                                                                    */
/*                                         General Purpose IOs (GPIO)                                                 */
/*                                                                                                                    */
/**********************************************************************************************************************/
/* ************************************  Bit definition for GPIO_MODER register  ************************************ */
#define GPIO_MODER_MODE0_Pos       (0U)
#define GPIO_MODER_MODE0_Msk       (0x3UL << GPIO_MODER_MODE0_Pos)        /*!< 0x00000003 */
#define GPIO_MODER_MODE0           GPIO_MODER_MODE0_Msk                   /*!< Port x configuration I/O pin y */
#define GPIO_MODER_MODE0_0         (0x1UL << GPIO_MODER_MODE0_Pos)        /*!< 0x00000001 */
#define GPIO_MODER_MODE0_1         (0x2UL << GPIO_MODER_MODE0_Pos)        /*!< 0x00000002 */
#define GPIO_MODER_MODE1_Pos       (2U)
#define GPIO_MODER_MODE1_Msk       (0x3UL << GPIO_MODER_MODE1_Pos)        /*!< 0x0000000C */
#define GPIO_MODER_MODE1           GPIO_MODER_MODE1_Msk                   /*!< Port x configuration I/O pin y */
#define GPIO_MODER_MODE1_0         (0x1UL << GPIO_MODER_MODE1_Pos)        /*!< 0x00000004 */
#define GPIO_MODER_MODE1_1         (0x2UL << GPIO_MODER_MODE1_Pos)        /*!< 0x00000008 */
#define GPIO_MODER_MODE2_Pos       (4U)
#define GPIO_MODER_MODE2_Msk       (0x3UL << GPIO_MODER_MODE2_Pos)        /*!< 0x00000030 */
#define GPIO_MODER_MODE2           GPIO_MODER_MODE2_Msk                   /*!< Port x configuration I/O pin y */
#define GPIO_MODER_MODE2_0         (0x1UL << GPIO_MODER_MODE2_Pos)        /*!< 0x00000010 */
#define GPIO_MODER_MODE2_1         (0x2UL << GPIO_MODER_MODE2_Pos)        /*!< 0x00000020 */
#define GPIO_MODER_MODE3_Pos       (6U)
#define GPIO_MODER_MODE3_Msk       (0x3UL << GPIO_MODER_MODE3_Pos)        /*!< 0x000000C0 */
#define GPIO_MODER_MODE3           GPIO_MODER_MODE3_Msk                   /*!< Port x configuration I/O pin y */
#define GPIO_MODER_MODE3_0         (0x1UL << GPIO_MODER_MODE3_Pos)        /*!< 0x00000040 */
#define GPIO_MODER_MODE3_1         (0x2UL << GPIO_MODER_MODE3_Pos)        /*!< 0x00000080 */
#define GPIO_MODER_MODE4_Pos       (8U)
#define GPIO_MODER_MODE4_Msk       (0x3UL << GPIO_MODER_MODE4_Pos)        /*!< 0x00000300 */
#define GPIO_MODER_MODE4           GPIO_MODER_MODE4_Msk                   /*!< Port x configuration I/O pin y */
#define GPIO_MODER_MODE4_0         (0x1UL << GPIO_MODER_MODE4_Pos)        /*!< 0x00000100 */
#define GPIO_MODER_MODE4_1         (0x2UL << GPIO_MODER_MODE4_Pos)        /*!< 0x00000200 */
#define GPIO_MODER_MODE5_Pos       (10U)
#define GPIO_MODER_MODE5_Msk       (0x3UL << GPIO_MODER_MODE5_Pos)        /*!< 0x00000C00 */
#define GPIO_MODER_MODE5           GPIO_MODER_MODE5_Msk                   /*!< Port x configuration I/O pin y */
#define GPIO_MODER_MODE5_0         (0x1UL << GPIO_MODER_MODE5_Pos)        /*!< 0x00000400 */
#define GPIO_MODER_MODE5_1         (0x2UL << GPIO_MODER_MODE5_Pos)        /*!< 0x00000800 */
#define GPIO_MODER_MODE6_Pos       (12U)
#define GPIO_MODER_MODE6_Msk       (0x3UL << GPIO_MODER_MODE6_Pos)        /*!< 0x00003000 */
#define GPIO_MODER_MODE6           GPIO_MODER_MODE6_Msk                   /*!< Port x configuration I/O pin y */
#define GPIO_MODER_MODE6_0         (0x1UL << GPIO_MODER_MODE6_Pos)        /*!< 0x00001000 */
#define GPIO_MODER_MODE6_1         (0x2UL << GPIO_MODER_MODE6_Pos)        /*!< 0x00002000 */
#define GPIO_MODER_MODE7_Pos       (14U)
#define GPIO_MODER_MODE7_Msk       (0x3UL << GPIO_MODER_MODE7_Pos)        /*!< 0x0000C000 */
#define GPIO_MODER_MODE7           GPIO_MODER_MODE7_Msk                   /*!< Port x configuration I/O pin y */
#define GPIO_MODER_MODE7_0         (0x1UL << GPIO_MODER_MODE7_Pos)        /*!< 0x00004000 */
#define GPIO_MODER_MODE7_1         (0x2UL << GPIO_MODER_MODE7_Pos)        /*!< 0x00008000 */
#define GPIO_MODER_MODE8_Pos       (16U)
#define GPIO_MODER_MODE8_Msk       (0x3UL << GPIO_MODER_MODE8_Pos)        /*!< 0x00030000 */
#define GPIO_MODER_MODE8           GPIO_MODER_MODE8_Msk                   /*!< Port x configuration I/O pin y */
#define GPIO_MODER_MODE8_0         (0x1UL << GPIO_MODER_MODE8_Pos)        /*!< 0x00010000 */
#define GPIO_MODER_MODE8_1         (0x2UL << GPIO_MODER_MODE8_Pos)        /*!< 0x00020000 */
#define GPIO_MODER_MODE9_Pos       (18U)
#define GPIO_MODER_MODE9_Msk       (0x3UL << GPIO_MODER_MODE9_Pos)        /*!< 0x000C0000 */
#define GPIO_MODER_MODE9           GPIO_MODER_MODE9_Msk                   /*!< Port x configuration I/O pin y */
#define GPIO_MODER_MODE9_0         (0x1UL << GPIO_MODER_MODE9_Pos)        /*!< 0x00040000 */
#define GPIO_MODER_MODE9_1         (0x2UL << GPIO_MODER_MODE9_Pos)        /*!< 0x00080000 */
#define GPIO_MODER_MODE10_Pos      (20U)
#define GPIO_MODER_MODE10_Msk      (0x3UL << GPIO_MODER_MODE10_Pos)       /*!< 0x00300000 */
#define GPIO_MODER_MODE10          GPIO_MODER_MODE10_Msk                  /*!< Port x configuration I/O pin y */
#define GPIO_MODER_MODE10_0        (0x1UL << GPIO_MODER_MODE10_Pos)       /*!< 0x00100000 */
#define GPIO_MODER_MODE10_1        (0x2UL << GPIO_MODER_MODE10_Pos)       /*!< 0x00200000 */
#define GPIO_MODER_MODE11_Pos      (22U)
#define GPIO_MODER_MODE11_Msk      (0x3UL << GPIO_MODER_MODE11_Pos)       /*!< 0x00C00000 */
#define GPIO_MODER_MODE11          GPIO_MODER_MODE11_Msk                  /*!< Port x configuration I/O pin y */
#define GPIO_MODER_MODE11_0        (0x1UL << GPIO_MODER_MODE11_Pos)       /*!< 0x00400000 */
#define GPIO_MODER_MODE11_1        (0x2UL << GPIO_MODER_MODE11_Pos)       /*!< 0x00800000 */
#define GPIO_MODER_MODE12_Pos      (24U)
#define GPIO_MODER_MODE12_Msk      (0x3UL << GPIO_MODER_MODE12_Pos)       /*!< 0x03000000 */
#define GPIO_MODER_MODE12          GPIO_MODER_MODE12_Msk                  /*!< Port x configuration I/O pin y */
#define GPIO_MODER_MODE12_0        (0x1UL << GPIO_MODER_MODE12_Pos)       /*!< 0x01000000 */
#define GPIO_MODER_MODE12_1        (0x2UL << GPIO_MODER_MODE12_Pos)       /*!< 0x02000000 */
#define GPIO_MODER_MODE13_Pos      (26U)
#define GPIO_MODER_MODE13_Msk      (0x3UL << GPIO_MODER_MODE13_Pos)       /*!< 0x0C000000 */
#define GPIO_MODER_MODE13          GPIO_MODER_MODE13_Msk                  /*!< Port x configuration I/O pin y */
#define GPIO_MODER_MODE13_0        (0x1UL << GPIO_MODER_MODE13_Pos)       /*!< 0x04000000 */
#define GPIO_MODER_MODE13_1        (0x2UL << GPIO_MODER_MODE13_Pos)       /*!< 0x08000000 */
#define GPIO_MODER_MODE14_Pos      (28U)
#define GPIO_MODER_MODE14_Msk      (0x3UL << GPIO_MODER_MODE14_Pos)       /*!< 0x30000000 */
#define GPIO_MODER_MODE14          GPIO_MODER_MODE14_Msk                  /*!< Port x configuration I/O pin y */
#define GPIO_MODER_MODE14_0        (0x1UL << GPIO_MODER_MODE14_Pos)       /*!< 0x10000000 */
#define GPIO_MODER_MODE14_1        (0x2UL << GPIO_MODER_MODE14_Pos)       /*!< 0x20000000 */
#define GPIO_MODER_MODE15_Pos      (30U)
#define GPIO_MODER_MODE15_Msk      (0x3UL << GPIO_MODER_MODE15_Pos)       /*!< 0xC0000000 */
#define GPIO_MODER_MODE15          GPIO_MODER_MODE15_Msk                  /*!< Port x configuration I/O pin y */
#define GPIO_MODER_MODE15_0        (0x1UL << GPIO_MODER_MODE15_Pos)       /*!< 0x40000000 */
#define GPIO_MODER_MODE15_1        (0x2UL << GPIO_MODER_MODE15_Pos)       /*!< 0x80000000 */

/* ***********************************  Bit definition for GPIO_OTYPER register  ************************************ */
#define GPIO_OTYPER_OT0_Pos        (0U)
#define GPIO_OTYPER_OT0_Msk        (0x1UL << GPIO_OTYPER_OT0_Pos)         /*!< 0x00000001 */
#define GPIO_OTYPER_OT0            GPIO_OTYPER_OT0_Msk                    /*!< Port x configuration I/O pin y */
#define GPIO_OTYPER_OT1_Pos        (1U)
#define GPIO_OTYPER_OT1_Msk        (0x1UL << GPIO_OTYPER_OT1_Pos)         /*!< 0x00000002 */
#define GPIO_OTYPER_OT1            GPIO_OTYPER_OT1_Msk                    /*!< Port x configuration I/O pin y */
#define GPIO_OTYPER_OT2_Pos        (2U)
#define GPIO_OTYPER_OT2_Msk        (0x1UL << GPIO_OTYPER_OT2_Pos)         /*!< 0x00000004 */
#define GPIO_OTYPER_OT2            GPIO_OTYPER_OT2_Msk                    /*!< Port x configuration I/O pin y */
#define GPIO_OTYPER_OT3_Pos        (3U)
#define GPIO_OTYPER_OT3_Msk        (0x1UL << GPIO_OTYPER_OT3_Pos)         /*!< 0x00000008 */
#define GPIO_OTYPER_OT3            GPIO_OTYPER_OT3_Msk                    /*!< Port x configuration I/O pin y */
#define GPIO_OTYPER_OT4_Pos        (4U)
#define GPIO_OTYPER_OT4_Msk        (0x1UL << GPIO_OTYPER_OT4_Pos)         /*!< 0x00000010 */
#define GPIO_OTYPER_OT4            GPIO_OTYPER_OT4_Msk                    /*!< Port x configuration I/O pin y */
#define GPIO_OTYPER_OT5_Pos        (5U)
#define GPIO_OTYPER_OT5_Msk        (0x1UL << GPIO_OTYPER_OT5_Pos)         /*!< 0x00000020 */
#define GPIO_OTYPER_OT5            GPIO_OTYPER_OT5_Msk                    /*!< Port x configuration I/O pin y */
#define GPIO_OTYPER_OT6_Pos        (6U)
#define GPIO_OTYPER_OT6_Msk        (0x1UL << GPIO_OTYPER_OT6_Pos)         /*!< 0x00000040 */
#define GPIO_OTYPER_OT6            GPIO_OTYPER_OT6_Msk                    /*!< Port x configuration I/O pin y */
#define GPIO_OTYPER_OT7_Pos        (7U)
#define GPIO_OTYPER_OT7_Msk        (0x1UL << GPIO_OTYPER_OT7_Pos)         /*!< 0x00000080 */
#define GPIO_OTYPER_OT7            GPIO_OTYPER_OT7_Msk                    /*!< Port x configuration I/O pin y */
#define GPIO_OTYPER_OT8_Pos        (8U)
#define GPIO_OTYPER_OT8_Msk        (0x1UL << GPIO_OTYPER_OT8_Pos)         /*!< 0x00000100 */
#define GPIO_OTYPER_OT8            GPIO_OTYPER_OT8_Msk                    /*!< Port x configuration I/O pin y */
#define GPIO_OTYPER_OT9_Pos        (9U)
#define GPIO_OTYPER_OT9_Msk        (0x1UL << GPIO_OTYPER_OT9_Pos)         /*!< 0x00000200 */
#define GPIO_OTYPER_OT9            GPIO_OTYPER_OT9_Msk                    /*!< Port x configuration I/O pin y */
#define GPIO_OTYPER_OT10_Pos       (10U)
#define GPIO_OTYPER_OT10_Msk       (0x1UL << GPIO_OTYPER_OT10_Pos)        /*!< 0x00000400 */
#define GPIO_OTYPER_OT10           GPIO_OTYPER_OT10_Msk                   /*!< Port x configuration I/O pin y */
#define GPIO_OTYPER_OT11_Pos       (11U)
#define GPIO_OTYPER_OT11_Msk       (0x1UL << GPIO_OTYPER_OT11_Pos)        /*!< 0x00000800 */
#define GPIO_OTYPER_OT11           GPIO_OTYPER_OT11_Msk                   /*!< Port x configuration I/O pin y */
#define GPIO_OTYPER_OT12_Pos       (12U)
#define GPIO_OTYPER_OT12_Msk       (0x1UL << GPIO_OTYPER_OT12_Pos)        /*!< 0x00001000 */
#define GPIO_OTYPER_OT12           GPIO_OTYPER_OT12_Msk                   /*!< Port x configuration I/O pin y */
#define GPIO_OTYPER_OT13_Pos       (13U)
#define GPIO_OTYPER_OT13_Msk       (0x1UL << GPIO_OTYPER_OT13_Pos)        /*!< 0x00002000 */
#define GPIO_OTYPER_OT13           GPIO_OTYPER_OT13_Msk                   /*!< Port x configuration I/O pin y */
#define GPIO_OTYPER_OT14_Pos       (14U)
#define GPIO_OTYPER_OT14_Msk       (0x1UL << GPIO_OTYPER_OT14_Pos)        /*!< 0x00004000 */
#define GPIO_OTYPER_OT14           GPIO_OTYPER_OT14_Msk                   /*!< Port x configuration I/O pin y */
#define GPIO_OTYPER_OT15_Pos       (15U)
#define GPIO_OTYPER_OT15_Msk       (0x1UL << GPIO_OTYPER_OT15_Pos)        /*!< 0x00008000 */
#define GPIO_OTYPER_OT15           GPIO_OTYPER_OT15_Msk                   /*!< Port x configuration I/O pin y */

/* ***********************************  Bit definition for GPIO_OSPEEDR register  *********************************** */
#define GPIO_OSPEEDR_OSPEED0_Pos   (0U)
#define GPIO_OSPEEDR_OSPEED0_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)   /*!< 0x00000003 */
#define GPIO_OSPEEDR_OSPEED0       GPIO_OSPEEDR_OSPEED0_Msk              /*!< Port x configuration I/O pin y */
#define GPIO_OSPEEDR_OSPEED0_0     (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)   /*!< 0x00000001 */
#define GPIO_OSPEEDR_OSPEED0_1     (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)   /*!< 0x00000002 */
#define GPIO_OSPEEDR_OSPEED1_Pos   (2U)
#define GPIO_OSPEEDR_OSPEED1_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)   /*!< 0x0000000C */
#define GPIO_OSPEEDR_OSPEED1       GPIO_OSPEEDR_OSPEED1_Msk              /*!< Port x configuration I/O pin y */
#define GPIO_OSPEEDR_OSPEED1_0     (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)   /*!< 0x00000004 */
#define GPIO_OSPEEDR_OSPEED1_1     (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)   /*!< 0x00000008 */
#define GPIO_OSPEEDR_OSPEED2_Pos   (4U)
#define GPIO_OSPEEDR_OSPEED2_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)   /*!< 0x00000030 */
#define GPIO_OSPEEDR_OSPEED2       GPIO_OSPEEDR_OSPEED2_Msk              /*!< Port x configuration I/O pin y */
#define GPIO_OSPEEDR_OSPEED2_0     (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)   /*!< 0x00000010 */
#define GPIO_OSPEEDR_OSPEED2_1     (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)   /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEED3_Pos   (6U)
#define GPIO_OSPEEDR_OSPEED3_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)   /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEED3       GPIO_OSPEEDR_OSPEED3_Msk              /*!< Port x configuration I/O pin y */
#define GPIO_OSPEEDR_OSPEED3_0     (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)   /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEED3_1     (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)   /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEED4_Pos   (8U)
#define GPIO_OSPEEDR_OSPEED4_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)   /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEED4       GPIO_OSPEEDR_OSPEED4_Msk              /*!< Port x configuration I/O pin y */
#define GPIO_OSPEEDR_OSPEED4_0     (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)   /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEED4_1     (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)   /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEED5_Pos   (10U)
#define GPIO_OSPEEDR_OSPEED5_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)   /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEED5       GPIO_OSPEEDR_OSPEED5_Msk              /*!< Port x configuration I/O pin y */
#define GPIO_OSPEEDR_OSPEED5_0     (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)   /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEED5_1     (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)   /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEED6_Pos   (12U)
#define GPIO_OSPEEDR_OSPEED6_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)   /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEED6       GPIO_OSPEEDR_OSPEED6_Msk              /*!< Port x configuration I/O pin y */
#define GPIO_OSPEEDR_OSPEED6_0     (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)   /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEED6_1     (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)   /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEED7_Pos   (14U)
#define GPIO_OSPEEDR_OSPEED7_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)   /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEED7       GPIO_OSPEEDR_OSPEED7_Msk              /*!< Port x configuration I/O pin y */
#define GPIO_OSPEEDR_OSPEED7_0     (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)   /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEED7_1     (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)   /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEED8_Pos   (16U)
#define GPIO_OSPEEDR_OSPEED8_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)   /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEED8       GPIO_OSPEEDR_OSPEED8_Msk              /*!< Port x configuration I/O pin y */
#define GPIO_OSPEEDR_OSPEED8_0     (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)   /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEED8_1     (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)   /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEED9_Pos   (18U)
#define GPIO_OSPEEDR_OSPEED9_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)   /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEED9       GPIO_OSPEEDR_OSPEED9_Msk              /*!< Port x configuration I/O pin y */
#define GPIO_OSPEEDR_OSPEED9_0     (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)   /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEED9_1     (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)   /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEED10_Pos  (20U)
#define GPIO_OSPEEDR_OSPEED10_Msk  (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)  /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEED10      GPIO_OSPEEDR_OSPEED10_Msk             /*!< Port x configuration I/O pin y */
#define GPIO_OSPEEDR_OSPEED10_0    (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)  /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEED10_1    (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)  /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEED11_Pos  (22U)
#define GPIO_OSPEEDR_OSPEED11_Msk  (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)  /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEED11      GPIO_OSPEEDR_OSPEED11_Msk             /*!< Port x configuration I/O pin y */
#define GPIO_OSPEEDR_OSPEED11_0    (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)  /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEED11_1    (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)  /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEED12_Pos  (24U)
#define GPIO_OSPEEDR_OSPEED12_Msk  (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)  /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEED12      GPIO_OSPEEDR_OSPEED12_Msk             /*!< Port x configuration I/O pin y */
#define GPIO_OSPEEDR_OSPEED12_0    (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)  /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEED12_1    (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)  /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEED13_Pos  (26U)
#define GPIO_OSPEEDR_OSPEED13_Msk  (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)  /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEED13      GPIO_OSPEEDR_OSPEED13_Msk             /*!< Port x configuration I/O pin y */
#define GPIO_OSPEEDR_OSPEED13_0    (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)  /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEED13_1    (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)  /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEED14_Pos  (28U)
#define GPIO_OSPEEDR_OSPEED14_Msk  (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)  /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEED14      GPIO_OSPEEDR_OSPEED14_Msk             /*!< Port x configuration I/O pin y */
#define GPIO_OSPEEDR_OSPEED14_0    (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)  /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEED14_1    (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)  /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEED15_Pos  (30U)
#define GPIO_OSPEEDR_OSPEED15_Msk  (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)  /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEED15      GPIO_OSPEEDR_OSPEED15_Msk             /*!< Port x configuration I/O pin y */
#define GPIO_OSPEEDR_OSPEED15_0    (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)  /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEED15_1    (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)  /*!< 0x80000000 */

/* ************************************  Bit definition for GPIO_PUPDR register  ************************************ */
#define GPIO_PUPDR_PUPD0_Pos       (0U)
#define GPIO_PUPDR_PUPD0_Msk       (0x3UL << GPIO_PUPDR_PUPD0_Pos)       /*!< 0x00000003 */
#define GPIO_PUPDR_PUPD0           GPIO_PUPDR_PUPD0_Msk                  /*!< Port x configuration I/O pin y */
#define GPIO_PUPDR_PUPD0_0         (0x1UL << GPIO_PUPDR_PUPD0_Pos)       /*!< 0x00000001 */
#define GPIO_PUPDR_PUPD0_1         (0x2UL << GPIO_PUPDR_PUPD0_Pos)       /*!< 0x00000002 */
#define GPIO_PUPDR_PUPD1_Pos       (2U)
#define GPIO_PUPDR_PUPD1_Msk       (0x3UL << GPIO_PUPDR_PUPD1_Pos)       /*!< 0x0000000C */
#define GPIO_PUPDR_PUPD1           GPIO_PUPDR_PUPD1_Msk                  /*!< Port x configuration I/O pin y */
#define GPIO_PUPDR_PUPD1_0         (0x1UL << GPIO_PUPDR_PUPD1_Pos)       /*!< 0x00000004 */
#define GPIO_PUPDR_PUPD1_1         (0x2UL << GPIO_PUPDR_PUPD1_Pos)       /*!< 0x00000008 */
#define GPIO_PUPDR_PUPD2_Pos       (4U)
#define GPIO_PUPDR_PUPD2_Msk       (0x3UL << GPIO_PUPDR_PUPD2_Pos)       /*!< 0x00000030 */
#define GPIO_PUPDR_PUPD2           GPIO_PUPDR_PUPD2_Msk                  /*!< Port x configuration I/O pin y */
#define GPIO_PUPDR_PUPD2_0         (0x1UL << GPIO_PUPDR_PUPD2_Pos)       /*!< 0x00000010 */
#define GPIO_PUPDR_PUPD2_1         (0x2UL << GPIO_PUPDR_PUPD2_Pos)       /*!< 0x00000020 */
#define GPIO_PUPDR_PUPD3_Pos       (6U)
#define GPIO_PUPDR_PUPD3_Msk       (0x3UL << GPIO_PUPDR_PUPD3_Pos)       /*!< 0x000000C0 */
#define GPIO_PUPDR_PUPD3           GPIO_PUPDR_PUPD3_Msk                  /*!< Port x configuration I/O pin y */
#define GPIO_PUPDR_PUPD3_0         (0x1UL << GPIO_PUPDR_PUPD3_Pos)       /*!< 0x00000040 */
#define GPIO_PUPDR_PUPD3_1         (0x2UL << GPIO_PUPDR_PUPD3_Pos)       /*!< 0x00000080 */
#define GPIO_PUPDR_PUPD4_Pos       (8U)
#define GPIO_PUPDR_PUPD4_Msk       (0x3UL << GPIO_PUPDR_PUPD4_Pos)       /*!< 0x00000300 */
#define GPIO_PUPDR_PUPD4           GPIO_PUPDR_PUPD4_Msk                  /*!< Port x configuration I/O pin y */
#define GPIO_PUPDR_PUPD4_0         (0x1UL << GPIO_PUPDR_PUPD4_Pos)       /*!< 0x00000100 */
#define GPIO_PUPDR_PUPD4_1         (0x2UL << GPIO_PUPDR_PUPD4_Pos)       /*!< 0x00000200 */
#define GPIO_PUPDR_PUPD5_Pos       (10U)
#define GPIO_PUPDR_PUPD5_Msk       (0x3UL << GPIO_PUPDR_PUPD5_Pos)       /*!< 0x00000C00 */
#define GPIO_PUPDR_PUPD5           GPIO_PUPDR_PUPD5_Msk                  /*!< Port x configuration I/O pin y */
#define GPIO_PUPDR_PUPD5_0         (0x1UL << GPIO_PUPDR_PUPD5_Pos)       /*!< 0x00000400 */
#define GPIO_PUPDR_PUPD5_1         (0x2UL << GPIO_PUPDR_PUPD5_Pos)       /*!< 0x00000800 */
#define GPIO_PUPDR_PUPD6_Pos       (12U)
#define GPIO_PUPDR_PUPD6_Msk       (0x3UL << GPIO_PUPDR_PUPD6_Pos)       /*!< 0x00003000 */
#define GPIO_PUPDR_PUPD6           GPIO_PUPDR_PUPD6_Msk                  /*!< Port x configuration I/O pin y */
#define GPIO_PUPDR_PUPD6_0         (0x1UL << GPIO_PUPDR_PUPD6_Pos)       /*!< 0x00001000 */
#define GPIO_PUPDR_PUPD6_1         (0x2UL << GPIO_PUPDR_PUPD6_Pos)       /*!< 0x00002000 */
#define GPIO_PUPDR_PUPD7_Pos       (14U)
#define GPIO_PUPDR_PUPD7_Msk       (0x3UL << GPIO_PUPDR_PUPD7_Pos)       /*!< 0x0000C000 */
#define GPIO_PUPDR_PUPD7           GPIO_PUPDR_PUPD7_Msk                  /*!< Port x configuration I/O pin y */
#define GPIO_PUPDR_PUPD7_0         (0x1UL << GPIO_PUPDR_PUPD7_Pos)       /*!< 0x00004000 */
#define GPIO_PUPDR_PUPD7_1         (0x2UL << GPIO_PUPDR_PUPD7_Pos)       /*!< 0x00008000 */
#define GPIO_PUPDR_PUPD8_Pos       (16U)
#define GPIO_PUPDR_PUPD8_Msk       (0x3UL << GPIO_PUPDR_PUPD8_Pos)       /*!< 0x00030000 */
#define GPIO_PUPDR_PUPD8           GPIO_PUPDR_PUPD8_Msk                  /*!< Port x configuration I/O pin y */
#define GPIO_PUPDR_PUPD8_0         (0x1UL << GPIO_PUPDR_PUPD8_Pos)       /*!< 0x00010000 */
#define GPIO_PUPDR_PUPD8_1         (0x2UL << GPIO_PUPDR_PUPD8_Pos)       /*!< 0x00020000 */
#define GPIO_PUPDR_PUPD9_Pos       (18U)
#define GPIO_PUPDR_PUPD9_Msk       (0x3UL << GPIO_PUPDR_PUPD9_Pos)       /*!< 0x000C0000 */
#define GPIO_PUPDR_PUPD9           GPIO_PUPDR_PUPD9_Msk                  /*!< Port x configuration I/O pin y */
#define GPIO_PUPDR_PUPD9_0         (0x1UL << GPIO_PUPDR_PUPD9_Pos)       /*!< 0x00040000 */
#define GPIO_PUPDR_PUPD9_1         (0x2UL << GPIO_PUPDR_PUPD9_Pos)       /*!< 0x00080000 */
#define GPIO_PUPDR_PUPD10_Pos      (20U)
#define GPIO_PUPDR_PUPD10_Msk      (0x3UL << GPIO_PUPDR_PUPD10_Pos)      /*!< 0x00300000 */
#define GPIO_PUPDR_PUPD10          GPIO_PUPDR_PUPD10_Msk                 /*!< Port x configuration I/O pin y */
#define GPIO_PUPDR_PUPD10_0        (0x1UL << GPIO_PUPDR_PUPD10_Pos)      /*!< 0x00100000 */
#define GPIO_PUPDR_PUPD10_1        (0x2UL << GPIO_PUPDR_PUPD10_Pos)      /*!< 0x00200000 */
#define GPIO_PUPDR_PUPD11_Pos      (22U)
#define GPIO_PUPDR_PUPD11_Msk      (0x3UL << GPIO_PUPDR_PUPD11_Pos)      /*!< 0x00C00000 */
#define GPIO_PUPDR_PUPD11          GPIO_PUPDR_PUPD11_Msk                 /*!< Port x configuration I/O pin y */
#define GPIO_PUPDR_PUPD11_0        (0x1UL << GPIO_PUPDR_PUPD11_Pos)      /*!< 0x00400000 */
#define GPIO_PUPDR_PUPD11_1        (0x2UL << GPIO_PUPDR_PUPD11_Pos)      /*!< 0x00800000 */
#define GPIO_PUPDR_PUPD12_Pos      (24U)
#define GPIO_PUPDR_PUPD12_Msk      (0x3UL << GPIO_PUPDR_PUPD12_Pos)      /*!< 0x03000000 */
#define GPIO_PUPDR_PUPD12          GPIO_PUPDR_PUPD12_Msk                 /*!< Port x configuration I/O pin y */
#define GPIO_PUPDR_PUPD12_0        (0x1UL << GPIO_PUPDR_PUPD12_Pos)      /*!< 0x01000000 */
#define GPIO_PUPDR_PUPD12_1        (0x2UL << GPIO_PUPDR_PUPD12_Pos)      /*!< 0x02000000 */
#define GPIO_PUPDR_PUPD13_Pos      (26U)
#define GPIO_PUPDR_PUPD13_Msk      (0x3UL << GPIO_PUPDR_PUPD13_Pos)      /*!< 0x0C000000 */
#define GPIO_PUPDR_PUPD13          GPIO_PUPDR_PUPD13_Msk                 /*!< Port x configuration I/O pin y */
#define GPIO_PUPDR_PUPD13_0        (0x1UL << GPIO_PUPDR_PUPD13_Pos)      /*!< 0x04000000 */
#define GPIO_PUPDR_PUPD13_1        (0x2UL << GPIO_PUPDR_PUPD13_Pos)      /*!< 0x08000000 */
#define GPIO_PUPDR_PUPD14_Pos      (28U)
#define GPIO_PUPDR_PUPD14_Msk      (0x3UL << GPIO_PUPDR_PUPD14_Pos)      /*!< 0x30000000 */
#define GPIO_PUPDR_PUPD14          GPIO_PUPDR_PUPD14_Msk                 /*!< Port x configuration I/O pin y */
#define GPIO_PUPDR_PUPD14_0        (0x1UL << GPIO_PUPDR_PUPD14_Pos)      /*!< 0x10000000 */
#define GPIO_PUPDR_PUPD14_1        (0x2UL << GPIO_PUPDR_PUPD14_Pos)      /*!< 0x20000000 */
#define GPIO_PUPDR_PUPD15_Pos      (30U)
#define GPIO_PUPDR_PUPD15_Msk      (0x3UL << GPIO_PUPDR_PUPD15_Pos)      /*!< 0xC0000000 */
#define GPIO_PUPDR_PUPD15          GPIO_PUPDR_PUPD15_Msk                 /*!< Port x configuration I/O pin y */
#define GPIO_PUPDR_PUPD15_0        (0x1UL << GPIO_PUPDR_PUPD15_Pos)      /*!< 0x40000000 */
#define GPIO_PUPDR_PUPD15_1        (0x2UL << GPIO_PUPDR_PUPD15_Pos)      /*!< 0x80000000 */

/* *************************************  Bit definition for GPIO_IDR register  ************************************* */
#define GPIO_IDR_ID0_Pos           (0U)
#define GPIO_IDR_ID0_Msk           (0x1UL << GPIO_IDR_ID0_Pos)           /*!< 0x00000001 */
#define GPIO_IDR_ID0               GPIO_IDR_ID0_Msk                      /*!< Port x input data I/O pin y */
#define GPIO_IDR_ID1_Pos           (1U)
#define GPIO_IDR_ID1_Msk           (0x1UL << GPIO_IDR_ID1_Pos)           /*!< 0x00000002 */
#define GPIO_IDR_ID1               GPIO_IDR_ID1_Msk                      /*!< Port x input data I/O pin y */
#define GPIO_IDR_ID2_Pos           (2U)
#define GPIO_IDR_ID2_Msk           (0x1UL << GPIO_IDR_ID2_Pos)           /*!< 0x00000004 */
#define GPIO_IDR_ID2               GPIO_IDR_ID2_Msk                      /*!< Port x input data I/O pin y */
#define GPIO_IDR_ID3_Pos           (3U)
#define GPIO_IDR_ID3_Msk           (0x1UL << GPIO_IDR_ID3_Pos)           /*!< 0x00000008 */
#define GPIO_IDR_ID3               GPIO_IDR_ID3_Msk                      /*!< Port x input data I/O pin y */
#define GPIO_IDR_ID4_Pos           (4U)
#define GPIO_IDR_ID4_Msk           (0x1UL << GPIO_IDR_ID4_Pos)           /*!< 0x00000010 */
#define GPIO_IDR_ID4               GPIO_IDR_ID4_Msk                      /*!< Port x input data I/O pin y */
#define GPIO_IDR_ID5_Pos           (5U)
#define GPIO_IDR_ID5_Msk           (0x1UL << GPIO_IDR_ID5_Pos)           /*!< 0x00000020 */
#define GPIO_IDR_ID5               GPIO_IDR_ID5_Msk                      /*!< Port x input data I/O pin y */
#define GPIO_IDR_ID6_Pos           (6U)
#define GPIO_IDR_ID6_Msk           (0x1UL << GPIO_IDR_ID6_Pos)           /*!< 0x00000040 */
#define GPIO_IDR_ID6               GPIO_IDR_ID6_Msk                      /*!< Port x input data I/O pin y */
#define GPIO_IDR_ID7_Pos           (7U)
#define GPIO_IDR_ID7_Msk           (0x1UL << GPIO_IDR_ID7_Pos)           /*!< 0x00000080 */
#define GPIO_IDR_ID7               GPIO_IDR_ID7_Msk                      /*!< Port x input data I/O pin y */
#define GPIO_IDR_ID8_Pos           (8U)
#define GPIO_IDR_ID8_Msk           (0x1UL << GPIO_IDR_ID8_Pos)           /*!< 0x00000100 */
#define GPIO_IDR_ID8               GPIO_IDR_ID8_Msk                      /*!< Port x input data I/O pin y */
#define GPIO_IDR_ID9_Pos           (9U)
#define GPIO_IDR_ID9_Msk           (0x1UL << GPIO_IDR_ID9_Pos)           /*!< 0x00000200 */
#define GPIO_IDR_ID9               GPIO_IDR_ID9_Msk                      /*!< Port x input data I/O pin y */
#define GPIO_IDR_ID10_Pos          (10U)
#define GPIO_IDR_ID10_Msk          (0x1UL << GPIO_IDR_ID10_Pos)          /*!< 0x00000400 */
#define GPIO_IDR_ID10              GPIO_IDR_ID10_Msk                     /*!< Port x input data I/O pin y */
#define GPIO_IDR_ID11_Pos          (11U)
#define GPIO_IDR_ID11_Msk          (0x1UL << GPIO_IDR_ID11_Pos)          /*!< 0x00000800 */
#define GPIO_IDR_ID11              GPIO_IDR_ID11_Msk                     /*!< Port x input data I/O pin y */
#define GPIO_IDR_ID12_Pos          (12U)
#define GPIO_IDR_ID12_Msk          (0x1UL << GPIO_IDR_ID12_Pos)          /*!< 0x00001000 */
#define GPIO_IDR_ID12              GPIO_IDR_ID12_Msk                     /*!< Port x input data I/O pin y */
#define GPIO_IDR_ID13_Pos          (13U)
#define GPIO_IDR_ID13_Msk          (0x1UL << GPIO_IDR_ID13_Pos)          /*!< 0x00002000 */
#define GPIO_IDR_ID13              GPIO_IDR_ID13_Msk                     /*!< Port x input data I/O pin y */
#define GPIO_IDR_ID14_Pos          (14U)
#define GPIO_IDR_ID14_Msk          (0x1UL << GPIO_IDR_ID14_Pos)          /*!< 0x00004000 */
#define GPIO_IDR_ID14              GPIO_IDR_ID14_Msk                     /*!< Port x input data I/O pin y */
#define GPIO_IDR_ID15_Pos          (15U)
#define GPIO_IDR_ID15_Msk          (0x1UL << GPIO_IDR_ID15_Pos)          /*!< 0x00008000 */
#define GPIO_IDR_ID15              GPIO_IDR_ID15_Msk                     /*!< Port x input data I/O pin y */

/* *************************************  Bit definition for GPIO_ODR register  ************************************* */
#define GPIO_ODR_OD0_Pos           (0U)
#define GPIO_ODR_OD0_Msk           (0x1UL << GPIO_ODR_OD0_Pos)           /*!< 0x00000001 */
#define GPIO_ODR_OD0               GPIO_ODR_OD0_Msk                      /*!< Port output data I/O pin y */
#define GPIO_ODR_OD1_Pos           (1U)
#define GPIO_ODR_OD1_Msk           (0x1UL << GPIO_ODR_OD1_Pos)           /*!< 0x00000002 */
#define GPIO_ODR_OD1               GPIO_ODR_OD1_Msk                      /*!< Port output data I/O pin y */
#define GPIO_ODR_OD2_Pos           (2U)
#define GPIO_ODR_OD2_Msk           (0x1UL << GPIO_ODR_OD2_Pos)           /*!< 0x00000004 */
#define GPIO_ODR_OD2               GPIO_ODR_OD2_Msk                      /*!< Port output data I/O pin y */
#define GPIO_ODR_OD3_Pos           (3U)
#define GPIO_ODR_OD3_Msk           (0x1UL << GPIO_ODR_OD3_Pos)           /*!< 0x00000008 */
#define GPIO_ODR_OD3               GPIO_ODR_OD3_Msk                      /*!< Port output data I/O pin y */
#define GPIO_ODR_OD4_Pos           (4U)
#define GPIO_ODR_OD4_Msk           (0x1UL << GPIO_ODR_OD4_Pos)           /*!< 0x00000010 */
#define GPIO_ODR_OD4               GPIO_ODR_OD4_Msk                      /*!< Port output data I/O pin y */
#define GPIO_ODR_OD5_Pos           (5U)
#define GPIO_ODR_OD5_Msk           (0x1UL << GPIO_ODR_OD5_Pos)           /*!< 0x00000020 */
#define GPIO_ODR_OD5               GPIO_ODR_OD5_Msk                      /*!< Port output data I/O pin y */
#define GPIO_ODR_OD6_Pos           (6U)
#define GPIO_ODR_OD6_Msk           (0x1UL << GPIO_ODR_OD6_Pos)           /*!< 0x00000040 */
#define GPIO_ODR_OD6               GPIO_ODR_OD6_Msk                      /*!< Port output data I/O pin y */
#define GPIO_ODR_OD7_Pos           (7U)
#define GPIO_ODR_OD7_Msk           (0x1UL << GPIO_ODR_OD7_Pos)           /*!< 0x00000080 */
#define GPIO_ODR_OD7               GPIO_ODR_OD7_Msk                      /*!< Port output data I/O pin y */
#define GPIO_ODR_OD8_Pos           (8U)
#define GPIO_ODR_OD8_Msk           (0x1UL << GPIO_ODR_OD8_Pos)           /*!< 0x00000100 */
#define GPIO_ODR_OD8               GPIO_ODR_OD8_Msk                      /*!< Port output data I/O pin y */
#define GPIO_ODR_OD9_Pos           (9U)
#define GPIO_ODR_OD9_Msk           (0x1UL << GPIO_ODR_OD9_Pos)           /*!< 0x00000200 */
#define GPIO_ODR_OD9               GPIO_ODR_OD9_Msk                      /*!< Port output data I/O pin y */
#define GPIO_ODR_OD10_Pos          (10U)
#define GPIO_ODR_OD10_Msk          (0x1UL << GPIO_ODR_OD10_Pos)          /*!< 0x00000400 */
#define GPIO_ODR_OD10              GPIO_ODR_OD10_Msk                     /*!< Port output data I/O pin y */
#define GPIO_ODR_OD11_Pos          (11U)
#define GPIO_ODR_OD11_Msk          (0x1UL << GPIO_ODR_OD11_Pos)          /*!< 0x00000800 */
#define GPIO_ODR_OD11              GPIO_ODR_OD11_Msk                     /*!< Port output data I/O pin y */
#define GPIO_ODR_OD12_Pos          (12U)
#define GPIO_ODR_OD12_Msk          (0x1UL << GPIO_ODR_OD12_Pos)          /*!< 0x00001000 */
#define GPIO_ODR_OD12              GPIO_ODR_OD12_Msk                     /*!< Port output data I/O pin y */
#define GPIO_ODR_OD13_Pos          (13U)
#define GPIO_ODR_OD13_Msk          (0x1UL << GPIO_ODR_OD13_Pos)          /*!< 0x00002000 */
#define GPIO_ODR_OD13              GPIO_ODR_OD13_Msk                     /*!< Port output data I/O pin y */
#define GPIO_ODR_OD14_Pos          (14U)
#define GPIO_ODR_OD14_Msk          (0x1UL << GPIO_ODR_OD14_Pos)          /*!< 0x00004000 */
#define GPIO_ODR_OD14              GPIO_ODR_OD14_Msk                     /*!< Port output data I/O pin y */
#define GPIO_ODR_OD15_Pos          (15U)
#define GPIO_ODR_OD15_Msk          (0x1UL << GPIO_ODR_OD15_Pos)          /*!< 0x00008000 */
#define GPIO_ODR_OD15              GPIO_ODR_OD15_Msk                     /*!< Port output data I/O pin y */

/* ************************************  Bit definition for GPIO_BSRR register  ************************************* */
#define GPIO_BSRR_BS0_Pos          (0U)
#define GPIO_BSRR_BS0_Msk          (0x1UL << GPIO_BSRR_BS0_Pos)          /*!< 0x00000001 */
#define GPIO_BSRR_BS0              GPIO_BSRR_BS0_Msk                     /*!< Port x set I/O pin y */
#define GPIO_BSRR_BS1_Pos          (1U)
#define GPIO_BSRR_BS1_Msk          (0x1UL << GPIO_BSRR_BS1_Pos)          /*!< 0x00000002 */
#define GPIO_BSRR_BS1              GPIO_BSRR_BS1_Msk                     /*!< Port x set I/O pin y */
#define GPIO_BSRR_BS2_Pos          (2U)
#define GPIO_BSRR_BS2_Msk          (0x1UL << GPIO_BSRR_BS2_Pos)          /*!< 0x00000004 */
#define GPIO_BSRR_BS2              GPIO_BSRR_BS2_Msk                     /*!< Port x set I/O pin y */
#define GPIO_BSRR_BS3_Pos          (3U)
#define GPIO_BSRR_BS3_Msk          (0x1UL << GPIO_BSRR_BS3_Pos)          /*!< 0x00000008 */
#define GPIO_BSRR_BS3              GPIO_BSRR_BS3_Msk                     /*!< Port x set I/O pin y */
#define GPIO_BSRR_BS4_Pos          (4U)
#define GPIO_BSRR_BS4_Msk          (0x1UL << GPIO_BSRR_BS4_Pos)          /*!< 0x00000010 */
#define GPIO_BSRR_BS4              GPIO_BSRR_BS4_Msk                     /*!< Port x set I/O pin y */
#define GPIO_BSRR_BS5_Pos          (5U)
#define GPIO_BSRR_BS5_Msk          (0x1UL << GPIO_BSRR_BS5_Pos)          /*!< 0x00000020 */
#define GPIO_BSRR_BS5              GPIO_BSRR_BS5_Msk                     /*!< Port x set I/O pin y */
#define GPIO_BSRR_BS6_Pos          (6U)
#define GPIO_BSRR_BS6_Msk          (0x1UL << GPIO_BSRR_BS6_Pos)          /*!< 0x00000040 */
#define GPIO_BSRR_BS6              GPIO_BSRR_BS6_Msk                     /*!< Port x set I/O pin y */
#define GPIO_BSRR_BS7_Pos          (7U)
#define GPIO_BSRR_BS7_Msk          (0x1UL << GPIO_BSRR_BS7_Pos)          /*!< 0x00000080 */
#define GPIO_BSRR_BS7              GPIO_BSRR_BS7_Msk                     /*!< Port x set I/O pin y */
#define GPIO_BSRR_BS8_Pos          (8U)
#define GPIO_BSRR_BS8_Msk          (0x1UL << GPIO_BSRR_BS8_Pos)          /*!< 0x00000100 */
#define GPIO_BSRR_BS8              GPIO_BSRR_BS8_Msk                     /*!< Port x set I/O pin y */
#define GPIO_BSRR_BS9_Pos          (9U)
#define GPIO_BSRR_BS9_Msk          (0x1UL << GPIO_BSRR_BS9_Pos)          /*!< 0x00000200 */
#define GPIO_BSRR_BS9              GPIO_BSRR_BS9_Msk                     /*!< Port x set I/O pin y */
#define GPIO_BSRR_BS10_Pos         (10U)
#define GPIO_BSRR_BS10_Msk         (0x1UL << GPIO_BSRR_BS10_Pos)         /*!< 0x00000400 */
#define GPIO_BSRR_BS10             GPIO_BSRR_BS10_Msk                    /*!< Port x set I/O pin y */
#define GPIO_BSRR_BS11_Pos         (11U)
#define GPIO_BSRR_BS11_Msk         (0x1UL << GPIO_BSRR_BS11_Pos)         /*!< 0x00000800 */
#define GPIO_BSRR_BS11             GPIO_BSRR_BS11_Msk                    /*!< Port x set I/O pin y */
#define GPIO_BSRR_BS12_Pos         (12U)
#define GPIO_BSRR_BS12_Msk         (0x1UL << GPIO_BSRR_BS12_Pos)         /*!< 0x00001000 */
#define GPIO_BSRR_BS12             GPIO_BSRR_BS12_Msk                    /*!< Port x set I/O pin y */
#define GPIO_BSRR_BS13_Pos         (13U)
#define GPIO_BSRR_BS13_Msk         (0x1UL << GPIO_BSRR_BS13_Pos)         /*!< 0x00002000 */
#define GPIO_BSRR_BS13             GPIO_BSRR_BS13_Msk                    /*!< Port x set I/O pin y */
#define GPIO_BSRR_BS14_Pos         (14U)
#define GPIO_BSRR_BS14_Msk         (0x1UL << GPIO_BSRR_BS14_Pos)         /*!< 0x00004000 */
#define GPIO_BSRR_BS14             GPIO_BSRR_BS14_Msk                    /*!< Port x set I/O pin y */
#define GPIO_BSRR_BS15_Pos         (15U)
#define GPIO_BSRR_BS15_Msk         (0x1UL << GPIO_BSRR_BS15_Pos)         /*!< 0x00008000 */
#define GPIO_BSRR_BS15             GPIO_BSRR_BS15_Msk                    /*!< Port x set I/O pin y */
#define GPIO_BSRR_BR0_Pos          (16U)
#define GPIO_BSRR_BR0_Msk          (0x1UL << GPIO_BSRR_BR0_Pos)          /*!< 0x00010000 */
#define GPIO_BSRR_BR0              GPIO_BSRR_BR0_Msk                     /*!< Port x reset I/O pin y */
#define GPIO_BSRR_BR1_Pos          (17U)
#define GPIO_BSRR_BR1_Msk          (0x1UL << GPIO_BSRR_BR1_Pos)          /*!< 0x00020000 */
#define GPIO_BSRR_BR1              GPIO_BSRR_BR1_Msk                     /*!< Port x reset I/O pin y */
#define GPIO_BSRR_BR2_Pos          (18U)
#define GPIO_BSRR_BR2_Msk          (0x1UL << GPIO_BSRR_BR2_Pos)          /*!< 0x00040000 */
#define GPIO_BSRR_BR2              GPIO_BSRR_BR2_Msk                     /*!< Port x reset I/O pin y */
#define GPIO_BSRR_BR3_Pos          (19U)
#define GPIO_BSRR_BR3_Msk          (0x1UL << GPIO_BSRR_BR3_Pos)          /*!< 0x00080000 */
#define GPIO_BSRR_BR3              GPIO_BSRR_BR3_Msk                     /*!< Port x reset I/O pin y */
#define GPIO_BSRR_BR4_Pos          (20U)
#define GPIO_BSRR_BR4_Msk          (0x1UL << GPIO_BSRR_BR4_Pos)          /*!< 0x00100000 */
#define GPIO_BSRR_BR4              GPIO_BSRR_BR4_Msk                     /*!< Port x reset I/O pin y */
#define GPIO_BSRR_BR5_Pos          (21U)
#define GPIO_BSRR_BR5_Msk          (0x1UL << GPIO_BSRR_BR5_Pos)          /*!< 0x00200000 */
#define GPIO_BSRR_BR5              GPIO_BSRR_BR5_Msk                     /*!< Port x reset I/O pin y */
#define GPIO_BSRR_BR6_Pos          (22U)
#define GPIO_BSRR_BR6_Msk          (0x1UL << GPIO_BSRR_BR6_Pos)          /*!< 0x00400000 */
#define GPIO_BSRR_BR6              GPIO_BSRR_BR6_Msk                     /*!< Port x reset I/O pin y */
#define GPIO_BSRR_BR7_Pos          (23U)
#define GPIO_BSRR_BR7_Msk          (0x1UL << GPIO_BSRR_BR7_Pos)          /*!< 0x00800000 */
#define GPIO_BSRR_BR7              GPIO_BSRR_BR7_Msk                     /*!< Port x reset I/O pin y */
#define GPIO_BSRR_BR8_Pos          (24U)
#define GPIO_BSRR_BR8_Msk          (0x1UL << GPIO_BSRR_BR8_Pos)          /*!< 0x01000000 */
#define GPIO_BSRR_BR8              GPIO_BSRR_BR8_Msk                     /*!< Port x reset I/O pin y */
#define GPIO_BSRR_BR9_Pos          (25U)
#define GPIO_BSRR_BR9_Msk          (0x1UL << GPIO_BSRR_BR9_Pos)          /*!< 0x02000000 */
#define GPIO_BSRR_BR9              GPIO_BSRR_BR9_Msk                     /*!< Port x reset I/O pin y */
#define GPIO_BSRR_BR10_Pos         (26U)
#define GPIO_BSRR_BR10_Msk         (0x1UL << GPIO_BSRR_BR10_Pos)         /*!< 0x04000000 */
#define GPIO_BSRR_BR10             GPIO_BSRR_BR10_Msk                    /*!< Port x reset I/O pin y */
#define GPIO_BSRR_BR11_Pos         (27U)
#define GPIO_BSRR_BR11_Msk         (0x1UL << GPIO_BSRR_BR11_Pos)         /*!< 0x08000000 */
#define GPIO_BSRR_BR11             GPIO_BSRR_BR11_Msk                    /*!< Port x reset I/O pin y */
#define GPIO_BSRR_BR12_Pos         (28U)
#define GPIO_BSRR_BR12_Msk         (0x1UL << GPIO_BSRR_BR12_Pos)         /*!< 0x10000000 */
#define GPIO_BSRR_BR12             GPIO_BSRR_BR12_Msk                    /*!< Port x reset I/O pin y */
#define GPIO_BSRR_BR13_Pos         (29U)
#define GPIO_BSRR_BR13_Msk         (0x1UL << GPIO_BSRR_BR13_Pos)         /*!< 0x20000000 */
#define GPIO_BSRR_BR13             GPIO_BSRR_BR13_Msk                    /*!< Port x reset I/O pin y */
#define GPIO_BSRR_BR14_Pos         (30U)
#define GPIO_BSRR_BR14_Msk         (0x1UL << GPIO_BSRR_BR14_Pos)         /*!< 0x40000000 */
#define GPIO_BSRR_BR14             GPIO_BSRR_BR14_Msk                    /*!< Port x reset I/O pin y */
#define GPIO_BSRR_BR15_Pos         (31U)
#define GPIO_BSRR_BR15_Msk         (0x1UL << GPIO_BSRR_BR15_Pos)         /*!< 0x80000000 */
#define GPIO_BSRR_BR15             GPIO_BSRR_BR15_Msk                    /*!< Port x reset I/O pin y */

/* ************************************  Bit definition for GPIO_LCKR register  ************************************* */
#define GPIO_LCKR_LCK0_Pos         (0U)
#define GPIO_LCKR_LCK0_Msk         (0x1UL << GPIO_LCKR_LCK0_Pos)         /*!< 0x00000001 */
#define GPIO_LCKR_LCK0             GPIO_LCKR_LCK0_Msk                    /*!< Port x lock I/O pin y */
#define GPIO_LCKR_LCK1_Pos         (1U)
#define GPIO_LCKR_LCK1_Msk         (0x1UL << GPIO_LCKR_LCK1_Pos)         /*!< 0x00000002 */
#define GPIO_LCKR_LCK1             GPIO_LCKR_LCK1_Msk                    /*!< Port x lock I/O pin y */
#define GPIO_LCKR_LCK2_Pos         (2U)
#define GPIO_LCKR_LCK2_Msk         (0x1UL << GPIO_LCKR_LCK2_Pos)         /*!< 0x00000004 */
#define GPIO_LCKR_LCK2             GPIO_LCKR_LCK2_Msk                    /*!< Port x lock I/O pin y */
#define GPIO_LCKR_LCK3_Pos         (3U)
#define GPIO_LCKR_LCK3_Msk         (0x1UL << GPIO_LCKR_LCK3_Pos)         /*!< 0x00000008 */
#define GPIO_LCKR_LCK3             GPIO_LCKR_LCK3_Msk                    /*!< Port x lock I/O pin y */
#define GPIO_LCKR_LCK4_Pos         (4U)
#define GPIO_LCKR_LCK4_Msk         (0x1UL << GPIO_LCKR_LCK4_Pos)         /*!< 0x00000010 */
#define GPIO_LCKR_LCK4             GPIO_LCKR_LCK4_Msk                    /*!< Port x lock I/O pin y */
#define GPIO_LCKR_LCK5_Pos         (5U)
#define GPIO_LCKR_LCK5_Msk         (0x1UL << GPIO_LCKR_LCK5_Pos)         /*!< 0x00000020 */
#define GPIO_LCKR_LCK5             GPIO_LCKR_LCK5_Msk                    /*!< Port x lock I/O pin y */
#define GPIO_LCKR_LCK6_Pos         (6U)
#define GPIO_LCKR_LCK6_Msk         (0x1UL << GPIO_LCKR_LCK6_Pos)         /*!< 0x00000040 */
#define GPIO_LCKR_LCK6             GPIO_LCKR_LCK6_Msk                    /*!< Port x lock I/O pin y */
#define GPIO_LCKR_LCK7_Pos         (7U)
#define GPIO_LCKR_LCK7_Msk         (0x1UL << GPIO_LCKR_LCK7_Pos)         /*!< 0x00000080 */
#define GPIO_LCKR_LCK7             GPIO_LCKR_LCK7_Msk                    /*!< Port x lock I/O pin y */
#define GPIO_LCKR_LCK8_Pos         (8U)
#define GPIO_LCKR_LCK8_Msk         (0x1UL << GPIO_LCKR_LCK8_Pos)         /*!< 0x00000100 */
#define GPIO_LCKR_LCK8             GPIO_LCKR_LCK8_Msk                    /*!< Port x lock I/O pin y */
#define GPIO_LCKR_LCK9_Pos         (9U)
#define GPIO_LCKR_LCK9_Msk         (0x1UL << GPIO_LCKR_LCK9_Pos)         /*!< 0x00000200 */
#define GPIO_LCKR_LCK9             GPIO_LCKR_LCK9_Msk                    /*!< Port x lock I/O pin y */
#define GPIO_LCKR_LCK10_Pos        (10U)
#define GPIO_LCKR_LCK10_Msk        (0x1UL << GPIO_LCKR_LCK10_Pos)        /*!< 0x00000400 */
#define GPIO_LCKR_LCK10            GPIO_LCKR_LCK10_Msk                   /*!< Port x lock I/O pin y */
#define GPIO_LCKR_LCK11_Pos        (11U)
#define GPIO_LCKR_LCK11_Msk        (0x1UL << GPIO_LCKR_LCK11_Pos)        /*!< 0x00000800 */
#define GPIO_LCKR_LCK11            GPIO_LCKR_LCK11_Msk                   /*!< Port x lock I/O pin y */
#define GPIO_LCKR_LCK12_Pos        (12U)
#define GPIO_LCKR_LCK12_Msk        (0x1UL << GPIO_LCKR_LCK12_Pos)        /*!< 0x00001000 */
#define GPIO_LCKR_LCK12            GPIO_LCKR_LCK12_Msk                   /*!< Port x lock I/O pin y */
#define GPIO_LCKR_LCK13_Pos        (13U)
#define GPIO_LCKR_LCK13_Msk        (0x1UL << GPIO_LCKR_LCK13_Pos)        /*!< 0x00002000 */
#define GPIO_LCKR_LCK13            GPIO_LCKR_LCK13_Msk                   /*!< Port x lock I/O pin y */
#define GPIO_LCKR_LCK14_Pos        (14U)
#define GPIO_LCKR_LCK14_Msk        (0x1UL << GPIO_LCKR_LCK14_Pos)        /*!< 0x00004000 */
#define GPIO_LCKR_LCK14            GPIO_LCKR_LCK14_Msk                   /*!< Port x lock I/O pin y */
#define GPIO_LCKR_LCK15_Pos        (15U)
#define GPIO_LCKR_LCK15_Msk        (0x1UL << GPIO_LCKR_LCK15_Pos)        /*!< 0x00008000 */
#define GPIO_LCKR_LCK15            GPIO_LCKR_LCK15_Msk                   /*!< Port x lock I/O pin y */
#define GPIO_LCKR_LCKK_Pos         (16U)
#define GPIO_LCKR_LCKK_Msk         (0x1UL << GPIO_LCKR_LCKK_Pos)         /*!< 0x00010000 */
#define GPIO_LCKR_LCKK             GPIO_LCKR_LCKK_Msk                    /*!< Lock key */

/* ************************************  Bit definition for GPIO_AFRL register  ************************************* */
#define GPIO_AFRL_AFSEL0_Pos       (0U)
#define GPIO_AFRL_AFSEL0_Msk       (0xFUL << GPIO_AFRL_AFSEL0_Pos)       /*!< 0x0000000F */
#define GPIO_AFRL_AFSEL0           GPIO_AFRL_AFSEL0_Msk                  /*!< Alternate function selection for port x
                                                                              I/O pin y */
#define GPIO_AFRL_AFSEL0_0         (0x1UL << GPIO_AFRL_AFSEL0_Pos)       /*!< 0x00000001 */
#define GPIO_AFRL_AFSEL0_1         (0x2UL << GPIO_AFRL_AFSEL0_Pos)       /*!< 0x00000002 */
#define GPIO_AFRL_AFSEL0_2         (0x4UL << GPIO_AFRL_AFSEL0_Pos)       /*!< 0x00000004 */
#define GPIO_AFRL_AFSEL0_3         (0x8UL << GPIO_AFRL_AFSEL0_Pos)       /*!< 0x00000008 */
#define GPIO_AFRL_AFSEL1_Pos       (4U)
#define GPIO_AFRL_AFSEL1_Msk       (0xFUL << GPIO_AFRL_AFSEL1_Pos)       /*!< 0x000000F0 */
#define GPIO_AFRL_AFSEL1           GPIO_AFRL_AFSEL1_Msk                  /*!< Alternate function selection for port x
                                                                             I/O pin y */
#define GPIO_AFRL_AFSEL1_0         (0x1UL << GPIO_AFRL_AFSEL1_Pos)       /*!< 0x00000010 */
#define GPIO_AFRL_AFSEL1_1         (0x2UL << GPIO_AFRL_AFSEL1_Pos)       /*!< 0x00000020 */
#define GPIO_AFRL_AFSEL1_2         (0x4UL << GPIO_AFRL_AFSEL1_Pos)       /*!< 0x00000040 */
#define GPIO_AFRL_AFSEL1_3         (0x8UL << GPIO_AFRL_AFSEL1_Pos)       /*!< 0x00000080 */
#define GPIO_AFRL_AFSEL2_Pos       (8U)
#define GPIO_AFRL_AFSEL2_Msk       (0xFUL << GPIO_AFRL_AFSEL2_Pos)       /*!< 0x00000F00 */
#define GPIO_AFRL_AFSEL2           GPIO_AFRL_AFSEL2_Msk                  /*!< Alternate function selection for port x
                                                                              I/O pin y */
#define GPIO_AFRL_AFSEL2_0         (0x1UL << GPIO_AFRL_AFSEL2_Pos)       /*!< 0x00000100 */
#define GPIO_AFRL_AFSEL2_1         (0x2UL << GPIO_AFRL_AFSEL2_Pos)       /*!< 0x00000200 */
#define GPIO_AFRL_AFSEL2_2         (0x4UL << GPIO_AFRL_AFSEL2_Pos)       /*!< 0x00000400 */
#define GPIO_AFRL_AFSEL2_3         (0x8UL << GPIO_AFRL_AFSEL2_Pos)       /*!< 0x00000800 */
#define GPIO_AFRL_AFSEL3_Pos       (12U)
#define GPIO_AFRL_AFSEL3_Msk       (0xFUL << GPIO_AFRL_AFSEL3_Pos)       /*!< 0x0000F000 */
#define GPIO_AFRL_AFSEL3           GPIO_AFRL_AFSEL3_Msk                  /*!< Alternate function selection for port x
                                                                              I/O pin y */
#define GPIO_AFRL_AFSEL3_0         (0x1UL << GPIO_AFRL_AFSEL3_Pos)       /*!< 0x00001000 */
#define GPIO_AFRL_AFSEL3_1         (0x2UL << GPIO_AFRL_AFSEL3_Pos)       /*!< 0x00002000 */
#define GPIO_AFRL_AFSEL3_2         (0x4UL << GPIO_AFRL_AFSEL3_Pos)       /*!< 0x00004000 */
#define GPIO_AFRL_AFSEL3_3         (0x8UL << GPIO_AFRL_AFSEL3_Pos)       /*!< 0x00008000 */
#define GPIO_AFRL_AFSEL4_Pos       (16U)
#define GPIO_AFRL_AFSEL4_Msk       (0xFUL << GPIO_AFRL_AFSEL4_Pos)       /*!< 0x000F0000 */
#define GPIO_AFRL_AFSEL4           GPIO_AFRL_AFSEL4_Msk                  /*!< Alternate function selection for port x
                                                                              I/O pin y */
#define GPIO_AFRL_AFSEL4_0         (0x1UL << GPIO_AFRL_AFSEL4_Pos)       /*!< 0x00010000 */
#define GPIO_AFRL_AFSEL4_1         (0x2UL << GPIO_AFRL_AFSEL4_Pos)       /*!< 0x00020000 */
#define GPIO_AFRL_AFSEL4_2         (0x4UL << GPIO_AFRL_AFSEL4_Pos)       /*!< 0x00040000 */
#define GPIO_AFRL_AFSEL4_3         (0x8UL << GPIO_AFRL_AFSEL4_Pos)       /*!< 0x00080000 */
#define GPIO_AFRL_AFSEL5_Pos       (20U)
#define GPIO_AFRL_AFSEL5_Msk       (0xFUL << GPIO_AFRL_AFSEL5_Pos)       /*!< 0x00F00000 */
#define GPIO_AFRL_AFSEL5           GPIO_AFRL_AFSEL5_Msk                  /*!< Alternate function selection for port x
                                                                              I/O pin y */
#define GPIO_AFRL_AFSEL5_0         (0x1UL << GPIO_AFRL_AFSEL5_Pos)       /*!< 0x00100000 */
#define GPIO_AFRL_AFSEL5_1         (0x2UL << GPIO_AFRL_AFSEL5_Pos)       /*!< 0x00200000 */
#define GPIO_AFRL_AFSEL5_2         (0x4UL << GPIO_AFRL_AFSEL5_Pos)       /*!< 0x00400000 */
#define GPIO_AFRL_AFSEL5_3         (0x8UL << GPIO_AFRL_AFSEL5_Pos)       /*!< 0x00800000 */
#define GPIO_AFRL_AFSEL6_Pos       (24U)
#define GPIO_AFRL_AFSEL6_Msk       (0xFUL << GPIO_AFRL_AFSEL6_Pos)       /*!< 0x0F000000 */
#define GPIO_AFRL_AFSEL6           GPIO_AFRL_AFSEL6_Msk                  /*!< Alternate function selection for port x
                                                                              I/O pin y */
#define GPIO_AFRL_AFSEL6_0         (0x1UL << GPIO_AFRL_AFSEL6_Pos)       /*!< 0x01000000 */
#define GPIO_AFRL_AFSEL6_1         (0x2UL << GPIO_AFRL_AFSEL6_Pos)       /*!< 0x02000000 */
#define GPIO_AFRL_AFSEL6_2         (0x4UL << GPIO_AFRL_AFSEL6_Pos)       /*!< 0x04000000 */
#define GPIO_AFRL_AFSEL6_3         (0x8UL << GPIO_AFRL_AFSEL6_Pos)       /*!< 0x08000000 */
#define GPIO_AFRL_AFSEL7_Pos       (28U)
#define GPIO_AFRL_AFSEL7_Msk       (0xFUL << GPIO_AFRL_AFSEL7_Pos)       /*!< 0xF0000000 */
#define GPIO_AFRL_AFSEL7           GPIO_AFRL_AFSEL7_Msk                  /*!< Alternate function selection for port x
                                                                              I/O pin y */
#define GPIO_AFRL_AFSEL7_0         (0x1UL << GPIO_AFRL_AFSEL7_Pos)       /*!< 0x10000000 */
#define GPIO_AFRL_AFSEL7_1         (0x2UL << GPIO_AFRL_AFSEL7_Pos)       /*!< 0x20000000 */
#define GPIO_AFRL_AFSEL7_2         (0x4UL << GPIO_AFRL_AFSEL7_Pos)       /*!< 0x40000000 */
#define GPIO_AFRL_AFSEL7_3         (0x8UL << GPIO_AFRL_AFSEL7_Pos)       /*!< 0x80000000 */

/* ************************************  Bit definition for GPIO_AFRH register  ************************************* */
#define GPIO_AFRH_AFSEL8_Pos       (0U)
#define GPIO_AFRH_AFSEL8_Msk       (0xFUL << GPIO_AFRH_AFSEL8_Pos)       /*!< 0x0000000F */
#define GPIO_AFRH_AFSEL8           GPIO_AFRH_AFSEL8_Msk                  /*!< Alternate function selection for port x
                                                                              I/O pin y */
#define GPIO_AFRH_AFSEL8_0         (0x1UL << GPIO_AFRH_AFSEL8_Pos)       /*!< 0x00000001 */
#define GPIO_AFRH_AFSEL8_1         (0x2UL << GPIO_AFRH_AFSEL8_Pos)       /*!< 0x00000002 */
#define GPIO_AFRH_AFSEL8_2         (0x4UL << GPIO_AFRH_AFSEL8_Pos)       /*!< 0x00000004 */
#define GPIO_AFRH_AFSEL8_3         (0x8UL << GPIO_AFRH_AFSEL8_Pos)       /*!< 0x00000008 */
#define GPIO_AFRH_AFSEL9_Pos       (4U)
#define GPIO_AFRH_AFSEL9_Msk       (0xFUL << GPIO_AFRH_AFSEL9_Pos)       /*!< 0x000000F0 */
#define GPIO_AFRH_AFSEL9           GPIO_AFRH_AFSEL9_Msk                  /*!< Alternate function selection for port x
                                                                              I/O pin y */
#define GPIO_AFRH_AFSEL9_0         (0x1UL << GPIO_AFRH_AFSEL9_Pos)       /*!< 0x00000010 */
#define GPIO_AFRH_AFSEL9_1         (0x2UL << GPIO_AFRH_AFSEL9_Pos)       /*!< 0x00000020 */
#define GPIO_AFRH_AFSEL9_2         (0x4UL << GPIO_AFRH_AFSEL9_Pos)       /*!< 0x00000040 */
#define GPIO_AFRH_AFSEL9_3         (0x8UL << GPIO_AFRH_AFSEL9_Pos)       /*!< 0x00000080 */
#define GPIO_AFRH_AFSEL10_Pos      (8U)
#define GPIO_AFRH_AFSEL10_Msk      (0xFUL << GPIO_AFRH_AFSEL10_Pos)      /*!< 0x00000F00 */
#define GPIO_AFRH_AFSEL10          GPIO_AFRH_AFSEL10_Msk                 /*!< Alternate function selection for port x
                                                                              I/O pin y */
#define GPIO_AFRH_AFSEL10_0        (0x1UL << GPIO_AFRH_AFSEL10_Pos)      /*!< 0x00000100 */
#define GPIO_AFRH_AFSEL10_1        (0x2UL << GPIO_AFRH_AFSEL10_Pos)      /*!< 0x00000200 */
#define GPIO_AFRH_AFSEL10_2        (0x4UL << GPIO_AFRH_AFSEL10_Pos)      /*!< 0x00000400 */
#define GPIO_AFRH_AFSEL10_3        (0x8UL << GPIO_AFRH_AFSEL10_Pos)      /*!< 0x00000800 */
#define GPIO_AFRH_AFSEL11_Pos      (12U)
#define GPIO_AFRH_AFSEL11_Msk      (0xFUL << GPIO_AFRH_AFSEL11_Pos)      /*!< 0x0000F000 */
#define GPIO_AFRH_AFSEL11          GPIO_AFRH_AFSEL11_Msk                 /*!< Alternate function selection for port x
                                                                              I/O pin y */
#define GPIO_AFRH_AFSEL11_0        (0x1UL << GPIO_AFRH_AFSEL11_Pos)      /*!< 0x00001000 */
#define GPIO_AFRH_AFSEL11_1        (0x2UL << GPIO_AFRH_AFSEL11_Pos)      /*!< 0x00002000 */
#define GPIO_AFRH_AFSEL11_2        (0x4UL << GPIO_AFRH_AFSEL11_Pos)      /*!< 0x00004000 */
#define GPIO_AFRH_AFSEL11_3        (0x8UL << GPIO_AFRH_AFSEL11_Pos)      /*!< 0x00008000 */
#define GPIO_AFRH_AFSEL12_Pos      (16U)
#define GPIO_AFRH_AFSEL12_Msk      (0xFUL << GPIO_AFRH_AFSEL12_Pos)      /*!< 0x000F0000 */
#define GPIO_AFRH_AFSEL12          GPIO_AFRH_AFSEL12_Msk                 /*!< Alternate function selection for port x
                                                                              I/O pin y */
#define GPIO_AFRH_AFSEL12_0        (0x1UL << GPIO_AFRH_AFSEL12_Pos)      /*!< 0x00010000 */
#define GPIO_AFRH_AFSEL12_1        (0x2UL << GPIO_AFRH_AFSEL12_Pos)      /*!< 0x00020000 */
#define GPIO_AFRH_AFSEL12_2        (0x4UL << GPIO_AFRH_AFSEL12_Pos)      /*!< 0x00040000 */
#define GPIO_AFRH_AFSEL12_3        (0x8UL << GPIO_AFRH_AFSEL12_Pos)      /*!< 0x00080000 */
#define GPIO_AFRH_AFSEL13_Pos      (20U)
#define GPIO_AFRH_AFSEL13_Msk      (0xFUL << GPIO_AFRH_AFSEL13_Pos)      /*!< 0x00F00000 */
#define GPIO_AFRH_AFSEL13          GPIO_AFRH_AFSEL13_Msk                 /*!< Alternate function selection for port x
                                                                              I/O pin y */
#define GPIO_AFRH_AFSEL13_0        (0x1UL << GPIO_AFRH_AFSEL13_Pos)      /*!< 0x00100000 */
#define GPIO_AFRH_AFSEL13_1        (0x2UL << GPIO_AFRH_AFSEL13_Pos)      /*!< 0x00200000 */
#define GPIO_AFRH_AFSEL13_2        (0x4UL << GPIO_AFRH_AFSEL13_Pos)      /*!< 0x00400000 */
#define GPIO_AFRH_AFSEL13_3        (0x8UL << GPIO_AFRH_AFSEL13_Pos)      /*!< 0x00800000 */
#define GPIO_AFRH_AFSEL14_Pos      (24U)
#define GPIO_AFRH_AFSEL14_Msk      (0xFUL << GPIO_AFRH_AFSEL14_Pos)      /*!< 0x0F000000 */
#define GPIO_AFRH_AFSEL14          GPIO_AFRH_AFSEL14_Msk                 /*!< Alternate function selection for port x
                                                                              I/O pin y */
#define GPIO_AFRH_AFSEL14_0        (0x1UL << GPIO_AFRH_AFSEL14_Pos)      /*!< 0x01000000 */
#define GPIO_AFRH_AFSEL14_1        (0x2UL << GPIO_AFRH_AFSEL14_Pos)      /*!< 0x02000000 */
#define GPIO_AFRH_AFSEL14_2        (0x4UL << GPIO_AFRH_AFSEL14_Pos)      /*!< 0x04000000 */
#define GPIO_AFRH_AFSEL14_3        (0x8UL << GPIO_AFRH_AFSEL14_Pos)      /*!< 0x08000000 */
#define GPIO_AFRH_AFSEL15_Pos      (28U)
#define GPIO_AFRH_AFSEL15_Msk      (0xFUL << GPIO_AFRH_AFSEL15_Pos)      /*!< 0xF0000000 */
#define GPIO_AFRH_AFSEL15          GPIO_AFRH_AFSEL15_Msk                 /*!< Alternate function selection for port x
                                                                              I/O pin y */
#define GPIO_AFRH_AFSEL15_0        (0x1UL << GPIO_AFRH_AFSEL15_Pos)      /*!< 0x10000000 */
#define GPIO_AFRH_AFSEL15_1        (0x2UL << GPIO_AFRH_AFSEL15_Pos)      /*!< 0x20000000 */
#define GPIO_AFRH_AFSEL15_2        (0x4UL << GPIO_AFRH_AFSEL15_Pos)      /*!< 0x40000000 */
#define GPIO_AFRH_AFSEL15_3        (0x8UL << GPIO_AFRH_AFSEL15_Pos)      /*!< 0x80000000 */

/* *************************************  Bit definition for GPIO_BRR register  ************************************* */
#define GPIO_BRR_BR0_Pos           (0U)
#define GPIO_BRR_BR0_Msk           (0x1UL << GPIO_BRR_BR0_Pos)           /*!< 0x00000001 */
#define GPIO_BRR_BR0               GPIO_BRR_BR0_Msk                      /*!< Port x reset IO pin y */
#define GPIO_BRR_BR1_Pos           (1U)
#define GPIO_BRR_BR1_Msk           (0x1UL << GPIO_BRR_BR1_Pos)           /*!< 0x00000002 */
#define GPIO_BRR_BR1               GPIO_BRR_BR1_Msk                      /*!< Port x reset IO pin y */
#define GPIO_BRR_BR2_Pos           (2U)
#define GPIO_BRR_BR2_Msk           (0x1UL << GPIO_BRR_BR2_Pos)           /*!< 0x00000004 */
#define GPIO_BRR_BR2               GPIO_BRR_BR2_Msk                      /*!< Port x reset IO pin y */
#define GPIO_BRR_BR3_Pos           (3U)
#define GPIO_BRR_BR3_Msk           (0x1UL << GPIO_BRR_BR3_Pos)           /*!< 0x00000008 */
#define GPIO_BRR_BR3               GPIO_BRR_BR3_Msk                      /*!< Port x reset IO pin y */
#define GPIO_BRR_BR4_Pos           (4U)
#define GPIO_BRR_BR4_Msk           (0x1UL << GPIO_BRR_BR4_Pos)           /*!< 0x00000010 */
#define GPIO_BRR_BR4               GPIO_BRR_BR4_Msk                      /*!< Port x reset IO pin y */
#define GPIO_BRR_BR5_Pos           (5U)
#define GPIO_BRR_BR5_Msk           (0x1UL << GPIO_BRR_BR5_Pos)           /*!< 0x00000020 */
#define GPIO_BRR_BR5               GPIO_BRR_BR5_Msk                      /*!< Port x reset IO pin y */
#define GPIO_BRR_BR6_Pos           (6U)
#define GPIO_BRR_BR6_Msk           (0x1UL << GPIO_BRR_BR6_Pos)           /*!< 0x00000040 */
#define GPIO_BRR_BR6               GPIO_BRR_BR6_Msk                      /*!< Port x reset IO pin y */
#define GPIO_BRR_BR7_Pos           (7U)
#define GPIO_BRR_BR7_Msk           (0x1UL << GPIO_BRR_BR7_Pos)           /*!< 0x00000080 */
#define GPIO_BRR_BR7               GPIO_BRR_BR7_Msk                      /*!< Port x reset IO pin y */
#define GPIO_BRR_BR8_Pos           (8U)
#define GPIO_BRR_BR8_Msk           (0x1UL << GPIO_BRR_BR8_Pos)           /*!< 0x00000100 */
#define GPIO_BRR_BR8               GPIO_BRR_BR8_Msk                      /*!< Port x reset IO pin y */
#define GPIO_BRR_BR9_Pos           (9U)
#define GPIO_BRR_BR9_Msk           (0x1UL << GPIO_BRR_BR9_Pos)           /*!< 0x00000200 */
#define GPIO_BRR_BR9               GPIO_BRR_BR9_Msk                      /*!< Port x reset IO pin y */
#define GPIO_BRR_BR10_Pos          (10U)
#define GPIO_BRR_BR10_Msk          (0x1UL << GPIO_BRR_BR10_Pos)          /*!< 0x00000400 */
#define GPIO_BRR_BR10              GPIO_BRR_BR10_Msk                     /*!< Port x reset IO pin y */
#define GPIO_BRR_BR11_Pos          (11U)
#define GPIO_BRR_BR11_Msk          (0x1UL << GPIO_BRR_BR11_Pos)          /*!< 0x00000800 */
#define GPIO_BRR_BR11              GPIO_BRR_BR11_Msk                     /*!< Port x reset IO pin y */
#define GPIO_BRR_BR12_Pos          (12U)
#define GPIO_BRR_BR12_Msk          (0x1UL << GPIO_BRR_BR12_Pos)          /*!< 0x00001000 */
#define GPIO_BRR_BR12              GPIO_BRR_BR12_Msk                     /*!< Port x reset IO pin y */
#define GPIO_BRR_BR13_Pos          (13U)
#define GPIO_BRR_BR13_Msk          (0x1UL << GPIO_BRR_BR13_Pos)          /*!< 0x00002000 */
#define GPIO_BRR_BR13              GPIO_BRR_BR13_Msk                     /*!< Port x reset IO pin y */
#define GPIO_BRR_BR14_Pos          (14U)
#define GPIO_BRR_BR14_Msk          (0x1UL << GPIO_BRR_BR14_Pos)          /*!< 0x00004000 */
#define GPIO_BRR_BR14              GPIO_BRR_BR14_Msk                     /*!< Port x reset IO pin y */
#define GPIO_BRR_BR15_Pos          (15U)
#define GPIO_BRR_BR15_Msk          (0x1UL << GPIO_BRR_BR15_Pos)          /*!< 0x00008000 */
#define GPIO_BRR_BR15              GPIO_BRR_BR15_Msk                     /*!< Port x reset IO pin y */

/* ****************************************************************************************************************** */
/*                                                                                                                    */
/*                                               Hash processor (HASH)                                                */
/*                                                                                                                    */
/* ****************************************************************************************************************** */
#define HASH_CSR_REGISTERS_NUMBER                     54U  /*!< Number of Context Swap Registers */
#define HASH_SHA1_SHA2256_CSR_REGISTER_NUMBER         38U   /*!< Number of context swap register in case of HASH SHA-1
                                                                 or SHA2-256 */
#define HASH_HMAC_SHA1_SHA2256_CSR_REGISTER_NUMBER    54U   /*!< Number of context swap register in case of HASH-HMAC
                                                                 SHA-1 or SHA2-256 */

/* *************************************  Bit definition for HASH_CR register  ************************************** */
#define HASH_CR_INIT_Pos     (2U)
#define HASH_CR_INIT_Msk     (0x1UL << HASH_CR_INIT_Pos)       /*!< 0x00000004 */
#define HASH_CR_INIT         HASH_CR_INIT_Msk                  /*!< Initialize message digest calculation */
#define HASH_CR_DMAE_Pos     (3U)
#define HASH_CR_DMAE_Msk     (0x1UL << HASH_CR_DMAE_Pos)       /*!< 0x00000008 */
#define HASH_CR_DMAE         HASH_CR_DMAE_Msk                  /*!< DMA enable */
#define HASH_CR_DATATYPE_Pos (4U)
#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos)   /*!< 0x00000030 */
#define HASH_CR_DATATYPE     HASH_CR_DATATYPE_Msk              /*!< Data type selection */
#define HASH_CR_DATATYPE_0   (0x1UL << HASH_CR_DATATYPE_Pos)   /*!< 0x00000010 */
#define HASH_CR_DATATYPE_1   (0x2UL << HASH_CR_DATATYPE_Pos)   /*!< 0x00000020 */
#define HASH_CR_MODE_Pos     (6U)
#define HASH_CR_MODE_Msk     (0x1UL << HASH_CR_MODE_Pos)       /*!< 0x00000040 */
#define HASH_CR_MODE         HASH_CR_MODE_Msk                  /*!< Mode selection */
#define HASH_CR_NBW_Pos      (8U)
#define HASH_CR_NBW_Msk      (0xFUL << HASH_CR_NBW_Pos)        /*!< 0x00000F00 */
#define HASH_CR_NBW          HASH_CR_NBW_Msk                   /*!< Number of words already pushed */
#define HASH_CR_NBW_0        (0x1UL << HASH_CR_NBW_Pos)        /*!< 0x00000100 */
#define HASH_CR_NBW_1        (0x2UL << HASH_CR_NBW_Pos)        /*!< 0x00000200 */
#define HASH_CR_NBW_2        (0x4UL << HASH_CR_NBW_Pos)        /*!< 0x00000400 */
#define HASH_CR_NBW_3        (0x8UL << HASH_CR_NBW_Pos)        /*!< 0x00000800 */
#define HASH_CR_DINNE_Pos    (12U)
#define HASH_CR_DINNE_Msk    (0x1UL << HASH_CR_DINNE_Pos)      /*!< 0x00001000 */
#define HASH_CR_DINNE        HASH_CR_DINNE_Msk                 /*!< DIN not empty */
#define HASH_CR_MDMAT_Pos    (13U)
#define HASH_CR_MDMAT_Msk    (0x1UL << HASH_CR_MDMAT_Pos)      /*!< 0x00002000 */
#define HASH_CR_MDMAT        HASH_CR_MDMAT_Msk                 /*!< Multiple DMA transfers */
#define HASH_CR_LKEY_Pos     (16U)
#define HASH_CR_LKEY_Msk     (0x1UL << HASH_CR_LKEY_Pos)       /*!< 0x00010000 */
#define HASH_CR_LKEY         HASH_CR_LKEY_Msk                  /*!< Long key selection */
#define HASH_CR_ALGO_Pos     (17U)
#define HASH_CR_ALGO_Msk     (0x3UL << HASH_CR_ALGO_Pos)       /*!< 0x00060000 */
#define HASH_CR_ALGO         HASH_CR_ALGO_Msk                  /*!< Algorithm selection */
#define HASH_CR_ALGO_0       (0x1UL << HASH_CR_ALGO_Pos)       /*!< 0x00020000 */
#define HASH_CR_ALGO_1       (0x2UL << HASH_CR_ALGO_Pos)       /*!< 0x00040000 */

/* *************************************  Bit definition for HASH_DIN register  ************************************* */
#define HASH_DIN_DATAIN_Pos  (0U)
#define HASH_DIN_DATAIN_Msk  (0xFFFFFFFFUL << HASH_DIN_DATAIN_Pos)  /*!< 0xFFFFFFFF */
#define HASH_DIN_DATAIN      HASH_DIN_DATAIN_Msk                    /*!< Data input */

/* *************************************  Bit definition for HASH_STR register  ************************************* */
#define HASH_STR_NBLW_Pos    (0U)
#define HASH_STR_NBLW_Msk    (0x1FUL << HASH_STR_NBLW_Pos)     /*!< 0x0000001F */
#define HASH_STR_NBLW        HASH_STR_NBLW_Msk                 /*!< Number of valid bits in the last word */
#define HASH_STR_NBLW_0      (0x1UL << HASH_STR_NBLW_Pos)      /*!< 0x00000001 */
#define HASH_STR_NBLW_1      (0x2UL << HASH_STR_NBLW_Pos)      /*!< 0x00000002 */
#define HASH_STR_NBLW_2      (0x4UL << HASH_STR_NBLW_Pos)      /*!< 0x00000004 */
#define HASH_STR_NBLW_3      (0x8UL << HASH_STR_NBLW_Pos)      /*!< 0x00000008 */
#define HASH_STR_NBLW_4      (0x10UL << HASH_STR_NBLW_Pos)     /*!< 0x00000010 */
#define HASH_STR_DCAL_Pos    (8U)
#define HASH_STR_DCAL_Msk    (0x1UL << HASH_STR_DCAL_Pos)      /*!< 0x00000100 */
#define HASH_STR_DCAL        HASH_STR_DCAL_Msk                 /*!< Digest calculation */

/* *************************************  Bit definition for HASH_IMR register  ************************************* */
#define HASH_IMR_DINIE_Pos   (0U)
#define HASH_IMR_DINIE_Msk   (0x1UL << HASH_IMR_DINIE_Pos)     /*!< 0x00000001 */
#define HASH_IMR_DINIE       HASH_IMR_DINIE_Msk                /*!< Data input interrupt enable */
#define HASH_IMR_DCIE_Pos    (1U)
#define HASH_IMR_DCIE_Msk    (0x1UL << HASH_IMR_DCIE_Pos)      /*!< 0x00000002 */
#define HASH_IMR_DCIE        HASH_IMR_DCIE_Msk                 /*!< Digest calculation completion interrupt enable */

/* *************************************  Bit definition for HASH_SR register  ************************************** */
#define HASH_SR_DINIS_Pos    (0U)
#define HASH_SR_DINIS_Msk    (0x1UL << HASH_SR_DINIS_Pos)      /*!< 0x00000001 */
#define HASH_SR_DINIS        HASH_SR_DINIS_Msk                 /*!< Data input interrupt status */
#define HASH_SR_DCIS_Pos     (1U)
#define HASH_SR_DCIS_Msk     (0x1UL << HASH_SR_DCIS_Pos)       /*!< 0x00000002 */
#define HASH_SR_DCIS         HASH_SR_DCIS_Msk                  /*!< Digest calculation completion interrupt status */
#define HASH_SR_DMAS_Pos     (2U)
#define HASH_SR_DMAS_Msk     (0x1UL << HASH_SR_DMAS_Pos)       /*!< 0x00000004 */
#define HASH_SR_DMAS         HASH_SR_DMAS_Msk                  /*!< DMA Status */
#define HASH_SR_BUSY_Pos     (3U)
#define HASH_SR_BUSY_Msk     (0x1UL << HASH_SR_BUSY_Pos)       /*!< 0x00000008 */
#define HASH_SR_BUSY         HASH_SR_BUSY_Msk                  /*!< Busy bit */
#define HASH_SR_NBWP_Pos     (9U)
#define HASH_SR_NBWP_Msk     (0x1FUL << HASH_SR_NBWP_Pos)      /*!< 0x00003E00 */
#define HASH_SR_NBWP         HASH_SR_NBWP_Msk                  /*!< Number of words already pushed */
#define HASH_SR_NBWP_0       (0x1UL << HASH_SR_NBWP_Pos)       /*!< 0x00000200 */
#define HASH_SR_NBWP_1       (0x2UL << HASH_SR_NBWP_Pos)       /*!< 0x00000400 */
#define HASH_SR_NBWP_2       (0x4UL << HASH_SR_NBWP_Pos)       /*!< 0x00000800 */
#define HASH_SR_NBWP_3       (0x8UL << HASH_SR_NBWP_Pos)       /*!< 0x00001000 */
#define HASH_SR_NBWP_4       (0x10UL << HASH_SR_NBWP_Pos)      /*!< 0x00002000 */
#define HASH_SR_DINNE_Pos    (15U)
#define HASH_SR_DINNE_Msk    (0x1UL << HASH_SR_DINNE_Pos)      /*!< 0x00008000 */
#define HASH_SR_DINNE        HASH_SR_DINNE_Msk                 /*!< DIN not empty */
#define HASH_SR_NBWE_Pos     (16U)
#define HASH_SR_NBWE_Msk     (0x1FUL << HASH_SR_NBWE_Pos)      /*!< 0x001F0000 */
#define HASH_SR_NBWE         HASH_SR_NBWE_Msk                  /*!< Number of words expected */
#define HASH_SR_NBWE_0       (0x1UL << HASH_SR_NBWE_Pos)       /*!< 0x00010000 */
#define HASH_SR_NBWE_1       (0x2UL << HASH_SR_NBWE_Pos)       /*!< 0x00020000 */
#define HASH_SR_NBWE_2       (0x4UL << HASH_SR_NBWE_Pos)       /*!< 0x00040000 */
#define HASH_SR_NBWE_3       (0x8UL << HASH_SR_NBWE_Pos)       /*!< 0x00080000 */
#define HASH_SR_NBWE_4       (0x10UL << HASH_SR_NBWE_Pos)      /*!< 0x00100000 */

/* *************************************  Bit definition for HASH_CSR register  ************************************* */
#define HASH_CSR_CS_Pos     (0U)
#define HASH_CSR_CS_Msk     (0xFFFFFFFFUL << HASH_CSR_CS_Pos)  /*!< 0xFFFFFFFF */
#define HASH_CSR_CS         HASH_CSR_CS_Msk                    /*!< Context swap x */

/* *************************************  Bit definition for HASH_HR register  ************************************** */
#define HASH_HR_H_Pos       (0U)
#define HASH_HR_H_Msk       (0xFFFFFFFFUL << HASH_HR_H_Pos)    /*!< 0xFFFFFFFF */
#define HASH_HR_H           HASH_HR_H_Msk                      /*!< Hash data x */

/******************************************************************************/
/*                                                                            */
/*                  Inter-integrated Circuit Interface (I2C)                  */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for I2C_CR1 register  *******************/
#define I2C_CR1_PE_Pos                      (0U)
#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)               /*!< 0x00000001 */
#define I2C_CR1_PE                          I2C_CR1_PE_Msk                          /*!< Peripheral enable */
#define I2C_CR1_TXIE_Pos                    (1U)
#define I2C_CR1_TXIE_Msk                    (0x1UL << I2C_CR1_TXIE_Pos)             /*!< 0x00000002 */
#define I2C_CR1_TXIE                        I2C_CR1_TXIE_Msk                        /*!< TX interrupt enable */
#define I2C_CR1_RXIE_Pos                    (2U)
#define I2C_CR1_RXIE_Msk                    (0x1UL << I2C_CR1_RXIE_Pos)             /*!< 0x00000004 */
#define I2C_CR1_RXIE                        I2C_CR1_RXIE_Msk                        /*!< RX interrupt enable */
#define I2C_CR1_ADDRIE_Pos                  (3U)
#define I2C_CR1_ADDRIE_Msk                  (0x1UL << I2C_CR1_ADDRIE_Pos)           /*!< 0x00000008 */
#define I2C_CR1_ADDRIE                      I2C_CR1_ADDRIE_Msk                      /*!< Address match interrupt enable */
#define I2C_CR1_NACKIE_Pos                  (4U)
#define I2C_CR1_NACKIE_Msk                  (0x1UL << I2C_CR1_NACKIE_Pos)           /*!< 0x00000010 */
#define I2C_CR1_NACKIE                      I2C_CR1_NACKIE_Msk                      /*!< NACK received interrupt enable */
#define I2C_CR1_STOPIE_Pos                  (5U)
#define I2C_CR1_STOPIE_Msk                  (0x1UL << I2C_CR1_STOPIE_Pos)           /*!< 0x00000020 */
#define I2C_CR1_STOPIE                      I2C_CR1_STOPIE_Msk                      /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE_Pos                    (6U)
#define I2C_CR1_TCIE_Msk                    (0x1UL << I2C_CR1_TCIE_Pos)             /*!< 0x00000040 */
#define I2C_CR1_TCIE                        I2C_CR1_TCIE_Msk                        /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE_Pos                   (7U)
#define I2C_CR1_ERRIE_Msk                   (0x1UL << I2C_CR1_ERRIE_Pos)            /*!< 0x00000080 */
#define I2C_CR1_ERRIE                       I2C_CR1_ERRIE_Msk                       /*!< Errors interrupt enable */
#define I2C_CR1_DNF_Pos                     (8U)
#define I2C_CR1_DNF_Msk                     (0xFUL << I2C_CR1_DNF_Pos)              /*!< 0x00000F00 */
#define I2C_CR1_DNF                         I2C_CR1_DNF_Msk                         /*!< Digital noise filter */
#define I2C_CR1_ANFOFF_Pos                  (12U)
#define I2C_CR1_ANFOFF_Msk                  (0x1UL << I2C_CR1_ANFOFF_Pos)           /*!< 0x00001000 */
#define I2C_CR1_ANFOFF                      I2C_CR1_ANFOFF_Msk                      /*!< Analog noise filter OFF */
#define I2C_CR1_TXDMAEN_Pos                 (14U)
#define I2C_CR1_TXDMAEN_Msk                 (0x1UL << I2C_CR1_TXDMAEN_Pos)          /*!< 0x00004000 */
#define I2C_CR1_TXDMAEN                     I2C_CR1_TXDMAEN_Msk                     /*!< DMA transmission requests enable */
#define I2C_CR1_RXDMAEN_Pos                 (15U)
#define I2C_CR1_RXDMAEN_Msk                 (0x1UL << I2C_CR1_RXDMAEN_Pos)          /*!< 0x00008000 */
#define I2C_CR1_RXDMAEN                     I2C_CR1_RXDMAEN_Msk                     /*!< DMA reception requests enable */
#define I2C_CR1_SBC_Pos                     (16U)
#define I2C_CR1_SBC_Msk                     (0x1UL << I2C_CR1_SBC_Pos)              /*!< 0x00010000 */
#define I2C_CR1_SBC                         I2C_CR1_SBC_Msk                         /*!< Slave byte control */
#define I2C_CR1_NOSTRETCH_Pos               (17U)
#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)        /*!< 0x00020000 */
#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk                   /*!< Clock stretching disable */
#define I2C_CR1_WUPEN_Pos                   (18U)
#define I2C_CR1_WUPEN_Msk                   (0x1UL << I2C_CR1_WUPEN_Pos)            /*!< 0x00040000 */
#define I2C_CR1_WUPEN                       I2C_CR1_WUPEN_Msk                       /*!< Wakeup from STOP enable */
#define I2C_CR1_GCEN_Pos                    (19U)
#define I2C_CR1_GCEN_Msk                    (0x1UL << I2C_CR1_GCEN_Pos)             /*!< 0x00080000 */
#define I2C_CR1_GCEN                        I2C_CR1_GCEN_Msk                        /*!< General call enable */
#define I2C_CR1_SMBHEN_Pos                  (20U)
#define I2C_CR1_SMBHEN_Msk                  (0x1UL << I2C_CR1_SMBHEN_Pos)           /*!< 0x00100000 */
#define I2C_CR1_SMBHEN                      I2C_CR1_SMBHEN_Msk                      /*!< SMBus host address enable */
#define I2C_CR1_SMBDEN_Pos                  (21U)
#define I2C_CR1_SMBDEN_Msk                  (0x1UL << I2C_CR1_SMBDEN_Pos)           /*!< 0x00200000 */
#define I2C_CR1_SMBDEN                      I2C_CR1_SMBDEN_Msk                      /*!< SMBus device default address enable */
#define I2C_CR1_ALERTEN_Pos                 (22U)
#define I2C_CR1_ALERTEN_Msk                 (0x1UL << I2C_CR1_ALERTEN_Pos)          /*!< 0x00400000 */
#define I2C_CR1_ALERTEN                     I2C_CR1_ALERTEN_Msk                     /*!< SMBus alert enable */
#define I2C_CR1_PECEN_Pos                   (23U)
#define I2C_CR1_PECEN_Msk                   (0x1UL << I2C_CR1_PECEN_Pos)            /*!< 0x00800000 */
#define I2C_CR1_PECEN                       I2C_CR1_PECEN_Msk                       /*!< PEC enable */
#define I2C_CR1_FMP_Pos                     (24U)
#define I2C_CR1_FMP_Msk                     (0x1UL << I2C_CR1_FMP_Pos)            /*!< 0x01000000 */
#define I2C_CR1_FMP                         I2C_CR1_FMP_Msk                       /*!< Fast-mode Plus 20 mA drive enable */
#define I2C_CR1_ADDRACLR_Pos                (30U)
#define I2C_CR1_ADDRACLR_Msk                (0x1UL << I2C_CR1_ADDRACLR_Pos)         /*!< 0x40000000 */
#define I2C_CR1_ADDRACLR                    I2C_CR1_ADDRACLR_Msk                    /*!< ADDRACLR enable */
#define I2C_CR1_STOPFACLR_Pos               (31U)
#define I2C_CR1_STOPFACLR_Msk               (0x1UL << I2C_CR1_STOPFACLR_Pos)        /*!< 0x80000000 */
#define I2C_CR1_STOPFACLR                   I2C_CR1_STOPFACLR_Msk                   /*!< STOPFACLR enable */

/******************  Bit definition for I2C_CR2 register  ********************/
#define I2C_CR2_SADD_Pos                    (0U)
#define I2C_CR2_SADD_Msk                    (0x3FFUL << I2C_CR2_SADD_Pos)           /*!< 0x000003FF */
#define I2C_CR2_SADD                        I2C_CR2_SADD_Msk                        /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN_Pos                  (10U)
#define I2C_CR2_RD_WRN_Msk                  (0x1UL << I2C_CR2_RD_WRN_Pos)           /*!< 0x00000400 */
#define I2C_CR2_RD_WRN                      I2C_CR2_RD_WRN_Msk                      /*!< Transfer direction (master mode) */
#define I2C_CR2_ADD10_Pos                   (11U)
#define I2C_CR2_ADD10_Msk                   (0x1UL << I2C_CR2_ADD10_Pos)            /*!< 0x00000800 */
#define I2C_CR2_ADD10                       I2C_CR2_ADD10_Msk                       /*!< 10-bit addressing mode (master mode) */
#define I2C_CR2_HEAD10R_Pos                 (12U)
#define I2C_CR2_HEAD10R_Msk                 (0x1UL << I2C_CR2_HEAD10R_Pos)          /*!< 0x00001000 */
#define I2C_CR2_HEAD10R                     I2C_CR2_HEAD10R_Msk                     /*!< 10-bit address header only read direction (master mode) */
#define I2C_CR2_START_Pos                   (13U)
#define I2C_CR2_START_Msk                   (0x1UL << I2C_CR2_START_Pos)            /*!< 0x00002000 */
#define I2C_CR2_START                       I2C_CR2_START_Msk                       /*!< START generation */
#define I2C_CR2_STOP_Pos                    (14U)
#define I2C_CR2_STOP_Msk                    (0x1UL << I2C_CR2_STOP_Pos)             /*!< 0x00004000 */
#define I2C_CR2_STOP                        I2C_CR2_STOP_Msk                        /*!< STOP generation (master mode) */
#define I2C_CR2_NACK_Pos                    (15U)
#define I2C_CR2_NACK_Msk                    (0x1UL << I2C_CR2_NACK_Pos)             /*!< 0x00008000 */
#define I2C_CR2_NACK                        I2C_CR2_NACK_Msk                        /*!< NACK generation (slave mode) */
#define I2C_CR2_NBYTES_Pos                  (16U)
#define I2C_CR2_NBYTES_Msk                  (0xFFUL << I2C_CR2_NBYTES_Pos)          /*!< 0x00FF0000 */
#define I2C_CR2_NBYTES                      I2C_CR2_NBYTES_Msk                      /*!< Number of bytes */
#define I2C_CR2_RELOAD_Pos                  (24U)
#define I2C_CR2_RELOAD_Msk                  (0x1UL << I2C_CR2_RELOAD_Pos)           /*!< 0x01000000 */
#define I2C_CR2_RELOAD                      I2C_CR2_RELOAD_Msk                      /*!< NBYTES reload mode */
#define I2C_CR2_AUTOEND_Pos                 (25U)
#define I2C_CR2_AUTOEND_Msk                 (0x1UL << I2C_CR2_AUTOEND_Pos)          /*!< 0x02000000 */
#define I2C_CR2_AUTOEND                     I2C_CR2_AUTOEND_Msk                     /*!< Automatic end mode (master mode) */
#define I2C_CR2_PECBYTE_Pos                 (26U)
#define I2C_CR2_PECBYTE_Msk                 (0x1UL << I2C_CR2_PECBYTE_Pos)          /*!< 0x04000000 */
#define I2C_CR2_PECBYTE                     I2C_CR2_PECBYTE_Msk                     /*!< Packet error checking byte */

/*******************  Bit definition for I2C_OAR1 register  ******************/
#define I2C_OAR1_OA1_Pos                    (0U)
#define I2C_OAR1_OA1_Msk                    (0x3FFUL << I2C_OAR1_OA1_Pos)           /*!< 0x000003FF */
#define I2C_OAR1_OA1                        I2C_OAR1_OA1_Msk                        /*!< Interface own address 1 */
#define I2C_OAR1_OA1MODE_Pos                (10U)
#define I2C_OAR1_OA1MODE_Msk                (0x1UL << I2C_OAR1_OA1MODE_Pos)         /*!< 0x00000400 */
#define I2C_OAR1_OA1MODE                    I2C_OAR1_OA1MODE_Msk                    /*!< Own address 1 10-bit mode */
#define I2C_OAR1_OA1EN_Pos                  (15U)
#define I2C_OAR1_OA1EN_Msk                  (0x1UL << I2C_OAR1_OA1EN_Pos)           /*!< 0x00008000 */
#define I2C_OAR1_OA1EN                      I2C_OAR1_OA1EN_Msk                      /*!< Own address 1 enable */

/*******************  Bit definition for I2C_OAR2 register  ******************/
#define I2C_OAR2_OA2_Pos                    (1U)
#define I2C_OAR2_OA2_Msk                    (0x7FUL << I2C_OAR2_OA2_Pos)            /*!< 0x000000FE */
#define I2C_OAR2_OA2                        I2C_OAR2_OA2_Msk                        /*!< Interface own address 2 */
#define I2C_OAR2_OA2MSK_Pos                 (8U)
#define I2C_OAR2_OA2MSK_Msk                 (0x7UL << I2C_OAR2_OA2MSK_Pos)          /*!< 0x00000700 */
#define I2C_OAR2_OA2MSK                     I2C_OAR2_OA2MSK_Msk                     /*!< Own address 2 masks */
#define I2C_OAR2_OA2NOMASK                  (0x00000000UL)                          /*!< No mask                                        */
#define I2C_OAR2_OA2MASK01_Pos              (8U)
#define I2C_OAR2_OA2MASK01_Msk              (0x1UL << I2C_OAR2_OA2MASK01_Pos)       /*!< 0x00000100 */
#define I2C_OAR2_OA2MASK01                  I2C_OAR2_OA2MASK01_Msk                  /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
#define I2C_OAR2_OA2MASK02_Pos              (9U)
#define I2C_OAR2_OA2MASK02_Msk              (0x1UL << I2C_OAR2_OA2MASK02_Pos)       /*!< 0x00000200 */
#define I2C_OAR2_OA2MASK02                  I2C_OAR2_OA2MASK02_Msk                  /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
#define I2C_OAR2_OA2MASK03_Pos              (8U)
#define I2C_OAR2_OA2MASK03_Msk              (0x3UL << I2C_OAR2_OA2MASK03_Pos)       /*!< 0x00000300 */
#define I2C_OAR2_OA2MASK03                  I2C_OAR2_OA2MASK03_Msk                  /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
#define I2C_OAR2_OA2MASK04_Pos              (10U)
#define I2C_OAR2_OA2MASK04_Msk              (0x1UL << I2C_OAR2_OA2MASK04_Pos)       /*!< 0x00000400 */
#define I2C_OAR2_OA2MASK04                  I2C_OAR2_OA2MASK04_Msk                  /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
#define I2C_OAR2_OA2MASK05_Pos              (8U)
#define I2C_OAR2_OA2MASK05_Msk              (0x5UL << I2C_OAR2_OA2MASK05_Pos)       /*!< 0x00000500 */
#define I2C_OAR2_OA2MASK05                  I2C_OAR2_OA2MASK05_Msk                  /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
#define I2C_OAR2_OA2MASK06_Pos              (9U)
#define I2C_OAR2_OA2MASK06_Msk              (0x3UL << I2C_OAR2_OA2MASK06_Pos)       /*!< 0x00000600 */
#define I2C_OAR2_OA2MASK06                  I2C_OAR2_OA2MASK06_Msk                  /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
#define I2C_OAR2_OA2MASK07_Pos              (8U)
#define I2C_OAR2_OA2MASK07_Msk              (0x7UL << I2C_OAR2_OA2MASK07_Pos)       /*!< 0x00000700 */
#define I2C_OAR2_OA2MASK07                  I2C_OAR2_OA2MASK07_Msk                  /*!< OA2[7:1] is masked, No comparison is done      */
#define I2C_OAR2_OA2EN_Pos                  (15U)
#define I2C_OAR2_OA2EN_Msk                  (0x1UL << I2C_OAR2_OA2EN_Pos)           /*!< 0x00008000 */
#define I2C_OAR2_OA2EN                      I2C_OAR2_OA2EN_Msk                      /*!< Own address 2 enable */

/*******************  Bit definition for I2C_TIMINGR register *******************/
#define I2C_TIMINGR_SCLL_Pos                (0U)
#define I2C_TIMINGR_SCLL_Msk                (0xFFUL << I2C_TIMINGR_SCLL_Pos)        /*!< 0x000000FF */
#define I2C_TIMINGR_SCLL                    I2C_TIMINGR_SCLL_Msk                    /*!< SCL low period (master mode) */
#define I2C_TIMINGR_SCLH_Pos                (8U)
#define I2C_TIMINGR_SCLH_Msk                (0xFFUL << I2C_TIMINGR_SCLH_Pos)        /*!< 0x0000FF00 */
#define I2C_TIMINGR_SCLH                    I2C_TIMINGR_SCLH_Msk                    /*!< SCL high period (master mode) */
#define I2C_TIMINGR_SDADEL_Pos              (16U)
#define I2C_TIMINGR_SDADEL_Msk              (0xFUL << I2C_TIMINGR_SDADEL_Pos)       /*!< 0x000F0000 */
#define I2C_TIMINGR_SDADEL                  I2C_TIMINGR_SDADEL_Msk                  /*!< Data hold time */
#define I2C_TIMINGR_SCLDEL_Pos              (20U)
#define I2C_TIMINGR_SCLDEL_Msk              (0xFUL << I2C_TIMINGR_SCLDEL_Pos)       /*!< 0x00F00000 */
#define I2C_TIMINGR_SCLDEL                  I2C_TIMINGR_SCLDEL_Msk                  /*!< Data setup time */
#define I2C_TIMINGR_PRESC_Pos               (28U)
#define I2C_TIMINGR_PRESC_Msk               (0xFUL << I2C_TIMINGR_PRESC_Pos)        /*!< 0xF0000000 */
#define I2C_TIMINGR_PRESC                   I2C_TIMINGR_PRESC_Msk                   /*!< Timings prescaler */

/******************* Bit definition for I2C_TIMEOUTR register *******************/
#define I2C_TIMEOUTR_TIMEOUTA_Pos           (0U)
#define I2C_TIMEOUTR_TIMEOUTA_Msk           (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)  /*!< 0x00000FFF */
#define I2C_TIMEOUTR_TIMEOUTA               I2C_TIMEOUTR_TIMEOUTA_Msk               /*!< Bus timeout A */
#define I2C_TIMEOUTR_TIDLE_Pos              (12U)
#define I2C_TIMEOUTR_TIDLE_Msk              (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)       /*!< 0x00001000 */
#define I2C_TIMEOUTR_TIDLE                  I2C_TIMEOUTR_TIDLE_Msk                  /*!< Idle clock timeout detection */
#define I2C_TIMEOUTR_TIMOUTEN_Pos           (15U)
#define I2C_TIMEOUTR_TIMOUTEN_Msk           (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)    /*!< 0x00008000 */
#define I2C_TIMEOUTR_TIMOUTEN               I2C_TIMEOUTR_TIMOUTEN_Msk               /*!< Clock timeout enable */
#define I2C_TIMEOUTR_TIMEOUTB_Pos           (16U)
#define I2C_TIMEOUTR_TIMEOUTB_Msk           (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)  /*!< 0x0FFF0000 */
#define I2C_TIMEOUTR_TIMEOUTB               I2C_TIMEOUTR_TIMEOUTB_Msk               /*!< Bus timeout B*/
#define I2C_TIMEOUTR_TEXTEN_Pos             (31U)
#define I2C_TIMEOUTR_TEXTEN_Msk             (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)      /*!< 0x80000000 */
#define I2C_TIMEOUTR_TEXTEN                 I2C_TIMEOUTR_TEXTEN_Msk                 /*!< Extended clock timeout enable */

/******************  Bit definition for I2C_ISR register  *********************/
#define I2C_ISR_TXE_Pos                     (0U)
#define I2C_ISR_TXE_Msk                     (0x1UL << I2C_ISR_TXE_Pos)              /*!< 0x00000001 */
#define I2C_ISR_TXE                         I2C_ISR_TXE_Msk                         /*!< Transmit data register empty */
#define I2C_ISR_TXIS_Pos                    (1U)
#define I2C_ISR_TXIS_Msk                    (0x1UL << I2C_ISR_TXIS_Pos)             /*!< 0x00000002 */
#define I2C_ISR_TXIS                        I2C_ISR_TXIS_Msk                        /*!< Transmit interrupt status */
#define I2C_ISR_RXNE_Pos                    (2U)
#define I2C_ISR_RXNE_Msk                    (0x1UL << I2C_ISR_RXNE_Pos)             /*!< 0x00000004 */
#define I2C_ISR_RXNE                        I2C_ISR_RXNE_Msk                        /*!< Receive data register not empty */
#define I2C_ISR_ADDR_Pos                    (3U)
#define I2C_ISR_ADDR_Msk                    (0x1UL << I2C_ISR_ADDR_Pos)             /*!< 0x00000008 */
#define I2C_ISR_ADDR                        I2C_ISR_ADDR_Msk                        /*!< Address matched (slave mode)*/
#define I2C_ISR_NACKF_Pos                   (4U)
#define I2C_ISR_NACKF_Msk                   (0x1UL << I2C_ISR_NACKF_Pos)            /*!< 0x00000010 */
#define I2C_ISR_NACKF                       I2C_ISR_NACKF_Msk                       /*!< NACK received flag */
#define I2C_ISR_STOPF_Pos                   (5U)
#define I2C_ISR_STOPF_Msk                   (0x1UL << I2C_ISR_STOPF_Pos)            /*!< 0x00000020 */
#define I2C_ISR_STOPF                       I2C_ISR_STOPF_Msk                       /*!< STOP detection flag */
#define I2C_ISR_TC_Pos                      (6U)
#define I2C_ISR_TC_Msk                      (0x1UL << I2C_ISR_TC_Pos)               /*!< 0x00000040 */
#define I2C_ISR_TC                          I2C_ISR_TC_Msk                          /*!< Transfer complete (master mode) */
#define I2C_ISR_TCR_Pos                     (7U)
#define I2C_ISR_TCR_Msk                     (0x1UL << I2C_ISR_TCR_Pos)              /*!< 0x00000080 */
#define I2C_ISR_TCR                         I2C_ISR_TCR_Msk                         /*!< Transfer complete reload */
#define I2C_ISR_BERR_Pos                    (8U)
#define I2C_ISR_BERR_Msk                    (0x1UL << I2C_ISR_BERR_Pos)             /*!< 0x00000100 */
#define I2C_ISR_BERR                        I2C_ISR_BERR_Msk                        /*!< Bus error */
#define I2C_ISR_ARLO_Pos                    (9U)
#define I2C_ISR_ARLO_Msk                    (0x1UL << I2C_ISR_ARLO_Pos)             /*!< 0x00000200 */
#define I2C_ISR_ARLO                        I2C_ISR_ARLO_Msk                        /*!< Arbitration lost */
#define I2C_ISR_OVR_Pos                     (10U)
#define I2C_ISR_OVR_Msk                     (0x1UL << I2C_ISR_OVR_Pos)              /*!< 0x00000400 */
#define I2C_ISR_OVR                         I2C_ISR_OVR_Msk                         /*!< Overrun/Underrun */
#define I2C_ISR_PECERR_Pos                  (11U)
#define I2C_ISR_PECERR_Msk                  (0x1UL << I2C_ISR_PECERR_Pos)           /*!< 0x00000800 */
#define I2C_ISR_PECERR                      I2C_ISR_PECERR_Msk                      /*!< PEC error in reception */
#define I2C_ISR_TIMEOUT_Pos                 (12U)
#define I2C_ISR_TIMEOUT_Msk                 (0x1UL << I2C_ISR_TIMEOUT_Pos)          /*!< 0x00001000 */
#define I2C_ISR_TIMEOUT                     I2C_ISR_TIMEOUT_Msk                     /*!< Timeout or Tlow detection flag */
#define I2C_ISR_ALERT_Pos                   (13U)
#define I2C_ISR_ALERT_Msk                   (0x1UL << I2C_ISR_ALERT_Pos)            /*!< 0x00002000 */
#define I2C_ISR_ALERT                       I2C_ISR_ALERT_Msk                       /*!< SMBus alert */
#define I2C_ISR_BUSY_Pos                    (15U)
#define I2C_ISR_BUSY_Msk                    (0x1UL << I2C_ISR_BUSY_Pos)             /*!< 0x00008000 */
#define I2C_ISR_BUSY                        I2C_ISR_BUSY_Msk                        /*!< Bus busy */
#define I2C_ISR_DIR_Pos                     (16U)
#define I2C_ISR_DIR_Msk                     (0x1UL << I2C_ISR_DIR_Pos)              /*!< 0x00010000 */
#define I2C_ISR_DIR                         I2C_ISR_DIR_Msk                         /*!< Transfer direction (slave mode) */
#define I2C_ISR_ADDCODE_Pos                 (17U)
#define I2C_ISR_ADDCODE_Msk                 (0x7FUL << I2C_ISR_ADDCODE_Pos)         /*!< 0x00FE0000 */
#define I2C_ISR_ADDCODE                     I2C_ISR_ADDCODE_Msk                     /*!< Address match code (slave mode) */

/******************  Bit definition for I2C_ICR register  *********************/
#define I2C_ICR_ADDRCF_Pos                  (3U)
#define I2C_ICR_ADDRCF_Msk                  (0x1UL << I2C_ICR_ADDRCF_Pos)           /*!< 0x00000008 */
#define I2C_ICR_ADDRCF                      I2C_ICR_ADDRCF_Msk                      /*!< Address matched clear flag */
#define I2C_ICR_NACKCF_Pos                  (4U)
#define I2C_ICR_NACKCF_Msk                  (0x1UL << I2C_ICR_NACKCF_Pos)           /*!< 0x00000010 */
#define I2C_ICR_NACKCF                      I2C_ICR_NACKCF_Msk                      /*!< NACK clear flag */
#define I2C_ICR_STOPCF_Pos                  (5U)
#define I2C_ICR_STOPCF_Msk                  (0x1UL << I2C_ICR_STOPCF_Pos)           /*!< 0x00000020 */
#define I2C_ICR_STOPCF                      I2C_ICR_STOPCF_Msk                      /*!< STOP detection clear flag */
#define I2C_ICR_BERRCF_Pos                  (8U)
#define I2C_ICR_BERRCF_Msk                  (0x1UL << I2C_ICR_BERRCF_Pos)           /*!< 0x00000100 */
#define I2C_ICR_BERRCF                      I2C_ICR_BERRCF_Msk                      /*!< Bus error clear flag */
#define I2C_ICR_ARLOCF_Pos                  (9U)
#define I2C_ICR_ARLOCF_Msk                  (0x1UL << I2C_ICR_ARLOCF_Pos)           /*!< 0x00000200 */
#define I2C_ICR_ARLOCF                      I2C_ICR_ARLOCF_Msk                      /*!< Arbitration lost clear flag */
#define I2C_ICR_OVRCF_Pos                   (10U)
#define I2C_ICR_OVRCF_Msk                   (0x1UL << I2C_ICR_OVRCF_Pos)            /*!< 0x00000400 */
#define I2C_ICR_OVRCF                       I2C_ICR_OVRCF_Msk                       /*!< Overrun/Underrun clear flag */
#define I2C_ICR_PECCF_Pos                   (11U)
#define I2C_ICR_PECCF_Msk                   (0x1UL << I2C_ICR_PECCF_Pos)            /*!< 0x00000800 */
#define I2C_ICR_PECCF                       I2C_ICR_PECCF_Msk                       /*!< PAC error clear flag */
#define I2C_ICR_TIMOUTCF_Pos                (12U)
#define I2C_ICR_TIMOUTCF_Msk                (0x1UL << I2C_ICR_TIMOUTCF_Pos)         /*!< 0x00001000 */
#define I2C_ICR_TIMOUTCF                    I2C_ICR_TIMOUTCF_Msk                    /*!< Timeout clear flag */
#define I2C_ICR_ALERTCF_Pos                 (13U)
#define I2C_ICR_ALERTCF_Msk                 (0x1UL << I2C_ICR_ALERTCF_Pos)          /*!< 0x00002000 */
#define I2C_ICR_ALERTCF                     I2C_ICR_ALERTCF_Msk                     /*!< Alert clear flag */

/******************  Bit definition for I2C_PECR register  *********************/
#define I2C_PECR_PEC_Pos                    (0U)
#define I2C_PECR_PEC_Msk                    (0xFFUL << I2C_PECR_PEC_Pos)            /*!< 0x000000FF */
#define I2C_PECR_PEC                        I2C_PECR_PEC_Msk                        /*!< PEC register */

/******************  Bit definition for I2C_RXDR register  *********************/
#define I2C_RXDR_RXDATA_Pos                 (0U)
#define I2C_RXDR_RXDATA_Msk                 (0xFFUL << I2C_RXDR_RXDATA_Pos)         /*!< 0x000000FF */
#define I2C_RXDR_RXDATA                     I2C_RXDR_RXDATA_Msk                     /*!< 8-bit receive data */

/******************  Bit definition for I2C_TXDR register  *********************/
#define I2C_TXDR_TXDATA_Pos                 (0U)
#define I2C_TXDR_TXDATA_Msk                 (0xFFUL << I2C_TXDR_TXDATA_Pos)         /*!< 0x000000FF */
#define I2C_TXDR_TXDATA                     I2C_TXDR_TXDATA_Msk                     /*!< 8-bit transmit data */

/******************************************************************************/
/*                                                                            */
/*             Improved Inter-integrated Circuit Interface (I3C)              */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for I3C_CR register  *********************/
#define I3C_CR_DCNT_Pos                 (0U)
#define I3C_CR_DCNT_Msk                 (0xFFFFUL << I3C_CR_DCNT_Pos)         /*!< 0x0000FFFF */
#define I3C_CR_DCNT                     I3C_CR_DCNT_Msk                       /*!< Data Byte Count */
#define I3C_CR_RNW_Pos                  (16U)
#define I3C_CR_RNW_Msk                  (0x1UL << I3C_CR_RNW_Pos)             /*!< 0x00010000 */
#define I3C_CR_RNW                      I3C_CR_RNW_Msk                        /*!< Read Not Write */
#define I3C_CR_CCC_Pos                  (16U)
#define I3C_CR_CCC_Msk                  (0xFFUL << I3C_CR_CCC_Pos)            /*!< 0x00FF0000 */
#define I3C_CR_CCC                      I3C_CR_CCC_Msk                        /*!< 8-Bit CCC code */
#define I3C_CR_ADD_Pos                  (17U)
#define I3C_CR_ADD_Msk                  (0x7FUL << I3C_CR_ADD_Pos)            /*!< 0x00FE0000 */
#define I3C_CR_ADD                      I3C_CR_ADD_Msk                        /*!< Target Address */
#define I3C_CR_MTYPE_Pos                (27U)
#define I3C_CR_MTYPE_Msk                (0xFUL << I3C_CR_MTYPE_Pos)           /*!< 0xF8000000 */
#define I3C_CR_MTYPE                    I3C_CR_MTYPE_Msk                      /*!< Message Type */
#define I3C_CR_MTYPE_0                  (0x1UL << I3C_CR_MTYPE_Pos)           /*!< 0x08000000 */
#define I3C_CR_MTYPE_1                  (0x2UL << I3C_CR_MTYPE_Pos)           /*!< 0x10000000 */
#define I3C_CR_MTYPE_2                  (0x4UL << I3C_CR_MTYPE_Pos)           /*!< 0x20000000 */
#define I3C_CR_MTYPE_3                  (0x8UL << I3C_CR_MTYPE_Pos)           /*!< 0x40000000 */
#define I3C_CR_MEND_Pos                 (31U)
#define I3C_CR_MEND_Msk                 (0x1UL << I3C_CR_MEND_Pos)            /*!< 0x80000000 */
#define I3C_CR_MEND                     I3C_CR_MEND_Msk                       /*!< Message End */

/*******************  Bit definition for I3C_CFGR register  *******************/
#define I3C_CFGR_EN_Pos                 (0U)
#define I3C_CFGR_EN_Msk                 (0x1UL << I3C_CFGR_EN_Pos)            /*!< 0x00000001 */
#define I3C_CFGR_EN                     I3C_CFGR_EN_Msk                       /*!< Peripheral Enable */
#define I3C_CFGR_CRINIT_Pos             (1U)
#define I3C_CFGR_CRINIT_Msk             (0x1UL << I3C_CFGR_CRINIT_Pos)        /*!< 0x00000002 */
#define I3C_CFGR_CRINIT                 I3C_CFGR_CRINIT_Msk                   /*!< Peripheral Init mode (Target/Controller) */
#define I3C_CFGR_NOARBH_Pos             (2U)
#define I3C_CFGR_NOARBH_Msk             (0x1UL << I3C_CFGR_NOARBH_Pos)        /*!< 0x00000004 */
#define I3C_CFGR_NOARBH                 I3C_CFGR_NOARBH_Msk                   /*!< No Arbitration Header (7'h7E)*/
#define I3C_CFGR_RSTPTRN_Pos            (3U)
#define I3C_CFGR_RSTPTRN_Msk            (0x1UL << I3C_CFGR_RSTPTRN_Pos)       /*!< 0x00000008 */
#define I3C_CFGR_RSTPTRN                I3C_CFGR_RSTPTRN_Msk                  /*!< Reset Pattern enable */
#define I3C_CFGR_EXITPTRN_Pos           (4U)
#define I3C_CFGR_EXITPTRN_Msk           (0x1UL << I3C_CFGR_EXITPTRN_Pos)      /*!< 0x00000010 */
#define I3C_CFGR_EXITPTRN               I3C_CFGR_EXITPTRN_Msk                 /*!< Exit Pattern enable */
#define I3C_CFGR_HKSDAEN_Pos            (5U)
#define I3C_CFGR_HKSDAEN_Msk            (0x1UL << I3C_CFGR_HKSDAEN_Pos)       /*!< 0x00000020 */
#define I3C_CFGR_HKSDAEN                I3C_CFGR_HKSDAEN_Msk                  /*!< High-Keeper on SDA Enable */
#define I3C_CFGR_HJACK_Pos              (7U)
#define I3C_CFGR_HJACK_Msk              (0x1UL << I3C_CFGR_HJACK_Pos)         /*!< 0x00000080 */
#define I3C_CFGR_HJACK                  I3C_CFGR_HJACK_Msk                    /*!< Hot Join Acknowledgment */
#define I3C_CFGR_RXDMAEN_Pos            (8U)
#define I3C_CFGR_RXDMAEN_Msk            (0x1UL << I3C_CFGR_RXDMAEN_Pos)       /*!< 0x00000100 */
#define I3C_CFGR_RXDMAEN                I3C_CFGR_RXDMAEN_Msk                  /*!< RX FIFO DMA mode Enable */
#define I3C_CFGR_RXFLUSH_Pos            (9U)
#define I3C_CFGR_RXFLUSH_Msk            (0x1UL << I3C_CFGR_RXFLUSH_Pos)       /*!< 0x00000200 */
#define I3C_CFGR_RXFLUSH                I3C_CFGR_RXFLUSH_Msk                  /*!< RX FIFO Flush */
#define I3C_CFGR_RXTHRES_Pos            (10U)
#define I3C_CFGR_RXTHRES_Msk            (0x1UL << I3C_CFGR_RXTHRES_Pos)       /*!< 0x00000400 */
#define I3C_CFGR_RXTHRES                I3C_CFGR_RXTHRES_Msk                  /*!< RX FIFO Threshold */
#define I3C_CFGR_TXDMAEN_Pos            (12U)
#define I3C_CFGR_TXDMAEN_Msk            (0x1UL << I3C_CFGR_TXDMAEN_Pos)       /*!< 0x00001000 */
#define I3C_CFGR_TXDMAEN                I3C_CFGR_TXDMAEN_Msk                  /*!< TX FIFO DMA mode Enable */
#define I3C_CFGR_TXFLUSH_Pos            (13U)
#define I3C_CFGR_TXFLUSH_Msk            (0x1UL << I3C_CFGR_TXFLUSH_Pos)       /*!< 0x00002000 */
#define I3C_CFGR_TXFLUSH                I3C_CFGR_TXFLUSH_Msk                  /*!< TX FIFO Flush */
#define I3C_CFGR_TXTHRES_Pos            (14U)
#define I3C_CFGR_TXTHRES_Msk            (0x1UL << I3C_CFGR_TXTHRES_Pos)       /*!< 0x00004000 */
#define I3C_CFGR_TXTHRES                I3C_CFGR_TXTHRES_Msk                  /*!< TX FIFO Threshold */
#define I3C_CFGR_SDMAEN_Pos             (16U)
#define I3C_CFGR_SDMAEN_Msk             (0x1UL << I3C_CFGR_SDMAEN_Pos)        /*!< 0x00010000 */
#define I3C_CFGR_SDMAEN                 I3C_CFGR_SDMAEN_Msk                   /*!< Status FIFO DMA mode Enable */
#define I3C_CFGR_SFLUSH_Pos             (17U)
#define I3C_CFGR_SFLUSH_Msk             (0x1UL << I3C_CFGR_SFLUSH_Pos)        /*!< 0x00020000 */
#define I3C_CFGR_SFLUSH                 I3C_CFGR_SFLUSH_Msk                   /*!< Status FIFO Flush */
#define I3C_CFGR_SMODE_Pos              (18U)
#define I3C_CFGR_SMODE_Msk              (0x1UL << I3C_CFGR_SMODE_Pos)         /*!< 0x00040000 */
#define I3C_CFGR_SMODE                  I3C_CFGR_SMODE_Msk                    /*!< Status FIFO mode Enable */
#define I3C_CFGR_TMODE_Pos              (19U)
#define I3C_CFGR_TMODE_Msk              (0x1UL << I3C_CFGR_TMODE_Pos)         /*!< 0x00080000 */
#define I3C_CFGR_TMODE                  I3C_CFGR_TMODE_Msk                    /*!< Control FIFO mode Enable */
#define I3C_CFGR_CDMAEN_Pos             (20U)
#define I3C_CFGR_CDMAEN_Msk             (0x1UL << I3C_CFGR_CDMAEN_Pos)        /*!< 0x00100000 */
#define I3C_CFGR_CDMAEN                 I3C_CFGR_CDMAEN_Msk                   /*!< Control FIFO DMA mode Enable */
#define I3C_CFGR_CFLUSH_Pos             (21U)
#define I3C_CFGR_CFLUSH_Msk             (0x1UL << I3C_CFGR_CFLUSH_Pos)        /*!< 0x00200000 */
#define I3C_CFGR_CFLUSH                 I3C_CFGR_CFLUSH_Msk                   /*!< Control FIFO Flush */
#define I3C_CFGR_FCFDIS_Pos             (23U)
#define I3C_CFGR_FCFDIS_Msk             (0x1UL << I3C_CFGR_FCFDIS_Pos)        /*!< 0x00800000 */
#define I3C_CFGR_FCFDIS                 I3C_CFGR_FCFDIS_Msk                   /*!< FCF generation disable */
#define I3C_CFGR_TSFSET_Pos             (30U)
#define I3C_CFGR_TSFSET_Msk             (0x1UL << I3C_CFGR_TSFSET_Pos)        /*!< 0x40000000 */
#define I3C_CFGR_TSFSET                 I3C_CFGR_TSFSET_Msk                   /*!< Transfer Set */

/*******************  Bit definition for I3C_RDR register  ********************/
#define I3C_RDR_RDB0_Pos                (0U)
#define I3C_RDR_RDB0_Msk                (0xFFUL << I3C_RDR_RDB0_Pos)          /*!< 0x000000FF */
#define I3C_RDR_RDB0                    I3C_RDR_RDB0_Msk                      /*!< Receive Data Byte */

/******************  Bit definition for I3C_RDWR register  ********************/
#define I3C_RDWR_RDBx_Pos               (0U)
#define I3C_RDWR_RDBx_Msk               (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos)   /*!< 0xFFFFFFFF */
#define I3C_RDWR_RDBx                   I3C_RDWR_RDBx_Msk                     /*!< Receive Data Byte, full double word */
#define I3C_RDWR_RDB0_Pos               (0U)
#define I3C_RDWR_RDB0_Msk               (0xFFUL << I3C_RDWR_RDB0_Pos)         /*!< 0x000000FF */
#define I3C_RDWR_RDB0                   I3C_RDWR_RDB0_Msk                     /*!< Receive Data Byte 0 */
#define I3C_RDWR_RDB1_Pos               (8U)
#define I3C_RDWR_RDB1_Msk               (0xFFUL << I3C_RDWR_RDB1_Pos)         /*!< 0x0000FF00 */
#define I3C_RDWR_RDB1                   I3C_RDWR_RDB1_Msk                     /*!< Receive Data Byte 1 */
#define I3C_RDWR_RDB2_Pos               (16U)
#define I3C_RDWR_RDB2_Msk               (0xFFUL << I3C_RDWR_RDB2_Pos)         /*!< 0x00FF0000 */
#define I3C_RDWR_RDB2                   I3C_RDWR_RDB2_Msk                     /*!< Receive Data Byte 2 */
#define I3C_RDWR_RDB3_Pos               (24U)
#define I3C_RDWR_RDB3_Msk               (0xFFUL << I3C_RDWR_RDB3_Pos)         /*!< 0xFF000000 */
#define I3C_RDWR_RDB3                   I3C_RDWR_RDB3_Msk                     /*!< Receive Data Byte 3 */

/*******************  Bit definition for I3C_TDR register  ********************/
#define I3C_TDR_TDB0_Pos                (0U)
#define I3C_TDR_TDB0_Msk                (0xFFUL << I3C_TDR_TDB0_Pos)          /*!< 0x000000FF */
#define I3C_TDR_TDB0                    I3C_TDR_TDB0_Msk                      /*!< Transmit Data Byte */

/******************  Bit definition for I3C_TDWR register  ********************/
#define I3C_TDWR_TDBx_Pos               (0U)
#define I3C_TDWR_TDBx_Msk               (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos)   /*!< 0xFFFFFFFF */
#define I3C_TDWR_TDBx                   I3C_TDWR_TDBx_Msk                     /*!< Transmit Data Byte, full double word */
#define I3C_TDWR_TDB0_Pos               (0U)
#define I3C_TDWR_TDB0_Msk               (0xFFUL << I3C_TDWR_TDB0_Pos)         /*!< 0x000000FF */
#define I3C_TDWR_TDB0                   I3C_TDWR_TDB0_Msk                     /*!< Transmit Data Byte 0 */
#define I3C_TDWR_TDB1_Pos               (8U)
#define I3C_TDWR_TDB1_Msk               (0xFFUL << I3C_TDWR_TDB1_Pos)         /*!< 0x0000FF00 */
#define I3C_TDWR_TDB1                   I3C_TDWR_TDB1_Msk                     /*!< Transmit Data Byte 1 */
#define I3C_TDWR_TDB2_Pos               (16U)
#define I3C_TDWR_TDB2_Msk               (0xFFUL << I3C_TDWR_TDB2_Pos)         /*!< 0x00FF0000 */
#define I3C_TDWR_TDB2                   I3C_TDWR_TDB2_Msk                     /*!< Transmit Data Byte 2 */
#define I3C_TDWR_TDB3_Pos               (24U)
#define I3C_TDWR_TDB3_Msk               (0xFFUL << I3C_TDWR_TDB3_Pos)         /*!< 0xFF000000 */
#define I3C_TDWR_TDB3                   I3C_TDWR_TDB3_Msk                     /*!< Transmit Data Byte 3 */

/*******************  Bit definition for I3C_IBIDR register  ******************/
#define I3C_IBIDR_IBIDBx_Pos            (0U)
#define I3C_IBIDR_IBIDBx_Msk            (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos) /*!< 0xFFFFFFFF */
#define I3C_IBIDR_IBIDBx                I3C_IBIDR_IBIDBx_Msk                   /*!< IBI Data Byte, full double word */
#define I3C_IBIDR_IBIDB0_Pos            (0U)
#define I3C_IBIDR_IBIDB0_Msk            (0xFFUL << I3C_IBIDR_IBIDB0_Pos)       /*!< 0x000000FF */
#define I3C_IBIDR_IBIDB0                I3C_IBIDR_IBIDB0_Msk                   /*!< IBI Data Byte 0 */
#define I3C_IBIDR_IBIDB1_Pos            (8U)
#define I3C_IBIDR_IBIDB1_Msk            (0xFFUL << I3C_IBIDR_IBIDB1_Pos)       /*!< 0x0000FF00 */
#define I3C_IBIDR_IBIDB1                I3C_IBIDR_IBIDB1_Msk                   /*!< IBI Data Byte 1 */
#define I3C_IBIDR_IBIDB2_Pos            (16U)
#define I3C_IBIDR_IBIDB2_Msk            (0xFFUL << I3C_IBIDR_IBIDB2_Pos)       /*!< 0x00FF0000 */
#define I3C_IBIDR_IBIDB2                I3C_IBIDR_IBIDB2_Msk                   /*!< IBI Data Byte 2 */
#define I3C_IBIDR_IBIDB3_Pos            (24U)
#define I3C_IBIDR_IBIDB3_Msk            (0xFFUL << I3C_IBIDR_IBIDB3_Pos)       /*!< 0xFF000000 */
#define I3C_IBIDR_IBIDB3                I3C_IBIDR_IBIDB3_Msk                   /*!< IBI Data Byte 3 */

/******************  Bit definition for I3C_TGTTDR register  ******************/
#define I3C_TGTTDR_TGTTDCNT_Pos         (0U)
#define I3C_TGTTDR_TGTTDCNT_Msk         (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos)   /*!< 0x0000FFFF */
#define I3C_TGTTDR_TGTTDCNT             I3C_TGTTDR_TGTTDCNT_Msk                 /*!< Target Transmit Data Counter */
#define I3C_TGTTDR_PRELOAD_Pos          (16U)
#define I3C_TGTTDR_PRELOAD_Msk          (0x1UL << I3C_TGTTDR_PRELOAD_Pos)       /*!< 0x00010000 */
#define I3C_TGTTDR_PRELOAD              I3C_TGTTDR_PRELOAD_Msk                  /*!< Transmit FIFO Preload Enable/Status */

/*******************  Bit definition for I3C_SR register  *********************/
#define I3C_SR_XDCNT_Pos                (0U)
#define I3C_SR_XDCNT_Msk                (0xFFFFUL << I3C_SR_XDCNT_Pos)          /*!< 0x0000FFFF */
#define I3C_SR_XDCNT                    I3C_SR_XDCNT_Msk                        /*!< Transfer Data Byte Count status */
#define I3C_SR_ABT_Pos                  (17U)
#define I3C_SR_ABT_Msk                  (0x1UL << I3C_SR_ABT_Pos)               /*!< 0x00020000 */
#define I3C_SR_ABT                      I3C_SR_ABT_Msk                          /*!< Target Abort Indication */
#define I3C_SR_DIR_Pos                  (18U)
#define I3C_SR_DIR_Msk                  (0x1UL << I3C_SR_DIR_Pos)               /*!< 0x00040000 */
#define I3C_SR_DIR                      I3C_SR_DIR_Msk                          /*!< Message Direction */
#define I3C_SR_MID_Pos                  (24U)
#define I3C_SR_MID_Msk                  (0xFFUL << I3C_SR_MID_Pos)              /*!< 0xFF000000 */
#define I3C_SR_MID                      I3C_SR_MID_Msk                          /*!< Message Identifier */

/*******************  Bit definition for I3C_SER register  ********************/
#define I3C_SER_CODERR_Pos              (0U)
#define I3C_SER_CODERR_Msk              (0xFUL << I3C_SER_CODERR_Pos)           /*!< 0x0000000F */
#define I3C_SER_CODERR                  I3C_SER_CODERR_Msk                      /*!< Protocol Error Code */
#define I3C_SER_CODERR_0                (0x1UL << I3C_SER_CODERR_Pos)           /*!< 0x00000001 */
#define I3C_SER_CODERR_1                (0x2UL << I3C_SER_CODERR_Pos)           /*!< 0x00000002 */
#define I3C_SER_CODERR_2                (0x4UL << I3C_SER_CODERR_Pos)           /*!< 0x00000004 */
#define I3C_SER_CODERR_3                (0x8UL << I3C_SER_CODERR_Pos)           /*!< 0x00000008 */
#define I3C_SER_PERR_Pos                (4U)
#define I3C_SER_PERR_Msk                (0x1UL << I3C_SER_PERR_Pos)             /*!< 0x00000010 */
#define I3C_SER_PERR                    I3C_SER_PERR_Msk                        /*!< Protocol Error */
#define I3C_SER_STALL_Pos               (5U)
#define I3C_SER_STALL_Msk               (0x1UL << I3C_SER_STALL_Pos)            /*!< 0x00000020 */
#define I3C_SER_STALL                   I3C_SER_STALL_Msk                       /*!< SCL Stall Error */
#define I3C_SER_DOVR_Pos                (6U)
#define I3C_SER_DOVR_Msk                (0x1UL << I3C_SER_DOVR_Pos)             /*!< 0x00000040 */
#define I3C_SER_DOVR                    I3C_SER_DOVR_Msk                        /*!< RX/TX FIFO Overrun */
#define I3C_SER_COVR_Pos                (7U)
#define I3C_SER_COVR_Msk                (0x1UL << I3C_SER_COVR_Pos)             /*!< 0x00000080 */
#define I3C_SER_COVR                    I3C_SER_COVR_Msk                        /*!< Status/Control FIFO Overrun */
#define I3C_SER_ANACK_Pos               (8U)
#define I3C_SER_ANACK_Msk               (0x1UL << I3C_SER_ANACK_Pos)            /*!< 0x00000100 */
#define I3C_SER_ANACK                   I3C_SER_ANACK_Msk                       /*!< Address Not Acknowledged */
#define I3C_SER_DNACK_Pos               (9U)
#define I3C_SER_DNACK_Msk               (0x1UL << I3C_SER_DNACK_Pos)            /*!< 0x00000200 */
#define I3C_SER_DNACK                   I3C_SER_DNACK_Msk                       /*!< Data Not Acknowledged */
#define I3C_SER_DERR_Pos                (10U)
#define I3C_SER_DERR_Msk                (0x1UL << I3C_SER_DERR_Pos)             /*!< 0x00000400 */
#define I3C_SER_DERR                    I3C_SER_DERR_Msk                        /*!< Data Error during the controller-role hand-off procedure */

/*******************  Bit definition for I3C_RMR register  ********************/
#define I3C_RMR_IBIRDCNT_Pos            (0U)
#define I3C_RMR_IBIRDCNT_Msk            (0x7UL << I3C_RMR_IBIRDCNT_Pos)         /*!< 0x00000007 */
#define I3C_RMR_IBIRDCNT                I3C_RMR_IBIRDCNT_Msk                    /*!< Data Count when reading IBI data */
#define I3C_RMR_RCODE_Pos               (8U)
#define I3C_RMR_RCODE_Msk               (0xFFUL << I3C_RMR_RCODE_Pos)           /*!< 0x0000FF00 */
#define I3C_RMR_RCODE                   I3C_RMR_RCODE_Msk                       /*!< CCC code of received command */
#define I3C_RMR_RADD_Pos                (17U)
#define I3C_RMR_RADD_Msk                (0x7FUL << I3C_RMR_RADD_Pos)            /*!< 0x00FE0000 */
#define I3C_RMR_RADD                    I3C_RMR_RADD_Msk                        /*!< Target Address Received during accepted IBI or Controller-role request */

/*******************  Bit definition for I3C_EVR register  ********************/
#define I3C_EVR_CFEF_Pos                (0U)
#define I3C_EVR_CFEF_Msk                (0x1UL << I3C_EVR_CFEF_Pos)             /*!< 0x00000001 */
#define I3C_EVR_CFEF                    I3C_EVR_CFEF_Msk                        /*!< Control FIFO Empty Flag */
#define I3C_EVR_TXFEF_Pos               (1U)
#define I3C_EVR_TXFEF_Msk               (0x1UL << I3C_EVR_TXFEF_Pos)            /*!< 0x00000002 */
#define I3C_EVR_TXFEF                   I3C_EVR_TXFEF_Msk                       /*!< TX FIFO Empty Flag */
#define I3C_EVR_CFNFF_Pos               (2U)
#define I3C_EVR_CFNFF_Msk               (0x1UL << I3C_EVR_CFNFF_Pos)            /*!< 0x00000004 */
#define I3C_EVR_CFNFF                   I3C_EVR_CFNFF_Msk                       /*!< Control FIFO Not Full Flag */
#define I3C_EVR_SFNEF_Pos               (3U)
#define I3C_EVR_SFNEF_Msk               (0x1UL << I3C_EVR_SFNEF_Pos)            /*!< 0x00000008 */
#define I3C_EVR_SFNEF                   I3C_EVR_SFNEF_Msk                       /*!< Status FIFO Not Empty Flag */
#define I3C_EVR_TXFNFF_Pos              (4U)
#define I3C_EVR_TXFNFF_Msk              (0x1UL << I3C_EVR_TXFNFF_Pos)           /*!< 0x00000010 */
#define I3C_EVR_TXFNFF                  I3C_EVR_TXFNFF_Msk                      /*!< TX FIFO Not Full Flag */
#define I3C_EVR_RXFNEF_Pos              (5U)
#define I3C_EVR_RXFNEF_Msk              (0x1UL << I3C_EVR_RXFNEF_Pos)           /*!< 0x00000020 */
#define I3C_EVR_RXFNEF                  I3C_EVR_RXFNEF_Msk                      /*!< RX FIFO Not Empty Flag */
#define I3C_EVR_TXLASTF_Pos             (6U)
#define I3C_EVR_TXLASTF_Msk             (0x1UL << I3C_EVR_TXLASTF_Pos)          /*!< 0x00000040 */
#define I3C_EVR_TXLASTF                 I3C_EVR_TXLASTF_Msk                     /*!< Last TX byte available in FIFO */
#define I3C_EVR_RXLASTF_Pos             (7U)
#define I3C_EVR_RXLASTF_Msk             (0x1UL << I3C_EVR_RXLASTF_Pos)          /*!< 0x00000080 */
#define I3C_EVR_RXLASTF                 I3C_EVR_RXLASTF_Msk                     /*!< Last RX byte read from FIFO */
#define I3C_EVR_FCF_Pos                 (9U)
#define I3C_EVR_FCF_Msk                 (0x1UL << I3C_EVR_FCF_Pos)              /*!< 0x00000200 */
#define I3C_EVR_FCF                     I3C_EVR_FCF_Msk                         /*!< Frame Complete Flag */
#define I3C_EVR_RXTGTENDF_Pos           (10U)
#define I3C_EVR_RXTGTENDF_Msk           (0x1UL << I3C_EVR_RXTGTENDF_Pos)        /*!< 0x00000400 */
#define I3C_EVR_RXTGTENDF               I3C_EVR_RXTGTENDF_Msk                   /*!< Reception Target End Flag */
#define I3C_EVR_ERRF_Pos                (11U)
#define I3C_EVR_ERRF_Msk                (0x1UL << I3C_EVR_ERRF_Pos)             /*!< 0x00000800 */
#define I3C_EVR_ERRF                    I3C_EVR_ERRF_Msk                        /*!< Error Flag */
#define I3C_EVR_IBIF_Pos                (15U)
#define I3C_EVR_IBIF_Msk                (0x1UL << I3C_EVR_IBIF_Pos)             /*!< 0x00008000 */
#define I3C_EVR_IBIF                    I3C_EVR_IBIF_Msk                        /*!< IBI Flag */
#define I3C_EVR_IBIENDF_Pos             (16U)
#define I3C_EVR_IBIENDF_Msk             (0x1UL << I3C_EVR_IBIENDF_Pos)          /*!< 0x00010000 */
#define I3C_EVR_IBIENDF                 I3C_EVR_IBIENDF_Msk                     /*!< IBI End Flag */
#define I3C_EVR_CRF_Pos                 (17U)
#define I3C_EVR_CRF_Msk                 (0x1UL << I3C_EVR_CRF_Pos)              /*!< 0x00020000 */
#define I3C_EVR_CRF                     I3C_EVR_CRF_Msk                         /*!< Controller-role Request Flag */
#define I3C_EVR_CRUPDF_Pos              (18U)
#define I3C_EVR_CRUPDF_Msk              (0x1UL << I3C_EVR_CRUPDF_Pos)           /*!< 0x00040000 */
#define I3C_EVR_CRUPDF                  I3C_EVR_CRUPDF_Msk                      /*!< Controller-role Update Flag */
#define I3C_EVR_HJF_Pos                 (19U)
#define I3C_EVR_HJF_Msk                 (0x1UL << I3C_EVR_HJF_Pos)              /*!< 0x00080000 */
#define I3C_EVR_HJF                     I3C_EVR_HJF_Msk                         /*!< Hot Join Flag */
#define I3C_EVR_WKPF_Pos                (21U)
#define I3C_EVR_WKPF_Msk                (0x1UL << I3C_EVR_WKPF_Pos)             /*!< 0x00200000 */
#define I3C_EVR_WKPF                    I3C_EVR_WKPF_Msk                        /*!< Wake Up Flag */
#define I3C_EVR_GETF_Pos                (22U)
#define I3C_EVR_GETF_Msk                (0x1UL << I3C_EVR_GETF_Pos)             /*!< 0x00400000 */
#define I3C_EVR_GETF                    I3C_EVR_GETF_Msk                        /*!< Get type CCC received Flag */
#define I3C_EVR_STAF_Pos                (23U)
#define I3C_EVR_STAF_Msk                (0x1UL << I3C_EVR_STAF_Pos)             /*!< 0x00800000 */
#define I3C_EVR_STAF                    I3C_EVR_STAF_Msk                        /*!< Get Status Flag */
#define I3C_EVR_DAUPDF_Pos              (24U)
#define I3C_EVR_DAUPDF_Msk              (0x1UL << I3C_EVR_DAUPDF_Pos)           /*!< 0x01000000 */
#define I3C_EVR_DAUPDF                  I3C_EVR_DAUPDF_Msk                      /*!< Dynamic Address Update Flag */
#define I3C_EVR_MWLUPDF_Pos             (25U)
#define I3C_EVR_MWLUPDF_Msk             (0x1UL << I3C_EVR_MWLUPDF_Pos)          /*!< 0x02000000 */
#define I3C_EVR_MWLUPDF                 I3C_EVR_MWLUPDF_Msk                     /*!< Max Write Length Update Flag */
#define I3C_EVR_MRLUPDF_Pos             (26U)
#define I3C_EVR_MRLUPDF_Msk             (0x1UL << I3C_EVR_MRLUPDF_Pos)          /*!< 0x04000000 */
#define I3C_EVR_MRLUPDF                 I3C_EVR_MRLUPDF_Msk                     /*!< Max Read Length Update Flag */
#define I3C_EVR_RSTF_Pos                (27U)
#define I3C_EVR_RSTF_Msk                (0x1UL << I3C_EVR_RSTF_Pos)             /*!< 0x08000000 */
#define I3C_EVR_RSTF                    I3C_EVR_RSTF_Msk                        /*!< Reset Flag, due to Reset pattern received */
#define I3C_EVR_ASUPDF_Pos              (28U)
#define I3C_EVR_ASUPDF_Msk              (0x1UL << I3C_EVR_ASUPDF_Pos)           /*!< 0x10000000 */
#define I3C_EVR_ASUPDF                  I3C_EVR_ASUPDF_Msk                      /*!< Activity State Flag */
#define I3C_EVR_INTUPDF_Pos             (29U)
#define I3C_EVR_INTUPDF_Msk             (0x1UL << I3C_EVR_INTUPDF_Pos)          /*!< 0x20000000 */
#define I3C_EVR_INTUPDF                 I3C_EVR_INTUPDF_Msk                     /*!< Interrupt Update Flag */
#define I3C_EVR_DEFF_Pos                (30U)
#define I3C_EVR_DEFF_Msk                (0x1UL << I3C_EVR_DEFF_Pos)             /*!< 0x40000000 */
#define I3C_EVR_DEFF                    I3C_EVR_DEFF_Msk                        /*!< List of Targets Command Received Flag */
#define I3C_EVR_GRPF_Pos                (31U)
#define I3C_EVR_GRPF_Msk                (0x1UL << I3C_EVR_GRPF_Pos)             /*!< 0x80000000 */
#define I3C_EVR_GRPF                    I3C_EVR_GRPF_Msk                        /*!< List of Group Addresses Command Received Flag */

/*******************  Bit definition for I3C_IER register  ********************/
#define I3C_IER_CFNFIE_Pos              (2U)
#define I3C_IER_CFNFIE_Msk              (0x1UL << I3C_IER_CFNFIE_Pos)           /*!< 0x00000004 */
#define I3C_IER_CFNFIE                  I3C_IER_CFNFIE_Msk                      /*!< Control FIFO Not Full Interrupt Enable */
#define I3C_IER_SFNEIE_Pos              (3U)
#define I3C_IER_SFNEIE_Msk              (0x1UL << I3C_IER_SFNEIE_Pos)           /*!< 0x00000008 */
#define I3C_IER_SFNEIE                  I3C_IER_SFNEIE_Msk                      /*!< Status FIFO Not Empty Interrupt Enable */
#define I3C_IER_TXFNFIE_Pos             (4U)
#define I3C_IER_TXFNFIE_Msk             (0x1UL << I3C_IER_TXFNFIE_Pos)          /*!< 0x00000010 */
#define I3C_IER_TXFNFIE                 I3C_IER_TXFNFIE_Msk                     /*!< TX FIFO Not Full Interrupt Enable */
#define I3C_IER_RXFNEIE_Pos             (5U)
#define I3C_IER_RXFNEIE_Msk             (0x1UL << I3C_IER_RXFNEIE_Pos)          /*!< 0x00000020 */
#define I3C_IER_RXFNEIE                 I3C_IER_RXFNEIE_Msk                     /*!< RX FIFO Not Empty Interrupt Enable */
#define I3C_IER_FCIE_Pos                (9U)
#define I3C_IER_FCIE_Msk                (0x1UL << I3C_IER_FCIE_Pos)             /*!< 0x00000200 */
#define I3C_IER_FCIE                    I3C_IER_FCIE_Msk                        /*!< Frame Complete Interrupt Enable */
#define I3C_IER_RXTGTENDIE_Pos          (10U)
#define I3C_IER_RXTGTENDIE_Msk          (0x1UL << I3C_IER_RXTGTENDIE_Pos)       /*!< 0x00000400 */
#define I3C_IER_RXTGTENDIE              I3C_IER_RXTGTENDIE_Msk                  /*!< Reception Target End Interrupt Enable */
#define I3C_IER_ERRIE_Pos               (11U)
#define I3C_IER_ERRIE_Msk               (0x1UL << I3C_IER_ERRIE_Pos)            /*!< 0x00000800 */
#define I3C_IER_ERRIE                   I3C_IER_ERRIE_Msk                       /*!< Error Interrupt Enable */
#define I3C_IER_IBIIE_Pos               (15U)
#define I3C_IER_IBIIE_Msk               (0x1UL << I3C_IER_IBIIE_Pos)            /*!< 0x00008000 */
#define I3C_IER_IBIIE                   I3C_IER_IBIIE_Msk                       /*!< IBI Interrupt Enable */
#define I3C_IER_IBIENDIE_Pos            (16U)
#define I3C_IER_IBIENDIE_Msk            (0x1UL << I3C_IER_IBIENDIE_Pos)         /*!< 0x00010000 */
#define I3C_IER_IBIENDIE                I3C_IER_IBIENDIE_Msk                    /*!< IBI End Interrupt Enable */
#define I3C_IER_CRIE_Pos                (17U)
#define I3C_IER_CRIE_Msk                (0x1UL << I3C_IER_CRIE_Pos)             /*!< 0x00020000 */
#define I3C_IER_CRIE                    I3C_IER_CRIE_Msk                        /*!< Controller-role Interrupt Enable */
#define I3C_IER_CRUPDIE_Pos             (18U)
#define I3C_IER_CRUPDIE_Msk             (0x1UL << I3C_IER_CRUPDIE_Pos)          /*!< 0x00040000 */
#define I3C_IER_CRUPDIE                 I3C_IER_CRUPDIE_Msk                     /*!< Controller-role Update Interrupt Enable */
#define I3C_IER_HJIE_Pos                (19U)
#define I3C_IER_HJIE_Msk                (0x1UL << I3C_IER_HJIE_Pos)             /*!< 0x00080000 */
#define I3C_IER_HJIE                    I3C_IER_HJIE_Msk                        /*!< Hot Join Interrupt Enable */
#define I3C_IER_WKPIE_Pos               (21U)
#define I3C_IER_WKPIE_Msk               (0x1UL << I3C_IER_WKPIE_Pos)            /*!< 0x00200000 */
#define I3C_IER_WKPIE                   I3C_IER_WKPIE_Msk                       /*!< Wake Up Interrupt Enable */
#define I3C_IER_GETIE_Pos               (22U)
#define I3C_IER_GETIE_Msk               (0x1UL << I3C_IER_GETIE_Pos)            /*!< 0x00400000 */
#define I3C_IER_GETIE                   I3C_IER_GETIE_Msk                       /*!< Get type CCC received Interrupt Enable */
#define I3C_IER_STAIE_Pos               (23U)
#define I3C_IER_STAIE_Msk               (0x1UL << I3C_IER_STAIE_Pos)            /*!< 0x00800000 */
#define I3C_IER_STAIE                   I3C_IER_STAIE_Msk                       /*!< Get Status Interrupt Enable */
#define I3C_IER_DAUPDIE_Pos             (24U)
#define I3C_IER_DAUPDIE_Msk             (0x1UL << I3C_IER_DAUPDIE_Pos)          /*!< 0x01000000 */
#define I3C_IER_DAUPDIE                 I3C_IER_DAUPDIE_Msk                     /*!< Dynamic Address Update Interrupt Enable */
#define I3C_IER_MWLUPDIE_Pos            (25U)
#define I3C_IER_MWLUPDIE_Msk            (0x1UL << I3C_IER_MWLUPDIE_Pos)         /*!< 0x02000000 */
#define I3C_IER_MWLUPDIE                I3C_IER_MWLUPDIE_Msk                    /*!< Max Write Length Update Interrupt Enable */
#define I3C_IER_MRLUPDIE_Pos            (26U)
#define I3C_IER_MRLUPDIE_Msk            (0x1UL << I3C_IER_MRLUPDIE_Pos)         /*!< 0x04000000 */
#define I3C_IER_MRLUPDIE                I3C_IER_MRLUPDIE_Msk                    /*!< Max Read Length Update Interrupt Enable */
#define I3C_IER_RSTIE_Pos               (27U)
#define I3C_IER_RSTIE_Msk               (0x1UL << I3C_IER_RSTIE_Pos)            /*!< 0x08000000 */
#define I3C_IER_RSTIE                   I3C_IER_RSTIE_Msk                       /*!< Reset Interrupt Enabled, due to Reset pattern received */
#define I3C_IER_ASUPDIE_Pos             (28U)
#define I3C_IER_ASUPDIE_Msk             (0x1UL << I3C_IER_ASUPDIE_Pos)          /*!< 0x10000000 */
#define I3C_IER_ASUPDIE                 I3C_IER_ASUPDIE_Msk                     /*!< Activity State Interrupt Enable */
#define I3C_IER_INTUPDIE_Pos            (29U)
#define I3C_IER_INTUPDIE_Msk            (0x1UL << I3C_IER_INTUPDIE_Pos)         /*!< 0x20000000 */
#define I3C_IER_INTUPDIE                I3C_IER_INTUPDIE_Msk                    /*!< Interrupt Update Interrupt Enable */
#define I3C_IER_DEFIE_Pos               (30U)
#define I3C_IER_DEFIE_Msk               (0x1UL << I3C_IER_DEFIE_Pos)            /*!< 0x40000000 */
#define I3C_IER_DEFIE                   I3C_IER_DEFIE_Msk                       /*!< List of Targets Command Received Interrupt Enable */
#define I3C_IER_GRPIE_Pos               (31U)
#define I3C_IER_GRPIE_Msk               (0x1UL << I3C_IER_GRPIE_Pos)            /*!< 0x80000000 */
#define I3C_IER_GRPIE                   I3C_IER_GRPIE_Msk                       /*!< List of Group Addresses Command Received Interrupt Enable */

/*******************  Bit definition for I3C_CEVR register  *******************/
#define I3C_CEVR_CFCF_Pos               (9U)
#define I3C_CEVR_CFCF_Msk               (0x1UL << I3C_CEVR_CFCF_Pos)            /*!< 0x00000200 */
#define I3C_CEVR_CFCF                   I3C_CEVR_CFCF_Msk                       /*!< Frame Complete Clear Flag */
#define I3C_CEVR_CRXTGTENDF_Pos         (10U)
#define I3C_CEVR_CRXTGTENDF_Msk         (0x1UL << I3C_CEVR_CRXTGTENDF_Pos)      /*!< 0x00000400 */
#define I3C_CEVR_CRXTGTENDF             I3C_CEVR_CRXTGTENDF_Msk                 /*!< Reception Target End Clear Flag */
#define I3C_CEVR_CERRF_Pos              (11U)
#define I3C_CEVR_CERRF_Msk              (0x1UL << I3C_CEVR_CERRF_Pos)           /*!< 0x00000800 */
#define I3C_CEVR_CERRF                  I3C_CEVR_CERRF_Msk                      /*!< Error Clear Flag */
#define I3C_CEVR_CIBIF_Pos              (15U)
#define I3C_CEVR_CIBIF_Msk              (0x1UL << I3C_CEVR_CIBIF_Pos)           /*!< 0x00008000 */
#define I3C_CEVR_CIBIF                  I3C_CEVR_CIBIF_Msk                      /*!< IBI Clear Flag */
#define I3C_CEVR_CIBIENDF_Pos           (16U)
#define I3C_CEVR_CIBIENDF_Msk           (0x1UL << I3C_CEVR_CIBIENDF_Pos)        /*!< 0x00010000 */
#define I3C_CEVR_CIBIENDF               I3C_CEVR_CIBIENDF_Msk                   /*!< IBI End Clear Flag */
#define I3C_CEVR_CCRF_Pos               (17U)
#define I3C_CEVR_CCRF_Msk               (0x1UL << I3C_CEVR_CCRF_Pos)            /*!< 0x00020000 */
#define I3C_CEVR_CCRF                   I3C_CEVR_CCRF_Msk                       /*!< Controller-role Clear Flag */
#define I3C_CEVR_CCRUPDF_Pos            (18U)
#define I3C_CEVR_CCRUPDF_Msk            (0x1UL << I3C_CEVR_CCRUPDF_Pos)         /*!< 0x00040000 */
#define I3C_CEVR_CCRUPDF                I3C_CEVR_CCRUPDF_Msk                    /*!< Controller-role Update Clear Flag */
#define I3C_CEVR_CHJF_Pos               (19U)
#define I3C_CEVR_CHJF_Msk               (0x1UL << I3C_CEVR_CHJF_Pos)            /*!< 0x00080000 */
#define I3C_CEVR_CHJF                   I3C_CEVR_CHJF_Msk                       /*!< Hot Join Clear Flag */
#define I3C_CEVR_CWKPF_Pos              (21U)
#define I3C_CEVR_CWKPF_Msk              (0x1UL << I3C_CEVR_CWKPF_Pos)           /*!< 0x00200000 */
#define I3C_CEVR_CWKPF                  I3C_CEVR_CWKPF_Msk                      /*!< Wake Up Clear Flag */
#define I3C_CEVR_CGETF_Pos              (22U)
#define I3C_CEVR_CGETF_Msk              (0x1UL << I3C_CEVR_CGETF_Pos)           /*!< 0x00400000 */
#define I3C_CEVR_CGETF                  I3C_CEVR_CGETF_Msk                      /*!< Get type CCC received Clear Flag */
#define I3C_CEVR_CSTAF_Pos              (23U)
#define I3C_CEVR_CSTAF_Msk              (0x1UL << I3C_CEVR_CSTAF_Pos)           /*!< 0x00800000 */
#define I3C_CEVR_CSTAF                  I3C_CEVR_CSTAF_Msk                      /*!< Get Status Clear Flag */
#define I3C_CEVR_CDAUPDF_Pos            (24U)
#define I3C_CEVR_CDAUPDF_Msk            (0x1UL << I3C_CEVR_CDAUPDF_Pos)         /*!< 0x01000000 */
#define I3C_CEVR_CDAUPDF                I3C_CEVR_CDAUPDF_Msk                    /*!< Dynamic Address Update Clear Flag */
#define I3C_CEVR_CMWLUPDF_Pos           (25U)
#define I3C_CEVR_CMWLUPDF_Msk           (0x1UL << I3C_CEVR_CMWLUPDF_Pos)        /*!< 0x02000000 */
#define I3C_CEVR_CMWLUPDF               I3C_CEVR_CMWLUPDF_Msk                   /*!< Max Write Length Update Clear Flag */
#define I3C_CEVR_CMRLUPDF_Pos           (26U)
#define I3C_CEVR_CMRLUPDF_Msk           (0x1UL << I3C_CEVR_CMRLUPDF_Pos)        /*!< 0x04000000 */
#define I3C_CEVR_CMRLUPDF               I3C_CEVR_CMRLUPDF_Msk                   /*!< Max Read Length Update Clear Flag */
#define I3C_CEVR_CRSTF_Pos              (27U)
#define I3C_CEVR_CRSTF_Msk              (0x1UL << I3C_CEVR_CRSTF_Pos)           /*!< 0x08000000 */
#define I3C_CEVR_CRSTF                  I3C_CEVR_CRSTF_Msk                      /*!< Reset Flag, due to Reset pattern received */
#define I3C_CEVR_CASUPDF_Pos            (28U)
#define I3C_CEVR_CASUPDF_Msk            (0x1UL << I3C_CEVR_CASUPDF_Pos)         /*!< 0x10000000 */
#define I3C_CEVR_CASUPDF                I3C_CEVR_CASUPDF_Msk                    /*!< Activity State Clear Flag */
#define I3C_CEVR_CINTUPDF_Pos           (29U)
#define I3C_CEVR_CINTUPDF_Msk           (0x1UL << I3C_CEVR_CINTUPDF_Pos)        /*!< 0x20000000 */
#define I3C_CEVR_CINTUPDF               I3C_CEVR_CINTUPDF_Msk                   /*!< Interrupt Update Clear Flag */
#define I3C_CEVR_CDEFF_Pos              (30U)
#define I3C_CEVR_CDEFF_Msk              (0x1UL << I3C_CEVR_CDEFF_Pos)           /*!< 0x40000000 */
#define I3C_CEVR_CDEFF                  I3C_CEVR_CDEFF_Msk                      /*!< List of Targets Command Received Clear Flag */
#define I3C_CEVR_CGRPF_Pos              (31U)
#define I3C_CEVR_CGRPF_Msk              (0x1UL << I3C_CEVR_CGRPF_Pos)           /*!< 0x80000000 */
#define I3C_CEVR_CGRPF                  I3C_CEVR_CGRPF_Msk                      /*!< List of Group Addresses Command Received Clear Flag */

/*******************  Bit definition for I3C_MISR register  *******************/
#define I3C_MISR_CFNFMIS_Pos            (2U)
#define I3C_MISR_CFNFMIS_Msk            (0x1UL << I3C_MISR_CFNFMIS_Pos)         /*!< 0x00000004 */
#define I3C_MISR_CFNFMIS                I3C_MISR_CFNFMIS_Msk                    /*!< Control FIFO Not Full Mask Interrupt Status */
#define I3C_MISR_SFNEMIS_Pos            (3U)
#define I3C_MISR_SFNEMIS_Msk            (0x1UL << I3C_MISR_SFNEMIS_Pos)         /*!< 0x00000008 */
#define I3C_MISR_SFNEMIS                I3C_MISR_SFNEMIS_Msk                    /*!< Status FIFO Not Empty Mask Interrupt Status */
#define I3C_MISR_TXFNFMIS_Pos           (4U)
#define I3C_MISR_TXFNFMIS_Msk           (0x1UL << I3C_MISR_TXFNFMIS_Pos)        /*!< 0x00000010 */
#define I3C_MISR_TXFNFMIS               I3C_MISR_TXFNFMIS_Msk                   /*!< TX FIFO Not Full Mask Interrupt Status */
#define I3C_MISR_RXFNEMIS_Pos           (5U)
#define I3C_MISR_RXFNEMIS_Msk           (0x1UL << I3C_MISR_RXFNEMIS_Pos)        /*!< 0x00000020 */
#define I3C_MISR_RXFNEMIS               I3C_MISR_RXFNEMIS_Msk                   /*!< RX FIFO Not Empty Mask Interrupt Status */
#define I3C_MISR_FCMIS_Pos              (9U)
#define I3C_MISR_FCMIS_Msk              (0x1UL << I3C_MISR_FCMIS_Pos)           /*!< 0x00000200 */
#define I3C_MISR_FCMIS                  I3C_MISR_FCMIS_Msk                      /*!< Frame Complete Mask Interrupt Status */
#define I3C_MISR_RXTGTENDMIS_Pos        (10U)
#define I3C_MISR_RXTGTENDMIS_Msk        (0x1UL << I3C_MISR_RXTGTENDMIS_Pos)     /*!< 0x00000400 */
#define I3C_MISR_RXTGTENDMIS            I3C_MISR_RXTGTENDMIS_Msk                /*!< Reception Target End Mask Interrupt Status */
#define I3C_MISR_ERRMIS_Pos             (11U)
#define I3C_MISR_ERRMIS_Msk             (0x1UL << I3C_MISR_ERRMIS_Pos)          /*!< 0x00000800 */
#define I3C_MISR_ERRMIS                 I3C_MISR_ERRMIS_Msk                     /*!< Error Mask Interrupt Status */
#define I3C_MISR_IBIMIS_Pos             (15U)
#define I3C_MISR_IBIMIS_Msk             (0x1UL << I3C_MISR_IBIMIS_Pos)          /*!< 0x00008000 */
#define I3C_MISR_IBIMIS                 I3C_MISR_IBIMIS_Msk                     /*!< IBI Mask Interrupt Status */
#define I3C_MISR_IBIENDMIS_Pos          (16U)
#define I3C_MISR_IBIENDMIS_Msk          (0x1UL << I3C_MISR_IBIENDMIS_Pos)       /*!< 0x00010000 */
#define I3C_MISR_IBIENDMIS              I3C_MISR_IBIENDMIS_Msk                  /*!< IBI End Mask Interrupt Status */
#define I3C_MISR_CRMIS_Pos              (17U)
#define I3C_MISR_CRMIS_Msk              (0x1UL << I3C_MISR_CRMIS_Pos)           /*!< 0x00020000 */
#define I3C_MISR_CRMIS                  I3C_MISR_CRMIS_Msk                      /*!< Controller-role Mask Interrupt Status */
#define I3C_MISR_CRUPDMIS_Pos           (18U)
#define I3C_MISR_CRUPDMIS_Msk           (0x1UL << I3C_MISR_CRUPDMIS_Pos)        /*!< 0x00040000 */
#define I3C_MISR_CRUPDMIS               I3C_MISR_CRUPDMIS_Msk                   /*!< Controller-role Update Mask Interrupt Status */
#define I3C_MISR_HJMIS_Pos              (19U)
#define I3C_MISR_HJMIS_Msk              (0x1UL << I3C_MISR_HJMIS_Pos)           /*!< 0x00080000 */
#define I3C_MISR_HJMIS                  I3C_MISR_HJMIS_Msk                      /*!< Hot Join Mask Interrupt Status */
#define I3C_MISR_WKPMIS_Pos             (21U)
#define I3C_MISR_WKPMIS_Msk             (0x1UL << I3C_MISR_WKPMIS_Pos)          /*!< 0x00200000 */
#define I3C_MISR_WKPMIS                 I3C_MISR_WKPMIS_Msk                     /*!< Wake Up Mask Interrupt Status */
#define I3C_MISR_GETMIS_Pos             (22U)
#define I3C_MISR_GETMIS_Msk             (0x1UL << I3C_MISR_GETMIS_Pos)          /*!< 0x00400000 */
#define I3C_MISR_GETMIS                 I3C_MISR_GETMIS_Msk                     /*!< Get type CCC received Mask Interrupt Status */
#define I3C_MISR_STAMIS_Pos             (23U)
#define I3C_MISR_STAMIS_Msk             (0x1UL << I3C_MISR_STAMIS_Pos)          /*!< 0x00800000 */
#define I3C_MISR_STAMIS                 I3C_MISR_STAMIS_Msk                     /*!< Get Status Mask Interrupt Status */
#define I3C_MISR_DAUPDMIS_Pos           (24U)
#define I3C_MISR_DAUPDMIS_Msk           (0x1UL << I3C_MISR_DAUPDMIS_Pos)        /*!< 0x01000000 */
#define I3C_MISR_DAUPDMIS               I3C_MISR_DAUPDMIS_Msk                   /*!< Dynamic Address Update Mask Interrupt Status */
#define I3C_MISR_MWLUPDMIS_Pos          (25U)
#define I3C_MISR_MWLUPDMIS_Msk          (0x1UL << I3C_MISR_MWLUPDMIS_Pos)       /*!< 0x02000000 */
#define I3C_MISR_MWLUPDMIS              I3C_MISR_MWLUPDMIS_Msk                  /*!< Max Write Length Update Mask Interrupt Status */
#define I3C_MISR_MRLUPDMIS_Pos          (26U)
#define I3C_MISR_MRLUPDMIS_Msk          (0x1UL << I3C_MISR_MRLUPDMIS_Pos)       /*!< 0x04000000 */
#define I3C_MISR_MRLUPDMIS              I3C_MISR_MRLUPDMIS_Msk                  /*!< Max Read Length Update Mask Interrupt Status */
#define I3C_MISR_RSTMIS_Pos             (27U)
#define I3C_MISR_RSTMIS_Msk             (0x1UL << I3C_MISR_RSTMIS_Pos)          /*!< 0x08000000 */
#define I3C_MISR_RSTMIS                 I3C_MISR_RSTMIS_Msk                     /*!< Reset Mask Interrupt Status, due to Reset pattern received */
#define I3C_MISR_ASUPDMIS_Pos           (28U)
#define I3C_MISR_ASUPDMIS_Msk           (0x1UL << I3C_MISR_ASUPDMIS_Pos)        /*!< 0x10000000 */
#define I3C_MISR_ASUPDMIS               I3C_MISR_ASUPDMIS_Msk                   /*!< Activity State Mask Interrupt Status */
#define I3C_MISR_INTUPDMIS_Pos          (29U)
#define I3C_MISR_INTUPDMIS_Msk          (0x1UL << I3C_MISR_INTUPDMIS_Pos)       /*!< 0x20000000 */
#define I3C_MISR_INTUPDMIS              I3C_MISR_INTUPDMIS_Msk                  /*!< Interrupt Update Mask Interrupt Status */
#define I3C_MISR_DEFMIS_Pos             (30U)
#define I3C_MISR_DEFMIS_Msk             (0x1UL << I3C_MISR_DEFMIS_Pos)          /*!< 0x40000000 */
#define I3C_MISR_DEFMIS                 I3C_MISR_DEFMIS_Msk                     /*!< List of Targets Command Received Mask Interrupt Status */
#define I3C_MISR_GRPMIS_Pos             (31U)
#define I3C_MISR_GRPMIS_Msk             (0x1UL << I3C_MISR_GRPMIS_Pos)          /*!< 0x80000000 */
#define I3C_MISR_GRPMIS                 I3C_MISR_GRPMIS_Msk                     /*!< List of Group Addresses Command Received Mask Interrupt Status */

/******************  Bit definition for I3C_DEVR0 register  *******************/
#define I3C_DEVR0_DAVAL_Pos             (0U)
#define I3C_DEVR0_DAVAL_Msk             (0x1UL << I3C_DEVR0_DAVAL_Pos)          /*!< 0x00000001 */
#define I3C_DEVR0_DAVAL                 I3C_DEVR0_DAVAL_Msk                     /*!< Dynamic Address Validity */
#define I3C_DEVR0_DA_Pos                (1U)
#define I3C_DEVR0_DA_Msk                (0x7FUL << I3C_DEVR0_DA_Pos)            /*!< 0x000000FE */
#define I3C_DEVR0_DA                    I3C_DEVR0_DA_Msk                        /*!< Own Target Device Address */
#define I3C_DEVR0_IBIEN_Pos             (16U)
#define I3C_DEVR0_IBIEN_Msk             (0x1UL << I3C_DEVR0_IBIEN_Pos)          /*!< 0x00010000 */
#define I3C_DEVR0_IBIEN                 I3C_DEVR0_IBIEN_Msk                     /*!< IBI Enable */
#define I3C_DEVR0_CREN_Pos              (17U)
#define I3C_DEVR0_CREN_Msk              (0x1UL << I3C_DEVR0_CREN_Pos)           /*!< 0x00020000 */
#define I3C_DEVR0_CREN                  I3C_DEVR0_CREN_Msk                      /*!< Controller-role Enable */
#define I3C_DEVR0_HJEN_Pos              (19U)
#define I3C_DEVR0_HJEN_Msk              (0x1UL << I3C_DEVR0_HJEN_Pos)           /*!< 0x00080000 */
#define I3C_DEVR0_HJEN                  I3C_DEVR0_HJEN_Msk                      /*!< Hot Join Enable */
#define I3C_DEVR0_AS_Pos                (20U)
#define I3C_DEVR0_AS_Msk                (0x3UL << I3C_DEVR0_AS_Pos)             /*!< 0x00300000 */
#define I3C_DEVR0_AS                    I3C_DEVR0_AS_Msk                        /*!< Activity State value update after ENTAx received */
#define I3C_DEVR0_AS_0                  (0x1UL << I3C_DEVR0_AS_Pos)             /*!< 0x00100000 */
#define I3C_DEVR0_AS_1                  (0x2UL << I3C_DEVR0_AS_Pos)             /*!< 0x00200000 */
#define I3C_DEVR0_RSTACT_Pos            (22U)
#define I3C_DEVR0_RSTACT_Msk            (0x3UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00C000000 */
#define I3C_DEVR0_RSTACT                I3C_DEVR0_RSTACT_Msk                    /*!< Reset Action value update after RSTACT received */
#define I3C_DEVR0_RSTACT_0              (0x1UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00400000 */
#define I3C_DEVR0_RSTACT_1              (0x2UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00800000 */
#define I3C_DEVR0_RSTVAL_Pos            (24U)
#define I3C_DEVR0_RSTVAL_Msk            (0x1UL << I3C_DEVR0_RSTVAL_Pos)         /*!< 0x01000000 */
#define I3C_DEVR0_RSTVAL                I3C_DEVR0_RSTVAL_Msk                    /*!< Reset Action Valid */

/******************  Bit definition for I3C_DEVRX register  *******************/
#define I3C_DEVRX_DA_Pos                (1U)
#define I3C_DEVRX_DA_Msk                (0x7FUL << I3C_DEVRX_DA_Pos)            /*!< 0x000000FE */
#define I3C_DEVRX_DA                    I3C_DEVRX_DA_Msk                        /*!< Dynamic Address Target x */
#define I3C_DEVRX_IBIACK_Pos            (16U)
#define I3C_DEVRX_IBIACK_Msk            (0x1UL << I3C_DEVRX_IBIACK_Pos)         /*!< 0x00010000 */
#define I3C_DEVRX_IBIACK                I3C_DEVRX_IBIACK_Msk                    /*!< IBI Acknowledge from Target x */
#define I3C_DEVRX_CRACK_Pos             (17U)
#define I3C_DEVRX_CRACK_Msk             (0x1UL << I3C_DEVRX_CRACK_Pos)          /*!< 0x00020000 */
#define I3C_DEVRX_CRACK                 I3C_DEVRX_CRACK_Msk                     /*!< Controller-role Acknowledge from Target x */
#define I3C_DEVRX_IBIDEN_Pos            (18U)
#define I3C_DEVRX_IBIDEN_Msk            (0x1UL << I3C_DEVRX_IBIDEN_Pos)         /*!< 0x00040000 */
#define I3C_DEVRX_IBIDEN                I3C_DEVRX_IBIDEN_Msk                    /*!< IBI Additional Data Enable */
#define I3C_DEVRX_SUSP_Pos              (19U)
#define I3C_DEVRX_SUSP_Msk              (0x1UL << I3C_DEVRX_SUSP_Pos)           /*!< 0x00080000 */
#define I3C_DEVRX_SUSP                  I3C_DEVRX_SUSP_Msk                      /*!< Suspended Transfer */
#define I3C_DEVRX_DIS_Pos               (31U)
#define I3C_DEVRX_DIS_Msk               (0x1UL << I3C_DEVRX_DIS_Pos)            /*!< 0x80000000 */
#define I3C_DEVRX_DIS                   I3C_DEVRX_DIS_Msk                       /*!< Disable Register access */

/******************  Bit definition for I3C_MAXRLR register  ******************/
#define I3C_MAXRLR_MRL_Pos              (0U)
#define I3C_MAXRLR_MRL_Msk              (0xFFFFUL << I3C_MAXRLR_MRL_Pos)        /*!< 0x0000FFFF */
#define I3C_MAXRLR_MRL                  I3C_MAXRLR_MRL_Msk                      /*!< Maximum Read Length */
#define I3C_MAXRLR_IBIP_Pos             (16U)
#define I3C_MAXRLR_IBIP_Msk             (0x7UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00070000 */
#define I3C_MAXRLR_IBIP                 I3C_MAXRLR_IBIP_Msk                     /*!< IBI Payload size */
#define I3C_MAXRLR_IBIP_0               (0x1UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00010000 */
#define I3C_MAXRLR_IBIP_1               (0x2UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00020000 */
#define I3C_MAXRLR_IBIP_2               (0x4UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00040000 */

/******************  Bit definition for I3C_MAXWLR register  ******************/
#define I3C_MAXWLR_MWL_Pos              (0U)
#define I3C_MAXWLR_MWL_Msk              (0xFFFFUL << I3C_MAXWLR_MWL_Pos)        /*!< 0x0000FFFF */
#define I3C_MAXWLR_MWL                  I3C_MAXWLR_MWL_Msk                      /*!< Maximum Write Length */

/****************  Bit definition for I3C_TIMINGR0 register  ******************/
#define I3C_TIMINGR0_SCLL_PP_Pos        (0U)
#define I3C_TIMINGR0_SCLL_PP_Msk        (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos)      /*!< 0x000000FF */
#define I3C_TIMINGR0_SCLL_PP            I3C_TIMINGR0_SCLL_PP_Msk                  /*!< SCL Low duration during I3C Push-Pull phases */
#define I3C_TIMINGR0_SCLH_I3C_Pos       (8U)
#define I3C_TIMINGR0_SCLH_I3C_Msk       (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos)     /*!< 0x0000FF00 */
#define I3C_TIMINGR0_SCLH_I3C           I3C_TIMINGR0_SCLH_I3C_Msk                 /*!< SCL High duration during I3C Open-drain and Push-Pull phases */
#define I3C_TIMINGR0_SCLL_OD_Pos        (16U)
#define I3C_TIMINGR0_SCLL_OD_Msk        (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos)      /*!< 0x00FF0000 */
#define I3C_TIMINGR0_SCLL_OD            I3C_TIMINGR0_SCLL_OD_Msk                  /*!< SCL Low duration during  I3C Open-drain phases and I2C transfer */
#define I3C_TIMINGR0_SCLH_I2C_Pos       (24U)
#define I3C_TIMINGR0_SCLH_I2C_Msk       (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos)     /*!< 0xFF000000 */
#define I3C_TIMINGR0_SCLH_I2C           I3C_TIMINGR0_SCLH_I2C_Msk                 /*!< SCL High duration during I2C transfer */

/****************  Bit definition for I3C_TIMINGR1 register  ******************/
#define I3C_TIMINGR1_AVAL_Pos           (0U)
#define I3C_TIMINGR1_AVAL_Msk           (0xFFUL << I3C_TIMINGR1_AVAL_Pos)         /*!< 0x000000FF */
#define I3C_TIMINGR1_AVAL               I3C_TIMINGR1_AVAL_Msk                     /*!< Timing for I3C Bus Idle or Available condition */
#define I3C_TIMINGR1_ASNCR_Pos          (8U)
#define I3C_TIMINGR1_ASNCR_Msk          (0x3UL << I3C_TIMINGR1_ASNCR_Pos)         /*!< 0x00000300 */
#define I3C_TIMINGR1_ASNCR              I3C_TIMINGR1_ASNCR_Msk                    /*!< Activity State of the New Controller */
#define I3C_TIMINGR1_ASNCR_0            (0x1UL << I3C_TIMINGR1_ASNCR_Pos)         /*!< 0x00000100 */
#define I3C_TIMINGR1_ASNCR_1            (0x2UL << I3C_TIMINGR1_ASNCR_Pos)         /*!< 0x00000200 */
#define I3C_TIMINGR1_FREE_Pos           (16U)
#define I3C_TIMINGR1_FREE_Msk           (0x7FUL << I3C_TIMINGR1_FREE_Pos)         /*!< 0x007F0000 */
#define I3C_TIMINGR1_FREE               I3C_TIMINGR1_FREE_Msk                     /*!< Timing for I3C Bus Free condition */
#define I3C_TIMINGR1_SDA_HD_Pos         (28U)
#define I3C_TIMINGR1_SDA_HD_Msk         (0x3UL << I3C_TIMINGR1_SDA_HD_Pos)        /*!< 0x30000000 */
#define I3C_TIMINGR1_SDA_HD             I3C_TIMINGR1_SDA_HD_Msk                   /*!< SDA Hold Duration */
#define I3C_TIMINGR1_SDA_HD_0           (0x1UL << I3C_TIMINGR1_SDA_HD_Pos)        /*!< 0x10000000 */
#define I3C_TIMINGR1_SDA_HD_1           (0x2UL << I3C_TIMINGR1_SDA_HD_Pos)        /*!< 0x20000000 */

/****************  Bit definition for I3C_TIMINGR2 register  ******************/
#define I3C_TIMINGR2_STALLT_Pos         (0U)
#define I3C_TIMINGR2_STALLT_Msk         (0x1UL << I3C_TIMINGR2_STALLT_Pos)        /*!< 0x00000001 */
#define I3C_TIMINGR2_STALLT             I3C_TIMINGR2_STALLT_Msk                   /*!< Stall on T bit */
#define I3C_TIMINGR2_STALLD_Pos         (1U)
#define I3C_TIMINGR2_STALLD_Msk         (0x1UL << I3C_TIMINGR2_STALLD_Pos)        /*!< 0x00000002 */
#define I3C_TIMINGR2_STALLD             I3C_TIMINGR2_STALLD_Msk                   /*!< Stall on PAR bit of data bytes */
#define I3C_TIMINGR2_STALLC_Pos         (2U)
#define I3C_TIMINGR2_STALLC_Msk         (0x1UL << I3C_TIMINGR2_STALLC_Pos)        /*!< 0x00000004 */
#define I3C_TIMINGR2_STALLC             I3C_TIMINGR2_STALLC_Msk                   /*!< Stall on PAR bit of CCC byte */
#define I3C_TIMINGR2_STALLA_Pos         (3U)
#define I3C_TIMINGR2_STALLA_Msk         (0x1UL << I3C_TIMINGR2_STALLA_Pos)        /*!< 0x00000008 */
#define I3C_TIMINGR2_STALLA             I3C_TIMINGR2_STALLA_Msk                   /*!< Stall on ACK bit */
#define I3C_TIMINGR2_STALLR_Pos         (4U)
#define I3C_TIMINGR2_STALLR_Msk         (0x1UL << I3C_TIMINGR2_STALLR_Pos)        /*!< 0x00000010 */
#define I3C_TIMINGR2_STALLR             I3C_TIMINGR2_STALLR_Msk                   /*!< Stall on I2C Read ACK bit */
#define I3C_TIMINGR2_STALLS_Pos         (5U)
#define I3C_TIMINGR2_STALLS_Msk         (0x1UL << I3C_TIMINGR2_STALLS_Pos)        /*!< 0x00000020 */
#define I3C_TIMINGR2_STALLS             I3C_TIMINGR2_STALLS_Msk                   /*!< Stall on I2C Write ACK bit */
#define I3C_TIMINGR2_STALLL_Pos         (6U)
#define I3C_TIMINGR2_STALLL_Msk         (0x1UL << I3C_TIMINGR2_STALLL_Pos)        /*!< 0x00000040 */
#define I3C_TIMINGR2_STALLL             I3C_TIMINGR2_STALLL_Msk                   /*!< Stall on I2C Address ACK bit */
#define I3C_TIMINGR2_STALL_Pos          (8U)
#define I3C_TIMINGR2_STALL_Msk          (0xFFUL << I3C_TIMINGR2_STALL_Pos)        /*!< 0x0000FF00 */
#define I3C_TIMINGR2_STALL              I3C_TIMINGR2_STALL_Msk                    /*!< Controller Stall duration */

/*******************  Bit definition for I3C_BCR register  ********************/
#define I3C_BCR_BCR_Pos                 (0U)
#define I3C_BCR_BCR_Msk                 (0xFFUL << I3C_BCR_BCR_Pos)               /*!< 0x000000FF */
#define I3C_BCR_BCR                     I3C_BCR_BCR_Msk                           /*!< Bus Characteristics */
#define I3C_BCR_BCR0_Pos                (0U)
#define I3C_BCR_BCR0_Msk                (0x1UL << I3C_BCR_BCR0_Pos)               /*!< 0x00000001 */
#define I3C_BCR_BCR0                    I3C_BCR_BCR0_Msk                          /*!< Max Data Speed Limitation */
#define I3C_BCR_BCR1_Pos                (1U)
#define I3C_BCR_BCR1_Msk                (0x1UL << I3C_BCR_BCR1_Pos)               /*!< 0x00000002 */
#define I3C_BCR_BCR1                    I3C_BCR_BCR1_Msk                          /*!< IBI Request capable */
#define I3C_BCR_BCR2_Pos                (2U)
#define I3C_BCR_BCR2_Msk                (0x1UL << I3C_BCR_BCR2_Pos)               /*!< 0x00000004 */
#define I3C_BCR_BCR2                    I3C_BCR_BCR2_Msk                          /*!< IBI Payload additional Mandatory Data Byte */
#define I3C_BCR_BCR3_Pos                (3U)
#define I3C_BCR_BCR3_Msk                (0x1UL << I3C_BCR_BCR3_Pos)               /*!< 0x00000008 */
#define I3C_BCR_BCR3                    I3C_BCR_BCR3_Msk                          /*!< Offline capable */
#define I3C_BCR_BCR4_Pos                (4U)
#define I3C_BCR_BCR4_Msk                (0x1UL << I3C_BCR_BCR4_Pos)               /*!< 0x00000010 */
#define I3C_BCR_BCR4                    I3C_BCR_BCR4_Msk                          /*!< Virtual target support */
#define I3C_BCR_BCR5_Pos                (5U)
#define I3C_BCR_BCR5_Msk                (0x1UL << I3C_BCR_BCR5_Pos)               /*!< 0x00000020 */
#define I3C_BCR_BCR5                    I3C_BCR_BCR5_Msk                          /*!< Advanced capabilities */
#define I3C_BCR_BCR6_Pos                (6U)
#define I3C_BCR_BCR6_Msk                (0x1UL << I3C_BCR_BCR6_Pos)               /*!< 0x00000040 */
#define I3C_BCR_BCR6                    I3C_BCR_BCR6_Msk                          /*!< Device Role shared during Dynamic Address Assignment */

/*******************  Bit definition for I3C_DCR register  ********************/
#define I3C_DCR_DCR_Pos                 (0U)
#define I3C_DCR_DCR_Msk                 (0xFFUL << I3C_DCR_DCR_Pos)               /*!< 0x000000FF */
#define I3C_DCR_DCR                     I3C_DCR_DCR_Msk                           /*!< Devices Characteristics */

/*****************  Bit definition for I3C_GETCAPR register  ******************/
#define I3C_GETCAPR_CAPPEND_Pos         (14U)
#define I3C_GETCAPR_CAPPEND_Msk         (0x1UL << I3C_GETCAPR_CAPPEND_Pos)        /*!< 0x00004000 */
#define I3C_GETCAPR_CAPPEND             I3C_GETCAPR_CAPPEND_Msk                   /*!< IBI Request with Mandatory Data Byte */

/*****************  Bit definition for I3C_CRCAPR register  *******************/
#define I3C_CRCAPR_CAPDHOFF_Pos         (3U)
#define I3C_CRCAPR_CAPDHOFF_Msk         (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos)        /*!< 0x00000008 */
#define I3C_CRCAPR_CAPDHOFF             I3C_CRCAPR_CAPDHOFF_Msk                   /*!< Controller-role handoff needed */
#define I3C_CRCAPR_CAPGRP_Pos           (9U)
#define I3C_CRCAPR_CAPGRP_Msk           (0x1UL << I3C_CRCAPR_CAPGRP_Pos)          /*!< 0x00000200 */
#define I3C_CRCAPR_CAPGRP               I3C_CRCAPR_CAPGRP_Msk                     /*!< Group Address handoff supported */

/****************  Bit definition for I3C_GETMXDSR register  ******************/
#define I3C_GETMXDSR_HOFFAS_Pos         (0U)
#define I3C_GETMXDSR_HOFFAS_Msk         (0x3UL << I3C_GETMXDSR_HOFFAS_Pos)        /*!< 0x00000003 */
#define I3C_GETMXDSR_HOFFAS             I3C_GETMXDSR_HOFFAS_Msk                   /*!< Handoff Activity State */
#define I3C_GETMXDSR_HOFFAS_0           (0x1UL << I3C_GETMXDSR_HOFFAS_Pos)        /*!< 0x00000001 */
#define I3C_GETMXDSR_HOFFAS_1           (0x2UL << I3C_GETMXDSR_HOFFAS_Pos)        /*!< 0x00000002 */
#define I3C_GETMXDSR_FMT_Pos            (8U)
#define I3C_GETMXDSR_FMT_Msk            (0x3UL << I3C_GETMXDSR_FMT_Pos)           /*!< 0x00000300 */
#define I3C_GETMXDSR_FMT                I3C_GETMXDSR_FMT_Msk                      /*!< Get Max Data Speed response in format 2 */
#define I3C_GETMXDSR_FMT_0              (0x1UL << I3C_GETMXDSR_FMT_Pos)           /*!< 0x00000100 */
#define I3C_GETMXDSR_FMT_1              (0x2UL << I3C_GETMXDSR_FMT_Pos)           /*!< 0x00000200 */
#define I3C_GETMXDSR_RDTURN_Pos         (16U)
#define I3C_GETMXDSR_RDTURN_Msk         (0xFFUL << I3C_GETMXDSR_RDTURN_Pos)       /*!< 0x00FF0000 */
#define I3C_GETMXDSR_RDTURN             I3C_GETMXDSR_RDTURN_Msk                   /*!< Max Read Turnaround Middle Byte  */
#define I3C_GETMXDSR_TSCO_Pos           (24U)
#define I3C_GETMXDSR_TSCO_Msk           (0x1UL << I3C_GETMXDSR_TSCO_Pos)          /*!< 0x01000000 */
#define I3C_GETMXDSR_TSCO               I3C_GETMXDSR_TSCO_Msk                     /*!< Clock-to-data Turnaround time */

/******************  Bit definition for I3C_EPIDR register  *******************/
#define I3C_EPIDR_MIPIID_Pos            (12U)
#define I3C_EPIDR_MIPIID_Msk            (0xFUL << I3C_EPIDR_MIPIID_Pos)           /*!< 0x0000F000 */
#define I3C_EPIDR_MIPIID                I3C_EPIDR_MIPIID_Msk                      /*!< MIPI Instance ID */
#define I3C_EPIDR_IDTSEL_Pos            (16U)
#define I3C_EPIDR_IDTSEL_Msk            (0x1UL << I3C_EPIDR_IDTSEL_Pos)           /*!< 0x00010000 */
#define I3C_EPIDR_IDTSEL                I3C_EPIDR_IDTSEL_Msk                      /*!< ID Type Selector */
#define I3C_EPIDR_MIPIMID_Pos           (17U)
#define I3C_EPIDR_MIPIMID_Msk           (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos)       /*!< 0xFFFE0000 */
#define I3C_EPIDR_MIPIMID               I3C_EPIDR_MIPIMID_Msk                     /*!< MIPI Manufacturer ID */

/* ****************************************************************************************************************** */
/*                                                                                                                    */
/*                                             Instruction cache (ICACHE)                                             */
/*                                                                                                                    */
/* ****************************************************************************************************************** */
/* ************************************  Bit definition for ICACHE_CR register  ************************************* */
#define ICACHE_CR_EN_Pos          (0U)
#define ICACHE_CR_EN_Msk          (0x1UL << ICACHE_CR_EN_Pos)            /*!< 0x00000001 */
#define ICACHE_CR_EN              ICACHE_CR_EN_Msk                       /*!< enable */
#define ICACHE_CR_CACHEINV_Pos    (1U)
#define ICACHE_CR_CACHEINV_Msk    (0x1UL << ICACHE_CR_CACHEINV_Pos)      /*!< 0x00000002 */
#define ICACHE_CR_CACHEINV        ICACHE_CR_CACHEINV_Msk                 /*!< cache invalidation */
#define ICACHE_CR_WAYSEL_Pos      (2U)
#define ICACHE_CR_WAYSEL_Msk      (0x1UL << ICACHE_CR_WAYSEL_Pos)        /*!< 0x00000004 */
#define ICACHE_CR_WAYSEL          ICACHE_CR_WAYSEL_Msk                   /*!< cache associativity mode selection */
#define ICACHE_CR_HITMEN_Pos      (16U)
#define ICACHE_CR_HITMEN_Msk      (0x1UL << ICACHE_CR_HITMEN_Pos)        /*!< 0x00010000 */
#define ICACHE_CR_HITMEN          ICACHE_CR_HITMEN_Msk                   /*!< hit monitor enable */
#define ICACHE_CR_MISSMEN_Pos     (17U)
#define ICACHE_CR_MISSMEN_Msk     (0x1UL << ICACHE_CR_MISSMEN_Pos)       /*!< 0x00020000 */
#define ICACHE_CR_MISSMEN         ICACHE_CR_MISSMEN_Msk                  /*!< miss monitor enable */
#define ICACHE_CR_HITMRST_Pos     (18U)
#define ICACHE_CR_HITMRST_Msk     (0x1UL << ICACHE_CR_HITMRST_Pos)       /*!< 0x00040000 */
#define ICACHE_CR_HITMRST         ICACHE_CR_HITMRST_Msk                  /*!< hit monitor reset */
#define ICACHE_CR_MISSMRST_Pos    (19U)
#define ICACHE_CR_MISSMRST_Msk    (0x1UL << ICACHE_CR_MISSMRST_Pos)      /*!< 0x00080000 */
#define ICACHE_CR_MISSMRST        ICACHE_CR_MISSMRST_Msk                 /*!< miss monitor reset */

/* ************************************  Bit definition for ICACHE_SR register  ************************************* */
#define ICACHE_SR_BUSYF_Pos       (0U)
#define ICACHE_SR_BUSYF_Msk       (0x1UL << ICACHE_SR_BUSYF_Pos)         /*!< 0x00000001 */
#define ICACHE_SR_BUSYF           ICACHE_SR_BUSYF_Msk                    /*!< busy flag */
#define ICACHE_SR_BSYENDF_Pos     (1U)
#define ICACHE_SR_BSYENDF_Msk     (0x1UL << ICACHE_SR_BSYENDF_Pos)       /*!< 0x00000002 */
#define ICACHE_SR_BSYENDF         ICACHE_SR_BSYENDF_Msk                  /*!< busy end flag */
#define ICACHE_SR_ERRF_Pos        (2U)
#define ICACHE_SR_ERRF_Msk        (0x1UL << ICACHE_SR_ERRF_Pos)          /*!< 0x00000004 */
#define ICACHE_SR_ERRF            ICACHE_SR_ERRF_Msk                     /*!< cache error flag */

/* ************************************  Bit definition for ICACHE_IER register  ************************************ */
#define ICACHE_IER_BSYENDIE_Pos   (1U)
#define ICACHE_IER_BSYENDIE_Msk   (0x1UL << ICACHE_IER_BSYENDIE_Pos)     /*!< 0x00000002 */
#define ICACHE_IER_BSYENDIE       ICACHE_IER_BSYENDIE_Msk                /*!< interrupt enable on busy end */
#define ICACHE_IER_ERRIE_Pos      (2U)
#define ICACHE_IER_ERRIE_Msk      (0x1UL << ICACHE_IER_ERRIE_Pos)        /*!< 0x00000004 */
#define ICACHE_IER_ERRIE          ICACHE_IER_ERRIE_Msk                   /*!< interrupt enable on cache error */

/* ************************************  Bit definition for ICACHE_FCR register  ************************************ */
#define ICACHE_FCR_CBSYENDF_Pos   (1U)
#define ICACHE_FCR_CBSYENDF_Msk   (0x1UL << ICACHE_FCR_CBSYENDF_Pos)     /*!< 0x00000002 */
#define ICACHE_FCR_CBSYENDF       ICACHE_FCR_CBSYENDF_Msk                /*!< clear busy end flag */
#define ICACHE_FCR_CERRF_Pos      (2U)
#define ICACHE_FCR_CERRF_Msk      (0x1UL << ICACHE_FCR_CERRF_Pos)        /*!< 0x00000004 */
#define ICACHE_FCR_CERRF          ICACHE_FCR_CERRF_Msk                   /*!< clear cache error flag */

/* ***********************************  Bit definition for ICACHE_HMONR register  *********************************** */
#define ICACHE_HMONR_HITMON_Pos   (0U)
#define ICACHE_HMONR_HITMON_Msk   (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos)     /*!< 0xFFFFFFFF */
#define ICACHE_HMONR_HITMON       ICACHE_HMONR_HITMON_Msk                       /*!< cache hit monitor counter */
#define ICACHE_HMONR_HITMON_0     (0x1UL << ICACHE_HMONR_HITMON_Pos)            /*!< 0x00000001 */
#define ICACHE_HMONR_HITMON_1     (0x2UL << ICACHE_HMONR_HITMON_Pos)            /*!< 0x00000002 */
#define ICACHE_HMONR_HITMON_2     (0x4UL << ICACHE_HMONR_HITMON_Pos)            /*!< 0x00000004 */
#define ICACHE_HMONR_HITMON_3     (0x8UL << ICACHE_HMONR_HITMON_Pos)            /*!< 0x00000008 */
#define ICACHE_HMONR_HITMON_4     (0x10UL << ICACHE_HMONR_HITMON_Pos)           /*!< 0x00000010 */
#define ICACHE_HMONR_HITMON_5     (0x20UL << ICACHE_HMONR_HITMON_Pos)           /*!< 0x00000020 */
#define ICACHE_HMONR_HITMON_6     (0x40UL << ICACHE_HMONR_HITMON_Pos)           /*!< 0x00000040 */
#define ICACHE_HMONR_HITMON_7     (0x80UL << ICACHE_HMONR_HITMON_Pos)           /*!< 0x00000080 */
#define ICACHE_HMONR_HITMON_8     (0x100UL << ICACHE_HMONR_HITMON_Pos)          /*!< 0x00000100 */
#define ICACHE_HMONR_HITMON_9     (0x200UL << ICACHE_HMONR_HITMON_Pos)          /*!< 0x00000200 */
#define ICACHE_HMONR_HITMON_10    (0x400UL << ICACHE_HMONR_HITMON_Pos)          /*!< 0x00000400 */
#define ICACHE_HMONR_HITMON_11    (0x800UL << ICACHE_HMONR_HITMON_Pos)          /*!< 0x00000800 */
#define ICACHE_HMONR_HITMON_12    (0x1000UL << ICACHE_HMONR_HITMON_Pos)         /*!< 0x00001000 */
#define ICACHE_HMONR_HITMON_13    (0x2000UL << ICACHE_HMONR_HITMON_Pos)         /*!< 0x00002000 */
#define ICACHE_HMONR_HITMON_14    (0x4000UL << ICACHE_HMONR_HITMON_Pos)         /*!< 0x00004000 */
#define ICACHE_HMONR_HITMON_15    (0x8000UL << ICACHE_HMONR_HITMON_Pos)         /*!< 0x00008000 */
#define ICACHE_HMONR_HITMON_16    (0x10000UL << ICACHE_HMONR_HITMON_Pos)        /*!< 0x00010000 */
#define ICACHE_HMONR_HITMON_17    (0x20000UL << ICACHE_HMONR_HITMON_Pos)        /*!< 0x00020000 */
#define ICACHE_HMONR_HITMON_18    (0x40000UL << ICACHE_HMONR_HITMON_Pos)        /*!< 0x00040000 */
#define ICACHE_HMONR_HITMON_19    (0x80000UL << ICACHE_HMONR_HITMON_Pos)        /*!< 0x00080000 */
#define ICACHE_HMONR_HITMON_20    (0x100000UL << ICACHE_HMONR_HITMON_Pos)       /*!< 0x00100000 */
#define ICACHE_HMONR_HITMON_21    (0x200000UL << ICACHE_HMONR_HITMON_Pos)       /*!< 0x00200000 */
#define ICACHE_HMONR_HITMON_22    (0x400000UL << ICACHE_HMONR_HITMON_Pos)       /*!< 0x00400000 */
#define ICACHE_HMONR_HITMON_23    (0x800000UL << ICACHE_HMONR_HITMON_Pos)       /*!< 0x00800000 */
#define ICACHE_HMONR_HITMON_24    (0x1000000UL << ICACHE_HMONR_HITMON_Pos)      /*!< 0x01000000 */
#define ICACHE_HMONR_HITMON_25    (0x2000000UL << ICACHE_HMONR_HITMON_Pos)      /*!< 0x02000000 */
#define ICACHE_HMONR_HITMON_26    (0x4000000UL << ICACHE_HMONR_HITMON_Pos)      /*!< 0x04000000 */
#define ICACHE_HMONR_HITMON_27    (0x8000000UL << ICACHE_HMONR_HITMON_Pos)      /*!< 0x08000000 */
#define ICACHE_HMONR_HITMON_28    (0x10000000UL << ICACHE_HMONR_HITMON_Pos)     /*!< 0x10000000 */
#define ICACHE_HMONR_HITMON_29    (0x20000000UL << ICACHE_HMONR_HITMON_Pos)     /*!< 0x20000000 */
#define ICACHE_HMONR_HITMON_30    (0x40000000UL << ICACHE_HMONR_HITMON_Pos)     /*!< 0x40000000 */
#define ICACHE_HMONR_HITMON_31    (0x80000000UL << ICACHE_HMONR_HITMON_Pos)     /*!< 0x80000000 */

/* ***********************************  Bit definition for ICACHE_MMONR register  *********************************** */
#define ICACHE_MMONR_MISSMON_Pos  (0U)
#define ICACHE_MMONR_MISSMON_Msk  (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */
#define ICACHE_MMONR_MISSMON      ICACHE_MMONR_MISSMON_Msk               /*!< cache miss monitor counter */
#define ICACHE_MMONR_MISSMON_0    (0x1UL << ICACHE_MMONR_MISSMON_Pos)    /*!< 0x00000001 */
#define ICACHE_MMONR_MISSMON_1    (0x2UL << ICACHE_MMONR_MISSMON_Pos)    /*!< 0x00000002 */
#define ICACHE_MMONR_MISSMON_2    (0x4UL << ICACHE_MMONR_MISSMON_Pos)    /*!< 0x00000004 */
#define ICACHE_MMONR_MISSMON_3    (0x8UL << ICACHE_MMONR_MISSMON_Pos)    /*!< 0x00000008 */
#define ICACHE_MMONR_MISSMON_4    (0x10UL << ICACHE_MMONR_MISSMON_Pos)   /*!< 0x00000010 */
#define ICACHE_MMONR_MISSMON_5    (0x20UL << ICACHE_MMONR_MISSMON_Pos)   /*!< 0x00000020 */
#define ICACHE_MMONR_MISSMON_6    (0x40UL << ICACHE_MMONR_MISSMON_Pos)   /*!< 0x00000040 */
#define ICACHE_MMONR_MISSMON_7    (0x80UL << ICACHE_MMONR_MISSMON_Pos)   /*!< 0x00000080 */
#define ICACHE_MMONR_MISSMON_8    (0x100UL << ICACHE_MMONR_MISSMON_Pos)  /*!< 0x00000100 */
#define ICACHE_MMONR_MISSMON_9    (0x200UL << ICACHE_MMONR_MISSMON_Pos)  /*!< 0x00000200 */
#define ICACHE_MMONR_MISSMON_10   (0x400UL << ICACHE_MMONR_MISSMON_Pos)  /*!< 0x00000400 */
#define ICACHE_MMONR_MISSMON_11   (0x800UL << ICACHE_MMONR_MISSMON_Pos)  /*!< 0x00000800 */
#define ICACHE_MMONR_MISSMON_12   (0x1000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00001000 */
#define ICACHE_MMONR_MISSMON_13   (0x2000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00002000 */
#define ICACHE_MMONR_MISSMON_14   (0x4000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00004000 */
#define ICACHE_MMONR_MISSMON_15   (0x8000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00008000 */

/* ***********************************  Bit definition for ICACHE_CRRx register  ************************************ */
#define ICACHE_CRRx_BASEADDR_Pos  (0U)
#define ICACHE_CRRx_BASEADDR_Msk  (0xFFUL << ICACHE_CRRx_BASEADDR_Pos)   /*!< 0x000000FF */
#define ICACHE_CRRx_BASEADDR      ICACHE_CRRx_BASEADDR_Msk               /*!< base address for region x */
#define ICACHE_CRRx_BASEADDR_0    (0x1UL << ICACHE_CRRx_BASEADDR_Pos)    /*!< 0x00000001 */
#define ICACHE_CRRx_BASEADDR_1    (0x2UL << ICACHE_CRRx_BASEADDR_Pos)    /*!< 0x00000002 */
#define ICACHE_CRRx_BASEADDR_2    (0x4UL << ICACHE_CRRx_BASEADDR_Pos)    /*!< 0x00000004 */
#define ICACHE_CRRx_BASEADDR_3    (0x8UL << ICACHE_CRRx_BASEADDR_Pos)    /*!< 0x00000008 */
#define ICACHE_CRRx_BASEADDR_4    (0x10UL << ICACHE_CRRx_BASEADDR_Pos)   /*!< 0x00000010 */
#define ICACHE_CRRx_BASEADDR_5    (0x20UL << ICACHE_CRRx_BASEADDR_Pos)   /*!< 0x00000020 */
#define ICACHE_CRRx_BASEADDR_6    (0x40UL << ICACHE_CRRx_BASEADDR_Pos)   /*!< 0x00000040 */
#define ICACHE_CRRx_BASEADDR_7    (0x80UL << ICACHE_CRRx_BASEADDR_Pos)   /*!< 0x00000080 */
#define ICACHE_CRRx_RSIZE_Pos     (9U)
#define ICACHE_CRRx_RSIZE_Msk     (0x7UL << ICACHE_CRRx_RSIZE_Pos)       /*!< 0x00000E00 */
#define ICACHE_CRRx_RSIZE         ICACHE_CRRx_RSIZE_Msk                  /*!< size for region x */
#define ICACHE_CRRx_RSIZE_0       (0x1UL << ICACHE_CRRx_RSIZE_Pos)       /*!< 0x00000200 */
#define ICACHE_CRRx_RSIZE_1       (0x2UL << ICACHE_CRRx_RSIZE_Pos)       /*!< 0x00000400 */
#define ICACHE_CRRx_RSIZE_2       (0x4UL << ICACHE_CRRx_RSIZE_Pos)       /*!< 0x00000800 */
#define ICACHE_CRRx_REN_Pos       (15U)
#define ICACHE_CRRx_REN_Msk       (0x1UL << ICACHE_CRRx_REN_Pos)         /*!< 0x00008000 */
#define ICACHE_CRRx_REN           ICACHE_CRRx_REN_Msk                    /*!< enable for region x */
#define ICACHE_CRRx_REMAPADDR_Pos (16U)
#define ICACHE_CRRx_REMAPADDR_Msk (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x07FF0000 */
#define ICACHE_CRRx_REMAPADDR     ICACHE_CRRx_REMAPADDR_Msk              /*!< remapped address for region x */
#define ICACHE_CRRx_REMAPADDR_0   (0x1UL << ICACHE_CRRx_REMAPADDR_Pos)   /*!< 0x00010000 */
#define ICACHE_CRRx_REMAPADDR_1   (0x2UL << ICACHE_CRRx_REMAPADDR_Pos)   /*!< 0x00020000 */
#define ICACHE_CRRx_REMAPADDR_2   (0x4UL << ICACHE_CRRx_REMAPADDR_Pos)   /*!< 0x00040000 */
#define ICACHE_CRRx_REMAPADDR_3   (0x8UL << ICACHE_CRRx_REMAPADDR_Pos)   /*!< 0x00080000 */
#define ICACHE_CRRx_REMAPADDR_4   (0x10UL << ICACHE_CRRx_REMAPADDR_Pos)  /*!< 0x00100000 */
#define ICACHE_CRRx_REMAPADDR_5   (0x20UL << ICACHE_CRRx_REMAPADDR_Pos)  /*!< 0x00200000 */
#define ICACHE_CRRx_REMAPADDR_6   (0x40UL << ICACHE_CRRx_REMAPADDR_Pos)  /*!< 0x00400000 */
#define ICACHE_CRRx_REMAPADDR_7   (0x80UL << ICACHE_CRRx_REMAPADDR_Pos)  /*!< 0x00800000 */
#define ICACHE_CRRx_REMAPADDR_8   (0x100UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x01000000 */
#define ICACHE_CRRx_REMAPADDR_9   (0x200UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x02000000 */
#define ICACHE_CRRx_REMAPADDR_10  (0x400UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x04000000 */
#define ICACHE_CRRx_HBURST_Pos    (31U)
#define ICACHE_CRRx_HBURST_Msk    (0x1UL << ICACHE_CRRx_HBURST_Pos)      /*!< 0x80000000 */
#define ICACHE_CRRx_HBURST        ICACHE_CRRx_HBURST_Msk                 /*!< output burst type for region x */

/**********************************************************************************************************************/
/*                                                                                                                    */
/*                                            Power Control (PWR)                                                     */
/*                                                                                                                    */
/**********************************************************************************************************************/
/* *************************************  Bit definition for PWR_PMCR register  ************************************* */
#define PWR_PMCR_LPMS_Pos          (0U)
#define PWR_PMCR_LPMS_Msk          (0x3UL << PWR_PMCR_LPMS_Pos)            /*!< 0x00000003 */
#define PWR_PMCR_LPMS              PWR_PMCR_LPMS_Msk                       /*!< low-power mode selection */
#define PWR_PMCR_LPMS_0            (0x1UL << PWR_PMCR_LPMS_Pos)            /*!< 0x00000001 */
#define PWR_PMCR_LPMS_1            (0x2UL << PWR_PMCR_LPMS_Pos)            /*!< 0x00000002 */
#define PWR_PMCR_CSSF_Pos          (7U)
#define PWR_PMCR_CSSF_Msk          (0x1UL << PWR_PMCR_CSSF_Pos)            /*!< 0x00000080 */
#define PWR_PMCR_CSSF              PWR_PMCR_CSSF_Msk                       /*!< Clear Standby and Stop flags (always
                                                                                read as 0) */
#define PWR_PMCR_FLPS_Pos          (9U)
#define PWR_PMCR_FLPS_Msk          (0x1UL << PWR_PMCR_FLPS_Pos)            /*!< 0x00000200 */
#define PWR_PMCR_FLPS              PWR_PMCR_FLPS_Msk                       /*!< Flash memory low-power mode in Stop mode
                                                                                */
#define PWR_PMCR_SRAM2_1_SO_Pos    (24U)
#define PWR_PMCR_SRAM2_1_SO_Msk    (0x1UL << PWR_PMCR_SRAM2_1_SO_Pos)      /*!< 0x01000000 */
#define PWR_PMCR_SRAM2_1_SO        PWR_PMCR_SRAM2_1_SO_Msk                 /*!< AHB SRAM2 block 1 shut-off in Stop mode
                                                                                */
#define PWR_PMCR_SRAM2_2_SO_Pos    (25U)
#define PWR_PMCR_SRAM2_2_SO_Msk    (0x1UL << PWR_PMCR_SRAM2_2_SO_Pos)      /*!< 0x02000000 */
#define PWR_PMCR_SRAM2_2_SO        PWR_PMCR_SRAM2_2_SO_Msk                 /*!< AHB SRAM2 block 2 shut-off in Stop mode
                                                                                */
#define PWR_PMCR_SRAM1SO_Pos       (26U)
#define PWR_PMCR_SRAM1SO_Msk       (0x1UL << PWR_PMCR_SRAM1SO_Pos)         /*!< 0x04000000 */
#define PWR_PMCR_SRAM1SO           PWR_PMCR_SRAM1SO_Msk                    /*!< AHB SRAM1 block 1 shut-off in Stop mode
                                                                                */

/* *************************************  Bit definition for PWR_PMSR register  ************************************* */
#define PWR_PMSR_STOPF_Pos         (5U)
#define PWR_PMSR_STOPF_Msk         (0x1UL << PWR_PMSR_STOPF_Pos)           /*!< 0x00000020 */
#define PWR_PMSR_STOPF             PWR_PMSR_STOPF_Msk                      /*!< Stop flag */
#define PWR_PMSR_SBF_Pos           (6U)
#define PWR_PMSR_SBF_Msk           (0x1UL << PWR_PMSR_SBF_Pos)             /*!< 0x00000040 */
#define PWR_PMSR_SBF               PWR_PMSR_SBF_Msk                        /*!< System standby flag */

/* ************************************  Bit definition for PWR_RTCCR register  ************************************* */
#define PWR_RTCCR_DRTCP_Pos        (0U)
#define PWR_RTCCR_DRTCP_Msk        (0x1UL << PWR_RTCCR_DRTCP_Pos)          /*!< 0x00000001 */
#define PWR_RTCCR_DRTCP            PWR_RTCCR_DRTCP_Msk                     /*!< Disable RTC domain write protection */

/* *************************************  Bit definition for PWR_VMCR register  ************************************* */
#define PWR_VMCR_PVDE_Pos          (0U)
#define PWR_VMCR_PVDE_Msk          (0x1UL << PWR_VMCR_PVDE_Pos)            /*!< 0x00000001 */
#define PWR_VMCR_PVDE              PWR_VMCR_PVDE_Msk                       /*!< PVD enable */

/* *************************************  Bit definition for PWR_VMSR register  ************************************* */
#define PWR_VMSR_PVDO_Pos          (22U)
#define PWR_VMSR_PVDO_Msk          (0x1UL << PWR_VMSR_PVDO_Pos)            /*!< 0x00400000 */
#define PWR_VMSR_PVDO              PWR_VMSR_PVDO_Msk                       /*!< programmable voltage detect output */

/* ************************************  Bit definition for PWR_WUSCR register  ************************************* */
#define PWR_WUSCR_CWUF1_Pos        (0U)
#define PWR_WUSCR_CWUF1_Msk        (0x1UL << PWR_WUSCR_CWUF1_Pos)          /*!< 0x00000001 */
#define PWR_WUSCR_CWUF1            PWR_WUSCR_CWUF1_Msk                     /*!< clear wake-up pin flag for WUFx (x = 7
                                                                                to 1) */
#define PWR_WUSCR_CWUF2_Pos        (1U)
#define PWR_WUSCR_CWUF2_Msk        (0x1UL << PWR_WUSCR_CWUF2_Pos)          /*!< 0x00000002 */
#define PWR_WUSCR_CWUF2            PWR_WUSCR_CWUF2_Msk                     /*!< clear wake-up pin flag for WUFx (x = 7
                                                                                to 1) */
#define PWR_WUSCR_CWUF3_Pos        (2U)
#define PWR_WUSCR_CWUF3_Msk        (0x1UL << PWR_WUSCR_CWUF3_Pos)          /*!< 0x00000004 */
#define PWR_WUSCR_CWUF3            PWR_WUSCR_CWUF3_Msk                     /*!< clear wake-up pin flag for WUFx (x = 7
                                                                               to 1) */
#define PWR_WUSCR_CWUF4_Pos        (3U)
#define PWR_WUSCR_CWUF4_Msk        (0x1UL << PWR_WUSCR_CWUF4_Pos)          /*!< 0x00000008 */
#define PWR_WUSCR_CWUF4            PWR_WUSCR_CWUF4_Msk                     /*!< clear wake-up pin flag for WUFx (x = 7
                                                                                to 1) */
#define PWR_WUSCR_CWUF5_Pos        (4U)
#define PWR_WUSCR_CWUF5_Msk        (0x1UL << PWR_WUSCR_CWUF5_Pos)          /*!< 0x00000010 */
#define PWR_WUSCR_CWUF5            PWR_WUSCR_CWUF5_Msk                     /*!< clear wake-up pin flag for WUFx (x = 7
                                                                                to 1) */
#define PWR_WUSCR_CWUF6_Pos        (5U)
#define PWR_WUSCR_CWUF6_Msk        (0x1UL << PWR_WUSCR_CWUF6_Pos)          /*!< 0x00000020 */
#define PWR_WUSCR_CWUF6            PWR_WUSCR_CWUF6_Msk                     /*!< clear wake-up pin flag for WUFx (x = 7
                                                                                to 1) */
#define PWR_WUSCR_CWUF7_Pos        (6U)
#define PWR_WUSCR_CWUF7_Msk        (0x1UL << PWR_WUSCR_CWUF7_Pos)          /*!< 0x00000040 */
#define PWR_WUSCR_CWUF7            PWR_WUSCR_CWUF7_Msk                     /*!< clear wake-up pin flag for WUFx (x = 7
                                                                                to 1) */

/* *************************************  Bit definition for PWR_WUSR register  ************************************* */
#define PWR_WUSR_WUF1_Pos          (0U)
#define PWR_WUSR_WUF1_Msk          (0x1UL << PWR_WUSR_WUF1_Pos)            /*!< 0x00000001 */
#define PWR_WUSR_WUF1              PWR_WUSR_WUF1_Msk                       /*!< wake-up pin WUFx flag */
#define PWR_WUSR_WUF2_Pos          (1U)
#define PWR_WUSR_WUF2_Msk          (0x1UL << PWR_WUSR_WUF2_Pos)            /*!< 0x00000002 */
#define PWR_WUSR_WUF2              PWR_WUSR_WUF2_Msk                       /*!< wake-up pin WUFx flag */
#define PWR_WUSR_WUF3_Pos          (2U)
#define PWR_WUSR_WUF3_Msk          (0x1UL << PWR_WUSR_WUF3_Pos)            /*!< 0x00000004 */
#define PWR_WUSR_WUF3              PWR_WUSR_WUF3_Msk                       /*!< wake-up pin WUFx flag */
#define PWR_WUSR_WUF4_Pos          (3U)
#define PWR_WUSR_WUF4_Msk          (0x1UL << PWR_WUSR_WUF4_Pos)            /*!< 0x00000008 */
#define PWR_WUSR_WUF4              PWR_WUSR_WUF4_Msk                       /*!< wake-up pin WUFx flag */
#define PWR_WUSR_WUF5_Pos          (4U)
#define PWR_WUSR_WUF5_Msk          (0x1UL << PWR_WUSR_WUF5_Pos)            /*!< 0x00000010 */
#define PWR_WUSR_WUF5              PWR_WUSR_WUF5_Msk                       /*!< wake-up pin WUFx flag */
#define PWR_WUSR_WUF6_Pos          (5U)
#define PWR_WUSR_WUF6_Msk          (0x1UL << PWR_WUSR_WUF6_Pos)            /*!< 0x00000020 */
#define PWR_WUSR_WUF6              PWR_WUSR_WUF6_Msk                       /*!< wake-up pin WUFx flag */
#define PWR_WUSR_WUF7_Pos          (6U)
#define PWR_WUSR_WUF7_Msk          (0x1UL << PWR_WUSR_WUF7_Pos)            /*!< 0x00000040 */
#define PWR_WUSR_WUF7              PWR_WUSR_WUF7_Msk                       /*!< wake-up pin WUFx flag */

/* *************************************  Bit definition for PWR_WUCR register  ************************************* */
#define PWR_WUCR_WUPEN1_Pos        (0U)
#define PWR_WUCR_WUPEN1_Msk        (0x1UL << PWR_WUCR_WUPEN1_Pos)          /*!< 0x00000001 */
#define PWR_WUCR_WUPEN1            PWR_WUCR_WUPEN1_Msk                     /*!< Enable wake-up pin WKUPx (x = 7 to 1) */
#define PWR_WUCR_WUPEN2_Pos        (1U)
#define PWR_WUCR_WUPEN2_Msk        (0x1UL << PWR_WUCR_WUPEN2_Pos)          /*!< 0x00000002 */
#define PWR_WUCR_WUPEN2            PWR_WUCR_WUPEN2_Msk                     /*!< Enable wake-up pin WKUPx (x = 7 to 1) */
#define PWR_WUCR_WUPEN3_Pos        (2U)
#define PWR_WUCR_WUPEN3_Msk        (0x1UL << PWR_WUCR_WUPEN3_Pos)          /*!< 0x00000004 */
#define PWR_WUCR_WUPEN3            PWR_WUCR_WUPEN3_Msk                     /*!< Enable wake-up pin WKUPx (x = 7 to 1) */
#define PWR_WUCR_WUPEN4_Pos        (3U)
#define PWR_WUCR_WUPEN4_Msk        (0x1UL << PWR_WUCR_WUPEN4_Pos)          /*!< 0x00000008 */
#define PWR_WUCR_WUPEN4            PWR_WUCR_WUPEN4_Msk                     /*!< Enable wake-up pin WKUPx (x = 7 to 1) */
#define PWR_WUCR_WUPEN5_Pos        (4U)
#define PWR_WUCR_WUPEN5_Msk        (0x1UL << PWR_WUCR_WUPEN5_Pos)          /*!< 0x00000010 */
#define PWR_WUCR_WUPEN5            PWR_WUCR_WUPEN5_Msk                     /*!< Enable wake-up pin WKUPx (x = 7 to 1) */
#define PWR_WUCR_WUPEN6_Pos        (5U)
#define PWR_WUCR_WUPEN6_Msk        (0x1UL << PWR_WUCR_WUPEN6_Pos)          /*!< 0x00000020 */
#define PWR_WUCR_WUPEN6            PWR_WUCR_WUPEN6_Msk                     /*!< Enable wake-up pin WKUPx (x = 7 to 1) */
#define PWR_WUCR_WUPEN7_Pos        (6U)
#define PWR_WUCR_WUPEN7_Msk        (0x1UL << PWR_WUCR_WUPEN7_Pos)          /*!< 0x00000040 */
#define PWR_WUCR_WUPEN7            PWR_WUCR_WUPEN7_Msk                     /*!< Enable wake-up pin WKUPx (x = 7 to 1) */
#define PWR_WUCR_WUPP1_Pos         (8U)
#define PWR_WUCR_WUPP1_Msk         (0x1UL << PWR_WUCR_WUPP1_Pos)           /*!< 0x00000100 */
#define PWR_WUCR_WUPP1             PWR_WUCR_WUPP1_Msk                      /*!< Wake-up pin polarity bit for WKUPx
                                                                                (x = 7 to 1) */
#define PWR_WUCR_WUPP2_Pos         (9U)
#define PWR_WUCR_WUPP2_Msk         (0x1UL << PWR_WUCR_WUPP2_Pos)           /*!< 0x00000200 */
#define PWR_WUCR_WUPP2             PWR_WUCR_WUPP2_Msk                      /*!< Wake-up pin polarity bit for WKUPx
                                                                                (x = 7 to 1) */
#define PWR_WUCR_WUPP3_Pos         (10U)
#define PWR_WUCR_WUPP3_Msk         (0x1UL << PWR_WUCR_WUPP3_Pos)           /*!< 0x00000400 */
#define PWR_WUCR_WUPP3             PWR_WUCR_WUPP3_Msk                      /*!< Wake-up pin polarity bit for WKUPx
                                                                                (x = 7 to 1) */
#define PWR_WUCR_WUPP4_Pos         (11U)
#define PWR_WUCR_WUPP4_Msk         (0x1UL << PWR_WUCR_WUPP4_Pos)           /*!< 0x00000800 */
#define PWR_WUCR_WUPP4             PWR_WUCR_WUPP4_Msk                      /*!< Wake-up pin polarity bit for WKUPx
                                                                                (x = 7 to 1) */
#define PWR_WUCR_WUPP5_Pos         (12U)
#define PWR_WUCR_WUPP5_Msk         (0x1UL << PWR_WUCR_WUPP5_Pos)           /*!< 0x00001000 */
#define PWR_WUCR_WUPP5             PWR_WUCR_WUPP5_Msk                      /*!< Wake-up pin polarity bit for WKUPx
                                                                                (x = 7 to 1) */
#define PWR_WUCR_WUPP6_Pos         (13U)
#define PWR_WUCR_WUPP6_Msk         (0x1UL << PWR_WUCR_WUPP6_Pos)           /*!< 0x00002000 */
#define PWR_WUCR_WUPP6             PWR_WUCR_WUPP6_Msk                      /*!< Wake-up pin polarity bit for WKUPx
                                                                                (x = 7 to 1) */
#define PWR_WUCR_WUPP7_Pos         (14U)
#define PWR_WUCR_WUPP7_Msk         (0x1UL << PWR_WUCR_WUPP7_Pos)           /*!< 0x00004000 */
#define PWR_WUCR_WUPP7             PWR_WUCR_WUPP7_Msk                      /*!< Wake-up pin polarity bit for WKUPx
                                                                                (x = 7 to 1) */
#define PWR_WUCR_WUPPUPD1_Pos      (16U)
#define PWR_WUCR_WUPPUPD1_Msk      (0x3UL << PWR_WUCR_WUPPUPD1_Pos)        /*!< 0x00030000 */
#define PWR_WUCR_WUPPUPD1          PWR_WUCR_WUPPUPD1_Msk                   /*!< Wake-up pin pull configuration for WKUPx
                                                                                (x = 7 to 1) */
#define PWR_WUCR_WUPPUPD1_0        (0x1UL << PWR_WUCR_WUPPUPD1_Pos)        /*!< 0x00010000 */
#define PWR_WUCR_WUPPUPD1_1        (0x2UL << PWR_WUCR_WUPPUPD1_Pos)        /*!< 0x00020000 */
#define PWR_WUCR_WUPPUPD2_Pos      (18U)
#define PWR_WUCR_WUPPUPD2_Msk      (0x3UL << PWR_WUCR_WUPPUPD2_Pos)        /*!< 0x000C0000 */
#define PWR_WUCR_WUPPUPD2          PWR_WUCR_WUPPUPD2_Msk                   /*!< Wake-up pin pull configuration for WKUPx
                                                                                (x = 7 to 1) */
#define PWR_WUCR_WUPPUPD2_0        (0x1UL << PWR_WUCR_WUPPUPD2_Pos)        /*!< 0x00040000 */
#define PWR_WUCR_WUPPUPD2_1        (0x2UL << PWR_WUCR_WUPPUPD2_Pos)        /*!< 0x00080000 */
#define PWR_WUCR_WUPPUPD3_Pos      (20U)
#define PWR_WUCR_WUPPUPD3_Msk      (0x3UL << PWR_WUCR_WUPPUPD3_Pos)        /*!< 0x00300000 */
#define PWR_WUCR_WUPPUPD3          PWR_WUCR_WUPPUPD3_Msk                   /*!< Wake-up pin pull configuration for WKUPx
                                                                                (x = 7 to 1) */
#define PWR_WUCR_WUPPUPD3_0        (0x1UL << PWR_WUCR_WUPPUPD3_Pos)        /*!< 0x00100000 */
#define PWR_WUCR_WUPPUPD3_1        (0x2UL << PWR_WUCR_WUPPUPD3_Pos)        /*!< 0x00200000 */
#define PWR_WUCR_WUPPUPD4_Pos      (22U)
#define PWR_WUCR_WUPPUPD4_Msk      (0x3UL << PWR_WUCR_WUPPUPD4_Pos)        /*!< 0x00C00000 */
#define PWR_WUCR_WUPPUPD4          PWR_WUCR_WUPPUPD4_Msk                   /*!< Wake-up pin pull configuration for WKUPx
                                                                                (x = 7 to 1) */
#define PWR_WUCR_WUPPUPD4_0        (0x1UL << PWR_WUCR_WUPPUPD4_Pos)        /*!< 0x00400000 */
#define PWR_WUCR_WUPPUPD4_1        (0x2UL << PWR_WUCR_WUPPUPD4_Pos)        /*!< 0x00800000 */
#define PWR_WUCR_WUPPUPD5_Pos      (24U)
#define PWR_WUCR_WUPPUPD5_Msk      (0x3UL << PWR_WUCR_WUPPUPD5_Pos)        /*!< 0x03000000 */
#define PWR_WUCR_WUPPUPD5          PWR_WUCR_WUPPUPD5_Msk                   /*!< Wake-up pin pull configuration for WKUPx
                                                                                (x = 7 to 1) */
#define PWR_WUCR_WUPPUPD5_0        (0x1UL << PWR_WUCR_WUPPUPD5_Pos)        /*!< 0x01000000 */
#define PWR_WUCR_WUPPUPD5_1        (0x2UL << PWR_WUCR_WUPPUPD5_Pos)        /*!< 0x02000000 */
#define PWR_WUCR_WUPPUPD6_Pos      (26U)
#define PWR_WUCR_WUPPUPD6_Msk      (0x3UL << PWR_WUCR_WUPPUPD6_Pos)        /*!< 0x0C000000 */
#define PWR_WUCR_WUPPUPD6          PWR_WUCR_WUPPUPD6_Msk                   /*!< Wake-up pin pull configuration for WKUPx
                                                                                (x = 7 to 1) */
#define PWR_WUCR_WUPPUPD6_0        (0x1UL << PWR_WUCR_WUPPUPD6_Pos)        /*!< 0x04000000 */
#define PWR_WUCR_WUPPUPD6_1        (0x2UL << PWR_WUCR_WUPPUPD6_Pos)        /*!< 0x08000000 */
#define PWR_WUCR_WUPPUPD7_Pos      (28U)
#define PWR_WUCR_WUPPUPD7_Msk      (0x3UL << PWR_WUCR_WUPPUPD7_Pos)        /*!< 0x30000000 */
#define PWR_WUCR_WUPPUPD7          PWR_WUCR_WUPPUPD7_Msk                   /*!< Wake-up pin pull configuration for WKUPx
                                                                                (x = 7 to 1) */
#define PWR_WUCR_WUPPUPD7_0        (0x1UL << PWR_WUCR_WUPPUPD7_Pos)        /*!< 0x10000000 */
#define PWR_WUCR_WUPPUPD7_1        (0x2UL << PWR_WUCR_WUPPUPD7_Pos)        /*!< 0x20000000 */

/* ************************************  Bit definition for PWR_IORETR register  ************************************ */
#define PWR_IORETR_IORETEN_Pos     (0U)
#define PWR_IORETR_IORETEN_Msk     (0x1UL << PWR_IORETR_IORETEN_Pos)       /*!< 0x00000001 */
#define PWR_IORETR_IORETEN         PWR_IORETR_IORETEN_Msk                  /*!< IO retention enable */
#define PWR_IORETR_JTAGIORETEN_Pos (16U)
#define PWR_IORETR_JTAGIORETEN_Msk (0x1UL << PWR_IORETR_JTAGIORETEN_Pos)   /*!< 0x00010000 */
#define PWR_IORETR_JTAGIORETEN     PWR_IORETR_JTAGIORETEN_Msk              /*!< IO retention enable for JTAG I/Os */

/* ***********************************  Bit definition for PWR_PRIVCFGR register  *********************************** */
#define PWR_PRIVCFGR_PRIV_Pos      (1U)
#define PWR_PRIVCFGR_PRIV_Msk      (0x1UL << PWR_PRIVCFGR_PRIV_Pos)        /*!< 0x00000002 */
#define PWR_PRIVCFGR_PRIV          PWR_PRIVCFGR_PRIV_Msk                   /*!< PWR nonsecure functions privilege
                                                                                configuration */

/* ****************************************************************************************************************** */
/*                                                                                                                    */
/*                                       RAMs configuration controller (RAMCFG)                                       */
/*                                                                                                                    */
/* ****************************************************************************************************************** */
/* ***********************************   Bit definition for RAMCFG_CR register   ************************************ */
#define RAMCFG_CR_ECCE_Pos         (0U)
#define RAMCFG_CR_ECCE_Msk         (0x1UL << RAMCFG_CR_ECCE_Pos)           /*!< 0x00000001 */
#define RAMCFG_CR_ECCE             RAMCFG_CR_ECCE_Msk                      /*!< ECC enable. */
#define RAMCFG_CR_ALE_Pos          (4U)
#define RAMCFG_CR_ALE_Msk          (0x1UL << RAMCFG_CR_ALE_Pos)            /*!< 0x00000010 */
#define RAMCFG_CR_ALE              RAMCFG_CR_ALE_Msk                       /*!< Address latch enable */
#define RAMCFG_CR_SRAMER_Pos       (8U)
#define RAMCFG_CR_SRAMER_Msk       (0x1UL << RAMCFG_CR_SRAMER_Pos)         /*!< 0x00000100 */
#define RAMCFG_CR_SRAMER           RAMCFG_CR_SRAMER_Msk                    /*!< SRAM erase */

/* ***********************************   Bit definition for RAMCFG_IER register   *********************************** */
#define RAMCFG_IER_SEIE_Pos        (0U)
#define RAMCFG_IER_SEIE_Msk        (0x1UL << RAMCFG_IER_SEIE_Pos)          /*!< 0x00000001 */
#define RAMCFG_IER_SEIE            RAMCFG_IER_SEIE_Msk                     /*!< ECC single error interrupt enable */
#define RAMCFG_IER_DEIE_Pos        (1U)
#define RAMCFG_IER_DEIE_Msk        (0x1UL << RAMCFG_IER_DEIE_Pos)          /*!< 0x00000002 */
#define RAMCFG_IER_DEIE            RAMCFG_IER_DEIE_Msk                     /*!< ECC double error interrupt enable */
#define RAMCFG_IER_ECCNMI_Pos      (3U)
#define RAMCFG_IER_ECCNMI_Msk      (0x1UL << RAMCFG_IER_ECCNMI_Pos)        /*!< 0x00000008 */
#define RAMCFG_IER_ECCNMI          RAMCFG_IER_ECCNMI_Msk                   /*!< Double error NMI */

/* ***********************************   Bit definition for RAMCFG_ISR register   *********************************** */
#define RAMCFG_ISR_SEDC_Pos        (0U)
#define RAMCFG_ISR_SEDC_Msk        (0x1UL << RAMCFG_ISR_SEDC_Pos)          /*!< 0x00000001 */
#define RAMCFG_ISR_SEDC            RAMCFG_ISR_SEDC_Msk                     /*!< ECC single error detected and
                                                                                corrected */
#define RAMCFG_ISR_DED_Pos         (1U)
#define RAMCFG_ISR_DED_Msk         (0x1UL << RAMCFG_ISR_DED_Pos)           /*!< 0x00000002 */
#define RAMCFG_ISR_DED             RAMCFG_ISR_DED_Msk                      /*!< ECC double error detected */
#define RAMCFG_ISR_SRAMBUSY_Pos    (8U)
#define RAMCFG_ISR_SRAMBUSY_Msk    (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos)      /*!< 0x00000100 */
#define RAMCFG_ISR_SRAMBUSY        RAMCFG_ISR_SRAMBUSY_Msk                 /*!< SRAM busy with erase operation */

/* **********************************   Bit definition for RAMCFG_SEAR register   *********************************** */
#define RAMCFG_SEAR_ESEA_Pos       (0U)
#define RAMCFG_SEAR_ESEA_Msk       (0xFFFFFFFFUL << RAMCFG_SEAR_ESEA_Pos)  /*!< 0xFFFFFFFF */
#define RAMCFG_SEAR_ESEA           RAMCFG_SEAR_ESEA_Msk                    /*!< ECC single error address */

/* **********************************   Bit definition for RAMCFG_DEAR register   *********************************** */
#define RAMCFG_DEAR_EDEA_Pos       (0U)
#define RAMCFG_DEAR_EDEA_Msk       (0xFFFFFFFFUL << RAMCFG_DEAR_EDEA_Pos)  /*!< 0xFFFFFFFF */
#define RAMCFG_DEAR_EDEA           RAMCFG_DEAR_EDEA_Msk                    /*!< ECC double error address */

/* ***********************************   Bit definition for RAMCFG_ICR register   *********************************** */
#define RAMCFG_ICR_CSEDC_Pos       (0U)
#define RAMCFG_ICR_CSEDC_Msk       (0x1UL << RAMCFG_ICR_CSEDC_Pos)         /*!< 0x00000001 */
#define RAMCFG_ICR_CSEDC           RAMCFG_ICR_CSEDC_Msk                    /*!< Clear ECC single error detected and
                                                                                corrected */
#define RAMCFG_ICR_CDED_Pos        (1U)
#define RAMCFG_ICR_CDED_Msk        (0x1UL << RAMCFG_ICR_CDED_Pos)          /*!< 0x00000002 */
#define RAMCFG_ICR_CDED            RAMCFG_ICR_CDED_Msk                     /*!< Clear ECC double error detected */

/* **********************************   Bit definition for RAMCFG_WPR1 register   *********************************** */
#define RAMCFG_WPR1_P0WP_Pos       (0U)
#define RAMCFG_WPR1_P0WP_Msk       (0x1UL << RAMCFG_WPR1_P0WP_Pos)         /*!< 0x00000001 */
#define RAMCFG_WPR1_P0WP           RAMCFG_WPR1_P0WP_Msk                    /*!< Write Protection Page 00 */
#define RAMCFG_WPR1_P1WP_Pos       (1U)
#define RAMCFG_WPR1_P1WP_Msk       (0x1UL << RAMCFG_WPR1_P1WP_Pos)         /*!< 0x00000002 */
#define RAMCFG_WPR1_P1WP           RAMCFG_WPR1_P1WP_Msk                    /*!< Write Protection Page 01 */
#define RAMCFG_WPR1_P2WP_Pos       (2U)
#define RAMCFG_WPR1_P2WP_Msk       (0x1UL << RAMCFG_WPR1_P2WP_Pos)         /*!< 0x00000004 */
#define RAMCFG_WPR1_P2WP           RAMCFG_WPR1_P2WP_Msk                    /*!< Write Protection Page 02 */
#define RAMCFG_WPR1_P3WP_Pos       (3U)
#define RAMCFG_WPR1_P3WP_Msk       (0x1UL << RAMCFG_WPR1_P3WP_Pos)         /*!< 0x00000008 */
#define RAMCFG_WPR1_P3WP           RAMCFG_WPR1_P3WP_Msk                    /*!< Write Protection Page 03 */
#define RAMCFG_WPR1_P4WP_Pos       (4U)
#define RAMCFG_WPR1_P4WP_Msk       (0x1UL << RAMCFG_WPR1_P4WP_Pos)         /*!< 0x00000010 */
#define RAMCFG_WPR1_P4WP           RAMCFG_WPR1_P4WP_Msk                    /*!< Write Protection Page 04 */
#define RAMCFG_WPR1_P5WP_Pos       (5U)
#define RAMCFG_WPR1_P5WP_Msk       (0x1UL << RAMCFG_WPR1_P5WP_Pos)         /*!< 0x00000020 */
#define RAMCFG_WPR1_P5WP           RAMCFG_WPR1_P5WP_Msk                    /*!< Write Protection Page 05 */
#define RAMCFG_WPR1_P6WP_Pos       (6U)
#define RAMCFG_WPR1_P6WP_Msk       (0x1UL << RAMCFG_WPR1_P6WP_Pos)         /*!< 0x00000040 */
#define RAMCFG_WPR1_P6WP           RAMCFG_WPR1_P6WP_Msk                    /*!< Write Protection Page 06 */
#define RAMCFG_WPR1_P7WP_Pos       (7U)
#define RAMCFG_WPR1_P7WP_Msk       (0x1UL << RAMCFG_WPR1_P7WP_Pos)         /*!< 0x00000080 */
#define RAMCFG_WPR1_P7WP           RAMCFG_WPR1_P7WP_Msk                    /*!< Write Protection Page 07 */
#define RAMCFG_WPR1_P8WP_Pos       (8U)
#define RAMCFG_WPR1_P8WP_Msk       (0x1UL << RAMCFG_WPR1_P8WP_Pos)         /*!< 0x00000100 */
#define RAMCFG_WPR1_P8WP           RAMCFG_WPR1_P8WP_Msk                    /*!< Write Protection Page 08 */
#define RAMCFG_WPR1_P9WP_Pos       (9U)
#define RAMCFG_WPR1_P9WP_Msk       (0x1UL << RAMCFG_WPR1_P9WP_Pos)         /*!< 0x00000200 */
#define RAMCFG_WPR1_P9WP           RAMCFG_WPR1_P9WP_Msk                    /*!< Write Protection Page 09 */
#define RAMCFG_WPR1_P10WP_Pos      (10U)
#define RAMCFG_WPR1_P10WP_Msk      (0x1UL << RAMCFG_WPR1_P10WP_Pos)        /*!< 0x00000400 */
#define RAMCFG_WPR1_P10WP          RAMCFG_WPR1_P10WP_Msk                   /*!< Write Protection Page 10 */
#define RAMCFG_WPR1_P11WP_Pos      (11U)
#define RAMCFG_WPR1_P11WP_Msk      (0x1UL << RAMCFG_WPR1_P11WP_Pos)        /*!< 0x00000800 */
#define RAMCFG_WPR1_P11WP          RAMCFG_WPR1_P11WP_Msk                   /*!< Write Protection Page 11 */
#define RAMCFG_WPR1_P12WP_Pos      (12U)
#define RAMCFG_WPR1_P12WP_Msk      (0x1UL << RAMCFG_WPR1_P12WP_Pos)        /*!< 0x00001000 */
#define RAMCFG_WPR1_P12WP          RAMCFG_WPR1_P12WP_Msk                   /*!< Write Protection Page 12 */
#define RAMCFG_WPR1_P13WP_Pos      (13U)
#define RAMCFG_WPR1_P13WP_Msk      (0x1UL << RAMCFG_WPR1_P13WP_Pos)        /*!< 0x00002000 */
#define RAMCFG_WPR1_P13WP          RAMCFG_WPR1_P13WP_Msk                   /*!< Write Protection Page 13 */
#define RAMCFG_WPR1_P14WP_Pos      (14U)
#define RAMCFG_WPR1_P14WP_Msk      (0x1UL << RAMCFG_WPR1_P14WP_Pos)        /*!< 0x00004000 */
#define RAMCFG_WPR1_P14WP          RAMCFG_WPR1_P14WP_Msk                   /*!< Write Protection Page 14 */
#define RAMCFG_WPR1_P15WP_Pos      (15U)
#define RAMCFG_WPR1_P15WP_Msk      (0x1UL << RAMCFG_WPR1_P15WP_Pos)        /*!< 0x00008000 */
#define RAMCFG_WPR1_P15WP          RAMCFG_WPR1_P15WP_Msk                   /*!< Write Protection Page 15 */
#define RAMCFG_WPR1_P16WP_Pos      (16U)
#define RAMCFG_WPR1_P16WP_Msk      (0x1UL << RAMCFG_WPR1_P16WP_Pos)        /*!< 0x00010000 */
#define RAMCFG_WPR1_P16WP          RAMCFG_WPR1_P16WP_Msk                   /*!< Write Protection Page 16 */
#define RAMCFG_WPR1_P17WP_Pos      (17U)
#define RAMCFG_WPR1_P17WP_Msk      (0x1UL << RAMCFG_WPR1_P17WP_Pos)        /*!< 0x00020000 */
#define RAMCFG_WPR1_P17WP          RAMCFG_WPR1_P17WP_Msk                   /*!< Write Protection Page 17 */
#define RAMCFG_WPR1_P18WP_Pos      (18U)
#define RAMCFG_WPR1_P18WP_Msk      (0x1UL << RAMCFG_WPR1_P18WP_Pos)        /*!< 0x00040000 */
#define RAMCFG_WPR1_P18WP          RAMCFG_WPR1_P18WP_Msk                   /*!< Write Protection Page 18 */
#define RAMCFG_WPR1_P19WP_Pos      (19U)
#define RAMCFG_WPR1_P19WP_Msk      (0x1UL << RAMCFG_WPR1_P19WP_Pos)        /*!< 0x00080000 */
#define RAMCFG_WPR1_P19WP          RAMCFG_WPR1_P19WP_Msk                   /*!< Write Protection Page 19 */
#define RAMCFG_WPR1_P20WP_Pos      (20U)
#define RAMCFG_WPR1_P20WP_Msk      (0x1UL << RAMCFG_WPR1_P20WP_Pos)        /*!< 0x00100000 */
#define RAMCFG_WPR1_P20WP          RAMCFG_WPR1_P20WP_Msk                   /*!< Write Protection Page 20 */
#define RAMCFG_WPR1_P21WP_Pos      (21U)
#define RAMCFG_WPR1_P21WP_Msk      (0x1UL << RAMCFG_WPR1_P21WP_Pos)        /*!< 0x00200000 */
#define RAMCFG_WPR1_P21WP          RAMCFG_WPR1_P21WP_Msk                   /*!< Write Protection Page 21 */
#define RAMCFG_WPR1_P22WP_Pos      (22U)
#define RAMCFG_WPR1_P22WP_Msk      (0x1UL << RAMCFG_WPR1_P22WP_Pos)        /*!< 0x00400000 */
#define RAMCFG_WPR1_P22WP          RAMCFG_WPR1_P22WP_Msk                   /*!< Write Protection Page 22 */
#define RAMCFG_WPR1_P23WP_Pos      (23U)
#define RAMCFG_WPR1_P23WP_Msk      (0x1UL << RAMCFG_WPR1_P23WP_Pos)        /*!< 0x00800000 */
#define RAMCFG_WPR1_P23WP          RAMCFG_WPR1_P23WP_Msk                   /*!< Write Protection Page 23 */
#define RAMCFG_WPR1_P24WP_Pos      (24U)
#define RAMCFG_WPR1_P24WP_Msk      (0x1UL << RAMCFG_WPR1_P24WP_Pos)        /*!< 0x01000000 */
#define RAMCFG_WPR1_P24WP          RAMCFG_WPR1_P24WP_Msk                   /*!< Write Protection Page 24 */
#define RAMCFG_WPR1_P25WP_Pos      (25U)
#define RAMCFG_WPR1_P25WP_Msk      (0x1UL << RAMCFG_WPR1_P25WP_Pos)        /*!< 0x02000000 */
#define RAMCFG_WPR1_P25WP          RAMCFG_WPR1_P25WP_Msk                   /*!< Write Protection Page 25 */
#define RAMCFG_WPR1_P26WP_Pos      (26U)
#define RAMCFG_WPR1_P26WP_Msk      (0x1UL << RAMCFG_WPR1_P26WP_Pos)        /*!< 0x04000000 */
#define RAMCFG_WPR1_P26WP          RAMCFG_WPR1_P26WP_Msk                   /*!< Write Protection Page 26 */
#define RAMCFG_WPR1_P27WP_Pos      (27U)
#define RAMCFG_WPR1_P27WP_Msk      (0x1UL << RAMCFG_WPR1_P27WP_Pos)        /*!< 0x08000000 */
#define RAMCFG_WPR1_P27WP          RAMCFG_WPR1_P27WP_Msk                   /*!< Write Protection Page 27 */
#define RAMCFG_WPR1_P28WP_Pos      (28U)
#define RAMCFG_WPR1_P28WP_Msk      (0x1UL << RAMCFG_WPR1_P28WP_Pos)        /*!< 0x10000000 */
#define RAMCFG_WPR1_P28WP          RAMCFG_WPR1_P28WP_Msk                   /*!< Write Protection Page 28 */
#define RAMCFG_WPR1_P29WP_Pos      (29U)
#define RAMCFG_WPR1_P29WP_Msk      (0x1UL << RAMCFG_WPR1_P29WP_Pos)        /*!< 0x20000000 */
#define RAMCFG_WPR1_P29WP          RAMCFG_WPR1_P29WP_Msk                   /*!< Write Protection Page 29 */
#define RAMCFG_WPR1_P30WP_Pos      (30U)
#define RAMCFG_WPR1_P30WP_Msk      (0x1UL << RAMCFG_WPR1_P30WP_Pos)        /*!< 0x40000000 */
#define RAMCFG_WPR1_P30WP          RAMCFG_WPR1_P30WP_Msk                   /*!< Write Protection Page 30 */
#define RAMCFG_WPR1_P31WP_Pos      (31U)
#define RAMCFG_WPR1_P31WP_Msk      (0x1UL << RAMCFG_WPR1_P31WP_Pos)        /*!< 0x80000000 */
#define RAMCFG_WPR1_P31WP          RAMCFG_WPR1_P31WP_Msk                   /*!< Write Protection Page 31 */

/* **********************************   Bit definition for RAMCFG_WPR2 register   *********************************** */
#define RAMCFG_WPR2_P32WP_Pos      (0U)
#define RAMCFG_WPR2_P32WP_Msk      (0x1UL << RAMCFG_WPR2_P32WP_Pos)        /*!< 0x00000001 */
#define RAMCFG_WPR2_P32WP          RAMCFG_WPR2_P32WP_Msk                   /*!< Write Protection Page 32 */
#define RAMCFG_WPR2_P33WP_Pos      (1U)
#define RAMCFG_WPR2_P33WP_Msk      (0x1UL << RAMCFG_WPR2_P33WP_Pos)        /*!< 0x00000002 */
#define RAMCFG_WPR2_P33WP          RAMCFG_WPR2_P33WP_Msk                   /*!< Write Protection Page 33 */
#define RAMCFG_WPR2_P34WP_Pos      (2U)
#define RAMCFG_WPR2_P34WP_Msk      (0x1UL << RAMCFG_WPR2_P34WP_Pos)        /*!< 0x00000004 */
#define RAMCFG_WPR2_P34WP          RAMCFG_WPR2_P34WP_Msk                   /*!< Write Protection Page 34 */
#define RAMCFG_WPR2_P35WP_Pos      (3U)
#define RAMCFG_WPR2_P35WP_Msk      (0x1UL << RAMCFG_WPR2_P35WP_Pos)        /*!< 0x00000008 */
#define RAMCFG_WPR2_P35WP          RAMCFG_WPR2_P35WP_Msk                   /*!< Write Protection Page 35 */
#define RAMCFG_WPR2_P36WP_Pos      (4U)
#define RAMCFG_WPR2_P36WP_Msk      (0x1UL << RAMCFG_WPR2_P36WP_Pos)        /*!< 0x00000010 */
#define RAMCFG_WPR2_P36WP          RAMCFG_WPR2_P36WP_Msk                   /*!< Write Protection Page 36 */
#define RAMCFG_WPR2_P37WP_Pos      (5U)
#define RAMCFG_WPR2_P37WP_Msk      (0x1UL << RAMCFG_WPR2_P37WP_Pos)        /*!< 0x00000020 */
#define RAMCFG_WPR2_P37WP          RAMCFG_WPR2_P37WP_Msk                   /*!< Write Protection Page 37 */
#define RAMCFG_WPR2_P38WP_Pos      (6U)
#define RAMCFG_WPR2_P38WP_Msk      (0x1UL << RAMCFG_WPR2_P38WP_Pos)        /*!< 0x00000040 */
#define RAMCFG_WPR2_P38WP          RAMCFG_WPR2_P38WP_Msk                   /*!< Write Protection Page 38 */
#define RAMCFG_WPR2_P39WP_Pos      (7U)
#define RAMCFG_WPR2_P39WP_Msk      (0x1UL << RAMCFG_WPR2_P39WP_Pos)        /*!< 0x00000080 */
#define RAMCFG_WPR2_P39WP          RAMCFG_WPR2_P39WP_Msk                   /*!< Write Protection Page 39 */
#define RAMCFG_WPR2_P40WP_Pos      (8U)
#define RAMCFG_WPR2_P40WP_Msk      (0x1UL << RAMCFG_WPR2_P40WP_Pos)        /*!< 0x00000100 */
#define RAMCFG_WPR2_P40WP          RAMCFG_WPR2_P40WP_Msk                   /*!< Write Protection Page 40 */
#define RAMCFG_WPR2_P41WP_Pos      (9U)
#define RAMCFG_WPR2_P41WP_Msk      (0x1UL << RAMCFG_WPR2_P41WP_Pos)        /*!< 0x00000200 */
#define RAMCFG_WPR2_P41WP          RAMCFG_WPR2_P41WP_Msk                   /*!< Write Protection Page 41 */
#define RAMCFG_WPR2_P42WP_Pos      (10U)
#define RAMCFG_WPR2_P42WP_Msk      (0x1UL << RAMCFG_WPR2_P42WP_Pos)        /*!< 0x00000400 */
#define RAMCFG_WPR2_P42WP          RAMCFG_WPR2_P42WP_Msk                   /*!< Write Protection Page 42 */
#define RAMCFG_WPR2_P43WP_Pos      (11U)
#define RAMCFG_WPR2_P43WP_Msk      (0x1UL << RAMCFG_WPR2_P43WP_Pos)        /*!< 0x00000800 */
#define RAMCFG_WPR2_P43WP          RAMCFG_WPR2_P43WP_Msk                   /*!< Write Protection Page 43 */
#define RAMCFG_WPR2_P44WP_Pos      (12U)
#define RAMCFG_WPR2_P44WP_Msk      (0x1UL << RAMCFG_WPR2_P44WP_Pos)        /*!< 0x00001000 */
#define RAMCFG_WPR2_P44WP          RAMCFG_WPR2_P44WP_Msk                   /*!< Write Protection Page 44 */
#define RAMCFG_WPR2_P45WP_Pos      (13U)
#define RAMCFG_WPR2_P45WP_Msk      (0x1UL << RAMCFG_WPR2_P45WP_Pos)        /*!< 0x00002000 */
#define RAMCFG_WPR2_P45WP          RAMCFG_WPR2_P45WP_Msk                   /*!< Write Protection Page 45 */
#define RAMCFG_WPR2_P46WP_Pos      (14U)
#define RAMCFG_WPR2_P46WP_Msk      (0x1UL << RAMCFG_WPR2_P46WP_Pos)        /*!< 0x00004000 */
#define RAMCFG_WPR2_P46WP          RAMCFG_WPR2_P46WP_Msk                   /*!< Write Protection Page 46 */
#define RAMCFG_WPR2_P47WP_Pos      (15U)
#define RAMCFG_WPR2_P47WP_Msk      (0x1UL << RAMCFG_WPR2_P47WP_Pos)        /*!< 0x00008000 */
#define RAMCFG_WPR2_P47WP          RAMCFG_WPR2_P47WP_Msk                   /*!< Write Protection Page 47 */
#define RAMCFG_WPR2_P48WP_Pos      (16U)
#define RAMCFG_WPR2_P48WP_Msk      (0x1UL << RAMCFG_WPR2_P48WP_Pos)        /*!< 0x00010000 */
#define RAMCFG_WPR2_P48WP          RAMCFG_WPR2_P48WP_Msk                   /*!< Write Protection Page 48 */
#define RAMCFG_WPR2_P49WP_Pos      (17U)
#define RAMCFG_WPR2_P49WP_Msk      (0x1UL << RAMCFG_WPR2_P49WP_Pos)        /*!< 0x00020000 */
#define RAMCFG_WPR2_P49WP          RAMCFG_WPR2_P49WP_Msk                   /*!< Write Protection Page 49 */
#define RAMCFG_WPR2_P50WP_Pos      (18U)
#define RAMCFG_WPR2_P50WP_Msk      (0x1UL << RAMCFG_WPR2_P50WP_Pos)        /*!< 0x00040000 */
#define RAMCFG_WPR2_P50WP          RAMCFG_WPR2_P50WP_Msk                   /*!< Write Protection Page 50 */
#define RAMCFG_WPR2_P51WP_Pos      (19U)
#define RAMCFG_WPR2_P51WP_Msk      (0x1UL << RAMCFG_WPR2_P51WP_Pos)        /*!< 0x00080000 */
#define RAMCFG_WPR2_P51WP          RAMCFG_WPR2_P51WP_Msk                   /*!< Write Protection Page 51 */
#define RAMCFG_WPR2_P52WP_Pos      (20U)
#define RAMCFG_WPR2_P52WP_Msk      (0x1UL << RAMCFG_WPR2_P52WP_Pos)        /*!< 0x00100000 */
#define RAMCFG_WPR2_P52WP          RAMCFG_WPR2_P52WP_Msk                   /*!< Write Protection Page 52 */
#define RAMCFG_WPR2_P53WP_Pos      (21U)
#define RAMCFG_WPR2_P53WP_Msk      (0x1UL << RAMCFG_WPR2_P53WP_Pos)        /*!< 0x00200000 */
#define RAMCFG_WPR2_P53WP          RAMCFG_WPR2_P53WP_Msk                   /*!< Write Protection Page 53 */
#define RAMCFG_WPR2_P54WP_Pos      (22U)
#define RAMCFG_WPR2_P54WP_Msk      (0x1UL << RAMCFG_WPR2_P54WP_Pos)        /*!< 0x00400000 */
#define RAMCFG_WPR2_P54WP          RAMCFG_WPR2_P54WP_Msk                   /*!< Write Protection Page 54 */
#define RAMCFG_WPR2_P55WP_Pos      (23U)
#define RAMCFG_WPR2_P55WP_Msk      (0x1UL << RAMCFG_WPR2_P55WP_Pos)        /*!< 0x00800000 */
#define RAMCFG_WPR2_P55WP          RAMCFG_WPR2_P55WP_Msk                   /*!< Write Protection Page 55 */
#define RAMCFG_WPR2_P56WP_Pos      (25U)
#define RAMCFG_WPR2_P56WP_Msk      (0x1UL << RAMCFG_WPR2_P56WP_Pos)        /*!< 0x01000000 */
#define RAMCFG_WPR2_P56WP          RAMCFG_WPR2_P56WP_Msk                   /*!< Write Protection Page 56 */
#define RAMCFG_WPR2_P57WP_Pos      (26U)
#define RAMCFG_WPR2_P57WP_Msk      (0x1UL << RAMCFG_WPR2_P57WP_Pos)        /*!< 0x02000000 */
#define RAMCFG_WPR2_P57WP          RAMCFG_WPR2_P57WP_Msk                   /*!< Write Protection Page 57 */
#define RAMCFG_WPR2_P58WP_Pos      (27U)
#define RAMCFG_WPR2_P58WP_Msk      (0x1UL << RAMCFG_WPR2_P58WP_Pos)        /*!< 0x04000000 */
#define RAMCFG_WPR2_P58WP          RAMCFG_WPR2_P58WP_Msk                   /*!< Write Protection Page 58 */
#define RAMCFG_WPR2_P59WP_Pos      (28U)
#define RAMCFG_WPR2_P59WP_Msk      (0x1UL << RAMCFG_WPR2_P59WP_Pos)        /*!< 0x08000000 */
#define RAMCFG_WPR2_P59WP          RAMCFG_WPR2_P59WP_Msk                   /*!< Write Protection Page 59 */
#define RAMCFG_WPR2_P60WP_Pos      (29U)
#define RAMCFG_WPR2_P60WP_Msk      (0x1UL << RAMCFG_WPR2_P60WP_Pos)        /*!< 0x10000000 */
#define RAMCFG_WPR2_P60WP          RAMCFG_WPR2_P60WP_Msk                   /*!< Write Protection Page 60 */
#define RAMCFG_WPR2_P61WP_Pos      (30U)
#define RAMCFG_WPR2_P61WP_Msk      (0x1UL << RAMCFG_WPR2_P61WP_Pos)        /*!< 0x20000000 */
#define RAMCFG_WPR2_P61WP          RAMCFG_WPR2_P61WP_Msk                   /*!< Write Protection Page 61 */
#define RAMCFG_WPR2_P62WP_Pos      (31U)
#define RAMCFG_WPR2_P62WP_Msk      (0x1UL << RAMCFG_WPR2_P62WP_Pos)        /*!< 0x40000000 */
#define RAMCFG_WPR2_P62WP          RAMCFG_WPR2_P62WP_Msk                   /*!< Write Protection Page 62 */
#define RAMCFG_WPR2_P63WP_Pos      (31U)
#define RAMCFG_WPR2_P63WP_Msk      (0x1UL << RAMCFG_WPR2_P63WP_Pos)        /*!< 0x80000000 */
#define RAMCFG_WPR2_P63WP          RAMCFG_WPR2_P63WP_Msk                   /*!< Write Protection Page 63 */

/* *********************************   Bit definition for RAMCFG_ECCKEYR register   ********************************* */
#define RAMCFG_ECCKEYR_ECCKEY_Pos  (0U)
#define RAMCFG_ECCKEYR_ECCKEY_Msk  (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos)   /*!< 0x000000FF */
#define RAMCFG_ECCKEYR_ECCKEY      RAMCFG_ECCKEYR_ECCKEY_Msk               /*!< ECC write protection key */

/* *********************************   Bit definition for RAMCFG_ERKEYR register   ********************************** */
#define RAMCFG_ERKEYR_ERASEKEY_Pos (0U)
#define RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos)  /*!< 0x000000FF */
#define RAMCFG_ERKEYR_ERASEKEY     RAMCFG_ERKEYR_ERASEKEY_Msk              /*!< Erase write protection key */

/**********************************************************************************************************************/
/*                                                                                                                    */
/*                                           Reset and Clock Control (RCC)                                            */
/*                                                                                                                    */
/**********************************************************************************************************************/
/* *************************************  Bit definition for RCC_CR1 register  ************************************** */
#define RCC_CR1_Rst                   (0x00000022UL)                             /*!< RCC_CR1 reset value */
#define RCC_CR1_HSISON_Pos            (0U)
#define RCC_CR1_HSISON_Msk            (0x1UL << RCC_CR1_HSISON_Pos)              /*!< 0x00000001 */
#define RCC_CR1_HSISON                RCC_CR1_HSISON_Msk                         /*!< HSIS clock enable */
#define RCC_CR1_HSIDIV3ON_Pos         (1U)
#define RCC_CR1_HSIDIV3ON_Msk         (0x1UL << RCC_CR1_HSIDIV3ON_Pos)           /*!< 0x00000002 */
#define RCC_CR1_HSIDIV3ON             RCC_CR1_HSIDIV3ON_Msk                      /*!< HSIDIV3 clock enable */
#define RCC_CR1_HSIKON_Pos            (2U)
#define RCC_CR1_HSIKON_Msk            (0x1UL << RCC_CR1_HSIKON_Pos)              /*!< 0x00000004 */
#define RCC_CR1_HSIKON                RCC_CR1_HSIKON_Msk                         /*!< HSIK clock enable */
#define RCC_CR1_HSIKERON_Pos          (3U)
#define RCC_CR1_HSIKERON_Msk          (0x1UL << RCC_CR1_HSIKERON_Pos)            /*!< 0x00000008 */
#define RCC_CR1_HSIKERON              RCC_CR1_HSIKERON_Msk                       /*!< HSI clock enable in Stop mode */
#define RCC_CR1_HSISRDY_Pos           (4U)
#define RCC_CR1_HSISRDY_Msk           (0x1UL << RCC_CR1_HSISRDY_Pos)             /*!< 0x00000010 */
#define RCC_CR1_HSISRDY               RCC_CR1_HSISRDY_Msk                        /*!< HSIS clock ready flag */
#define RCC_CR1_HSIDIV3RDY_Pos        (5U)
#define RCC_CR1_HSIDIV3RDY_Msk        (0x1UL << RCC_CR1_HSIDIV3RDY_Pos)          /*!< 0x00000020 */
#define RCC_CR1_HSIDIV3RDY            RCC_CR1_HSIDIV3RDY_Msk                     /*!< HSIDIV3 clock ready flag */
#define RCC_CR1_HSIKRDY_Pos           (6U)
#define RCC_CR1_HSIKRDY_Msk           (0x1UL << RCC_CR1_HSIKRDY_Pos)             /*!< 0x00000040 */
#define RCC_CR1_HSIKRDY               RCC_CR1_HSIKRDY_Msk                        /*!< HSIK clock ready flag */
#define RCC_CR1_PSISON_Pos            (8U)
#define RCC_CR1_PSISON_Msk            (0x1UL << RCC_CR1_PSISON_Pos)              /*!< 0x00000100 */
#define RCC_CR1_PSISON                RCC_CR1_PSISON_Msk                         /*!< PSIS clock enable */
#define RCC_CR1_PSIDIV3ON_Pos         (9U)
#define RCC_CR1_PSIDIV3ON_Msk         (0x1UL << RCC_CR1_PSIDIV3ON_Pos)           /*!< 0x00000200 */
#define RCC_CR1_PSIDIV3ON             RCC_CR1_PSIDIV3ON_Msk                      /*!< PSIDIV3 clock enable */
#define RCC_CR1_PSIKON_Pos            (10U)
#define RCC_CR1_PSIKON_Msk            (0x1UL << RCC_CR1_PSIKON_Pos)              /*!< 0x00000400 */
#define RCC_CR1_PSIKON                RCC_CR1_PSIKON_Msk                         /*!< PSIK clock enable */
#define RCC_CR1_PSIKERON_Pos          (11U)
#define RCC_CR1_PSIKERON_Msk          (0x1UL << RCC_CR1_PSIKERON_Pos)            /*!< 0x00000800 */
#define RCC_CR1_PSIKERON              RCC_CR1_PSIKERON_Msk                       /*!< PSI clock enable in Stop mode */
#define RCC_CR1_PSISRDY_Pos           (12U)
#define RCC_CR1_PSISRDY_Msk           (0x1UL << RCC_CR1_PSISRDY_Pos)             /*!< 0x00001000 */
#define RCC_CR1_PSISRDY               RCC_CR1_PSISRDY_Msk                        /*!< PSIS clock ready flag */
#define RCC_CR1_PSIDIV3RDY_Pos        (13U)
#define RCC_CR1_PSIDIV3RDY_Msk        (0x1UL << RCC_CR1_PSIDIV3RDY_Pos)          /*!< 0x00002000 */
#define RCC_CR1_PSIDIV3RDY            RCC_CR1_PSIDIV3RDY_Msk                     /*!< PSIDIV3 clock ready flag */
#define RCC_CR1_PSIKRDY_Pos           (14U)
#define RCC_CR1_PSIKRDY_Msk           (0x1UL << RCC_CR1_PSIKRDY_Pos)             /*!< 0x00004000 */
#define RCC_CR1_PSIKRDY               RCC_CR1_PSIKRDY_Msk                        /*!< PSIK clock ready flag */
#define RCC_CR1_HSEON_Pos             (16U)
#define RCC_CR1_HSEON_Msk             (0x1UL << RCC_CR1_HSEON_Pos)               /*!< 0x00010000 */
#define RCC_CR1_HSEON                 RCC_CR1_HSEON_Msk                          /*!< HSE clock enable */
#define RCC_CR1_HSERDY_Pos            (17U)
#define RCC_CR1_HSERDY_Msk            (0x1UL << RCC_CR1_HSERDY_Pos)              /*!< 0x00020000 */
#define RCC_CR1_HSERDY                RCC_CR1_HSERDY_Msk                         /*!< HSE clock ready flag */
#define RCC_CR1_HSEBYP_Pos            (18U)
#define RCC_CR1_HSEBYP_Msk            (0x1UL << RCC_CR1_HSEBYP_Pos)              /*!< 0x00040000 */
#define RCC_CR1_HSEBYP                RCC_CR1_HSEBYP_Msk                         /*!< HSE clock bypass */
#define RCC_CR1_HSECSSON_Pos          (19U)
#define RCC_CR1_HSECSSON_Msk          (0x1UL << RCC_CR1_HSECSSON_Pos)            /*!< 0x00080000 */
#define RCC_CR1_HSECSSON              RCC_CR1_HSECSSON_Msk                       /*!< HSE clock security system enable
                                                                                      */
#define RCC_CR1_HSEEXT_Pos            (20U)
#define RCC_CR1_HSEEXT_Msk            (0x1UL << RCC_CR1_HSEEXT_Pos)              /*!< 0x00100000 */
#define RCC_CR1_HSEEXT                RCC_CR1_HSEEXT_Msk                         /*!< External high speed clock type in
                                                                                      Bypass mode */

/* *************************************  Bit definition for RCC_CR2 register  ************************************** */
#define RCC_CR2_Rst                   (0x00000000UL)                             /*!< RCC_CR2 reset value */
#define RCC_CR2_HSIKDIV_Pos           (0U)
#define RCC_CR2_HSIKDIV_Msk           (0xFUL << RCC_CR2_HSIKDIV_Pos)             /*!< 0x0000000F */
#define RCC_CR2_HSIKDIV               RCC_CR2_HSIKDIV_Msk                        /*!< HSI clock out divider factor */
#define RCC_CR2_HSIKDIV_0             (0x1UL << RCC_CR2_HSIKDIV_Pos)             /*!< 0x00000001 */
#define RCC_CR2_HSIKDIV_1             (0x2UL << RCC_CR2_HSIKDIV_Pos)             /*!< 0x00000002 */
#define RCC_CR2_HSIKDIV_2             (0x4UL << RCC_CR2_HSIKDIV_Pos)             /*!< 0x00000004 */
#define RCC_CR2_HSIKDIV_3             (0x8UL << RCC_CR2_HSIKDIV_Pos)             /*!< 0x00000008 */
#define RCC_CR2_PSIKDIV_Pos           (8U)
#define RCC_CR2_PSIKDIV_Msk           (0xFUL << RCC_CR2_PSIKDIV_Pos)             /*!< 0x00000F00 */
#define RCC_CR2_PSIKDIV               RCC_CR2_PSIKDIV_Msk                        /*!< PSI clock out divider factor */
#define RCC_CR2_PSIKDIV_0             (0x1UL << RCC_CR2_PSIKDIV_Pos)             /*!< 0x00000100 */
#define RCC_CR2_PSIKDIV_1             (0x2UL << RCC_CR2_PSIKDIV_Pos)             /*!< 0x00000200 */
#define RCC_CR2_PSIKDIV_2             (0x4UL << RCC_CR2_PSIKDIV_Pos)             /*!< 0x00000400 */
#define RCC_CR2_PSIKDIV_3             (0x8UL << RCC_CR2_PSIKDIV_Pos)             /*!< 0x00000800 */
#define RCC_CR2_PSIREFSRC_Pos         (16U)
#define RCC_CR2_PSIREFSRC_Msk         (0x3UL << RCC_CR2_PSIREFSRC_Pos)           /*!< 0x00030000 */
#define RCC_CR2_PSIREFSRC             RCC_CR2_PSIREFSRC_Msk                      /*!< PSI reference clock source
                                                                                      selection */
#define RCC_CR2_PSIREFSRC_0           (0x1UL << RCC_CR2_PSIREFSRC_Pos)           /*!< 0x00010000 */
#define RCC_CR2_PSIREFSRC_1           (0x2UL << RCC_CR2_PSIREFSRC_Pos)           /*!< 0x00020000 */
#define RCC_CR2_PSIREF_Pos            (20U)
#define RCC_CR2_PSIREF_Msk            (0x7UL << RCC_CR2_PSIREF_Pos)              /*!< 0x00700000 */
#define RCC_CR2_PSIREF                RCC_CR2_PSIREF_Msk                         /*!< PSI reference clock frequency
                                                                                      selection */
#define RCC_CR2_PSIREF_0              (0x1UL << RCC_CR2_PSIREF_Pos)              /*!< 0x00100000 */
#define RCC_CR2_PSIREF_1              (0x2UL << RCC_CR2_PSIREF_Pos)              /*!< 0x00200000 */
#define RCC_CR2_PSIREF_2              (0x4UL << RCC_CR2_PSIREF_Pos)              /*!< 0x00400000 */
#define RCC_CR2_PSIFREQ_Pos           (28U)
#define RCC_CR2_PSIFREQ_Msk           (0x3UL << RCC_CR2_PSIFREQ_Pos)             /*!< 0x30000000 */
#define RCC_CR2_PSIFREQ               RCC_CR2_PSIFREQ_Msk                        /*!< PSI target frequency configuration
                                                                                      */
#define RCC_CR2_PSIFREQ_0             (0x1UL << RCC_CR2_PSIFREQ_Pos)             /*!< 0x10000000 */
#define RCC_CR2_PSIFREQ_1             (0x2UL << RCC_CR2_PSIFREQ_Pos)             /*!< 0x20000000 */

/* ************************************  Bit definition for RCC_CFGR1 register  ************************************* */
#define RCC_CFGR1_Rst                 (0x00000000UL)                             /*!< RCC_CFGR1 reset value */
#define RCC_CFGR1_SW_Pos              (0U)
#define RCC_CFGR1_SW_Msk              (0x3UL << RCC_CFGR1_SW_Pos)                /*!< 0x00000003 */
#define RCC_CFGR1_SW                  RCC_CFGR1_SW_Msk                           /*!< System clock and trace clock
                                                                                      switch */
#define RCC_CFGR1_SW_0                (0x1UL << RCC_CFGR1_SW_Pos)                /*!< 0x00000001 */
#define RCC_CFGR1_SW_1                (0x2UL << RCC_CFGR1_SW_Pos)                /*!< 0x00000002 */
#define RCC_CFGR1_SWS_Pos             (3U)
#define RCC_CFGR1_SWS_Msk             (0x3UL << RCC_CFGR1_SWS_Pos)               /*!< 0x00000018 */
#define RCC_CFGR1_SWS                 RCC_CFGR1_SWS_Msk                          /*!< System clock switch status */
#define RCC_CFGR1_SWS_0               (0x1UL << RCC_CFGR1_SWS_Pos)               /*!< 0x00000008 */
#define RCC_CFGR1_SWS_1               (0x2UL << RCC_CFGR1_SWS_Pos)               /*!< 0x00000010 */
#define RCC_CFGR1_STOPWUCK_Pos        (6U)
#define RCC_CFGR1_STOPWUCK_Msk        (0x1UL << RCC_CFGR1_STOPWUCK_Pos)          /*!< 0x00000040 */
#define RCC_CFGR1_STOPWUCK            RCC_CFGR1_STOPWUCK_Msk                     /*!< System clock selection after a
                                                                                      wake-up from system Stop mode */
#define RCC_CFGR1_RTCPRE_Pos          (7U)
#define RCC_CFGR1_RTCPRE_Msk          (0x1FFUL << RCC_CFGR1_RTCPRE_Pos)          /*!< 0x0000FF80 */
#define RCC_CFGR1_RTCPRE              RCC_CFGR1_RTCPRE_Msk                       /*!< HSE division factor for RTC clock
                                                                                      (source of HSE_1MHz clock) */
#define RCC_CFGR1_RTCPRE_0            (0x1UL << RCC_CFGR1_RTCPRE_Pos)            /*!< 0x00000080 */
#define RCC_CFGR1_RTCPRE_1            (0x2UL << RCC_CFGR1_RTCPRE_Pos)            /*!< 0x00000100 */
#define RCC_CFGR1_RTCPRE_2            (0x4UL << RCC_CFGR1_RTCPRE_Pos)            /*!< 0x00000200 */
#define RCC_CFGR1_RTCPRE_3            (0x8UL << RCC_CFGR1_RTCPRE_Pos)            /*!< 0x00000400 */
#define RCC_CFGR1_RTCPRE_4            (0x10UL << RCC_CFGR1_RTCPRE_Pos)           /*!< 0x00000800 */
#define RCC_CFGR1_RTCPRE_5            (0x20UL << RCC_CFGR1_RTCPRE_Pos)           /*!< 0x00001000 */
#define RCC_CFGR1_RTCPRE_6            (0x40UL << RCC_CFGR1_RTCPRE_Pos)           /*!< 0x00002000 */
#define RCC_CFGR1_RTCPRE_7            (0x80UL << RCC_CFGR1_RTCPRE_Pos)           /*!< 0x00004000 */
#define RCC_CFGR1_RTCPRE_8            (0x100UL << RCC_CFGR1_RTCPRE_Pos)          /*!< 0x00008000 */
#define RCC_CFGR1_MCO1PRE_Pos         (18U)
#define RCC_CFGR1_MCO1PRE_Msk         (0xFUL << RCC_CFGR1_MCO1PRE_Pos)           /*!< 0x003C0000 */
#define RCC_CFGR1_MCO1PRE             RCC_CFGR1_MCO1PRE_Msk                      /*!< MCO1 prescaler */
#define RCC_CFGR1_MCO1PRE_0           (0x1UL << RCC_CFGR1_MCO1PRE_Pos)           /*!< 0x00040000 */
#define RCC_CFGR1_MCO1PRE_1           (0x2UL << RCC_CFGR1_MCO1PRE_Pos)           /*!< 0x00080000 */
#define RCC_CFGR1_MCO1PRE_2           (0x4UL << RCC_CFGR1_MCO1PRE_Pos)           /*!< 0x00100000 */
#define RCC_CFGR1_MCO1PRE_3           (0x8UL << RCC_CFGR1_MCO1PRE_Pos)           /*!< 0x00200000 */
#define RCC_CFGR1_MCO1SEL_Pos         (22U)
#define RCC_CFGR1_MCO1SEL_Msk         (0x7UL << RCC_CFGR1_MCO1SEL_Pos)           /*!< 0x01C00000 */
#define RCC_CFGR1_MCO1SEL             RCC_CFGR1_MCO1SEL_Msk                      /*!< Microcontroller clock output 1 */
#define RCC_CFGR1_MCO1SEL_0           (0x1UL << RCC_CFGR1_MCO1SEL_Pos)           /*!< 0x00400000 */
#define RCC_CFGR1_MCO1SEL_1           (0x2UL << RCC_CFGR1_MCO1SEL_Pos)           /*!< 0x00800000 */
#define RCC_CFGR1_MCO1SEL_2           (0x4UL << RCC_CFGR1_MCO1SEL_Pos)           /*!< 0x01000000 */
#define RCC_CFGR1_MCO2PRE_Pos         (25U)
#define RCC_CFGR1_MCO2PRE_Msk         (0xFUL << RCC_CFGR1_MCO2PRE_Pos)           /*!< 0x1E000000 */
#define RCC_CFGR1_MCO2PRE             RCC_CFGR1_MCO2PRE_Msk                      /*!< MCO2 prescaler */
#define RCC_CFGR1_MCO2PRE_0           (0x1UL << RCC_CFGR1_MCO2PRE_Pos)           /*!< 0x02000000 */
#define RCC_CFGR1_MCO2PRE_1           (0x2UL << RCC_CFGR1_MCO2PRE_Pos)           /*!< 0x04000000 */
#define RCC_CFGR1_MCO2PRE_2           (0x4UL << RCC_CFGR1_MCO2PRE_Pos)           /*!< 0x08000000 */
#define RCC_CFGR1_MCO2PRE_3           (0x8UL << RCC_CFGR1_MCO2PRE_Pos)           /*!< 0x10000000 */
#define RCC_CFGR1_MCO2SEL_Pos         (29U)
#define RCC_CFGR1_MCO2SEL_Msk         (0x7UL << RCC_CFGR1_MCO2SEL_Pos)           /*!< 0xE0000000 */
#define RCC_CFGR1_MCO2SEL             RCC_CFGR1_MCO2SEL_Msk                      /*!< Microcontroller clock output 2 */
#define RCC_CFGR1_MCO2SEL_0           (0x1UL << RCC_CFGR1_MCO2SEL_Pos)           /*!< 0x20000000 */
#define RCC_CFGR1_MCO2SEL_1           (0x2UL << RCC_CFGR1_MCO2SEL_Pos)           /*!< 0x40000000 */
#define RCC_CFGR1_MCO2SEL_2           (0x4UL << RCC_CFGR1_MCO2SEL_Pos)           /*!< 0x80000000 */

/* ************************************  Bit definition for RCC_CFGR2 register  ************************************* */
#define RCC_CFGR2_Rst                 (0x00000000UL)                             /*!< RCC_CFGR2 reset value */
#define RCC_CFGR2_HPRE_Pos            (0U)
#define RCC_CFGR2_HPRE_Msk            (0xFUL << RCC_CFGR2_HPRE_Pos)              /*!< 0x0000000F */
#define RCC_CFGR2_HPRE                RCC_CFGR2_HPRE_Msk                         /*!< AHB prescaler */
#define RCC_CFGR2_HPRE_0              (0x1UL << RCC_CFGR2_HPRE_Pos)              /*!< 0x00000001 */
#define RCC_CFGR2_HPRE_1              (0x2UL << RCC_CFGR2_HPRE_Pos)              /*!< 0x00000002 */
#define RCC_CFGR2_HPRE_2              (0x4UL << RCC_CFGR2_HPRE_Pos)              /*!< 0x00000004 */
#define RCC_CFGR2_HPRE_3              (0x8UL << RCC_CFGR2_HPRE_Pos)              /*!< 0x00000008 */
#define RCC_CFGR2_PPRE1_Pos           (4U)
#define RCC_CFGR2_PPRE1_Msk           (0x7UL << RCC_CFGR2_PPRE1_Pos)             /*!< 0x00000070 */
#define RCC_CFGR2_PPRE1               RCC_CFGR2_PPRE1_Msk                        /*!< APB low-speed prescaler (APB1) */
#define RCC_CFGR2_PPRE1_0             (0x1UL << RCC_CFGR2_PPRE1_Pos)             /*!< 0x00000010 */
#define RCC_CFGR2_PPRE1_1             (0x2UL << RCC_CFGR2_PPRE1_Pos)             /*!< 0x00000020 */
#define RCC_CFGR2_PPRE1_2             (0x4UL << RCC_CFGR2_PPRE1_Pos)             /*!< 0x00000040 */
#define RCC_CFGR2_PPRE2_Pos           (8U)
#define RCC_CFGR2_PPRE2_Msk           (0x7UL << RCC_CFGR2_PPRE2_Pos)             /*!< 0x00000700 */
#define RCC_CFGR2_PPRE2               RCC_CFGR2_PPRE2_Msk                        /*!< APB high-speed prescaler (APB2) */
#define RCC_CFGR2_PPRE2_0             (0x1UL << RCC_CFGR2_PPRE2_Pos)             /*!< 0x00000100 */
#define RCC_CFGR2_PPRE2_1             (0x2UL << RCC_CFGR2_PPRE2_Pos)             /*!< 0x00000200 */
#define RCC_CFGR2_PPRE2_2             (0x4UL << RCC_CFGR2_PPRE2_Pos)             /*!< 0x00000400 */
#define RCC_CFGR2_PPRE3_Pos           (12U)
#define RCC_CFGR2_PPRE3_Msk           (0x7UL << RCC_CFGR2_PPRE3_Pos)             /*!< 0x00007000 */
#define RCC_CFGR2_PPRE3               RCC_CFGR2_PPRE3_Msk                        /*!< APB low-speed prescaler (APB3) */
#define RCC_CFGR2_PPRE3_0             (0x1UL << RCC_CFGR2_PPRE3_Pos)             /*!< 0x00001000 */
#define RCC_CFGR2_PPRE3_1             (0x2UL << RCC_CFGR2_PPRE3_Pos)             /*!< 0x00002000 */
#define RCC_CFGR2_PPRE3_2             (0x4UL << RCC_CFGR2_PPRE3_Pos)             /*!< 0x00004000 */
#define RCC_CFGR2_AHB1DIS_Pos         (16U)
#define RCC_CFGR2_AHB1DIS_Msk         (0x1UL << RCC_CFGR2_AHB1DIS_Pos)           /*!< 0x00010000 */
#define RCC_CFGR2_AHB1DIS             RCC_CFGR2_AHB1DIS_Msk                      /*!< AHB1 clock disable */
#define RCC_CFGR2_AHB2DIS_Pos         (17U)
#define RCC_CFGR2_AHB2DIS_Msk         (0x1UL << RCC_CFGR2_AHB2DIS_Pos)           /*!< 0x00020000 */
#define RCC_CFGR2_AHB2DIS             RCC_CFGR2_AHB2DIS_Msk                      /*!< AHB2 clock disable */
#define RCC_CFGR2_APB1DIS_Pos         (20U)
#define RCC_CFGR2_APB1DIS_Msk         (0x1UL << RCC_CFGR2_APB1DIS_Pos)           /*!< 0x00100000 */
#define RCC_CFGR2_APB1DIS             RCC_CFGR2_APB1DIS_Msk                      /*!< APB1 clock disable value */
#define RCC_CFGR2_APB2DIS_Pos         (21U)
#define RCC_CFGR2_APB2DIS_Msk         (0x1UL << RCC_CFGR2_APB2DIS_Pos)           /*!< 0x00200000 */
#define RCC_CFGR2_APB2DIS             RCC_CFGR2_APB2DIS_Msk                      /*!< APB2 clock disable value */
#define RCC_CFGR2_APB3DIS_Pos         (22U)
#define RCC_CFGR2_APB3DIS_Msk         (0x1UL << RCC_CFGR2_APB3DIS_Pos)           /*!< 0x00400000 */
#define RCC_CFGR2_APB3DIS             RCC_CFGR2_APB3DIS_Msk                      /*!< APB3 clock disable value.Set and
                                                                                      cleared by software */

/* *************************************  Bit definition for RCC_CIER register  ************************************* */
#define RCC_CIER_Rst                  (0x00000000UL)                             /*!< RCC_CIER reset value */
#define RCC_CIER_LSIRDYIE_Pos         (0U)
#define RCC_CIER_LSIRDYIE_Msk         (0x1UL << RCC_CIER_LSIRDYIE_Pos)           /*!< 0x00000001 */
#define RCC_CIER_LSIRDYIE             RCC_CIER_LSIRDYIE_Msk                      /*!< LSI ready interrupt enable */
#define RCC_CIER_LSERDYIE_Pos         (1U)
#define RCC_CIER_LSERDYIE_Msk         (0x1UL << RCC_CIER_LSERDYIE_Pos)           /*!< 0x00000002 */
#define RCC_CIER_LSERDYIE             RCC_CIER_LSERDYIE_Msk                      /*!< LSE ready interrupt enable */
#define RCC_CIER_HSISRDYIE_Pos        (2U)
#define RCC_CIER_HSISRDYIE_Msk        (0x1UL << RCC_CIER_HSISRDYIE_Pos)          /*!< 0x00000004 */
#define RCC_CIER_HSISRDYIE            RCC_CIER_HSISRDYIE_Msk                     /*!< HSIS ready interrupt enable */
#define RCC_CIER_HSIDIV3RDYIE_Pos     (3U)
#define RCC_CIER_HSIDIV3RDYIE_Msk     (0x1UL << RCC_CIER_HSIDIV3RDYIE_Pos)       /*!< 0x00000008 */
#define RCC_CIER_HSIDIV3RDYIE         RCC_CIER_HSIDIV3RDYIE_Msk                  /*!< HSIDIV3 ready interrupt enable */
#define RCC_CIER_HSIKRDYIE_Pos        (4U)
#define RCC_CIER_HSIKRDYIE_Msk        (0x1UL << RCC_CIER_HSIKRDYIE_Pos)          /*!< 0x00000010 */
#define RCC_CIER_HSIKRDYIE            RCC_CIER_HSIKRDYIE_Msk                     /*!< HSIK ready interrupt enable */
#define RCC_CIER_PSISRDYIE_Pos        (5U)
#define RCC_CIER_PSISRDYIE_Msk        (0x1UL << RCC_CIER_PSISRDYIE_Pos)          /*!< 0x00000020 */
#define RCC_CIER_PSISRDYIE            RCC_CIER_PSISRDYIE_Msk                     /*!< PSIS ready interrupt enable */
#define RCC_CIER_PSIDIV3RDYIE_Pos     (6U)
#define RCC_CIER_PSIDIV3RDYIE_Msk     (0x1UL << RCC_CIER_PSIDIV3RDYIE_Pos)       /*!< 0x00000040 */
#define RCC_CIER_PSIDIV3RDYIE         RCC_CIER_PSIDIV3RDYIE_Msk                  /*!< PSIDIV3 ready interrupt enable */
#define RCC_CIER_PSIKRDYIE_Pos        (7U)
#define RCC_CIER_PSIKRDYIE_Msk        (0x1UL << RCC_CIER_PSIKRDYIE_Pos)          /*!< 0x00000080 */
#define RCC_CIER_PSIKRDYIE            RCC_CIER_PSIKRDYIE_Msk                     /*!< PSIK ready interrupt enable */
#define RCC_CIER_HSERDYIE_Pos         (8U)
#define RCC_CIER_HSERDYIE_Msk         (0x1UL << RCC_CIER_HSERDYIE_Pos)           /*!< 0x00000100 */
#define RCC_CIER_HSERDYIE             RCC_CIER_HSERDYIE_Msk                      /*!< HSE ready interrupt enable */

/* *************************************  Bit definition for RCC_CIFR register  ************************************* */
#define RCC_CIFR_LSIRDYF_Pos          (0U)
#define RCC_CIFR_LSIRDYF_Msk          (0x1UL << RCC_CIFR_LSIRDYF_Pos)            /*!< 0x00000001 */
#define RCC_CIFR_LSIRDYF              RCC_CIFR_LSIRDYF_Msk                       /*!< LSI ready interrupt flag */
#define RCC_CIFR_LSERDYF_Pos          (1U)
#define RCC_CIFR_LSERDYF_Msk          (0x1UL << RCC_CIFR_LSERDYF_Pos)            /*!< 0x00000002 */
#define RCC_CIFR_LSERDYF              RCC_CIFR_LSERDYF_Msk                       /*!< LSE ready interrupt flag */
#define RCC_CIFR_HSISRDYF_Pos         (2U)
#define RCC_CIFR_HSISRDYF_Msk         (0x1UL << RCC_CIFR_HSISRDYF_Pos)           /*!< 0x00000004 */
#define RCC_CIFR_HSISRDYF             RCC_CIFR_HSISRDYF_Msk                      /*!< HSIS ready interrupt flag */
#define RCC_CIFR_HSIDIV3RDYF_Pos      (3U)
#define RCC_CIFR_HSIDIV3RDYF_Msk      (0x1UL << RCC_CIFR_HSIDIV3RDYF_Pos)        /*!< 0x00000008 */
#define RCC_CIFR_HSIDIV3RDYF          RCC_CIFR_HSIDIV3RDYF_Msk                   /*!< HSIDIV3 ready interrupt flag */
#define RCC_CIFR_HSIKRDYF_Pos         (4U)
#define RCC_CIFR_HSIKRDYF_Msk         (0x1UL << RCC_CIFR_HSIKRDYF_Pos)           /*!< 0x00000010 */
#define RCC_CIFR_HSIKRDYF             RCC_CIFR_HSIKRDYF_Msk                      /*!< HSIK ready interrupt flag */
#define RCC_CIFR_PSISRDYF_Pos         (5U)
#define RCC_CIFR_PSISRDYF_Msk         (0x1UL << RCC_CIFR_PSISRDYF_Pos)           /*!< 0x00000020 */
#define RCC_CIFR_PSISRDYF             RCC_CIFR_PSISRDYF_Msk                      /*!< PSIS ready interrupt flag */
#define RCC_CIFR_PSIDIV3RDYF_Pos      (6U)
#define RCC_CIFR_PSIDIV3RDYF_Msk      (0x1UL << RCC_CIFR_PSIDIV3RDYF_Pos)        /*!< 0x00000040 */
#define RCC_CIFR_PSIDIV3RDYF          RCC_CIFR_PSIDIV3RDYF_Msk                   /*!< PSIDIV3 ready interrupt flag */
#define RCC_CIFR_PSIKRDYF_Pos         (7U)
#define RCC_CIFR_PSIKRDYF_Msk         (0x1UL << RCC_CIFR_PSIKRDYF_Pos)           /*!< 0x00000080 */
#define RCC_CIFR_PSIKRDYF             RCC_CIFR_PSIKRDYF_Msk                      /*!< PSIK ready interrupt flag */
#define RCC_CIFR_HSERDYF_Pos          (8U)
#define RCC_CIFR_HSERDYF_Msk          (0x1UL << RCC_CIFR_HSERDYF_Pos)            /*!< 0x00000100 */
#define RCC_CIFR_HSERDYF              RCC_CIFR_HSERDYF_Msk                       /*!< HSE ready interrupt flag */
#define RCC_CIFR_HSECSSF_Pos          (10U)
#define RCC_CIFR_HSECSSF_Msk          (0x1UL << RCC_CIFR_HSECSSF_Pos)            /*!< 0x00000400 */
#define RCC_CIFR_HSECSSF              RCC_CIFR_HSECSSF_Msk                       /*!< HSE clock security system
                                                                                      interrupt flag */
#define RCC_CIFR_LSECSSF_Pos          (11U)
#define RCC_CIFR_LSECSSF_Msk          (0x1UL << RCC_CIFR_LSECSSF_Pos)            /*!< 0x00000800 */
#define RCC_CIFR_LSECSSF              RCC_CIFR_LSECSSF_Msk                       /*!< LSE clock security system
                                                                                      interrupt flag */

/* *************************************  Bit definition for RCC_CICR register  ************************************* */
#define RCC_CICR_Rst                  (0x00000000UL)                             /*!< RCC_CICR reset value */
#define RCC_CICR_LSIRDYC_Pos          (0U)
#define RCC_CICR_LSIRDYC_Msk          (0x1UL << RCC_CICR_LSIRDYC_Pos)            /*!< 0x00000001 */
#define RCC_CICR_LSIRDYC              RCC_CICR_LSIRDYC_Msk                       /*!< LSI ready interrupt clear */
#define RCC_CICR_LSERDYC_Pos          (1U)
#define RCC_CICR_LSERDYC_Msk          (0x1UL << RCC_CICR_LSERDYC_Pos)            /*!< 0x00000002 */
#define RCC_CICR_LSERDYC              RCC_CICR_LSERDYC_Msk                       /*!< LSE ready interrupt clear */
#define RCC_CICR_HSISRDYC_Pos         (2U)
#define RCC_CICR_HSISRDYC_Msk         (0x1UL << RCC_CICR_HSISRDYC_Pos)           /*!< 0x00000004 */
#define RCC_CICR_HSISRDYC             RCC_CICR_HSISRDYC_Msk                      /*!< HSIS ready interrupt clear */
#define RCC_CICR_HSIDIV3RDYC_Pos      (3U)
#define RCC_CICR_HSIDIV3RDYC_Msk      (0x1UL << RCC_CICR_HSIDIV3RDYC_Pos)        /*!< 0x00000008 */
#define RCC_CICR_HSIDIV3RDYC          RCC_CICR_HSIDIV3RDYC_Msk                   /*!< HSIDIV3 ready interrupt clear */
#define RCC_CICR_HSIKRDYC_Pos         (4U)
#define RCC_CICR_HSIKRDYC_Msk         (0x1UL << RCC_CICR_HSIKRDYC_Pos)           /*!< 0x00000010 */
#define RCC_CICR_HSIKRDYC             RCC_CICR_HSIKRDYC_Msk                      /*!< HSIK ready interrupt clear */
#define RCC_CICR_PSISRDYC_Pos         (5U)
#define RCC_CICR_PSISRDYC_Msk         (0x1UL << RCC_CICR_PSISRDYC_Pos)           /*!< 0x00000020 */
#define RCC_CICR_PSISRDYC             RCC_CICR_PSISRDYC_Msk                      /*!< PSIS ready interrupt clear */
#define RCC_CICR_PSIDIV3RDYC_Pos      (6U)
#define RCC_CICR_PSIDIV3RDYC_Msk      (0x1UL << RCC_CICR_PSIDIV3RDYC_Pos)        /*!< 0x00000040 */
#define RCC_CICR_PSIDIV3RDYC          RCC_CICR_PSIDIV3RDYC_Msk                   /*!< PSIDIV3 ready interrupt clear */
#define RCC_CICR_PSIKRDYC_Pos         (7U)
#define RCC_CICR_PSIKRDYC_Msk         (0x1UL << RCC_CICR_PSIKRDYC_Pos)           /*!< 0x00000080 */
#define RCC_CICR_PSIKRDYC             RCC_CICR_PSIKRDYC_Msk                      /*!< PSIK ready interrupt clear */
#define RCC_CICR_HSERDYC_Pos          (8U)
#define RCC_CICR_HSERDYC_Msk          (0x1UL << RCC_CICR_HSERDYC_Pos)            /*!< 0x00000100 */
#define RCC_CICR_HSERDYC              RCC_CICR_HSERDYC_Msk                       /*!< HSE ready interrupt clear */
#define RCC_CICR_HSECSSC_Pos          (10U)
#define RCC_CICR_HSECSSC_Msk          (0x1UL << RCC_CICR_HSECSSC_Pos)            /*!< 0x00000400 */
#define RCC_CICR_HSECSSC              RCC_CICR_HSECSSC_Msk                       /*!< HSE clock security system
                                                                                      interrupt clear */
#define RCC_CICR_LSECSSC_Pos          (11U)
#define RCC_CICR_LSECSSC_Msk          (0x1UL << RCC_CICR_LSECSSC_Pos)            /*!< 0x00000800 */
#define RCC_CICR_LSECSSC              RCC_CICR_LSECSSC_Msk                       /*!< LSE clock security system
                                                                                      interrupt clear */

/* ***********************************  Bit definition for RCC_AHB1RSTR register  *********************************** */
#define RCC_AHB1RSTR_Rst              (0x00000000UL)                             /*!< RCC_AHB1RSTR reset value */
#define RCC_AHB1RSTR_LPDMA1RST_Pos    (0U)
#define RCC_AHB1RSTR_LPDMA1RST_Msk    (0x1UL << RCC_AHB1RSTR_LPDMA1RST_Pos)      /*!< 0x00000001 */
#define RCC_AHB1RSTR_LPDMA1RST        RCC_AHB1RSTR_LPDMA1RST_Msk                 /*!< LPDMA1 reset */
#define RCC_AHB1RSTR_LPDMA2RST_Pos    (1U)
#define RCC_AHB1RSTR_LPDMA2RST_Msk    (0x1UL << RCC_AHB1RSTR_LPDMA2RST_Pos)      /*!< 0x00000002 */
#define RCC_AHB1RSTR_LPDMA2RST        RCC_AHB1RSTR_LPDMA2RST_Msk                 /*!< LPDMA2 reset */
#define RCC_AHB1RSTR_CRCRST_Pos       (12U)
#define RCC_AHB1RSTR_CRCRST_Msk       (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)         /*!< 0x00001000 */
#define RCC_AHB1RSTR_CRCRST           RCC_AHB1RSTR_CRCRST_Msk                    /*!< CRC reset */
#define RCC_AHB1RSTR_CORDICRST_Pos    (14U)
#define RCC_AHB1RSTR_CORDICRST_Msk    (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos)      /*!< 0x00004000 */
#define RCC_AHB1RSTR_CORDICRST        RCC_AHB1RSTR_CORDICRST_Msk                 /*!< CORDIC reset */
#define RCC_AHB1RSTR_RAMCFGRST_Pos    (17U)
#define RCC_AHB1RSTR_RAMCFGRST_Msk    (0x1UL << RCC_AHB1RSTR_RAMCFGRST_Pos)      /*!< 0x00020000 */
#define RCC_AHB1RSTR_RAMCFGRST        RCC_AHB1RSTR_RAMCFGRST_Msk                 /*!< RAMCFG reset */

/* ***********************************  Bit definition for RCC_AHB2RSTR register  *********************************** */
#define RCC_AHB2RSTR_Rst              (0x00000000UL)                             /*!< RCC_AHB2RSTR reset value */
#define RCC_AHB2RSTR_GPIOARST_Pos     (0U)
#define RCC_AHB2RSTR_GPIOARST_Msk     (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)       /*!< 0x00000001 */
#define RCC_AHB2RSTR_GPIOARST         RCC_AHB2RSTR_GPIOARST_Msk                  /*!< GPIOA reset */
#define RCC_AHB2RSTR_GPIOBRST_Pos     (1U)
#define RCC_AHB2RSTR_GPIOBRST_Msk     (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)       /*!< 0x00000002 */
#define RCC_AHB2RSTR_GPIOBRST         RCC_AHB2RSTR_GPIOBRST_Msk                  /*!< GPIOB reset */
#define RCC_AHB2RSTR_GPIOCRST_Pos     (2U)
#define RCC_AHB2RSTR_GPIOCRST_Msk     (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)       /*!< 0x00000004 */
#define RCC_AHB2RSTR_GPIOCRST         RCC_AHB2RSTR_GPIOCRST_Msk                  /*!< GPIOC reset */
#define RCC_AHB2RSTR_GPIODRST_Pos     (3U)
#define RCC_AHB2RSTR_GPIODRST_Msk     (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)       /*!< 0x00000008 */
#define RCC_AHB2RSTR_GPIODRST         RCC_AHB2RSTR_GPIODRST_Msk                  /*!< GPIOD reset */
#define RCC_AHB2RSTR_GPIOERST_Pos     (4U)
#define RCC_AHB2RSTR_GPIOERST_Msk     (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)       /*!< 0x00000010 */
#define RCC_AHB2RSTR_GPIOERST         RCC_AHB2RSTR_GPIOERST_Msk                  /*!< GPIOE reset */
#define RCC_AHB2RSTR_GPIOHRST_Pos     (7U)
#define RCC_AHB2RSTR_GPIOHRST_Msk     (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */
#define RCC_AHB2RSTR_GPIOHRST         RCC_AHB2RSTR_GPIOHRST_Msk                  /*!< GPIOH reset */
#define RCC_AHB2RSTR_ADC12RST_Pos     (10U)
#define RCC_AHB2RSTR_ADC12RST_Msk     (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos)       /*!< 0x00000400 */
#define RCC_AHB2RSTR_ADC12RST         RCC_AHB2RSTR_ADC12RST_Msk                  /*!< ADC1 and ADC2 reset */
#define RCC_AHB2RSTR_DAC1RST_Pos      (11U)
#define RCC_AHB2RSTR_DAC1RST_Msk      (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos)        /*!< 0x00000800 */
#define RCC_AHB2RSTR_DAC1RST          RCC_AHB2RSTR_DAC1RST_Msk                   /*!< DAC reset */
#define RCC_AHB2RSTR_AESRST_Pos       (16U)
#define RCC_AHB2RSTR_AESRST_Msk       (0x1UL << RCC_AHB2RSTR_AESRST_Pos)         /*!< 0x00010000 */
#define RCC_AHB2RSTR_AESRST           RCC_AHB2RSTR_AESRST_Msk                    /*!< AES reset */
#define RCC_AHB2RSTR_HASHRST_Pos      (17U)
#define RCC_AHB2RSTR_HASHRST_Msk      (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)        /*!< 0x00020000 */
#define RCC_AHB2RSTR_HASHRST          RCC_AHB2RSTR_HASHRST_Msk                   /*!< HASH reset */
#define RCC_AHB2RSTR_RNGRST_Pos       (18U)
#define RCC_AHB2RSTR_RNGRST_Msk       (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)         /*!< 0x00040000 */
#define RCC_AHB2RSTR_RNGRST           RCC_AHB2RSTR_RNGRST_Msk                    /*!< RNG reset */

/* **********************************  Bit definition for RCC_APB1LRSTR register  *********************************** */
#define RCC_APB1LRSTR_Rst             (0x00000000UL)                             /*!< RCC_APB1LRSTR reset value */
#define RCC_APB1LRSTR_TIM2RST_Pos     (0U)
#define RCC_APB1LRSTR_TIM2RST_Msk     (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos)       /*!< 0x00000001 */
#define RCC_APB1LRSTR_TIM2RST         RCC_APB1LRSTR_TIM2RST_Msk                  /*!< TIM2 reset */
#define RCC_APB1LRSTR_TIM5RST_Pos     (3U)
#define RCC_APB1LRSTR_TIM5RST_Msk     (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos)       /*!< 0x00000008 */
#define RCC_APB1LRSTR_TIM5RST         RCC_APB1LRSTR_TIM5RST_Msk                  /*!< TIM5 reset */
#define RCC_APB1LRSTR_TIM6RST_Pos     (4U)
#define RCC_APB1LRSTR_TIM6RST_Msk     (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos)       /*!< 0x00000010 */
#define RCC_APB1LRSTR_TIM6RST         RCC_APB1LRSTR_TIM6RST_Msk                  /*!< TIM6 reset */
#define RCC_APB1LRSTR_TIM7RST_Pos     (5U)
#define RCC_APB1LRSTR_TIM7RST_Msk     (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos)       /*!< 0x00000020 */
#define RCC_APB1LRSTR_TIM7RST         RCC_APB1LRSTR_TIM7RST_Msk                  /*!< TIM7 reset */
#define RCC_APB1LRSTR_TIM12RST_Pos    (6U)
#define RCC_APB1LRSTR_TIM12RST_Msk    (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos)      /*!< 0x00000040 */
#define RCC_APB1LRSTR_TIM12RST        RCC_APB1LRSTR_TIM12RST_Msk                 /*!< TIM12 reset */
#define RCC_APB1LRSTR_OPAMP1RST_Pos   (13U)
#define RCC_APB1LRSTR_OPAMP1RST_Msk   (0x1UL << RCC_APB1LRSTR_OPAMP1RST_Pos)     /*!< 0x00002000 */
#define RCC_APB1LRSTR_OPAMP1RST       RCC_APB1LRSTR_OPAMP1RST_Msk                /*!< OPAMP1 reset */
#define RCC_APB1LRSTR_SPI2RST_Pos     (14U)
#define RCC_APB1LRSTR_SPI2RST_Msk     (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos)       /*!< 0x00004000 */
#define RCC_APB1LRSTR_SPI2RST         RCC_APB1LRSTR_SPI2RST_Msk                  /*!< SPI2 reset */
#define RCC_APB1LRSTR_SPI3RST_Pos     (15U)
#define RCC_APB1LRSTR_SPI3RST_Msk     (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos)       /*!< 0x00008000 */
#define RCC_APB1LRSTR_SPI3RST         RCC_APB1LRSTR_SPI3RST_Msk                  /*!< SPI3 reset */
#define RCC_APB1LRSTR_USART2RST_Pos   (17U)
#define RCC_APB1LRSTR_USART2RST_Msk   (0x1UL << RCC_APB1LRSTR_USART2RST_Pos)     /*!< 0x00020000 */
#define RCC_APB1LRSTR_USART2RST       RCC_APB1LRSTR_USART2RST_Msk                /*!< USART2 reset */
#define RCC_APB1LRSTR_USART3RST_Pos   (18U)
#define RCC_APB1LRSTR_USART3RST_Msk   (0x1UL << RCC_APB1LRSTR_USART3RST_Pos)     /*!< 0x00040000 */
#define RCC_APB1LRSTR_USART3RST       RCC_APB1LRSTR_USART3RST_Msk                /*!< USART3 reset */
#define RCC_APB1LRSTR_UART4RST_Pos    (19U)
#define RCC_APB1LRSTR_UART4RST_Msk    (0x1UL << RCC_APB1LRSTR_UART4RST_Pos)      /*!< 0x00080000 */
#define RCC_APB1LRSTR_UART4RST        RCC_APB1LRSTR_UART4RST_Msk                 /*!< UART4 reset */
#define RCC_APB1LRSTR_UART5RST_Pos    (20U)
#define RCC_APB1LRSTR_UART5RST_Msk    (0x1UL << RCC_APB1LRSTR_UART5RST_Pos)      /*!< 0x00100000 */
#define RCC_APB1LRSTR_UART5RST        RCC_APB1LRSTR_UART5RST_Msk                 /*!< UART5 reset */
#define RCC_APB1LRSTR_I2C1RST_Pos     (21U)
#define RCC_APB1LRSTR_I2C1RST_Msk     (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos)       /*!< 0x00200000 */
#define RCC_APB1LRSTR_I2C1RST         RCC_APB1LRSTR_I2C1RST_Msk                  /*!< I2C1 reset */
#define RCC_APB1LRSTR_I2C2RST_Pos     (22U)
#define RCC_APB1LRSTR_I2C2RST_Msk     (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos)       /*!< 0x00400000 */
#define RCC_APB1LRSTR_I2C2RST         RCC_APB1LRSTR_I2C2RST_Msk                  /*!< I2C2 reset */
#define RCC_APB1LRSTR_I3C1RST_Pos     (23U)
#define RCC_APB1LRSTR_I3C1RST_Msk     (0x1UL << RCC_APB1LRSTR_I3C1RST_Pos)       /*!< 0x00800000 */
#define RCC_APB1LRSTR_I3C1RST         RCC_APB1LRSTR_I3C1RST_Msk                  /*!< I3C1 block reset */
#define RCC_APB1LRSTR_CRSRST_Pos      (24U)
#define RCC_APB1LRSTR_CRSRST_Msk      (0x1UL << RCC_APB1LRSTR_CRSRST_Pos)        /*!< 0x01000000 */
#define RCC_APB1LRSTR_CRSRST          RCC_APB1LRSTR_CRSRST_Msk                   /*!< CRS reset */

/* **********************************  Bit definition for RCC_APB1HRSTR register  *********************************** */
#define RCC_APB1HRSTR_Rst             (0x00000000UL)                             /*!< RCC_APB1HRSTR reset value */
#define RCC_APB1HRSTR_COMP12RST_Pos   (3U)
#define RCC_APB1HRSTR_COMP12RST_Msk   (0x1UL << RCC_APB1HRSTR_COMP12RST_Pos)     /*!< 0x00000008 */
#define RCC_APB1HRSTR_COMP12RST       RCC_APB1HRSTR_COMP12RST_Msk                /*!< COMP1 and COMP2 reset */
#define RCC_APB1HRSTR_FDCANRST_Pos    (9U)
#define RCC_APB1HRSTR_FDCANRST_Msk    (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos)      /*!< 0x00000200 */
#define RCC_APB1HRSTR_FDCANRST        RCC_APB1HRSTR_FDCANRST_Msk                 /*!< FDCAN1 reset */

/* ***********************************  Bit definition for RCC_APB2RSTR register  *********************************** */
#define RCC_APB2RSTR_Rst              (0x00000000UL)                             /*!< RCC_APB2RSTR reset value */
#define RCC_APB2RSTR_TIM1RST_Pos      (11U)
#define RCC_APB2RSTR_TIM1RST_Msk      (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)        /*!< 0x00000800 */
#define RCC_APB2RSTR_TIM1RST          RCC_APB2RSTR_TIM1RST_Msk                   /*!< TIM1 reset */
#define RCC_APB2RSTR_SPI1RST_Pos      (12U)
#define RCC_APB2RSTR_SPI1RST_Msk      (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)        /*!< 0x00001000 */
#define RCC_APB2RSTR_SPI1RST          RCC_APB2RSTR_SPI1RST_Msk                   /*!< SPI1 reset */
#define RCC_APB2RSTR_TIM8RST_Pos      (13U)
#define RCC_APB2RSTR_TIM8RST_Msk      (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)        /*!< 0x00002000 */
#define RCC_APB2RSTR_TIM8RST          RCC_APB2RSTR_TIM8RST_Msk                   /*!< TIM8 reset */
#define RCC_APB2RSTR_USART1RST_Pos    (14U)
#define RCC_APB2RSTR_USART1RST_Msk    (0x1UL << RCC_APB2RSTR_USART1RST_Pos)      /*!< 0x00004000 */
#define RCC_APB2RSTR_USART1RST        RCC_APB2RSTR_USART1RST_Msk                 /*!< USART1 reset */
#define RCC_APB2RSTR_TIM15RST_Pos     (16U)
#define RCC_APB2RSTR_TIM15RST_Msk     (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)       /*!< 0x00010000 */
#define RCC_APB2RSTR_TIM15RST         RCC_APB2RSTR_TIM15RST_Msk                  /*!< TIM15 reset */
#define RCC_APB2RSTR_TIM16RST_Pos     (17U)
#define RCC_APB2RSTR_TIM16RST_Msk     (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)       /*!< 0x00020000 */
#define RCC_APB2RSTR_TIM16RST         RCC_APB2RSTR_TIM16RST_Msk                  /*!< TIM16 reset */
#define RCC_APB2RSTR_TIM17RST_Pos     (18U)
#define RCC_APB2RSTR_TIM17RST_Msk     (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)       /*!< 0x00040000 */
#define RCC_APB2RSTR_TIM17RST         RCC_APB2RSTR_TIM17RST_Msk                  /*!< TIM17 reset */
#define RCC_APB2RSTR_USBRST_Pos       (24U)
#define RCC_APB2RSTR_USBRST_Msk       (0x1UL << RCC_APB2RSTR_USBRST_Pos)         /*!< 0x01000000 */
#define RCC_APB2RSTR_USBRST           RCC_APB2RSTR_USBRST_Msk                    /*!< USBRST (USB block reset) */

/* ***********************************  Bit definition for RCC_APB3RSTR register  *********************************** */
#define RCC_APB3RSTR_Rst              (0x00000000UL)                             /*!< RCC_APB3RSTR reset value */
#define RCC_APB3RSTR_SBSRST_Pos       (1U)
#define RCC_APB3RSTR_SBSRST_Msk       (0x1UL << RCC_APB3RSTR_SBSRST_Pos)         /*!< 0x00000002 */
#define RCC_APB3RSTR_SBSRST           RCC_APB3RSTR_SBSRST_Msk                    /*!< SBS reset */
#define RCC_APB3RSTR_LPUART1RST_Pos   (6U)
#define RCC_APB3RSTR_LPUART1RST_Msk   (0x1UL << RCC_APB3RSTR_LPUART1RST_Pos)     /*!< 0x00000040 */
#define RCC_APB3RSTR_LPUART1RST       RCC_APB3RSTR_LPUART1RST_Msk                /*!< LPUART1 reset */
#define RCC_APB3RSTR_LPTIM1RST_Pos    (11U)
#define RCC_APB3RSTR_LPTIM1RST_Msk    (0x1UL << RCC_APB3RSTR_LPTIM1RST_Pos)      /*!< 0x00000800 */
#define RCC_APB3RSTR_LPTIM1RST        RCC_APB3RSTR_LPTIM1RST_Msk                 /*!< LPTIM1RST (LPTIM1 block reset) */

/* ***********************************  Bit definition for RCC_AHB1ENR register  ************************************ */
#define RCC_AHB1ENR_Rst               (0xC0000100UL)                             /*!< RCC_AHB1ENR reset value */
#define RCC_AHB1ENR_LPDMA1EN_Pos      (0U)
#define RCC_AHB1ENR_LPDMA1EN_Msk      (0x1UL << RCC_AHB1ENR_LPDMA1EN_Pos)        /*!< 0x00000001 */
#define RCC_AHB1ENR_LPDMA1EN          RCC_AHB1ENR_LPDMA1EN_Msk                   /*!< LPDMA1 clock enable */
#define RCC_AHB1ENR_LPDMA2EN_Pos      (1U)
#define RCC_AHB1ENR_LPDMA2EN_Msk      (0x1UL << RCC_AHB1ENR_LPDMA2EN_Pos)        /*!< 0x00000002 */
#define RCC_AHB1ENR_LPDMA2EN          RCC_AHB1ENR_LPDMA2EN_Msk                   /*!< LPDMA2 clock enable */
#define RCC_AHB1ENR_FLASHEN_Pos       (8U)
#define RCC_AHB1ENR_FLASHEN_Msk       (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)         /*!< 0x00000100 */
#define RCC_AHB1ENR_FLASHEN           RCC_AHB1ENR_FLASHEN_Msk                    /*!< Flash interface clock enable */
#define RCC_AHB1ENR_CRCEN_Pos         (12U)
#define RCC_AHB1ENR_CRCEN_Msk         (0x1UL << RCC_AHB1ENR_CRCEN_Pos)           /*!< 0x00001000 */
#define RCC_AHB1ENR_CRCEN             RCC_AHB1ENR_CRCEN_Msk                      /*!< CRC clock enable */
#define RCC_AHB1ENR_CORDICEN_Pos      (14U)
#define RCC_AHB1ENR_CORDICEN_Msk      (0x1UL << RCC_AHB1ENR_CORDICEN_Pos)        /*!< 0x00004000 */
#define RCC_AHB1ENR_CORDICEN          RCC_AHB1ENR_CORDICEN_Msk                   /*!< CORDIC clock enable */
#define RCC_AHB1ENR_RAMCFGEN_Pos      (17U)
#define RCC_AHB1ENR_RAMCFGEN_Msk      (0x1UL << RCC_AHB1ENR_RAMCFGEN_Pos)        /*!< 0x00020000 */
#define RCC_AHB1ENR_RAMCFGEN          RCC_AHB1ENR_RAMCFGEN_Msk                   /*!< RAMCFG clock enable */

#define RCC_AHB1ENR_SRAM2EN_Pos       (30U)
#define RCC_AHB1ENR_SRAM2EN_Msk       (0x1UL << RCC_AHB1ENR_SRAM2EN_Pos)         /*!< 0x40000000 */
#define RCC_AHB1ENR_SRAM2EN           RCC_AHB1ENR_SRAM2EN_Msk                    /*!< SRAM2 clock enable */
#define RCC_AHB1ENR_SRAM1EN_Pos       (31U)
#define RCC_AHB1ENR_SRAM1EN_Msk       (0x1UL << RCC_AHB1ENR_SRAM1EN_Pos)         /*!< 0x80000000 */
#define RCC_AHB1ENR_SRAM1EN           RCC_AHB1ENR_SRAM1EN_Msk                    /*!< SRAM1 clock enable */

/* ***********************************  Bit definition for RCC_AHB2ENR register  ************************************ */
#define RCC_AHB2ENR_Rst               (0x00000000UL)                             /*!< RCC_AHB2ENR reset value */
#define RCC_AHB2ENR_GPIOAEN_Pos       (0U)
#define RCC_AHB2ENR_GPIOAEN_Msk       (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)         /*!< 0x00000001 */
#define RCC_AHB2ENR_GPIOAEN           RCC_AHB2ENR_GPIOAEN_Msk                    /*!< GPIOA clock enable */
#define RCC_AHB2ENR_GPIOBEN_Pos       (1U)
#define RCC_AHB2ENR_GPIOBEN_Msk       (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)         /*!< 0x00000002 */
#define RCC_AHB2ENR_GPIOBEN           RCC_AHB2ENR_GPIOBEN_Msk                    /*!< GPIOB clock enable */
#define RCC_AHB2ENR_GPIOCEN_Pos       (2U)
#define RCC_AHB2ENR_GPIOCEN_Msk       (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)         /*!< 0x00000004 */
#define RCC_AHB2ENR_GPIOCEN           RCC_AHB2ENR_GPIOCEN_Msk                    /*!< GPIOC clock enable */
#define RCC_AHB2ENR_GPIODEN_Pos       (3U)
#define RCC_AHB2ENR_GPIODEN_Msk       (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)         /*!< 0x00000008 */
#define RCC_AHB2ENR_GPIODEN           RCC_AHB2ENR_GPIODEN_Msk                    /*!< GPIOD clock enable */
#define RCC_AHB2ENR_GPIOEEN_Pos       (4U)
#define RCC_AHB2ENR_GPIOEEN_Msk       (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)         /*!< 0x00000010 */
#define RCC_AHB2ENR_GPIOEEN           RCC_AHB2ENR_GPIOEEN_Msk                    /*!< GPIOE clock enable */
#define RCC_AHB2ENR_GPIOHEN_Pos       (7U)
#define RCC_AHB2ENR_GPIOHEN_Msk       (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos)         /*!< 0x00000080 */
#define RCC_AHB2ENR_GPIOHEN           RCC_AHB2ENR_GPIOHEN_Msk                    /*!< GPIOH clock enable */
#define RCC_AHB2ENR_ADC12EN_Pos       (10U)
#define RCC_AHB2ENR_ADC12EN_Msk       (0x1UL << RCC_AHB2ENR_ADC12EN_Pos)         /*!< 0x00000400 */
#define RCC_AHB2ENR_ADC12EN           RCC_AHB2ENR_ADC12EN_Msk                    /*!< ADC1 and ADC2 clock enable */
#define RCC_AHB2ENR_DAC1EN_Pos        (11U)
#define RCC_AHB2ENR_DAC1EN_Msk        (0x1UL << RCC_AHB2ENR_DAC1EN_Pos)          /*!< 0x00000800 */
#define RCC_AHB2ENR_DAC1EN            RCC_AHB2ENR_DAC1EN_Msk                     /*!< DAC1 clock enable */
#define RCC_AHB2ENR_AESEN_Pos         (16U)
#define RCC_AHB2ENR_AESEN_Msk         (0x1UL << RCC_AHB2ENR_AESEN_Pos)           /*!< 0x00010000 */
#define RCC_AHB2ENR_AESEN             RCC_AHB2ENR_AESEN_Msk                      /*!< AES clock enable */
#define RCC_AHB2ENR_HASHEN_Pos        (17U)
#define RCC_AHB2ENR_HASHEN_Msk        (0x1UL << RCC_AHB2ENR_HASHEN_Pos)          /*!< 0x00020000 */
#define RCC_AHB2ENR_HASHEN            RCC_AHB2ENR_HASHEN_Msk                     /*!< HASH clock enable */
#define RCC_AHB2ENR_RNGEN_Pos         (18U)
#define RCC_AHB2ENR_RNGEN_Msk         (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00040000 */
#define RCC_AHB2ENR_RNGEN             RCC_AHB2ENR_RNGEN_Msk                      /*!< RNG clock enable */

/* ***********************************  Bit definition for RCC_APB1LENR register  *********************************** */
#define RCC_APB1LENR_Rst              (0x00000000UL)                             /*!< RCC_APB1LENR reset value */
#define RCC_APB1LENR_TIM2EN_Pos       (0U)
#define RCC_APB1LENR_TIM2EN_Msk       (0x1UL << RCC_APB1LENR_TIM2EN_Pos)         /*!< 0x00000001 */
#define RCC_APB1LENR_TIM2EN           RCC_APB1LENR_TIM2EN_Msk                    /*!< TIM2 clock enable */
#define RCC_APB1LENR_TIM5EN_Pos       (3U)
#define RCC_APB1LENR_TIM5EN_Msk       (0x1UL << RCC_APB1LENR_TIM5EN_Pos)         /*!< 0x00000008 */
#define RCC_APB1LENR_TIM5EN           RCC_APB1LENR_TIM5EN_Msk                    /*!< TIM5 clock enable */
#define RCC_APB1LENR_TIM6EN_Pos       (4U)
#define RCC_APB1LENR_TIM6EN_Msk       (0x1UL << RCC_APB1LENR_TIM6EN_Pos)         /*!< 0x00000010 */
#define RCC_APB1LENR_TIM6EN           RCC_APB1LENR_TIM6EN_Msk                    /*!< TIM6 clock enable */
#define RCC_APB1LENR_TIM7EN_Pos       (5U)
#define RCC_APB1LENR_TIM7EN_Msk       (0x1UL << RCC_APB1LENR_TIM7EN_Pos)         /*!< 0x00000020 */
#define RCC_APB1LENR_TIM7EN           RCC_APB1LENR_TIM7EN_Msk                    /*!< TIM7 clock enable */
#define RCC_APB1LENR_TIM12EN_Pos      (6U)
#define RCC_APB1LENR_TIM12EN_Msk      (0x1UL << RCC_APB1LENR_TIM12EN_Pos)        /*!< 0x00000040 */
#define RCC_APB1LENR_TIM12EN          RCC_APB1LENR_TIM12EN_Msk                   /*!< TIM12 clock enable */
#define RCC_APB1LENR_WWDGEN_Pos       (11U)
#define RCC_APB1LENR_WWDGEN_Msk       (0x1UL << RCC_APB1LENR_WWDGEN_Pos)         /*!< 0x00000800 */
#define RCC_APB1LENR_WWDGEN           RCC_APB1LENR_WWDGEN_Msk                    /*!< WWDG clock enable */
#define RCC_APB1LENR_OPAMP1EN_Pos     (13U)
#define RCC_APB1LENR_OPAMP1EN_Msk     (0x1UL << RCC_APB1LENR_OPAMP1EN_Pos)       /*!< 0x00002000 */
#define RCC_APB1LENR_OPAMP1EN         RCC_APB1LENR_OPAMP1EN_Msk                  /*!< OPAMP1 clock enable */
#define RCC_APB1LENR_SPI2EN_Pos       (14U)
#define RCC_APB1LENR_SPI2EN_Msk       (0x1UL << RCC_APB1LENR_SPI2EN_Pos)         /*!< 0x00004000 */
#define RCC_APB1LENR_SPI2EN           RCC_APB1LENR_SPI2EN_Msk                    /*!< SPI2 clock enable */
#define RCC_APB1LENR_SPI3EN_Pos       (15U)
#define RCC_APB1LENR_SPI3EN_Msk       (0x1UL << RCC_APB1LENR_SPI3EN_Pos)         /*!< 0x00008000 */
#define RCC_APB1LENR_SPI3EN           RCC_APB1LENR_SPI3EN_Msk                    /*!< SPI3 clock enable */
#define RCC_APB1LENR_USART2EN_Pos     (17U)
#define RCC_APB1LENR_USART2EN_Msk     (0x1UL << RCC_APB1LENR_USART2EN_Pos)       /*!< 0x00020000 */
#define RCC_APB1LENR_USART2EN         RCC_APB1LENR_USART2EN_Msk                  /*!< USART2 clock enable */
#define RCC_APB1LENR_USART3EN_Pos     (18U)
#define RCC_APB1LENR_USART3EN_Msk     (0x1UL << RCC_APB1LENR_USART3EN_Pos)       /*!< 0x00040000 */
#define RCC_APB1LENR_USART3EN         RCC_APB1LENR_USART3EN_Msk                  /*!< USART3 clock enable */
#define RCC_APB1LENR_UART4EN_Pos      (19U)
#define RCC_APB1LENR_UART4EN_Msk      (0x1UL << RCC_APB1LENR_UART4EN_Pos)        /*!< 0x00080000 */
#define RCC_APB1LENR_UART4EN          RCC_APB1LENR_UART4EN_Msk                   /*!< UART4 clock enable */
#define RCC_APB1LENR_UART5EN_Pos      (20U)
#define RCC_APB1LENR_UART5EN_Msk      (0x1UL << RCC_APB1LENR_UART5EN_Pos)        /*!< 0x00100000 */
#define RCC_APB1LENR_UART5EN          RCC_APB1LENR_UART5EN_Msk                   /*!< UART5 clock enable */
#define RCC_APB1LENR_I2C1EN_Pos       (21U)
#define RCC_APB1LENR_I2C1EN_Msk       (0x1UL << RCC_APB1LENR_I2C1EN_Pos)         /*!< 0x00200000 */
#define RCC_APB1LENR_I2C1EN           RCC_APB1LENR_I2C1EN_Msk                    /*!< I2C1 clock enable */
#define RCC_APB1LENR_I2C2EN_Pos       (22U)
#define RCC_APB1LENR_I2C2EN_Msk       (0x1UL << RCC_APB1LENR_I2C2EN_Pos)         /*!< 0x00400000 */
#define RCC_APB1LENR_I2C2EN           RCC_APB1LENR_I2C2EN_Msk                    /*!< I2C2 clock enable */
#define RCC_APB1LENR_I3C1EN_Pos       (23U)
#define RCC_APB1LENR_I3C1EN_Msk       (0x1UL << RCC_APB1LENR_I3C1EN_Pos)         /*!< 0x00800000 */
#define RCC_APB1LENR_I3C1EN           RCC_APB1LENR_I3C1EN_Msk                    /*!< I3C1 clock enable */
#define RCC_APB1LENR_CRSEN_Pos        (24U)
#define RCC_APB1LENR_CRSEN_Msk        (0x1UL << RCC_APB1LENR_CRSEN_Pos)          /*!< 0x01000000 */
#define RCC_APB1LENR_CRSEN            RCC_APB1LENR_CRSEN_Msk                     /*!< CRS clock enable */

/* ***********************************  Bit definition for RCC_APB1HENR register  *********************************** */
#define RCC_APB1HENR_Rst              (0x00000000UL)                             /*!< RCC_APB1HENR reset value */
#define RCC_APB1HENR_COMP12EN_Pos     (3U)
#define RCC_APB1HENR_COMP12EN_Msk     (0x1UL << RCC_APB1HENR_COMP12EN_Pos)       /*!< 0x00000008 */
#define RCC_APB1HENR_COMP12EN         RCC_APB1HENR_COMP12EN_Msk                  /*!< COMP1 and COMP2 clock enable */
#define RCC_APB1HENR_FDCANEN_Pos      (9U)
#define RCC_APB1HENR_FDCANEN_Msk      (0x1UL << RCC_APB1HENR_FDCANEN_Pos)        /*!< 0x00000200 */
#define RCC_APB1HENR_FDCANEN          RCC_APB1HENR_FDCANEN_Msk                   /*!< FDCAN1 clock enable */

/* ***********************************  Bit definition for RCC_APB2ENR register  ************************************ */
#define RCC_APB2ENR_Rst               (0x00000000UL)                             /*!< RCC_APB2ENR reset value */
#define RCC_APB2ENR_TIM1EN_Pos        (11U)
#define RCC_APB2ENR_TIM1EN_Msk        (0x1UL << RCC_APB2ENR_TIM1EN_Pos)          /*!< 0x00000800 */
#define RCC_APB2ENR_TIM1EN            RCC_APB2ENR_TIM1EN_Msk                     /*!< TIM1 clock enable */
#define RCC_APB2ENR_SPI1EN_Pos        (12U)
#define RCC_APB2ENR_SPI1EN_Msk        (0x1UL << RCC_APB2ENR_SPI1EN_Pos)          /*!< 0x00001000 */
#define RCC_APB2ENR_SPI1EN            RCC_APB2ENR_SPI1EN_Msk                     /*!< SPI1 clock enable */
#define RCC_APB2ENR_TIM8EN_Pos        (13U)
#define RCC_APB2ENR_TIM8EN_Msk        (0x1UL << RCC_APB2ENR_TIM8EN_Pos)          /*!< 0x00002000 */
#define RCC_APB2ENR_TIM8EN            RCC_APB2ENR_TIM8EN_Msk                     /*!< TIM8 clock enable */
#define RCC_APB2ENR_USART1EN_Pos      (14U)
#define RCC_APB2ENR_USART1EN_Msk      (0x1UL << RCC_APB2ENR_USART1EN_Pos)        /*!< 0x00004000 */
#define RCC_APB2ENR_USART1EN          RCC_APB2ENR_USART1EN_Msk                   /*!< USART1 clock enable */
#define RCC_APB2ENR_TIM15EN_Pos       (16U)
#define RCC_APB2ENR_TIM15EN_Msk       (0x1UL << RCC_APB2ENR_TIM15EN_Pos)         /*!< 0x00010000 */
#define RCC_APB2ENR_TIM15EN           RCC_APB2ENR_TIM15EN_Msk                    /*!< TIM15 clock enable */
#define RCC_APB2ENR_TIM16EN_Pos       (17U)
#define RCC_APB2ENR_TIM16EN_Msk       (0x1UL << RCC_APB2ENR_TIM16EN_Pos)         /*!< 0x00020000 */
#define RCC_APB2ENR_TIM16EN           RCC_APB2ENR_TIM16EN_Msk                    /*!< TIM16 clock enable */
#define RCC_APB2ENR_TIM17EN_Pos       (18U)
#define RCC_APB2ENR_TIM17EN_Msk       (0x1UL << RCC_APB2ENR_TIM17EN_Pos)         /*!< 0x00040000 */
#define RCC_APB2ENR_TIM17EN           RCC_APB2ENR_TIM17EN_Msk                    /*!< TIM17 clock enable */
#define RCC_APB2ENR_USBEN_Pos         (24U)
#define RCC_APB2ENR_USBEN_Msk         (0x1UL << RCC_APB2ENR_USBEN_Pos)           /*!< 0x01000000 */
#define RCC_APB2ENR_USBEN             RCC_APB2ENR_USBEN_Msk                      /*!< USBEN (USB clock enable) */

/* ***********************************  Bit definition for RCC_APB3ENR register  ************************************ */
#define RCC_APB3ENR_Rst               (0x00000000UL)                             /*!< RCC_APB3ENR reset value */
#define RCC_APB3ENR_SBSEN_Pos         (1U)
#define RCC_APB3ENR_SBSEN_Msk         (0x1UL << RCC_APB3ENR_SBSEN_Pos)           /*!< 0x00000002 */
#define RCC_APB3ENR_SBSEN             RCC_APB3ENR_SBSEN_Msk                      /*!< SBS clock enable */
#define RCC_APB3ENR_LPUART1EN_Pos     (6U)
#define RCC_APB3ENR_LPUART1EN_Msk     (0x1UL << RCC_APB3ENR_LPUART1EN_Pos)       /*!< 0x00000040 */
#define RCC_APB3ENR_LPUART1EN         RCC_APB3ENR_LPUART1EN_Msk                  /*!< LPUART1 clock enable */
#define RCC_APB3ENR_LPTIM1EN_Pos      (11U)
#define RCC_APB3ENR_LPTIM1EN_Msk      (0x1UL << RCC_APB3ENR_LPTIM1EN_Pos)        /*!< 0x00000800 */
#define RCC_APB3ENR_LPTIM1EN          RCC_APB3ENR_LPTIM1EN_Msk                   /*!< LPTIM1EN (LPTIM1 clock enable) */
#define RCC_APB3ENR_RTCAPBEN_Pos      (21U)
#define RCC_APB3ENR_RTCAPBEN_Msk      (0x1UL << RCC_APB3ENR_RTCAPBEN_Pos)        /*!< 0x00200000 */
#define RCC_APB3ENR_RTCAPBEN          RCC_APB3ENR_RTCAPBEN_Msk                   /*!< RTC APB interface clock enable */

/* **********************************  Bit definition for RCC_AHB1LPENR register  *********************************** */
#define RCC_AHB1LPENR_Rst             (0xC4025103UL)                             /*!< RCC_AHB1LPENR reset value */
#define RCC_AHB1LPENR_LPDMA1LPEN_Pos  (0U)
#define RCC_AHB1LPENR_LPDMA1LPEN_Msk  (0x1UL << RCC_AHB1LPENR_LPDMA1LPEN_Pos)    /*!< 0x00000001 */
#define RCC_AHB1LPENR_LPDMA1LPEN      RCC_AHB1LPENR_LPDMA1LPEN_Msk               /*!< LPDMA1 clock enable during Sleep
                                                                                      mode */
#define RCC_AHB1LPENR_LPDMA2LPEN_Pos  (1U)
#define RCC_AHB1LPENR_LPDMA2LPEN_Msk  (0x1UL << RCC_AHB1LPENR_LPDMA2LPEN_Pos)    /*!< 0x00000002 */
#define RCC_AHB1LPENR_LPDMA2LPEN      RCC_AHB1LPENR_LPDMA2LPEN_Msk               /*!< LPDMA2 clock enable during Sleep
                                                                                      mode */
#define RCC_AHB1LPENR_FLASHLPEN_Pos   (8U)
#define RCC_AHB1LPENR_FLASHLPEN_Msk   (0x1UL << RCC_AHB1LPENR_FLASHLPEN_Pos)     /*!< 0x00000100 */
#define RCC_AHB1LPENR_FLASHLPEN       RCC_AHB1LPENR_FLASHLPEN_Msk                /*!< Flash interface clock enable
                                                                                      during Sleep mode */
#define RCC_AHB1LPENR_CRCLPEN_Pos     (12U)
#define RCC_AHB1LPENR_CRCLPEN_Msk     (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)       /*!< 0x00001000 */
#define RCC_AHB1LPENR_CRCLPEN         RCC_AHB1LPENR_CRCLPEN_Msk                  /*!< CRC clock enable during Sleep mode
                                                                                      */
#define RCC_AHB1LPENR_CORDICLPEN_Pos  (14U)
#define RCC_AHB1LPENR_CORDICLPEN_Msk  (0x1UL << RCC_AHB1LPENR_CORDICLPEN_Pos)    /*!< 0x00004000 */
#define RCC_AHB1LPENR_CORDICLPEN      RCC_AHB1LPENR_CORDICLPEN_Msk               /*!< CORDIC clock enable during Sleep
                                                                                      mode */
#define RCC_AHB1LPENR_RAMCFGLPEN_Pos  (17U)
#define RCC_AHB1LPENR_RAMCFGLPEN_Msk  (0x1UL << RCC_AHB1LPENR_RAMCFGLPEN_Pos)    /*!< 0x00020000 */
#define RCC_AHB1LPENR_RAMCFGLPEN      RCC_AHB1LPENR_RAMCFGLPEN_Msk               /*!< RAMCFG clock enable during Sleep
                                                                                      mode */
#define RCC_AHB1LPENR_ICACHELPEN_Pos  (26U)
#define RCC_AHB1LPENR_ICACHELPEN_Msk  (0x1UL << RCC_AHB1LPENR_ICACHELPEN_Pos)    /*!< 0x04000000 */
#define RCC_AHB1LPENR_ICACHELPEN      RCC_AHB1LPENR_ICACHELPEN_Msk               /*!< ICACHE clock enable during Sleep
                                                                                      mode */
#define RCC_AHB1LPENR_SRAM2LPEN_Pos   (30U)
#define RCC_AHB1LPENR_SRAM2LPEN_Msk   (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos)     /*!< 0x40000000 */
#define RCC_AHB1LPENR_SRAM2LPEN       RCC_AHB1LPENR_SRAM2LPEN_Msk                /*!< SRAM2 clock enable during Sleep
                                                                                      mode */
#define RCC_AHB1LPENR_SRAM1LPEN_Pos   (31U)
#define RCC_AHB1LPENR_SRAM1LPEN_Msk   (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)     /*!< 0x80000000 */
#define RCC_AHB1LPENR_SRAM1LPEN       RCC_AHB1LPENR_SRAM1LPEN_Msk                /*!< SRAM1 clock enable during Sleep
                                                                                      mode */

/* **********************************  Bit definition for RCC_AHB2LPENR register  *********************************** */
#define RCC_AHB2LPENR_Rst             (0x00070C9FUL)                             /*!< RCC_AHB2LPENR reset value */
#define RCC_AHB2LPENR_GPIOALPEN_Pos   (0U)
#define RCC_AHB2LPENR_GPIOALPEN_Msk   (0x1UL << RCC_AHB2LPENR_GPIOALPEN_Pos)     /*!< 0x00000001 */
#define RCC_AHB2LPENR_GPIOALPEN       RCC_AHB2LPENR_GPIOALPEN_Msk                /*!< GPIOA clock enable during Sleep
                                                                                      mode */
#define RCC_AHB2LPENR_GPIOBLPEN_Pos   (1U)
#define RCC_AHB2LPENR_GPIOBLPEN_Msk   (0x1UL << RCC_AHB2LPENR_GPIOBLPEN_Pos)     /*!< 0x00000002 */
#define RCC_AHB2LPENR_GPIOBLPEN       RCC_AHB2LPENR_GPIOBLPEN_Msk                /*!< GPIOB clock enable during Sleep
                                                                                      mode */
#define RCC_AHB2LPENR_GPIOCLPEN_Pos   (2U)
#define RCC_AHB2LPENR_GPIOCLPEN_Msk   (0x1UL << RCC_AHB2LPENR_GPIOCLPEN_Pos)     /*!< 0x00000004 */
#define RCC_AHB2LPENR_GPIOCLPEN       RCC_AHB2LPENR_GPIOCLPEN_Msk                /*!< GPIOC clock enable during Sleep
                                                                                      mode */
#define RCC_AHB2LPENR_GPIODLPEN_Pos   (3U)
#define RCC_AHB2LPENR_GPIODLPEN_Msk   (0x1UL << RCC_AHB2LPENR_GPIODLPEN_Pos)     /*!< 0x00000008 */
#define RCC_AHB2LPENR_GPIODLPEN       RCC_AHB2LPENR_GPIODLPEN_Msk                /*!< GPIOD clock enable during Sleep
                                                                                      mode */
#define RCC_AHB2LPENR_GPIOELPEN_Pos   (4U)
#define RCC_AHB2LPENR_GPIOELPEN_Msk   (0x1UL << RCC_AHB2LPENR_GPIOELPEN_Pos)     /*!< 0x00000010 */
#define RCC_AHB2LPENR_GPIOELPEN       RCC_AHB2LPENR_GPIOELPEN_Msk                /*!< GPIOE clock enable during Sleep
                                                                                      mode */
#define RCC_AHB2LPENR_GPIOHLPEN_Pos   (7U)
#define RCC_AHB2LPENR_GPIOHLPEN_Msk   (0x1UL << RCC_AHB2LPENR_GPIOHLPEN_Pos)     /*!< 0x00000080 */
#define RCC_AHB2LPENR_GPIOHLPEN       RCC_AHB2LPENR_GPIOHLPEN_Msk                /*!< GPIOH clock enable during Sleep
                                                                                      mode */
#define RCC_AHB2LPENR_ADC12LPEN_Pos   (10U)
#define RCC_AHB2LPENR_ADC12LPEN_Msk   (0x1UL << RCC_AHB2LPENR_ADC12LPEN_Pos)     /*!< 0x00000400 */
#define RCC_AHB2LPENR_ADC12LPEN       RCC_AHB2LPENR_ADC12LPEN_Msk                /*!< ADC1 and ADC2 clock enable during
                                                                                      Sleep mode */
#define RCC_AHB2LPENR_DAC1LPEN_Pos    (11U)
#define RCC_AHB2LPENR_DAC1LPEN_Msk    (0x1UL << RCC_AHB2LPENR_DAC1LPEN_Pos)      /*!< 0x00000800 */
#define RCC_AHB2LPENR_DAC1LPEN        RCC_AHB2LPENR_DAC1LPEN_Msk                 /*!< DAC1 clock enable during Sleep
                                                                                      mode */
#define RCC_AHB2LPENR_AESLPEN_Pos     (16U)
#define RCC_AHB2LPENR_AESLPEN_Msk     (0x1UL << RCC_AHB2LPENR_AESLPEN_Pos)       /*!< 0x00010000 */
#define RCC_AHB2LPENR_AESLPEN         RCC_AHB2LPENR_AESLPEN_Msk                  /*!< AES clock enable during Sleep mode
                                                                                      */
#define RCC_AHB2LPENR_HASHLPEN_Pos    (17U)
#define RCC_AHB2LPENR_HASHLPEN_Msk    (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos)      /*!< 0x00020000 */
#define RCC_AHB2LPENR_HASHLPEN        RCC_AHB2LPENR_HASHLPEN_Msk                 /*!< HASH clock enable during Sleep
                                                                                      mode */
#define RCC_AHB2LPENR_RNGLPEN_Pos     (18U)
#define RCC_AHB2LPENR_RNGLPEN_Msk     (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)       /*!< 0x00040000 */
#define RCC_AHB2LPENR_RNGLPEN         RCC_AHB2LPENR_RNGLPEN_Msk                  /*!< RNG clock enable during Sleep mode
                                                                                      */

/* **********************************  Bit definition for RCC_APB1LLPENR register  ********************************** */
#define RCC_APB1LLPENR_Rst            (0x01FEC879UL)                             /*!< RCC_APB1LLPENR reset value */
#define RCC_APB1LLPENR_TIM2LPEN_Pos   (0U)
#define RCC_APB1LLPENR_TIM2LPEN_Msk   (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos)     /*!< 0x00000001 */
#define RCC_APB1LLPENR_TIM2LPEN       RCC_APB1LLPENR_TIM2LPEN_Msk                /*!< TIM2 clock enable during Sleep
                                                                                      mode */
#define RCC_APB1LLPENR_TIM5LPEN_Pos   (3U)
#define RCC_APB1LLPENR_TIM5LPEN_Msk   (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos)     /*!< 0x00000008 */
#define RCC_APB1LLPENR_TIM5LPEN       RCC_APB1LLPENR_TIM5LPEN_Msk                /*!< TIM5 clock enable during Sleep
                                                                                      mode */
#define RCC_APB1LLPENR_TIM6LPEN_Pos   (4U)
#define RCC_APB1LLPENR_TIM6LPEN_Msk   (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos)     /*!< 0x00000010 */
#define RCC_APB1LLPENR_TIM6LPEN       RCC_APB1LLPENR_TIM6LPEN_Msk                /*!< TIM6 clock enable during Sleep
                                                                                      mode */
#define RCC_APB1LLPENR_TIM7LPEN_Pos   (5U)
#define RCC_APB1LLPENR_TIM7LPEN_Msk   (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos)     /*!< 0x00000020 */
#define RCC_APB1LLPENR_TIM7LPEN       RCC_APB1LLPENR_TIM7LPEN_Msk                /*!< TIM7 clock enable during Sleep
                                                                                      mode */
#define RCC_APB1LLPENR_TIM12LPEN_Pos  (6U)
#define RCC_APB1LLPENR_TIM12LPEN_Msk  (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos)    /*!< 0x00000040 */
#define RCC_APB1LLPENR_TIM12LPEN      RCC_APB1LLPENR_TIM12LPEN_Msk               /*!< TIM12 clock enable during Sleep
                                                                                      mode */
#define RCC_APB1LLPENR_WWDGLPEN_Pos   (11U)
#define RCC_APB1LLPENR_WWDGLPEN_Msk   (0x1UL << RCC_APB1LLPENR_WWDGLPEN_Pos)     /*!< 0x00000800 */
#define RCC_APB1LLPENR_WWDGLPEN       RCC_APB1LLPENR_WWDGLPEN_Msk                /*!< WWDG clock enable during Sleep
                                                                                      mode */
#define RCC_APB1LLPENR_OPAMP1LPEN_Pos (13U)
#define RCC_APB1LLPENR_OPAMP1LPEN_Msk (0x1UL << RCC_APB1LLPENR_OPAMP1LPEN_Pos)   /*!< 0x00002000 */
#define RCC_APB1LLPENR_OPAMP1LPEN     RCC_APB1LLPENR_OPAMP1LPEN_Msk              /*!< OPAMP1 clock enable during Sleep
                                                                                      mode */
#define RCC_APB1LLPENR_SPI2LPEN_Pos   (14U)
#define RCC_APB1LLPENR_SPI2LPEN_Msk   (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos)     /*!< 0x00004000 */
#define RCC_APB1LLPENR_SPI2LPEN       RCC_APB1LLPENR_SPI2LPEN_Msk                /*!< SPI2 clock enable during Sleep
                                                                                      mode */
#define RCC_APB1LLPENR_SPI3LPEN_Pos   (15U)
#define RCC_APB1LLPENR_SPI3LPEN_Msk   (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos)     /*!< 0x00008000 */
#define RCC_APB1LLPENR_SPI3LPEN       RCC_APB1LLPENR_SPI3LPEN_Msk                /*!< SPI3 clock enable during Sleep
                                                                                      mode */
#define RCC_APB1LLPENR_USART2LPEN_Pos (17U)
#define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos)   /*!< 0x00020000 */
#define RCC_APB1LLPENR_USART2LPEN     RCC_APB1LLPENR_USART2LPEN_Msk              /*!< USART2 clock enable during Sleep
                                                                                      mode */
#define RCC_APB1LLPENR_USART3LPEN_Pos (18U)
#define RCC_APB1LLPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos)   /*!< 0x00040000 */
#define RCC_APB1LLPENR_USART3LPEN     RCC_APB1LLPENR_USART3LPEN_Msk              /*!< USART3 clock enable during Sleep
                                                                                      mode */
#define RCC_APB1LLPENR_UART4LPEN_Pos  (19U)
#define RCC_APB1LLPENR_UART4LPEN_Msk  (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos)    /*!< 0x00080000 */
#define RCC_APB1LLPENR_UART4LPEN      RCC_APB1LLPENR_UART4LPEN_Msk               /*!< UART4 clock enable during Sleep
                                                                                      mode */
#define RCC_APB1LLPENR_UART5LPEN_Pos  (20U)
#define RCC_APB1LLPENR_UART5LPEN_Msk  (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos)    /*!< 0x00100000 */
#define RCC_APB1LLPENR_UART5LPEN      RCC_APB1LLPENR_UART5LPEN_Msk               /*!< UART5 clock enable during Sleep
                                                                                      mode */
#define RCC_APB1LLPENR_I2C1LPEN_Pos   (21U)
#define RCC_APB1LLPENR_I2C1LPEN_Msk   (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos)     /*!< 0x00200000 */
#define RCC_APB1LLPENR_I2C1LPEN       RCC_APB1LLPENR_I2C1LPEN_Msk                /*!< I2C1 clock enable during Sleep
                                                                                      mode */
#define RCC_APB1LLPENR_I2C2LPEN_Pos   (22U)
#define RCC_APB1LLPENR_I2C2LPEN_Msk   (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos)     /*!< 0x00400000 */
#define RCC_APB1LLPENR_I2C2LPEN       RCC_APB1LLPENR_I2C2LPEN_Msk                /*!< I2C2 clock enable during Sleep
                                                                                      mode */
#define RCC_APB1LLPENR_I3C1LPEN_Pos   (23U)
#define RCC_APB1LLPENR_I3C1LPEN_Msk   (0x1UL << RCC_APB1LLPENR_I3C1LPEN_Pos)     /*!< 0x00800000 */
#define RCC_APB1LLPENR_I3C1LPEN       RCC_APB1LLPENR_I3C1LPEN_Msk                /*!< I3C1 clock enable during Sleep
                                                                                      mode */
#define RCC_APB1LLPENR_CRSLPEN_Pos    (24U)
#define RCC_APB1LLPENR_CRSLPEN_Msk    (0x1UL << RCC_APB1LLPENR_CRSLPEN_Pos)      /*!< 0x01000000 */
#define RCC_APB1LLPENR_CRSLPEN        RCC_APB1LLPENR_CRSLPEN_Msk                 /*!< CRS clock enable during Sleep mode
                                                                                      */

/* **********************************  Bit definition for RCC_APB1HLPENR register  ********************************** */
#define RCC_APB1HLPENR_Rst            (0x40000208UL)                             /*!< RCC_APB1HLPENR reset value */
#define RCC_APB1HLPENR_COMP12LPEN_Pos (3U)
#define RCC_APB1HLPENR_COMP12LPEN_Msk (0x1UL << RCC_APB1HLPENR_COMP12LPEN_Pos)   /*!< 0x00000008 */
#define RCC_APB1HLPENR_COMP12LPEN     RCC_APB1HLPENR_COMP12LPEN_Msk              /*!< COMP1 and COMP2 clock enable
                                                                                      during Sleep mode */
#define RCC_APB1HLPENR_FDCANLPEN_Pos  (9U)
#define RCC_APB1HLPENR_FDCANLPEN_Msk  (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos)    /*!< 0x00000200 */
#define RCC_APB1HLPENR_FDCANLPEN      RCC_APB1HLPENR_FDCANLPEN_Msk               /*!< FDCAN1 clock enable during Sleep
                                                                                      mode */

/* **********************************  Bit definition for RCC_APB2LPENR register  *********************************** */
#define RCC_APB2LPENR_Rst             (0x01077800UL)                             /*!< RCC_APB2LPENR reset value */
#define RCC_APB2LPENR_TIM1LPEN_Pos    (11U)
#define RCC_APB2LPENR_TIM1LPEN_Msk    (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)      /*!< 0x00000800 */
#define RCC_APB2LPENR_TIM1LPEN        RCC_APB2LPENR_TIM1LPEN_Msk                 /*!< TIM1 clock enable during Sleep
                                                                                      mode */
#define RCC_APB2LPENR_SPI1LPEN_Pos    (12U)
#define RCC_APB2LPENR_SPI1LPEN_Msk    (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)      /*!< 0x00001000 */
#define RCC_APB2LPENR_SPI1LPEN        RCC_APB2LPENR_SPI1LPEN_Msk                 /*!< SPI1 clock enable during Sleep
                                                                                      mode */
#define RCC_APB2LPENR_TIM8LPEN_Pos    (13U)
#define RCC_APB2LPENR_TIM8LPEN_Msk    (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)      /*!< 0x00002000 */
#define RCC_APB2LPENR_TIM8LPEN        RCC_APB2LPENR_TIM8LPEN_Msk                 /*!< TIM8 clock enable during Sleep
                                                                                      mode */
#define RCC_APB2LPENR_USART1LPEN_Pos  (14U)
#define RCC_APB2LPENR_USART1LPEN_Msk  (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)    /*!< 0x00004000 */
#define RCC_APB2LPENR_USART1LPEN      RCC_APB2LPENR_USART1LPEN_Msk               /*!< USART1 clock enable during Sleep
                                                                                      mode */
#define RCC_APB2LPENR_TIM15LPEN_Pos   (16U)
#define RCC_APB2LPENR_TIM15LPEN_Msk   (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos)     /*!< 0x00010000 */
#define RCC_APB2LPENR_TIM15LPEN       RCC_APB2LPENR_TIM15LPEN_Msk                /*!< TIM15 clock enable during Sleep
                                                                                      mode */
#define RCC_APB2LPENR_TIM16LPEN_Pos   (17U)
#define RCC_APB2LPENR_TIM16LPEN_Msk   (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos)     /*!< 0x00020000 */
#define RCC_APB2LPENR_TIM16LPEN       RCC_APB2LPENR_TIM16LPEN_Msk                /*!< TIM16 clock enable during Sleep
                                                                                      mode */
#define RCC_APB2LPENR_TIM17LPEN_Pos   (18U)
#define RCC_APB2LPENR_TIM17LPEN_Msk   (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos)     /*!< 0x00040000 */
#define RCC_APB2LPENR_TIM17LPEN       RCC_APB2LPENR_TIM17LPEN_Msk                /*!< TIM17 clock enable during Sleep
                                                                                      mode */
#define RCC_APB2LPENR_USBLPEN_Pos     (24U)
#define RCC_APB2LPENR_USBLPEN_Msk     (0x1UL << RCC_APB2LPENR_USBLPEN_Pos)       /*!< 0x01000000 */
#define RCC_APB2LPENR_USBLPEN         RCC_APB2LPENR_USBLPEN_Msk                  /*!< USBLPEN (USB clock enable during
                                                                                      Sleep mode) */

/* **********************************  Bit definition for RCC_APB3LPENR register  *********************************** */
#define RCC_APB3LPENR_Rst             (0x00200842UL)                             /*!< RCC_APB3LPENR reset value */
#define RCC_APB3LPENR_SBSLPEN_Pos     (1U)
#define RCC_APB3LPENR_SBSLPEN_Msk     (0x1UL << RCC_APB3LPENR_SBSLPEN_Pos)       /*!< 0x00000002 */
#define RCC_APB3LPENR_SBSLPEN         RCC_APB3LPENR_SBSLPEN_Msk                  /*!< SBS clock enable during Sleep mode
                                                                                      */
#define RCC_APB3LPENR_LPUART1LPEN_Pos (6U)
#define RCC_APB3LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB3LPENR_LPUART1LPEN_Pos)   /*!< 0x00000040 */
#define RCC_APB3LPENR_LPUART1LPEN     RCC_APB3LPENR_LPUART1LPEN_Msk              /*!< LPUART1 clock enable during Sleep
                                                                                      mode */
#define RCC_APB3LPENR_LPTIM1LPEN_Pos  (11U)
#define RCC_APB3LPENR_LPTIM1LPEN_Msk  (0x1UL << RCC_APB3LPENR_LPTIM1LPEN_Pos)    /*!< 0x00000800 */
#define RCC_APB3LPENR_LPTIM1LPEN      RCC_APB3LPENR_LPTIM1LPEN_Msk               /*!< LPTIM1LPEN (LPTIM1 clock enable
                                                                                      during Sleep mode) */
#define RCC_APB3LPENR_RTCAPBLPEN_Pos  (21U)
#define RCC_APB3LPENR_RTCAPBLPEN_Msk  (0x1UL << RCC_APB3LPENR_RTCAPBLPEN_Pos)    /*!< 0x00200000 */
#define RCC_APB3LPENR_RTCAPBLPEN      RCC_APB3LPENR_RTCAPBLPEN_Msk               /*!< RTC APB interface clock enable
                                                                                      during Sleep mode */

/* ************************************  Bit definition for RCC_CCIPR1 register  ************************************ */
#define RCC_CCIPR1_Rst                (0x00000000UL)                             /*!< RCC_CCIPR1 reset value */
#define RCC_CCIPR1_USART1SEL_Pos      (0U)
#define RCC_CCIPR1_USART1SEL_Msk      (0x3UL << RCC_CCIPR1_USART1SEL_Pos)        /*!< 0x00000003 */
#define RCC_CCIPR1_USART1SEL          RCC_CCIPR1_USART1SEL_Msk                   /*!< USART1 kernel clock source
                                                                                      selection */
#define RCC_CCIPR1_USART1SEL_0        (0x1UL << RCC_CCIPR1_USART1SEL_Pos)        /*!< 0x00000001 */
#define RCC_CCIPR1_USART1SEL_1        (0x2UL << RCC_CCIPR1_USART1SEL_Pos)        /*!< 0x00000002 */
#define RCC_CCIPR1_USART2SEL_Pos      (2U)
#define RCC_CCIPR1_USART2SEL_Msk      (0x3UL << RCC_CCIPR1_USART2SEL_Pos)        /*!< 0x0000000C */
#define RCC_CCIPR1_USART2SEL          RCC_CCIPR1_USART2SEL_Msk                   /*!< USART2 kernel clock source
                                                                                      selection */
#define RCC_CCIPR1_USART2SEL_0        (0x1UL << RCC_CCIPR1_USART2SEL_Pos)        /*!< 0x00000004 */
#define RCC_CCIPR1_USART2SEL_1        (0x2UL << RCC_CCIPR1_USART2SEL_Pos)        /*!< 0x00000008 */
#define RCC_CCIPR1_USART3SEL_Pos      (4U)
#define RCC_CCIPR1_USART3SEL_Msk      (0x3UL << RCC_CCIPR1_USART3SEL_Pos)        /*!< 0x00000030 */
#define RCC_CCIPR1_USART3SEL          RCC_CCIPR1_USART3SEL_Msk                   /*!< UART3 kernel clock source
                                                                                      selection */
#define RCC_CCIPR1_USART3SEL_0        (0x1UL << RCC_CCIPR1_USART3SEL_Pos)        /*!< 0x00000010 */
#define RCC_CCIPR1_USART3SEL_1        (0x2UL << RCC_CCIPR1_USART3SEL_Pos)        /*!< 0x00000020 */
#define RCC_CCIPR1_UART4SEL_Pos       (6U)
#define RCC_CCIPR1_UART4SEL_Msk       (0x3UL << RCC_CCIPR1_UART4SEL_Pos)         /*!< 0x000000C0 */
#define RCC_CCIPR1_UART4SEL           RCC_CCIPR1_UART4SEL_Msk                    /*!< UART4 kernel clock source
                                                                                      selection */
#define RCC_CCIPR1_UART4SEL_0         (0x1UL << RCC_CCIPR1_UART4SEL_Pos)         /*!< 0x00000040 */
#define RCC_CCIPR1_UART4SEL_1         (0x2UL << RCC_CCIPR1_UART4SEL_Pos)         /*!< 0x00000080 */
#define RCC_CCIPR1_UART5SEL_Pos       (8U)
#define RCC_CCIPR1_UART5SEL_Msk       (0x3UL << RCC_CCIPR1_UART5SEL_Pos)         /*!< 0x00000300 */
#define RCC_CCIPR1_UART5SEL           RCC_CCIPR1_UART5SEL_Msk                    /*!< UART5 kernel clock source
                                                                                      selection */
#define RCC_CCIPR1_UART5SEL_0         (0x1UL << RCC_CCIPR1_UART5SEL_Pos)         /*!< 0x00000100 */
#define RCC_CCIPR1_UART5SEL_1         (0x2UL << RCC_CCIPR1_UART5SEL_Pos)         /*!< 0x00000200 */
#define RCC_CCIPR1_LPUART1SEL_Pos     (14U)
#define RCC_CCIPR1_LPUART1SEL_Msk     (0x3UL << RCC_CCIPR1_LPUART1SEL_Pos)       /*!< 0x0000C000 */
#define RCC_CCIPR1_LPUART1SEL         RCC_CCIPR1_LPUART1SEL_Msk                  /*!< LPUART1 kernel clock source
                                                                                      selection */
#define RCC_CCIPR1_LPUART1SEL_0       (0x1UL << RCC_CCIPR1_LPUART1SEL_Pos)       /*!< 0x00004000 */
#define RCC_CCIPR1_LPUART1SEL_1       (0x2UL << RCC_CCIPR1_LPUART1SEL_Pos)       /*!< 0x00008000 */
#define RCC_CCIPR1_SPI1SEL_Pos        (16U)
#define RCC_CCIPR1_SPI1SEL_Msk        (0x3UL << RCC_CCIPR1_SPI1SEL_Pos)          /*!< 0x00030000 */
#define RCC_CCIPR1_SPI1SEL            RCC_CCIPR1_SPI1SEL_Msk                     /*!< SPI1 kernel clock source selection
                                                                                      */
#define RCC_CCIPR1_SPI1SEL_0          (0x1UL << RCC_CCIPR1_SPI1SEL_Pos)          /*!< 0x00010000 */
#define RCC_CCIPR1_SPI1SEL_1          (0x2UL << RCC_CCIPR1_SPI1SEL_Pos)          /*!< 0x00020000 */
#define RCC_CCIPR1_SPI2SEL_Pos        (18U)
#define RCC_CCIPR1_SPI2SEL_Msk        (0x3UL << RCC_CCIPR1_SPI2SEL_Pos)          /*!< 0x000C0000 */
#define RCC_CCIPR1_SPI2SEL            RCC_CCIPR1_SPI2SEL_Msk                     /*!< SPI2 kernel clock source selection
                                                                                      */
#define RCC_CCIPR1_SPI2SEL_0          (0x1UL << RCC_CCIPR1_SPI2SEL_Pos)          /*!< 0x00040000 */
#define RCC_CCIPR1_SPI2SEL_1          (0x2UL << RCC_CCIPR1_SPI2SEL_Pos)          /*!< 0x00080000 */
#define RCC_CCIPR1_SPI3SEL_Pos        (20U)
#define RCC_CCIPR1_SPI3SEL_Msk        (0x3UL << RCC_CCIPR1_SPI3SEL_Pos)          /*!< 0x00300000 */
#define RCC_CCIPR1_SPI3SEL            RCC_CCIPR1_SPI3SEL_Msk                     /*!< SPI3 kernel clock source selection
                                                                                      */
#define RCC_CCIPR1_SPI3SEL_0          (0x1UL << RCC_CCIPR1_SPI3SEL_Pos)          /*!< 0x00100000 */
#define RCC_CCIPR1_SPI3SEL_1          (0x2UL << RCC_CCIPR1_SPI3SEL_Pos)          /*!< 0x00200000 */
#define RCC_CCIPR1_FDCANSEL_Pos       (26U)
#define RCC_CCIPR1_FDCANSEL_Msk       (0x3UL << RCC_CCIPR1_FDCANSEL_Pos)         /*!< 0x0C000000 */
#define RCC_CCIPR1_FDCANSEL           RCC_CCIPR1_FDCANSEL_Msk                    /*!< FDCAN1 kernel clock source
                                                                                      selection */
#define RCC_CCIPR1_FDCANSEL_0         (0x1UL << RCC_CCIPR1_FDCANSEL_Pos)         /*!< 0x04000000 */
#define RCC_CCIPR1_FDCANSEL_1         (0x2UL << RCC_CCIPR1_FDCANSEL_Pos)         /*!< 0x08000000 */

/* ************************************  Bit definition for RCC_CCIPR2 register  ************************************ */
#define RCC_CCIPR2_Rst                (0x00000000UL)                             /*!< RCC_CCIPR2 reset value */
#define RCC_CCIPR2_I2C1SEL_Pos        (0U)
#define RCC_CCIPR2_I2C1SEL_Msk        (0x3UL << RCC_CCIPR2_I2C1SEL_Pos)          /*!< 0x00000003 */
#define RCC_CCIPR2_I2C1SEL            RCC_CCIPR2_I2C1SEL_Msk                     /*!< I2C1 kernel clock source selection
                                                                                      */
#define RCC_CCIPR2_I2C1SEL_0          (0x1UL << RCC_CCIPR2_I2C1SEL_Pos)          /*!< 0x00000001 */
#define RCC_CCIPR2_I2C1SEL_1          (0x2UL << RCC_CCIPR2_I2C1SEL_Pos)          /*!< 0x00000002 */
#define RCC_CCIPR2_I2C2SEL_Pos        (2U)
#define RCC_CCIPR2_I2C2SEL_Msk        (0x3UL << RCC_CCIPR2_I2C2SEL_Pos)          /*!< 0x0000000C */
#define RCC_CCIPR2_I2C2SEL            RCC_CCIPR2_I2C2SEL_Msk                     /*!< I2C2 kernel clock source selection
                                                                                      */
#define RCC_CCIPR2_I2C2SEL_0          (0x1UL << RCC_CCIPR2_I2C2SEL_Pos)          /*!< 0x00000004 */
#define RCC_CCIPR2_I2C2SEL_1          (0x2UL << RCC_CCIPR2_I2C2SEL_Pos)          /*!< 0x00000008 */
#define RCC_CCIPR2_I3C1SEL_Pos        (6U)
#define RCC_CCIPR2_I3C1SEL_Msk        (0x3UL << RCC_CCIPR2_I3C1SEL_Pos)          /*!< 0x000000C0 */
#define RCC_CCIPR2_I3C1SEL            RCC_CCIPR2_I3C1SEL_Msk                     /*!< I3C1 kernel clock source selection
                                                                                      */
#define RCC_CCIPR2_I3C1SEL_0          (0x1UL << RCC_CCIPR2_I3C1SEL_Pos)          /*!< 0x00000040 */
#define RCC_CCIPR2_I3C1SEL_1          (0x2UL << RCC_CCIPR2_I3C1SEL_Pos)          /*!< 0x00000080 */
#define RCC_CCIPR2_ADCDACSEL_Pos      (10U)
#define RCC_CCIPR2_ADCDACSEL_Msk      (0x3UL << RCC_CCIPR2_ADCDACSEL_Pos)        /*!< 0x00000C00 */
#define RCC_CCIPR2_ADCDACSEL          RCC_CCIPR2_ADCDACSEL_Msk                   /*!< ADC and DAC kernel clock source
                                                                                      selection */
#define RCC_CCIPR2_ADCDACSEL_0        (0x1UL << RCC_CCIPR2_ADCDACSEL_Pos)        /*!< 0x00000400 */
#define RCC_CCIPR2_ADCDACSEL_1        (0x2UL << RCC_CCIPR2_ADCDACSEL_Pos)        /*!< 0x00000800 */
/*!< ADCDAPRE configuration */
#define RCC_CCIPR2_ADCDACPRE_Pos      (12U)
#define RCC_CCIPR2_ADCDACPRE_Msk      (0x7UL << RCC_CCIPR2_ADCDACPRE_Pos)        /*!< 0x00007000 */
#define RCC_CCIPR2_ADCDACPRE          RCC_CCIPR2_ADCDACPRE_Msk                   /*!< ADCDACPRE[2:0] bits (ADC and DAC
                                                                                      prescaler for kernel clock
                                                                                      source) */
#define RCC_CCIPR2_ADCDACPRE_0        (0x1UL << RCC_CCIPR2_ADCDACPRE_Pos)        /*!< 0x00001000 */
#define RCC_CCIPR2_ADCDACPRE_1        (0x2UL << RCC_CCIPR2_ADCDACPRE_Pos)        /*!< 0x00002000 */
#define RCC_CCIPR2_ADCDACPRE_2        (0x4UL << RCC_CCIPR2_ADCDACPRE_Pos)        /*!< 0x00004000 */
#define RCC_CCIPR2_DACSEL_Pos         (15U)
#define RCC_CCIPR2_DACSEL_Msk         (0x1UL << RCC_CCIPR2_DACSEL_Pos)           /*!< 0x00008000 */
#define RCC_CCIPR2_DACSEL             RCC_CCIPR2_DACSEL_Msk                      /*!< DAC sample and hold clock */
#define RCC_CCIPR2_LPTIM1SEL_Pos      (16U)
#define RCC_CCIPR2_LPTIM1SEL_Msk      (0x3UL << RCC_CCIPR2_LPTIM1SEL_Pos)        /*!< 0x00030000 */
#define RCC_CCIPR2_LPTIM1SEL          RCC_CCIPR2_LPTIM1SEL_Msk                   /*!< LPTIM1SEL[1:0] bits (LPTIM1 kernel
                                                                                      clock source selection) */
#define RCC_CCIPR2_LPTIM1SEL_0        (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos)        /*!< 0x00010000 */
#define RCC_CCIPR2_LPTIM1SEL_1        (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos)        /*!< 0x00020000 */
#define RCC_CCIPR2_CK48SEL_Pos        (24U)
#define RCC_CCIPR2_CK48SEL_Msk        (0x3UL << RCC_CCIPR2_CK48SEL_Pos)          /*!< 0x03000000 */
#define RCC_CCIPR2_CK48SEL            RCC_CCIPR2_CK48SEL_Msk                     /*!< CK48 clock source selection */
#define RCC_CCIPR2_CK48SEL_0          (0x1UL << RCC_CCIPR2_CK48SEL_Pos)          /*!< 0x01000000 */
#define RCC_CCIPR2_CK48SEL_1          (0x2UL << RCC_CCIPR2_CK48SEL_Pos)          /*!< 0x02000000 */
#define RCC_CCIPR2_SYSTICKSEL_Pos     (30U)
#define RCC_CCIPR2_SYSTICKSEL_Msk     (0x3UL << RCC_CCIPR2_SYSTICKSEL_Pos)       /*!< 0xC0000000 */
#define RCC_CCIPR2_SYSTICKSEL         RCC_CCIPR2_SYSTICKSEL_Msk                  /*!< SYSTICK clock source selection */
#define RCC_CCIPR2_SYSTICKSEL_0       (0x1UL << RCC_CCIPR2_SYSTICKSEL_Pos)       /*!< 0x40000000 */
#define RCC_CCIPR2_SYSTICKSEL_1       (0x2UL << RCC_CCIPR2_SYSTICKSEL_Pos)       /*!< 0x80000000 */

/* ************************************  Bit definition for RCC_RTCCR register  ************************************* */
#define RCC_RTCCR_Rst                 (0x00000000UL)                             /*!< RCC_RTCCR reset value */
#define RCC_RTCCR_LSEON_Pos           (0U)
#define RCC_RTCCR_LSEON_Msk           (0x1UL << RCC_RTCCR_LSEON_Pos)             /*!< 0x00000001 */
#define RCC_RTCCR_LSEON               RCC_RTCCR_LSEON_Msk                        /*!< LSE oscillator enabled */
#define RCC_RTCCR_LSERDY_Pos          (1U)
#define RCC_RTCCR_LSERDY_Msk          (0x1UL << RCC_RTCCR_LSERDY_Pos)            /*!< 0x00000002 */
#define RCC_RTCCR_LSERDY              RCC_RTCCR_LSERDY_Msk                       /*!< LSE oscillator ready */
#define RCC_RTCCR_LSEBYP_Pos          (2U)
#define RCC_RTCCR_LSEBYP_Msk          (0x1UL << RCC_RTCCR_LSEBYP_Pos)            /*!< 0x00000004 */
#define RCC_RTCCR_LSEBYP              RCC_RTCCR_LSEBYP_Msk                       /*!< LSE oscillator bypass */
#define RCC_RTCCR_LSEDRV_Pos          (3U)
#define RCC_RTCCR_LSEDRV_Msk          (0x3UL << RCC_RTCCR_LSEDRV_Pos)            /*!< 0x00000018 */
#define RCC_RTCCR_LSEDRV              RCC_RTCCR_LSEDRV_Msk                       /*!< LSE oscillator driving capability
                                                                                      */
#define RCC_RTCCR_LSEDRV_0            (0x1UL << RCC_RTCCR_LSEDRV_Pos)            /*!< 0x00000008 */
#define RCC_RTCCR_LSEDRV_1            (0x2UL << RCC_RTCCR_LSEDRV_Pos)            /*!< 0x00000010 */
#define RCC_RTCCR_LSECSSON_Pos        (5U)
#define RCC_RTCCR_LSECSSON_Msk        (0x1UL << RCC_RTCCR_LSECSSON_Pos)          /*!< 0x00000020 */
#define RCC_RTCCR_LSECSSON            RCC_RTCCR_LSECSSON_Msk                     /*!< LSE clock security system enable
                                                                                      */
#define RCC_RTCCR_LSECSSD_Pos         (6U)
#define RCC_RTCCR_LSECSSD_Msk         (0x1UL << RCC_RTCCR_LSECSSD_Pos)           /*!< 0x00000040 */
#define RCC_RTCCR_LSECSSD             RCC_RTCCR_LSECSSD_Msk                      /*!< LSE clock security system failure
                                                                                      detection */
#define RCC_RTCCR_LSEEXT_Pos          (7U)
#define RCC_RTCCR_LSEEXT_Msk          (0x1UL << RCC_RTCCR_LSEEXT_Pos)            /*!< 0x00000080 */
#define RCC_RTCCR_LSEEXT              RCC_RTCCR_LSEEXT_Msk                       /*!< Low-speed external clock type in
                                                                                      bypass mode */
#define RCC_RTCCR_RTCSEL_Pos          (8U)
#define RCC_RTCCR_RTCSEL_Msk          (0x3UL << RCC_RTCCR_RTCSEL_Pos)            /*!< 0x00000300 */
#define RCC_RTCCR_RTCSEL              RCC_RTCCR_RTCSEL_Msk                       /*!< RTC clock source selection */
#define RCC_RTCCR_RTCSEL_0            (0x1UL << RCC_RTCCR_RTCSEL_Pos)            /*!< 0x00000100 */
#define RCC_RTCCR_RTCSEL_1            (0x2UL << RCC_RTCCR_RTCSEL_Pos)            /*!< 0x00000200 */
#define RCC_RTCCR_RTCEN_Pos           (15U)
#define RCC_RTCCR_RTCEN_Msk           (0x1UL << RCC_RTCCR_RTCEN_Pos)             /*!< 0x00008000 */
#define RCC_RTCCR_RTCEN               RCC_RTCCR_RTCEN_Msk                        /*!< RTC clock enable */
#define RCC_RTCCR_RTCDRST_Pos         (16U)
#define RCC_RTCCR_RTCDRST_Msk         (0x1UL << RCC_RTCCR_RTCDRST_Pos)           /*!< 0x00010000 */
#define RCC_RTCCR_RTCDRST             RCC_RTCCR_RTCDRST_Msk                      /*!< RTC domain software reset */
#define RCC_RTCCR_LSCOEN_Pos          (24U)
#define RCC_RTCCR_LSCOEN_Msk          (0x1UL << RCC_RTCCR_LSCOEN_Pos)            /*!< 0x01000000 */
#define RCC_RTCCR_LSCOEN              RCC_RTCCR_LSCOEN_Msk                       /*!< Low-speed clock output (LSCO)
                                                                                      enable */
#define RCC_RTCCR_LSCOSEL_Pos         (25U)
#define RCC_RTCCR_LSCOSEL_Msk         (0x1UL << RCC_RTCCR_LSCOSEL_Pos)           /*!< 0x02000000 */
#define RCC_RTCCR_LSCOSEL             RCC_RTCCR_LSCOSEL_Msk                      /*!< Low-speed clock output selection
                                                                                      */
#define RCC_RTCCR_LSION_Pos           (26U)
#define RCC_RTCCR_LSION_Msk           (0x1UL << RCC_RTCCR_LSION_Pos)             /*!< 0x04000000 */
#define RCC_RTCCR_LSION               RCC_RTCCR_LSION_Msk                        /*!< LSI oscillator enable */
#define RCC_RTCCR_LSIRDY_Pos          (27U)
#define RCC_RTCCR_LSIRDY_Msk          (0x1UL << RCC_RTCCR_LSIRDY_Pos)            /*!< 0x08000000 */
#define RCC_RTCCR_LSIRDY              RCC_RTCCR_LSIRDY_Msk                       /*!< LSI oscillator ready */

/* *************************************  Bit definition for RCC_RSR register  ************************************** */
#define RCC_RSR_Rst                   (0x00000000UL)                             /*!< RCC_RSR reset value */
#define RCC_RSR_RMVF_Pos              (23U)
#define RCC_RSR_RMVF_Msk              (0x1UL << RCC_RSR_RMVF_Pos)                /*!< 0x00800000 */
#define RCC_RSR_RMVF                  RCC_RSR_RMVF_Msk                           /*!< Remove reset flag */
#define RCC_RSR_PINRSTF_Pos           (26U)
#define RCC_RSR_PINRSTF_Msk           (0x1UL << RCC_RSR_PINRSTF_Pos)             /*!< 0x04000000 */
#define RCC_RSR_PINRSTF               RCC_RSR_PINRSTF_Msk                        /*!< Pin reset flag (NRST) */
#define RCC_RSR_BORRSTF_Pos           (27U)
#define RCC_RSR_BORRSTF_Msk           (0x1UL << RCC_RSR_BORRSTF_Pos)             /*!< 0x08000000 */
#define RCC_RSR_BORRSTF               RCC_RSR_BORRSTF_Msk                        /*!< POR reset flag */
#define RCC_RSR_SFTRSTF_Pos           (28U)
#define RCC_RSR_SFTRSTF_Msk           (0x1UL << RCC_RSR_SFTRSTF_Pos)             /*!< 0x10000000 */
#define RCC_RSR_SFTRSTF               RCC_RSR_SFTRSTF_Msk                        /*!< System reset from CPU reset flag
                                                                                      */
#define RCC_RSR_IWDGRSTF_Pos          (29U)
#define RCC_RSR_IWDGRSTF_Msk          (0x1UL << RCC_RSR_IWDGRSTF_Pos)            /*!< 0x20000000 */
#define RCC_RSR_IWDGRSTF              RCC_RSR_IWDGRSTF_Msk                       /*!< Independent watchdog reset flag */
#define RCC_RSR_WWDGRSTF_Pos          (30U)
#define RCC_RSR_WWDGRSTF_Msk          (0x1UL << RCC_RSR_WWDGRSTF_Pos)            /*!< 0x40000000 */
#define RCC_RSR_WWDGRSTF              RCC_RSR_WWDGRSTF_Msk                       /*!< Window watchdog reset flag */
#define RCC_RSR_LPWRRSTF_Pos          (31U)
#define RCC_RSR_LPWRRSTF_Msk          (0x1UL << RCC_RSR_LPWRRSTF_Pos)            /*!< 0x80000000 */
#define RCC_RSR_LPWRRSTF              RCC_RSR_LPWRRSTF_Msk                       /*!< Low-power reset flag */

/* ***********************************  Bit definition for RCC_PRIVCFGR register  *********************************** */
#define RCC_PRIVCFGR_Rst              (0x00000000UL)                             /*!< RCC_PRIVCFGR reset value */
#define RCC_PRIVCFGR_PRIV_Pos         (1U)
#define RCC_PRIVCFGR_PRIV_Msk         (0x1UL << RCC_PRIVCFGR_PRIV_Pos)           /*!< 0x00000002 */
#define RCC_PRIVCFGR_PRIV             RCC_PRIVCFGR_PRIV_Msk                      /*!< RCC function privileged
                                                                                      configuration */

/**********************************************************************************************************************/
/*                                                                                                                    */
/*                                    True random number generator (RNG)                                              */
/*                                                                                                                    */
/**********************************************************************************************************************/
#define RNG_HTCRx_VALUE                     0x0003FFFF
/********************  NIST candidate certification value *******************/
#define RNG_CAND_NIST                        (0U)
#define RNG_CAND_NIST_CR_VALUE               0x08451F00
#define RNG_CAND_NIST_NSCR_VALUE             0x000001FF
#define RNG_CAND_NIST_HTCR_VALUE             0x0000AAC7
/********************  GermanBSI candidate certification value *******************/
#define RNG_CAND_GermanBSI_CR_VALUE          0x08301F00
#define RNG_CAND_GermanBSI_NSCR_VALUE        0x000001FF
#define RNG_CAND_GermanBSI_HTCR_VALUE        0x0000AAC7

/*****************  Bit definition for RNG_CR register  ***************************************************************/
#define RNG_CR_RNGEN_Pos        (2U)
#define RNG_CR_RNGEN_Msk        (0x1UL << RNG_CR_RNGEN_Pos)            /*!< 0x00000004 */
#define RNG_CR_RNGEN            RNG_CR_RNGEN_Msk                       /*!< True random number generator enable */
#define RNG_CR_IE_Pos           (3U)
#define RNG_CR_IE_Msk           (0x1UL << RNG_CR_IE_Pos)               /*!< 0x00000008 */
#define RNG_CR_IE               RNG_CR_IE_Msk                          /*!< Interrupt enable */
#define RNG_CR_CED_Pos          (5U)
#define RNG_CR_CED_Msk          (0x1UL << RNG_CR_CED_Pos)              /*!< 0x00000020 */
#define RNG_CR_CED              RNG_CR_CED_Msk                         /*!< Clock error detection */
#define RNG_CR_ARDIS_Pos        (7U)
#define RNG_CR_ARDIS_Msk        (0x1UL << RNG_CR_ARDIS_Pos)            /*!< 0x00000080 */
#define RNG_CR_ARDIS            RNG_CR_ARDIS_Msk                       /*!< Auto reset disable */
#define RNG_CR_RNG_CONFIG3_Pos  (8U)
#define RNG_CR_RNG_CONFIG3_Msk  (0xFUL << RNG_CR_RNG_CONFIG3_Pos)      /*!< 0x00000F00 */
#define RNG_CR_RNG_CONFIG3      RNG_CR_RNG_CONFIG3_Msk                 /*!< RNG configuration 3 */
#define RNG_CR_NISTC_Pos        (12U)
#define RNG_CR_NISTC_Msk        (0x1UL << RNG_CR_NISTC_Pos)            /*!< 0x00001000 */
#define RNG_CR_NISTC            RNG_CR_NISTC_Msk                       /*!< NIST custom */
#define RNG_CR_RNG_CONFIG2_Pos  (13U)
#define RNG_CR_RNG_CONFIG2_Msk  (0x7UL << RNG_CR_RNG_CONFIG2_Pos)      /*!< 0x0000E000 */
#define RNG_CR_RNG_CONFIG2      RNG_CR_RNG_CONFIG2_Msk                 /*!< RNG configuration 2 */
#define RNG_CR_CLKDIV_Pos       (16U)
#define RNG_CR_CLKDIV_Msk       (0xFUL << RNG_CR_CLKDIV_Pos)           /*!< 0x000F0000 */
#define RNG_CR_CLKDIV           RNG_CR_CLKDIV_Msk                      /*!< Clock divider factor */
#define RNG_CR_CLKDIV_0         (0x1UL << RNG_CR_CLKDIV_Pos)           /*!< 0x00010000 */
#define RNG_CR_CLKDIV_1         (0x2UL << RNG_CR_CLKDIV_Pos)           /*!< 0x00020000 */
#define RNG_CR_CLKDIV_2         (0x4UL << RNG_CR_CLKDIV_Pos)           /*!< 0x00040000 */
#define RNG_CR_CLKDIV_3         (0x8UL << RNG_CR_CLKDIV_Pos)           /*!< 0x00080000 */
#define RNG_CR_RNG_CONFIG1_Pos  (20U)
#define RNG_CR_RNG_CONFIG1_Msk  (0xFFUL << RNG_CR_RNG_CONFIG1_Pos)     /*!< 0x0FF00000 */
#define RNG_CR_RNG_CONFIG1      RNG_CR_RNG_CONFIG1_Msk                 /*!< RNG configuration 1 */
#define RNG_CR_CONDRST_Pos      (30U)
#define RNG_CR_CONDRST_Msk      (0x1UL << RNG_CR_CONDRST_Pos)          /*!< 0x40000000 */
#define RNG_CR_CONDRST          RNG_CR_CONDRST_Msk                     /*!< Conditioning soft reset */
#define RNG_CR_CONFIGLOCK_Pos   (31U)
#define RNG_CR_CONFIGLOCK_Msk   (0x1UL << RNG_CR_CONFIGLOCK_Pos)       /*!< 0x80000000 */
#define RNG_CR_CONFIGLOCK       RNG_CR_CONFIGLOCK_Msk                  /*!< RNG configuration lock */

/*****************  Bit definition for RNG_SR register  ***************************************************************/
#define RNG_SR_DRDY_Pos         (0U)
#define RNG_SR_DRDY_Msk         (0x1UL << RNG_SR_DRDY_Pos)             /*!< 0x00000001 */
#define RNG_SR_DRDY             RNG_SR_DRDY_Msk                        /*!< Data ready */
#define RNG_SR_CECS_Pos         (1U)
#define RNG_SR_CECS_Msk         (0x1UL << RNG_SR_CECS_Pos)             /*!< 0x00000002 */
#define RNG_SR_CECS             RNG_SR_CECS_Msk                        /*!< Clock error current status */
#define RNG_SR_SECS_Pos         (2U)
#define RNG_SR_SECS_Msk         (0x1UL << RNG_SR_SECS_Pos)             /*!< 0x00000004 */
#define RNG_SR_SECS             RNG_SR_SECS_Msk                        /*!< Seed error current status */
#define RNG_SR_BUSY_Pos         (4U)
#define RNG_SR_BUSY_Msk         (0x1UL << RNG_SR_BUSY_Pos)             /*!< 0x00000010 */
#define RNG_SR_BUSY             RNG_SR_BUSY_Msk                        /*!< Busy */
#define RNG_SR_CEIS_Pos         (5U)
#define RNG_SR_CEIS_Msk         (0x1UL << RNG_SR_CEIS_Pos)             /*!< 0x00000020 */
#define RNG_SR_CEIS             RNG_SR_CEIS_Msk                        /*!< Clock error interrupt status */
#define RNG_SR_SEIS_Pos         (6U)
#define RNG_SR_SEIS_Msk         (0x1UL << RNG_SR_SEIS_Pos)             /*!< 0x00000040 */
#define RNG_SR_SEIS             RNG_SR_SEIS_Msk                        /*!< Seed error interrupt status */

/*****************  Bit definition for RNG_DR register  ***************************************************************/
#define RNG_DR_RNDATA_Pos       (0U)
#define RNG_DR_RNDATA_Msk       (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos)    /*!< 0xFFFFFFFF */
#define RNG_DR_RNDATA           RNG_DR_RNDATA_Msk                      /*!< Random data */

/*****************  Bit definition for RNG_NSCR register  *************************************************************/
#define RNG_NSCR_EN_OSC1_Pos    (0U)
#define RNG_NSCR_EN_OSC1_Msk    (0x7UL << RNG_NSCR_EN_OSC1_Pos)        /*!< 0x00000007 */
#define RNG_NSCR_EN_OSC1        RNG_NSCR_EN_OSC1_Msk                   /*!< Each bit drives one oscillator enable
                                                                            signal input of instance number 1*/
#define RNG_NSCR_EN_OSC2_Pos    (3U)
#define RNG_NSCR_EN_OSC2_Msk    (0x7UL << RNG_NSCR_EN_OSC2_Pos)        /*!< 0x00000038 */
#define RNG_NSCR_EN_OSC2        RNG_NSCR_EN_OSC2_Msk                   /*!< Each bit drives one oscillator enable
                                                                            signal input of instance number 2*/
#define RNG_NSCR_EN_OSC3_Pos    (6U)
#define RNG_NSCR_EN_OSC3_Msk    (0x7UL << RNG_NSCR_EN_OSC3_Pos)        /*!< 0x000001C0 */
#define RNG_NSCR_EN_OSC3        RNG_NSCR_EN_OSC3_Msk                   /*!< Each bit drives one oscillator enable
                                                                            signal input of instance number 3 */

/*****************  Bit definition for RNG_HTCR register  *************************************************************/
#define RNG_HTCR_HTCFG_Pos      (0U)
#define RNG_HTCR_HTCFG_Msk      (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos)    /*!< 0xFFFFFFFF */
#define RNG_HTCR_HTCFG          RNG_HTCR_HTCFG_Msk                      /*!< health test configuration */

/* ************************************  Bit definition for RNG_HTSR0 register  ************************************* */
#define RNG_HTSR0_RPERRX_Pos   (0U)
#define RNG_HTSR0_RPERRX_Msk   (0x1UL << RNG_HTSR0_RPERRX_Pos)     /*!< 0x00000001 */
#define RNG_HTSR0_RPERRX       RNG_HTSR0_RPERRX_Msk                /*!< Repetitive error after the XOR */
#define RNG_HTSR0_RPERR1_Pos   (1U)
#define RNG_HTSR0_RPERR1_Msk   (0x1UL << RNG_HTSR0_RPERR1_Pos)     /*!< 0x00000002 */
#define RNG_HTSR0_RPERR1       RNG_HTSR0_RPERR1_Msk                /*!< Repetitive error for oscillator i */
#define RNG_HTSR0_RPERR2_Pos   (2U)
#define RNG_HTSR0_RPERR2_Msk   (0x1UL << RNG_HTSR0_RPERR2_Pos)     /*!< 0x00000004 */
#define RNG_HTSR0_RPERR2       RNG_HTSR0_RPERR2_Msk                /*!< Repetitive error for oscillator i */
#define RNG_HTSR0_RPERR3_Pos   (3U)
#define RNG_HTSR0_RPERR3_Msk   (0x1UL << RNG_HTSR0_RPERR3_Pos)     /*!< 0x00000008 */
#define RNG_HTSR0_RPERR3       RNG_HTSR0_RPERR3_Msk                /*!< Repetitive error for oscillator i */
#define RNG_HTSR0_RPERR4_Pos   (4U)
#define RNG_HTSR0_RPERR4_Msk   (0x1UL << RNG_HTSR0_RPERR4_Pos)     /*!< 0x00000010 */
#define RNG_HTSR0_RPERR4       RNG_HTSR0_RPERR4_Msk                /*!< Repetitive error for oscillator i */
#define RNG_HTSR0_RPERR5_Pos   (5U)
#define RNG_HTSR0_RPERR5_Msk   (0x1UL << RNG_HTSR0_RPERR5_Pos)     /*!< 0x00000020 */
#define RNG_HTSR0_RPERR5       RNG_HTSR0_RPERR5_Msk                /*!< Repetitive error for oscillator i */
#define RNG_HTSR0_RPERR6_Pos   (6U)
#define RNG_HTSR0_RPERR6_Msk   (0x1UL << RNG_HTSR0_RPERR6_Pos)     /*!< 0x00000040 */
#define RNG_HTSR0_RPERR6       RNG_HTSR0_RPERR6_Msk                /*!< Repetitive error for oscillator i */
#define RNG_HTSR0_RPERR7_Pos   (7U)
#define RNG_HTSR0_RPERR7_Msk   (0x1UL << RNG_HTSR0_RPERR7_Pos)     /*!< 0x00000080 */
#define RNG_HTSR0_RPERR7       RNG_HTSR0_RPERR7_Msk                /*!< Repetitive error for oscillator i */
#define RNG_HTSR0_RPERR8_Pos   (8U)
#define RNG_HTSR0_RPERR8_Msk   (0x1UL << RNG_HTSR0_RPERR8_Pos)     /*!< 0x00000100 */
#define RNG_HTSR0_RPERR8       RNG_HTSR0_RPERR8_Msk                /*!< Repetitive error for oscillator i */
#define RNG_HTSR0_RPERR9_Pos   (9U)
#define RNG_HTSR0_RPERR9_Msk   (0x1UL << RNG_HTSR0_RPERR9_Pos)     /*!< 0x00000200 */
#define RNG_HTSR0_RPERR9       RNG_HTSR0_RPERR9_Msk                /*!< Repetitive error for oscillator i */

/* ************************************  Bit definition for RNG_HTSR1 register  ************************************* */
#define RNG_HTSR1_ADERRX_Pos   (0U)
#define RNG_HTSR1_ADERRX_Msk   (0x1UL << RNG_HTSR1_ADERRX_Pos)     /*!< 0x00000001 */
#define RNG_HTSR1_ADERRX       RNG_HTSR1_ADERRX_Msk                /*!< Adaptative error after the XOR */
#define RNG_HTSR1_ADERR1_Pos   (1U)
#define RNG_HTSR1_ADERR1_Msk   (0x1UL << RNG_HTSR1_ADERR1_Pos)     /*!< 0x00000002 */
#define RNG_HTSR1_ADERR1       RNG_HTSR1_ADERR1_Msk                /*!< Adaptative error for oscillator i */
#define RNG_HTSR1_ADERR2_Pos   (2U)
#define RNG_HTSR1_ADERR2_Msk   (0x1UL << RNG_HTSR1_ADERR2_Pos)     /*!< 0x00000004 */
#define RNG_HTSR1_ADERR2       RNG_HTSR1_ADERR2_Msk                /*!< Adaptative error for oscillator i */
#define RNG_HTSR1_ADERR3_Pos   (3U)
#define RNG_HTSR1_ADERR3_Msk   (0x1UL << RNG_HTSR1_ADERR3_Pos)     /*!< 0x00000008 */
#define RNG_HTSR1_ADERR3       RNG_HTSR1_ADERR3_Msk                /*!< Adaptative error for oscillator i */
#define RNG_HTSR1_ADERR4_Pos   (4U)
#define RNG_HTSR1_ADERR4_Msk   (0x1UL << RNG_HTSR1_ADERR4_Pos)     /*!< 0x00000010 */
#define RNG_HTSR1_ADERR4       RNG_HTSR1_ADERR4_Msk                /*!< Adaptative error for oscillator i */
#define RNG_HTSR1_ADERR5_Pos   (5U)
#define RNG_HTSR1_ADERR5_Msk   (0x1UL << RNG_HTSR1_ADERR5_Pos)     /*!< 0x00000020 */
#define RNG_HTSR1_ADERR5       RNG_HTSR1_ADERR5_Msk                /*!< Adaptative error for oscillator i */
#define RNG_HTSR1_ADERR6_Pos   (6U)
#define RNG_HTSR1_ADERR6_Msk   (0x1UL << RNG_HTSR1_ADERR6_Pos)     /*!< 0x00000040 */
#define RNG_HTSR1_ADERR6       RNG_HTSR1_ADERR6_Msk                /*!< Adaptative error for oscillator i */
#define RNG_HTSR1_ADERR7_Pos   (7U)
#define RNG_HTSR1_ADERR7_Msk   (0x1UL << RNG_HTSR1_ADERR7_Pos)     /*!< 0x00000080 */
#define RNG_HTSR1_ADERR7       RNG_HTSR1_ADERR7_Msk                /*!< Adaptative error for oscillator i */
#define RNG_HTSR1_ADERR8_Pos   (8U)
#define RNG_HTSR1_ADERR8_Msk   (0x1UL << RNG_HTSR1_ADERR8_Pos)     /*!< 0x00000100 */
#define RNG_HTSR1_ADERR8       RNG_HTSR1_ADERR8_Msk                /*!< Adaptative error for oscillator i */
#define RNG_HTSR1_ADERR9_Pos   (9U)
#define RNG_HTSR1_ADERR9_Msk   (0x1UL << RNG_HTSR1_ADERR9_Pos)     /*!< 0x00000200 */
#define RNG_HTSR1_ADERR9       RNG_HTSR1_ADERR9_Msk                /*!< Adaptative error for oscillator i */

/* *************************************  Bit definition for RNG_NSMR register  ************************************* */
#define RNG_NSMR_MOSC1_Pos     (0U)
#define RNG_NSMR_MOSC1_Msk     (0x1UL << RNG_NSMR_MOSC1_Pos)       /*!< 0x00000001 */
#define RNG_NSMR_MOSC1         RNG_NSMR_MOSC1_Msk                  /*!< Mask oscillator i */
#define RNG_NSMR_MOSC2_Pos     (1U)
#define RNG_NSMR_MOSC2_Msk     (0x1UL << RNG_NSMR_MOSC2_Pos)       /*!< 0x00000002 */
#define RNG_NSMR_MOSC2         RNG_NSMR_MOSC2_Msk                  /*!< Mask oscillator i */
#define RNG_NSMR_MOSC3_Pos     (2U)
#define RNG_NSMR_MOSC3_Msk     (0x1UL << RNG_NSMR_MOSC3_Pos)       /*!< 0x00000004 */
#define RNG_NSMR_MOSC3         RNG_NSMR_MOSC3_Msk                  /*!< Mask oscillator i */
#define RNG_NSMR_MOSC4_Pos     (3U)
#define RNG_NSMR_MOSC4_Msk     (0x1UL << RNG_NSMR_MOSC4_Pos)       /*!< 0x00000008 */
#define RNG_NSMR_MOSC4         RNG_NSMR_MOSC4_Msk                  /*!< Mask oscillator i */
#define RNG_NSMR_MOSC5_Pos     (4U)
#define RNG_NSMR_MOSC5_Msk     (0x1UL << RNG_NSMR_MOSC5_Pos)       /*!< 0x00000010 */
#define RNG_NSMR_MOSC5         RNG_NSMR_MOSC5_Msk                  /*!< Mask oscillator i */
#define RNG_NSMR_MOSC6_Pos     (5U)
#define RNG_NSMR_MOSC6_Msk     (0x1UL << RNG_NSMR_MOSC6_Pos)       /*!< 0x00000020 */
#define RNG_NSMR_MOSC6         RNG_NSMR_MOSC6_Msk                  /*!< Mask oscillator i */
#define RNG_NSMR_MOSC7_Pos     (6U)
#define RNG_NSMR_MOSC7_Msk     (0x1UL << RNG_NSMR_MOSC7_Pos)       /*!< 0x00000040 */
#define RNG_NSMR_MOSC7         RNG_NSMR_MOSC7_Msk                  /*!< Mask oscillator i */
#define RNG_NSMR_MOSC8_Pos     (7U)
#define RNG_NSMR_MOSC8_Msk     (0x1UL << RNG_NSMR_MOSC8_Pos)       /*!< 0x00000080 */
#define RNG_NSMR_MOSC8         RNG_NSMR_MOSC8_Msk                  /*!< Mask oscillator i */
#define RNG_NSMR_MOSC9_Pos     (8U)
#define RNG_NSMR_MOSC9_Msk     (0x1UL << RNG_NSMR_MOSC9_Pos)       /*!< 0x00000100 */
#define RNG_NSMR_MOSC9         RNG_NSMR_MOSC9_Msk                  /*!< Mask oscillator i */

/******************************************************************************/
/*                                                                            */
/*                           Real-Time Clock (RTC)                            */
/*                                                                            */
/******************************************************************************/
/********************  Bits definition for RTC_TR register  *******************/
#define RTC_TR_SU_Pos                       (0U)
#define RTC_TR_SU_Msk                       (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */
#define RTC_TR_SU                           RTC_TR_SU_Msk                           /*!< Second units in BCD format */
#define RTC_TR_SU_0                         (0x1UL << RTC_TR_SU_Pos)                /*!< 0x00000001 */
#define RTC_TR_SU_1                         (0x2UL << RTC_TR_SU_Pos)                /*!< 0x00000002 */
#define RTC_TR_SU_2                         (0x4UL << RTC_TR_SU_Pos)                /*!< 0x00000004 */
#define RTC_TR_SU_3                         (0x8UL << RTC_TR_SU_Pos)                /*!< 0x00000008 */
#define RTC_TR_ST_Pos                       (4U)
#define RTC_TR_ST_Msk                       (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */
#define RTC_TR_ST                           RTC_TR_ST_Msk                           /*!< Second tens in BCD format */
#define RTC_TR_ST_0                         (0x1UL << RTC_TR_ST_Pos)                /*!< 0x00000010 */
#define RTC_TR_ST_1                         (0x2UL << RTC_TR_ST_Pos)                /*!< 0x00000020 */
#define RTC_TR_ST_2                         (0x4UL << RTC_TR_ST_Pos)                /*!< 0x00000040 */
#define RTC_TR_MNU_Pos                      (8U)
#define RTC_TR_MNU_Msk                      (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */
#define RTC_TR_MNU                          RTC_TR_MNU_Msk                          /*!< Minute units in BCD format */
#define RTC_TR_MNU_0                        (0x1UL << RTC_TR_MNU_Pos)               /*!< 0x00000100 */
#define RTC_TR_MNU_1                        (0x2UL << RTC_TR_MNU_Pos)               /*!< 0x00000200 */
#define RTC_TR_MNU_2                        (0x4UL << RTC_TR_MNU_Pos)               /*!< 0x00000400 */
#define RTC_TR_MNU_3                        (0x8UL << RTC_TR_MNU_Pos)               /*!< 0x00000800 */
#define RTC_TR_MNT_Pos                      (12U)
#define RTC_TR_MNT_Msk                      (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */
#define RTC_TR_MNT                          RTC_TR_MNT_Msk                          /*!< Minute tens in BCD format */
#define RTC_TR_MNT_0                        (0x1UL << RTC_TR_MNT_Pos)               /*!< 0x00001000 */
#define RTC_TR_MNT_1                        (0x2UL << RTC_TR_MNT_Pos)               /*!< 0x00002000 */
#define RTC_TR_MNT_2                        (0x4UL << RTC_TR_MNT_Pos)               /*!< 0x00004000 */
#define RTC_TR_HU_Pos                       (16U)
#define RTC_TR_HU_Msk                       (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */
#define RTC_TR_HU                           RTC_TR_HU_Msk                           /*!< Hour units in BCD format */
#define RTC_TR_HU_0                         (0x1UL << RTC_TR_HU_Pos)                /*!< 0x00010000 */
#define RTC_TR_HU_1                         (0x2UL << RTC_TR_HU_Pos)                /*!< 0x00020000 */
#define RTC_TR_HU_2                         (0x4UL << RTC_TR_HU_Pos)                /*!< 0x00040000 */
#define RTC_TR_HU_3                         (0x8UL << RTC_TR_HU_Pos)                /*!< 0x00080000 */
#define RTC_TR_HT_Pos                       (20U)
#define RTC_TR_HT_Msk                       (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */
#define RTC_TR_HT                           RTC_TR_HT_Msk                           /*!< Hour tens in BCD format */
#define RTC_TR_HT_0                         (0x1UL << RTC_TR_HT_Pos)                /*!< 0x00100000 */
#define RTC_TR_HT_1                         (0x2UL << RTC_TR_HT_Pos)                /*!< 0x00200000 */
#define RTC_TR_PM_Pos                       (22U)
#define RTC_TR_PM_Msk                       (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */
#define RTC_TR_PM                           RTC_TR_PM_Msk                           /*!< AM/PM notation */

/********************  Bits definition for RTC_DR register  *******************/
#define RTC_DR_DU_Pos                       (0U)
#define RTC_DR_DU_Msk                       (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */
#define RTC_DR_DU                           RTC_DR_DU_Msk                           /*!< Date units in BCD format */
#define RTC_DR_DU_0                         (0x1UL << RTC_DR_DU_Pos)                /*!< 0x00000001 */
#define RTC_DR_DU_1                         (0x2UL << RTC_DR_DU_Pos)                /*!< 0x00000002 */
#define RTC_DR_DU_2                         (0x4UL << RTC_DR_DU_Pos)                /*!< 0x00000004 */
#define RTC_DR_DU_3                         (0x8UL << RTC_DR_DU_Pos)                /*!< 0x00000008 */
#define RTC_DR_DT_Pos                       (4U)
#define RTC_DR_DT_Msk                       (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */
#define RTC_DR_DT                           RTC_DR_DT_Msk                           /*!< Date tens in BCD format */
#define RTC_DR_DT_0                         (0x1UL << RTC_DR_DT_Pos)                /*!< 0x00000010 */
#define RTC_DR_DT_1                         (0x2UL << RTC_DR_DT_Pos)                /*!< 0x00000020 */
#define RTC_DR_MU_Pos                       (8U)
#define RTC_DR_MU_Msk                       (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */
#define RTC_DR_MU                           RTC_DR_MU_Msk                           /*!< Month units in BCD format */
#define RTC_DR_MU_0                         (0x1UL << RTC_DR_MU_Pos)                /*!< 0x00000100 */
#define RTC_DR_MU_1                         (0x2UL << RTC_DR_MU_Pos)                /*!< 0x00000200 */
#define RTC_DR_MU_2                         (0x4UL << RTC_DR_MU_Pos)                /*!< 0x00000400 */
#define RTC_DR_MU_3                         (0x8UL << RTC_DR_MU_Pos)                /*!< 0x00000800 */
#define RTC_DR_MT_Pos                       (12U)
#define RTC_DR_MT_Msk                       (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */
#define RTC_DR_MT                           RTC_DR_MT_Msk                           /*!< Month tens in BCD format */
#define RTC_DR_WDU_Pos                      (13U)
#define RTC_DR_WDU_Msk                      (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */
#define RTC_DR_WDU                          RTC_DR_WDU_Msk                          /*!< Week day units */
#define RTC_DR_WDU_0                        (0x1UL << RTC_DR_WDU_Pos)               /*!< 0x00002000 */
#define RTC_DR_WDU_1                        (0x2UL << RTC_DR_WDU_Pos)               /*!< 0x00004000 */
#define RTC_DR_WDU_2                        (0x4UL << RTC_DR_WDU_Pos)               /*!< 0x00008000 */
#define RTC_DR_YU_Pos                       (16U)
#define RTC_DR_YU_Msk                       (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */
#define RTC_DR_YU                           RTC_DR_YU_Msk                           /*!< Year units in BCD format */
#define RTC_DR_YU_0                         (0x1UL << RTC_DR_YU_Pos)                /*!< 0x00010000 */
#define RTC_DR_YU_1                         (0x2UL << RTC_DR_YU_Pos)                /*!< 0x00020000 */
#define RTC_DR_YU_2                         (0x4UL << RTC_DR_YU_Pos)                /*!< 0x00040000 */
#define RTC_DR_YU_3                         (0x8UL << RTC_DR_YU_Pos)                /*!< 0x00080000 */
#define RTC_DR_YT_Pos                       (20U)
#define RTC_DR_YT_Msk                       (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */
#define RTC_DR_YT                           RTC_DR_YT_Msk                           /*!< Year tens in BCD format */
#define RTC_DR_YT_0                         (0x1UL << RTC_DR_YT_Pos)                /*!< 0x00100000 */
#define RTC_DR_YT_1                         (0x2UL << RTC_DR_YT_Pos)                /*!< 0x00200000 */
#define RTC_DR_YT_2                         (0x4UL << RTC_DR_YT_Pos)                /*!< 0x00400000 */
#define RTC_DR_YT_3                         (0x8UL << RTC_DR_YT_Pos)                /*!< 0x00800000 */

/********************  Bits definition for RTC_SSR register  ******************/
#define RTC_SSR_SS_Pos                      (0U)
#define RTC_SSR_SS_Msk                      (0xFFFFFFFFUL << RTC_SSR_SS_Pos)        /*!< 0xFFFFFFFF */
#define RTC_SSR_SS                          RTC_SSR_SS_Msk                          /*!< Synchronous binary counter */

/********************  Bits definition for RTC_ICSR register  ******************/
#define RTC_ICSR_WUTWF_Pos                  (2U)
#define RTC_ICSR_WUTWF_Msk                  (0x1UL << RTC_ICSR_WUTWF_Pos)           /*!< 0x00000004 */
#define RTC_ICSR_WUTWF                      RTC_ICSR_WUTWF_Msk                      /*!< Wake-up timer write flag */
#define RTC_ICSR_SHPF_Pos                   (3U)
#define RTC_ICSR_SHPF_Msk                   (0x1UL << RTC_ICSR_SHPF_Pos)            /*!< 0x00000008 */
#define RTC_ICSR_SHPF                       RTC_ICSR_SHPF_Msk                       /*!< Shift operation pending */
#define RTC_ICSR_INITS_Pos                  (4U)
#define RTC_ICSR_INITS_Msk                  (0x1UL << RTC_ICSR_INITS_Pos)           /*!< 0x00000010 */
#define RTC_ICSR_INITS                      RTC_ICSR_INITS_Msk                      /*!< Initialization status flag */
#define RTC_ICSR_RSF_Pos                    (5U)
#define RTC_ICSR_RSF_Msk                    (0x1UL << RTC_ICSR_RSF_Pos)             /*!< 0x00000020 */
#define RTC_ICSR_RSF                        RTC_ICSR_RSF_Msk                        /*!< Registers synchronization flag */
#define RTC_ICSR_INITF_Pos                  (6U)
#define RTC_ICSR_INITF_Msk                  (0x1UL << RTC_ICSR_INITF_Pos)           /*!< 0x00000040 */
#define RTC_ICSR_INITF                      RTC_ICSR_INITF_Msk                      /*!< Initialization flag */
#define RTC_ICSR_INIT_Pos                   (7U)
#define RTC_ICSR_INIT_Msk                   (0x1UL << RTC_ICSR_INIT_Pos)            /*!< 0x00000080 */
#define RTC_ICSR_INIT                       RTC_ICSR_INIT_Msk                       /*!< Initialization mode */
#define RTC_ICSR_BIN_Pos                    (8U)
#define RTC_ICSR_BIN_Msk                    (0x3UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000300 */
#define RTC_ICSR_BIN                        RTC_ICSR_BIN_Msk                        /*!< Binary mode */
#define RTC_ICSR_BIN_0                      (0x1UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000100 */
#define RTC_ICSR_BIN_1                      (0x2UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000200 */
#define RTC_ICSR_BCDU_Pos                   (10U)
#define RTC_ICSR_BCDU_Msk                   (0x7UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001C00 */
#define RTC_ICSR_BCDU                       RTC_ICSR_BCDU_Msk                       /*!< BCD update (BIN = 10 or 11) */
#define RTC_ICSR_BCDU_0                     (0x1UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000400 */
#define RTC_ICSR_BCDU_1                     (0x2UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000800 */
#define RTC_ICSR_BCDU_2                     (0x4UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001000 */
#define RTC_ICSR_RECALPF_Pos                (16U)
#define RTC_ICSR_RECALPF_Msk                (0x1UL << RTC_ICSR_RECALPF_Pos)         /*!< 0x00010000 */
#define RTC_ICSR_RECALPF                    RTC_ICSR_RECALPF_Msk                    /*!< Recalibration pending Flag */

/********************  Bits definition for RTC_PRER register  *****************/
#define RTC_PRER_PREDIV_S_Pos               (0U)
#define RTC_PRER_PREDIV_S_Msk               (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */
#define RTC_PRER_PREDIV_S                   RTC_PRER_PREDIV_S_Msk                   /*!< Synchronous prescaler factor */
#define RTC_PRER_PREDIV_A_Pos               (16U)
#define RTC_PRER_PREDIV_A_Msk               (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */
#define RTC_PRER_PREDIV_A                   RTC_PRER_PREDIV_A_Msk                   /*!< Asynchronous prescaler factor */

/********************  Bits definition for RTC_WUTR register  *****************/
#define RTC_WUTR_WUT_Pos                    (0U)
#define RTC_WUTR_WUT_Msk                    (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */
#define RTC_WUTR_WUT                        RTC_WUTR_WUT_Msk                        /*!< Wake-up auto-reload value bits */
#define RTC_WUTR_WUTOCLR_Pos                (16U)
#define RTC_WUTR_WUTOCLR_Msk                (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos)      /*!< 0x0000FFFF */
#define RTC_WUTR_WUTOCLR                    RTC_WUTR_WUTOCLR_Msk                    /*!< Wake-up auto-reload output clear value */

/********************  Bits definition for RTC_CR register  *******************/
#define RTC_CR_WUCKSEL_Pos                  (0U)
#define RTC_CR_WUCKSEL_Msk                  (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */
#define RTC_CR_WUCKSEL                      RTC_CR_WUCKSEL_Msk                      /*!< ck_wut wake-up clock selection */
#define RTC_CR_WUCKSEL_0                    (0x1UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000001 */
#define RTC_CR_WUCKSEL_1                    (0x2UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2                    (0x4UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000004 */
#define RTC_CR_TSEDGE_Pos                   (3U)
#define RTC_CR_TSEDGE_Msk                   (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */
#define RTC_CR_TSEDGE                       RTC_CR_TSEDGE_Msk                       /*!< Timestamp event active edge */
#define RTC_CR_REFCKON_Pos                  (4U)
#define RTC_CR_REFCKON_Msk                  (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */
#define RTC_CR_REFCKON                      RTC_CR_REFCKON_Msk                      /*!< RTC_REFIN reference clock detection enable (50 or 60 Hz) */
#define RTC_CR_BYPSHAD_Pos                  (5U)
#define RTC_CR_BYPSHAD_Msk                  (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */
#define RTC_CR_BYPSHAD                      RTC_CR_BYPSHAD_Msk                      /*!< Bypass the shadow registers */
#define RTC_CR_FMT_Pos                      (6U)
#define RTC_CR_FMT_Msk                      (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */
#define RTC_CR_FMT                          RTC_CR_FMT_Msk                          /*!< Hour format */
#define RTC_CR_SSRUIE_Pos                   (7U)
#define RTC_CR_SSRUIE_Msk                   (0x1UL << RTC_CR_SSRUIE_Pos)            /*!< 0x00000080 */
#define RTC_CR_SSRUIE                       RTC_CR_SSRUIE_Msk                       /*!< SSR underflow interrupt enable */
#define RTC_CR_ALRAE_Pos                    (8U)
#define RTC_CR_ALRAE_Msk                    (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */
#define RTC_CR_ALRAE                        RTC_CR_ALRAE_Msk                        /*!< Alarm A enable */
#define RTC_CR_ALRBE_Pos                    (9U)
#define RTC_CR_ALRBE_Msk                    (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */
#define RTC_CR_ALRBE                        RTC_CR_ALRBE_Msk                        /*!< Alarm B enable */
#define RTC_CR_WUTE_Pos                     (10U)
#define RTC_CR_WUTE_Msk                     (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */
#define RTC_CR_WUTE                         RTC_CR_WUTE_Msk                         /*!< Wake-up timer enable */
#define RTC_CR_TSE_Pos                      (11U)
#define RTC_CR_TSE_Msk                      (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */
#define RTC_CR_TSE                          RTC_CR_TSE_Msk                          /*!< timestamp enable */
#define RTC_CR_ALRAIE_Pos                   (12U)
#define RTC_CR_ALRAIE_Msk                   (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */
#define RTC_CR_ALRAIE                       RTC_CR_ALRAIE_Msk                       /*!< Alarm A interrupt enable */
#define RTC_CR_ALRBIE_Pos                   (13U)
#define RTC_CR_ALRBIE_Msk                   (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */
#define RTC_CR_ALRBIE                       RTC_CR_ALRBIE_Msk                       /*!< Alarm B interrupt enable */
#define RTC_CR_WUTIE_Pos                    (14U)
#define RTC_CR_WUTIE_Msk                    (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */
#define RTC_CR_WUTIE                        RTC_CR_WUTIE_Msk                        /*!< Wake-up timer interrupt enable */
#define RTC_CR_TSIE_Pos                     (15U)
#define RTC_CR_TSIE_Msk                     (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */
#define RTC_CR_TSIE                         RTC_CR_TSIE_Msk                         /*!< Timestamp interrupt enable */
#define RTC_CR_ADD1H_Pos                    (16U)
#define RTC_CR_ADD1H_Msk                    (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */
#define RTC_CR_ADD1H                        RTC_CR_ADD1H_Msk                        /*!< Add 1 hour (summer time change) */
#define RTC_CR_SUB1H_Pos                    (17U)
#define RTC_CR_SUB1H_Msk                    (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */
#define RTC_CR_SUB1H                        RTC_CR_SUB1H_Msk                        /*!< Subtract 1 hour (winter time change) */
#define RTC_CR_BKP_Pos                      (18U)
#define RTC_CR_BKP_Msk                      (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */
#define RTC_CR_BKP                          RTC_CR_BKP_Msk                          /*!< Backup */
#define RTC_CR_COSEL_Pos                    (19U)
#define RTC_CR_COSEL_Msk                    (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */
#define RTC_CR_COSEL                        RTC_CR_COSEL_Msk                        /*!< Calibration output selection */
#define RTC_CR_POL_Pos                      (20U)
#define RTC_CR_POL_Msk                      (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */
#define RTC_CR_POL                          RTC_CR_POL_Msk                          /*!< Output polarity */
#define RTC_CR_OSEL_Pos                     (21U)
#define RTC_CR_OSEL_Msk                     (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */
#define RTC_CR_OSEL                         RTC_CR_OSEL_Msk                         /*!< Output selection */
#define RTC_CR_OSEL_0                       (0x1UL << RTC_CR_OSEL_Pos)              /*!< 0x00200000 */
#define RTC_CR_OSEL_1                       (0x2UL << RTC_CR_OSEL_Pos)              /*!< 0x00400000 */
#define RTC_CR_COE_Pos                      (23U)
#define RTC_CR_COE_Msk                      (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */
#define RTC_CR_COE                          RTC_CR_COE_Msk                          /*!< Calibration output enable */
#define RTC_CR_TAMPTS_Pos                   (25U)
#define RTC_CR_TAMPTS_Msk                   (0x1UL << RTC_CR_TAMPTS_Pos)            /*!< 0x02000000 */
#define RTC_CR_TAMPTS                       RTC_CR_TAMPTS_Msk                       /*!<Activate timestamp on tamper detection event  */
#define RTC_CR_TAMPOE_Pos                   (26U)
#define RTC_CR_TAMPOE_Msk                   (0x1UL << RTC_CR_TAMPOE_Pos)            /*!< 0x04000000 */
#define RTC_CR_TAMPOE                       RTC_CR_TAMPOE_Msk                       /*!<Tamper detection output enable on TAMPALARM  */
#define RTC_CR_ALRAFCLR_Pos                 (27U)
#define RTC_CR_ALRAFCLR_Msk                 (0x1UL << RTC_CR_ALRAFCLR_Pos)          /*!< 0x8000000 */
#define RTC_CR_ALRAFCLR                     RTC_CR_ALRAFCLR_Msk                     /*!<Alarm A mask */
#define RTC_CR_ALRBFCLR_Pos                 (28U)
#define RTC_CR_ALRBFCLR_Msk                 (0x1UL << RTC_CR_ALRBFCLR_Pos)          /*!< 0x10000000 */
#define RTC_CR_ALRBFCLR                     RTC_CR_ALRBFCLR_Msk                     /*!<Alarm B mask */
#define RTC_CR_TAMPALRM_PU_Pos              (29U)
#define RTC_CR_TAMPALRM_PU_Msk              (0x1UL << RTC_CR_TAMPALRM_PU_Pos)       /*!< 0x20000000 */
#define RTC_CR_TAMPALRM_PU                  RTC_CR_TAMPALRM_PU_Msk                  /*!<TAMPALARM output pull-up config */
#define RTC_CR_TAMPALRM_TYPE_Pos            (30U)
#define RTC_CR_TAMPALRM_TYPE_Msk            (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)     /*!< 0x40000000 */
#define RTC_CR_TAMPALRM_TYPE                RTC_CR_TAMPALRM_TYPE_Msk                /*!<TAMPALARM output type  */
#define RTC_CR_OUT2EN_Pos                   (31U)
#define RTC_CR_OUT2EN_Msk                   (0x1UL << RTC_CR_OUT2EN_Pos)            /*!< 0x80000000 */
#define RTC_CR_OUT2EN                       RTC_CR_OUT2EN_Msk                       /*!<RTC_OUT2 output enable */

/********************  Bits definition for RTC_PRIVCFGR register  *****************/
#define RTC_PRIVCFGR_ALRAPRIV_Pos           (0U)
#define RTC_PRIVCFGR_ALRAPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRAPRIV_Pos)    /*!< 0x00000001 */
#define RTC_PRIVCFGR_ALRAPRIV               RTC_PRIVCFGR_ALRAPRIV_Msk               /*!< Alarm A and SSR underflow privilege protection */
#define RTC_PRIVCFGR_ALRBPRIV_Pos           (1U)
#define RTC_PRIVCFGR_ALRBPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRBPRIV_Pos)    /*!< 0x00000002 */
#define RTC_PRIVCFGR_ALRBPRIV               RTC_PRIVCFGR_ALRBPRIV_Msk               /*!< Alarm B privilege protection */
#define RTC_PRIVCFGR_WUTPRIV_Pos            (2U)
#define RTC_PRIVCFGR_WUTPRIV_Msk            (0x1UL << RTC_PRIVCFGR_WUTPRIV_Pos)     /*!< 0x00000004 */
#define RTC_PRIVCFGR_WUTPRIV                RTC_PRIVCFGR_WUTPRIV_Msk                /*!< Wake-up timer privilege protection */
#define RTC_PRIVCFGR_TSPRIV_Pos             (3U)
#define RTC_PRIVCFGR_TSPRIV_Msk             (0x1UL << RTC_PRIVCFGR_TSPRIV_Pos)      /*!< 0x00000008 */
#define RTC_PRIVCFGR_TSPRIV                 RTC_PRIVCFGR_TSPRIV_Msk                 /*!< Timestamp privilege protection */
#define RTC_PRIVCFGR_CALPRIV_Pos            (13U)
#define RTC_PRIVCFGR_CALPRIV_Msk            (0x1UL << RTC_PRIVCFGR_CALPRIV_Pos)     /*!< 0x00002000 */
#define RTC_PRIVCFGR_CALPRIV                RTC_PRIVCFGR_CALPRIV_Msk                /*!< Shift register, Delight saving, calibration and reference clock privilege protection */
#define RTC_PRIVCFGR_INITPRIV_Pos           (14U)
#define RTC_PRIVCFGR_INITPRIV_Msk           (0x1UL << RTC_PRIVCFGR_INITPRIV_Pos)    /*!< 0x00004000 */
#define RTC_PRIVCFGR_INITPRIV               RTC_PRIVCFGR_INITPRIV_Msk               /*!< Initialization privilege protection */
#define RTC_PRIVCFGR_PRIV_Pos               (15U)
#define RTC_PRIVCFGR_PRIV_Msk               (0x1UL << RTC_PRIVCFGR_PRIV_Pos)        /*!< 0x00008000 */
#define RTC_PRIVCFGR_PRIV                   RTC_PRIVCFGR_PRIV_Msk                   /*!< RTC privilege protection */

/********************  Bits definition for RTC_WPR register  ******************/
#define RTC_WPR_KEY_Pos                     (0U)
#define RTC_WPR_KEY_Msk                     (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */
#define RTC_WPR_KEY                         RTC_WPR_KEY_Msk                         /*!< Write protection key */

/********************  Bits definition for RTC_CALR register  *****************/
#define RTC_CALR_CALM_Pos                   (0U)
#define RTC_CALR_CALM_Msk                   (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */
#define RTC_CALR_CALM                       RTC_CALR_CALM_Msk                       /*!< Calibration minus */
#define RTC_CALR_CALM_0                     (0x001UL << RTC_CALR_CALM_Pos)          /*!< 0x00000001 */
#define RTC_CALR_CALM_1                     (0x002UL << RTC_CALR_CALM_Pos)          /*!< 0x00000002 */
#define RTC_CALR_CALM_2                     (0x004UL << RTC_CALR_CALM_Pos)          /*!< 0x00000004 */
#define RTC_CALR_CALM_3                     (0x008UL << RTC_CALR_CALM_Pos)          /*!< 0x00000008 */
#define RTC_CALR_CALM_4                     (0x010UL << RTC_CALR_CALM_Pos)          /*!< 0x00000010 */
#define RTC_CALR_CALM_5                     (0x020UL << RTC_CALR_CALM_Pos)          /*!< 0x00000020 */
#define RTC_CALR_CALM_6                     (0x040UL << RTC_CALR_CALM_Pos)          /*!< 0x00000040 */
#define RTC_CALR_CALM_7                     (0x080UL << RTC_CALR_CALM_Pos)          /*!< 0x00000080 */
#define RTC_CALR_CALM_8                     (0x100UL << RTC_CALR_CALM_Pos)          /*!< 0x00000100 */
#define RTC_CALR_LPCAL_Pos                  (12U)
#define RTC_CALR_LPCAL_Msk                  (0x1UL << RTC_CALR_LPCAL_Pos)           /*!< 0x00001000 */
#define RTC_CALR_LPCAL                      RTC_CALR_LPCAL_Msk                      /*!< RTC low-power mode */
#define RTC_CALR_CALW16_Pos                 (13U)
#define RTC_CALR_CALW16_Msk                 (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */
#define RTC_CALR_CALW16                     RTC_CALR_CALW16_Msk                     /*!< Use a 16-second calibration cycle period */
#define RTC_CALR_CALW8_Pos                  (14U)
#define RTC_CALR_CALW8_Msk                  (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */
#define RTC_CALR_CALW8                      RTC_CALR_CALW8_Msk                      /*!< Use an 8-second calibration cycle period */
#define RTC_CALR_CALP_Pos                   (15U)
#define RTC_CALR_CALP_Msk                   (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */
#define RTC_CALR_CALP                       RTC_CALR_CALP_Msk                       /*!< Increase frequency of RTC by 488.5 ppm */

/********************  Bits definition for RTC_SHIFTR register  ***************/
#define RTC_SHIFTR_SUBFS_Pos                (0U)
#define RTC_SHIFTR_SUBFS_Msk                (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */
#define RTC_SHIFTR_SUBFS                    RTC_SHIFTR_SUBFS_Msk                    /*!< Subtract a fraction of a second */
#define RTC_SHIFTR_ADD1S_Pos                (31U)
#define RTC_SHIFTR_ADD1S_Msk                (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */
#define RTC_SHIFTR_ADD1S                    RTC_SHIFTR_ADD1S_Msk                    /*!< Add one second */

/********************  Bits definition for RTC_TSTR register  *****************/
#define RTC_TSTR_SU_Pos                     (0U)
#define RTC_TSTR_SU_Msk                     (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */
#define RTC_TSTR_SU                         RTC_TSTR_SU_Msk                         /*!< Second units in BCD format. */
#define RTC_TSTR_SU_0                       (0x1UL << RTC_TSTR_SU_Pos)              /*!< 0x00000001 */
#define RTC_TSTR_SU_1                       (0x2UL << RTC_TSTR_SU_Pos)              /*!< 0x00000002 */
#define RTC_TSTR_SU_2                       (0x4UL << RTC_TSTR_SU_Pos)              /*!< 0x00000004 */
#define RTC_TSTR_SU_3                       (0x8UL << RTC_TSTR_SU_Pos)              /*!< 0x00000008 */
#define RTC_TSTR_ST_Pos                     (4U)
#define RTC_TSTR_ST_Msk                     (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */
#define RTC_TSTR_ST                         RTC_TSTR_ST_Msk                         /*!< Second tens in BCD format. */
#define RTC_TSTR_ST_0                       (0x1UL << RTC_TSTR_ST_Pos)              /*!< 0x00000010 */
#define RTC_TSTR_ST_1                       (0x2UL << RTC_TSTR_ST_Pos)              /*!< 0x00000020 */
#define RTC_TSTR_ST_2                       (0x4UL << RTC_TSTR_ST_Pos)              /*!< 0x00000040 */
#define RTC_TSTR_MNU_Pos                    (8U)
#define RTC_TSTR_MNU_Msk                    (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */
#define RTC_TSTR_MNU                        RTC_TSTR_MNU_Msk                        /*!< Minute units in BCD format. */
#define RTC_TSTR_MNU_0                      (0x1UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000100 */
#define RTC_TSTR_MNU_1                      (0x2UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000200 */
#define RTC_TSTR_MNU_2                      (0x4UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000400 */
#define RTC_TSTR_MNU_3                      (0x8UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000800 */
#define RTC_TSTR_MNT_Pos                    (12U)
#define RTC_TSTR_MNT_Msk                    (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */
#define RTC_TSTR_MNT                        RTC_TSTR_MNT_Msk                        /*!< Minute tens in BCD format. */
#define RTC_TSTR_MNT_0                      (0x1UL << RTC_TSTR_MNT_Pos)             /*!< 0x00001000 */
#define RTC_TSTR_MNT_1                      (0x2UL << RTC_TSTR_MNT_Pos)             /*!< 0x00002000 */
#define RTC_TSTR_MNT_2                      (0x4UL << RTC_TSTR_MNT_Pos)             /*!< 0x00004000 */
#define RTC_TSTR_HU_Pos                     (16U)
#define RTC_TSTR_HU_Msk                     (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */
#define RTC_TSTR_HU                         RTC_TSTR_HU_Msk                         /*!< Hour units in BCD format. */
#define RTC_TSTR_HU_0                       (0x1UL << RTC_TSTR_HU_Pos)              /*!< 0x00010000 */
#define RTC_TSTR_HU_1                       (0x2UL << RTC_TSTR_HU_Pos)              /*!< 0x00020000 */
#define RTC_TSTR_HU_2                       (0x4UL << RTC_TSTR_HU_Pos)              /*!< 0x00040000 */
#define RTC_TSTR_HU_3                       (0x8UL << RTC_TSTR_HU_Pos)              /*!< 0x00080000 */
#define RTC_TSTR_HT_Pos                     (20U)
#define RTC_TSTR_HT_Msk                     (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */
#define RTC_TSTR_HT                         RTC_TSTR_HT_Msk                         /*!< Hour tens in BCD format. */
#define RTC_TSTR_HT_0                       (0x1UL << RTC_TSTR_HT_Pos)              /*!< 0x00100000 */
#define RTC_TSTR_HT_1                       (0x2UL << RTC_TSTR_HT_Pos)              /*!< 0x00200000 */
#define RTC_TSTR_PM_Pos                     (22U)
#define RTC_TSTR_PM_Msk                     (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */
#define RTC_TSTR_PM                         RTC_TSTR_PM_Msk                         /*!< AM/PM notation */

/********************  Bits definition for RTC_TSDR register  *****************/
#define RTC_TSDR_DU_Pos                     (0U)
#define RTC_TSDR_DU_Msk                     (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */
#define RTC_TSDR_DU                         RTC_TSDR_DU_Msk                         /*!< Date units in BCD format */
#define RTC_TSDR_DU_0                       (0x1UL << RTC_TSDR_DU_Pos)              /*!< 0x00000001 */
#define RTC_TSDR_DU_1                       (0x2UL << RTC_TSDR_DU_Pos)              /*!< 0x00000002 */
#define RTC_TSDR_DU_2                       (0x4UL << RTC_TSDR_DU_Pos)              /*!< 0x00000004 */
#define RTC_TSDR_DU_3                       (0x8UL << RTC_TSDR_DU_Pos)              /*!< 0x00000008 */
#define RTC_TSDR_DT_Pos                     (4U)
#define RTC_TSDR_DT_Msk                     (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */
#define RTC_TSDR_DT                         RTC_TSDR_DT_Msk                         /*!< Date tens in BCD format */
#define RTC_TSDR_DT_0                       (0x1UL << RTC_TSDR_DT_Pos)              /*!< 0x00000010 */
#define RTC_TSDR_DT_1                       (0x2UL << RTC_TSDR_DT_Pos)              /*!< 0x00000020 */
#define RTC_TSDR_MU_Pos                     (8U)
#define RTC_TSDR_MU_Msk                     (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */
#define RTC_TSDR_MU                         RTC_TSDR_MU_Msk                         /*!< Month units in BCD format */
#define RTC_TSDR_MU_0                       (0x1UL << RTC_TSDR_MU_Pos)              /*!< 0x00000100 */
#define RTC_TSDR_MU_1                       (0x2UL << RTC_TSDR_MU_Pos)              /*!< 0x00000200 */
#define RTC_TSDR_MU_2                       (0x4UL << RTC_TSDR_MU_Pos)              /*!< 0x00000400 */
#define RTC_TSDR_MU_3                       (0x8UL << RTC_TSDR_MU_Pos)              /*!< 0x00000800 */
#define RTC_TSDR_MT_Pos                     (12U)
#define RTC_TSDR_MT_Msk                     (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */
#define RTC_TSDR_MT                         RTC_TSDR_MT_Msk                         /*!< Month tens in BCD format */
#define RTC_TSDR_WDU_Pos                    (13U)
#define RTC_TSDR_WDU_Msk                    (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */
#define RTC_TSDR_WDU                        RTC_TSDR_WDU_Msk                        /*!< Week day units */
#define RTC_TSDR_WDU_0                      (0x1UL << RTC_TSDR_WDU_Pos)             /*!< 0x00002000 */
#define RTC_TSDR_WDU_1                      (0x2UL << RTC_TSDR_WDU_Pos)             /*!< 0x00004000 */
#define RTC_TSDR_WDU_2                      (0x4UL << RTC_TSDR_WDU_Pos)             /*!< 0x00008000 */

/********************  Bits definition for RTC_TSSSR register  ****************/
#define RTC_TSSSR_SS_Pos                    (0U)
#define RTC_TSSSR_SS_Msk                    (0xFFFFFFFFUL << RTC_TSSSR_SS_Pos)      /*!< 0xFFFFFFFF */
#define RTC_TSSSR_SS                        RTC_TSSSR_SS_Msk                        /*!< Subsecond value/synchronous binary counter values */

/********************  Bits definition for RTC_ALRMAR register  ***************/
#define RTC_ALRMAR_SU_Pos                   (0U)
#define RTC_ALRMAR_SU_Msk                   (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */
#define RTC_ALRMAR_SU                       RTC_ALRMAR_SU_Msk                       /*!< Second units in BCD format. */
#define RTC_ALRMAR_SU_0                     (0x1UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000001 */
#define RTC_ALRMAR_SU_1                     (0x2UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000002 */
#define RTC_ALRMAR_SU_2                     (0x4UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000004 */
#define RTC_ALRMAR_SU_3                     (0x8UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000008 */
#define RTC_ALRMAR_ST_Pos                   (4U)
#define RTC_ALRMAR_ST_Msk                   (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */
#define RTC_ALRMAR_ST                       RTC_ALRMAR_ST_Msk                       /*!< Second tens in BCD format. */
#define RTC_ALRMAR_ST_0                     (0x1UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000010 */
#define RTC_ALRMAR_ST_1                     (0x2UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000020 */
#define RTC_ALRMAR_ST_2                     (0x4UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000040 */
#define RTC_ALRMAR_MSK1_Pos                 (7U)
#define RTC_ALRMAR_MSK1_Msk                 (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */
#define RTC_ALRMAR_MSK1                     RTC_ALRMAR_MSK1_Msk                     /*!< Alarm A seconds mask */
#define RTC_ALRMAR_MNU_Pos                  (8U)
#define RTC_ALRMAR_MNU_Msk                  (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */
#define RTC_ALRMAR_MNU                      RTC_ALRMAR_MNU_Msk                      /*!< Minute units in BCD format */
#define RTC_ALRMAR_MNU_0                    (0x1UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000100 */
#define RTC_ALRMAR_MNU_1                    (0x2UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000200 */
#define RTC_ALRMAR_MNU_2                    (0x4UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000400 */
#define RTC_ALRMAR_MNU_3                    (0x8UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000800 */
#define RTC_ALRMAR_MNT_Pos                  (12U)
#define RTC_ALRMAR_MNT_Msk                  (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */
#define RTC_ALRMAR_MNT                      RTC_ALRMAR_MNT_Msk                      /*!< Minute tens in BCD format */
#define RTC_ALRMAR_MNT_0                    (0x1UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00001000 */
#define RTC_ALRMAR_MNT_1                    (0x2UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00002000 */
#define RTC_ALRMAR_MNT_2                    (0x4UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00004000 */
#define RTC_ALRMAR_MSK2_Pos                 (15U)
#define RTC_ALRMAR_MSK2_Msk                 (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */
#define RTC_ALRMAR_MSK2                     RTC_ALRMAR_MSK2_Msk                     /*!< Alarm A minutes mask */
#define RTC_ALRMAR_HU_Pos                   (16U)
#define RTC_ALRMAR_HU_Msk                   (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */
#define RTC_ALRMAR_HU                       RTC_ALRMAR_HU_Msk                       /*!< Hour units in BCD format */
#define RTC_ALRMAR_HU_0                     (0x1UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00010000 */
#define RTC_ALRMAR_HU_1                     (0x2UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00020000 */
#define RTC_ALRMAR_HU_2                     (0x4UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00040000 */
#define RTC_ALRMAR_HU_3                     (0x8UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00080000 */
#define RTC_ALRMAR_HT_Pos                   (20U)
#define RTC_ALRMAR_HT_Msk                   (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */
#define RTC_ALRMAR_HT                       RTC_ALRMAR_HT_Msk                       /*!< Hour tens in BCD format */
#define RTC_ALRMAR_HT_0                     (0x1UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00100000 */
#define RTC_ALRMAR_HT_1                     (0x2UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00200000 */
#define RTC_ALRMAR_PM_Pos                   (22U)
#define RTC_ALRMAR_PM_Msk                   (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */
#define RTC_ALRMAR_PM                       RTC_ALRMAR_PM_Msk                       /*!< AM/PM notation */
#define RTC_ALRMAR_MSK3_Pos                 (23U)
#define RTC_ALRMAR_MSK3_Msk                 (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */
#define RTC_ALRMAR_MSK3                     RTC_ALRMAR_MSK3_Msk                     /*!< Alarm A hours mask */
#define RTC_ALRMAR_DU_Pos                   (24U)
#define RTC_ALRMAR_DU_Msk                   (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */
#define RTC_ALRMAR_DU                       RTC_ALRMAR_DU_Msk                       /*!< Date units or day in BCD format */
#define RTC_ALRMAR_DU_0                     (0x1UL << RTC_ALRMAR_DU_Pos)            /*!< 0x01000000 */
#define RTC_ALRMAR_DU_1                     (0x2UL << RTC_ALRMAR_DU_Pos)            /*!< 0x02000000 */
#define RTC_ALRMAR_DU_2                     (0x4UL << RTC_ALRMAR_DU_Pos)            /*!< 0x04000000 */
#define RTC_ALRMAR_DU_3                     (0x8UL << RTC_ALRMAR_DU_Pos)            /*!< 0x08000000 */
#define RTC_ALRMAR_DT_Pos                   (28U)
#define RTC_ALRMAR_DT_Msk                   (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */
#define RTC_ALRMAR_DT                       RTC_ALRMAR_DT_Msk                       /*!< Date tens in BCD format */
#define RTC_ALRMAR_DT_0                     (0x1UL << RTC_ALRMAR_DT_Pos)            /*!< 0x10000000 */
#define RTC_ALRMAR_DT_1                     (0x2UL << RTC_ALRMAR_DT_Pos)            /*!< 0x20000000 */
#define RTC_ALRMAR_WDSEL_Pos                (30U)
#define RTC_ALRMAR_WDSEL_Msk                (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */
#define RTC_ALRMAR_WDSEL                    RTC_ALRMAR_WDSEL_Msk                    /*!< Week day selection */
#define RTC_ALRMAR_MSK4_Pos                 (31U)
#define RTC_ALRMAR_MSK4_Msk                 (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */
#define RTC_ALRMAR_MSK4                     RTC_ALRMAR_MSK4_Msk                     /*!< Alarm A date mask */

/********************  Bits definition for RTC_ALRMASSR register  *************/
#define RTC_ALRMASSR_SS_Pos                 (0U)
#define RTC_ALRMASSR_SS_Msk                 (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */
#define RTC_ALRMASSR_SS                     RTC_ALRMASSR_SS_Msk                     /*!< Subseconds value */
#define RTC_ALRMASSR_MASKSS_Pos             (24U)
#define RTC_ALRMASSR_MASKSS_Msk             (0x3FUL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x3F000000 */
#define RTC_ALRMASSR_MASKSS                 RTC_ALRMASSR_MASKSS_Msk                 /*!< Mask the most-significant bits starting at this bit */
#define RTC_ALRMASSR_MASKSS_0               (0x1UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x01000000 */
#define RTC_ALRMASSR_MASKSS_1               (0x2UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x02000000 */
#define RTC_ALRMASSR_MASKSS_2               (0x4UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x04000000 */
#define RTC_ALRMASSR_MASKSS_3               (0x8UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x08000000 */
#define RTC_ALRMASSR_MASKSS_4               (0x10UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x10000000 */
#define RTC_ALRMASSR_MASKSS_5               (0x20UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x20000000 */
#define RTC_ALRMASSR_SSCLR_Pos              (31U)
#define RTC_ALRMASSR_SSCLR_Msk              (0x1UL << RTC_ALRMASSR_SSCLR_Pos)       /*!< 0x80000000 */
#define RTC_ALRMASSR_SSCLR                  RTC_ALRMASSR_SSCLR_Msk                  /*!< Clear synchronous counter on alarm (Binary mode only) */

/********************  Bits definition for RTC_ALRMBR register  ***************/
#define RTC_ALRMBR_SU_Pos                   (0U)
#define RTC_ALRMBR_SU_Msk                   (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */
#define RTC_ALRMBR_SU                       RTC_ALRMBR_SU_Msk                       /*!< Second units in BCD format */
#define RTC_ALRMBR_SU_0                     (0x1UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000001 */
#define RTC_ALRMBR_SU_1                     (0x2UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000002 */
#define RTC_ALRMBR_SU_2                     (0x4UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000004 */
#define RTC_ALRMBR_SU_3                     (0x8UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000008 */
#define RTC_ALRMBR_ST_Pos                   (4U)
#define RTC_ALRMBR_ST_Msk                   (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */
#define RTC_ALRMBR_ST                       RTC_ALRMBR_ST_Msk                       /*!< Second tens in BCD format */
#define RTC_ALRMBR_ST_0                     (0x1UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000010 */
#define RTC_ALRMBR_ST_1                     (0x2UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000020 */
#define RTC_ALRMBR_ST_2                     (0x4UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000040 */
#define RTC_ALRMBR_MSK1_Pos                 (7U)
#define RTC_ALRMBR_MSK1_Msk                 (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */
#define RTC_ALRMBR_MSK1                     RTC_ALRMBR_MSK1_Msk                     /*!< Alarm B seconds mask */
#define RTC_ALRMBR_MNU_Pos                  (8U)
#define RTC_ALRMBR_MNU_Msk                  (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */
#define RTC_ALRMBR_MNU                      RTC_ALRMBR_MNU_Msk                      /*!< Minute units in BCD format */
#define RTC_ALRMBR_MNU_0                    (0x1UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000100 */
#define RTC_ALRMBR_MNU_1                    (0x2UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000200 */
#define RTC_ALRMBR_MNU_2                    (0x4UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000400 */
#define RTC_ALRMBR_MNU_3                    (0x8UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000800 */
#define RTC_ALRMBR_MNT_Pos                  (12U)
#define RTC_ALRMBR_MNT_Msk                  (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */
#define RTC_ALRMBR_MNT                      RTC_ALRMBR_MNT_Msk                      /*!< Minute tens in BCD format */
#define RTC_ALRMBR_MNT_0                    (0x1UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00001000 */
#define RTC_ALRMBR_MNT_1                    (0x2UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00002000 */
#define RTC_ALRMBR_MNT_2                    (0x4UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00004000 */
#define RTC_ALRMBR_MSK2_Pos                 (15U)
#define RTC_ALRMBR_MSK2_Msk                 (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */
#define RTC_ALRMBR_MSK2                     RTC_ALRMBR_MSK2_Msk                     /*!< Alarm B minutes mask */
#define RTC_ALRMBR_HU_Pos                   (16U)
#define RTC_ALRMBR_HU_Msk                   (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */
#define RTC_ALRMBR_HU                       RTC_ALRMBR_HU_Msk                       /*!< Hour units in BCD format */
#define RTC_ALRMBR_HU_0                     (0x1UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00010000 */
#define RTC_ALRMBR_HU_1                     (0x2UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00020000 */
#define RTC_ALRMBR_HU_2                     (0x4UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00040000 */
#define RTC_ALRMBR_HU_3                     (0x8UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00080000 */
#define RTC_ALRMBR_HT_Pos                   (20U)
#define RTC_ALRMBR_HT_Msk                   (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */
#define RTC_ALRMBR_HT                       RTC_ALRMBR_HT_Msk                       /*!< Hour tens in BCD format */
#define RTC_ALRMBR_HT_0                     (0x1UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00100000 */
#define RTC_ALRMBR_HT_1                     (0x2UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00200000 */
#define RTC_ALRMBR_PM_Pos                   (22U)
#define RTC_ALRMBR_PM_Msk                   (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */
#define RTC_ALRMBR_PM                       RTC_ALRMBR_PM_Msk                       /*!< AM/PM notation */
#define RTC_ALRMBR_MSK3_Pos                 (23U)
#define RTC_ALRMBR_MSK3_Msk                 (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */
#define RTC_ALRMBR_MSK3                     RTC_ALRMBR_MSK3_Msk                     /*!< Alarm B hours mask */
#define RTC_ALRMBR_DU_Pos                   (24U)
#define RTC_ALRMBR_DU_Msk                   (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */
#define RTC_ALRMBR_DU                       RTC_ALRMBR_DU_Msk                       /*!< Date units or day in BCD format */
#define RTC_ALRMBR_DU_0                     (0x1UL << RTC_ALRMBR_DU_Pos)            /*!< 0x01000000 */
#define RTC_ALRMBR_DU_1                     (0x2UL << RTC_ALRMBR_DU_Pos)            /*!< 0x02000000 */
#define RTC_ALRMBR_DU_2                     (0x4UL << RTC_ALRMBR_DU_Pos)            /*!< 0x04000000 */
#define RTC_ALRMBR_DU_3                     (0x8UL << RTC_ALRMBR_DU_Pos)            /*!< 0x08000000 */
#define RTC_ALRMBR_DT_Pos                   (28U)
#define RTC_ALRMBR_DT_Msk                   (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */
#define RTC_ALRMBR_DT                       RTC_ALRMBR_DT_Msk                       /*!< Date tens in BCD format */
#define RTC_ALRMBR_DT_0                     (0x1UL << RTC_ALRMBR_DT_Pos)            /*!< 0x10000000 */
#define RTC_ALRMBR_DT_1                     (0x2UL << RTC_ALRMBR_DT_Pos)            /*!< 0x20000000 */
#define RTC_ALRMBR_WDSEL_Pos                (30U)
#define RTC_ALRMBR_WDSEL_Msk                (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */
#define RTC_ALRMBR_WDSEL                    RTC_ALRMBR_WDSEL_Msk                    /*!< Week day selection */
#define RTC_ALRMBR_MSK4_Pos                 (31U)
#define RTC_ALRMBR_MSK4_Msk                 (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */
#define RTC_ALRMBR_MSK4                     RTC_ALRMBR_MSK4_Msk                     /*!< Alarm B date mask */

/********************  Bits definition for RTC_ALRMBSSR register  *************/
#define RTC_ALRMBSSR_SS_Pos                 (0U)
#define RTC_ALRMBSSR_SS_Msk                 (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */
#define RTC_ALRMBSSR_SS                     RTC_ALRMBSSR_SS_Msk                     /*!< Subseconds value */
#define RTC_ALRMBSSR_MASKSS_Pos             (24U)
#define RTC_ALRMBSSR_MASKSS_Msk             (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x3F000000 */
#define RTC_ALRMBSSR_MASKSS                 RTC_ALRMBSSR_MASKSS_Msk                 /*!< Mask the most-significant bits starting at this bit */
#define RTC_ALRMBSSR_MASKSS_0               (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x01000000 */
#define RTC_ALRMBSSR_MASKSS_1               (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x02000000 */
#define RTC_ALRMBSSR_MASKSS_2               (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x04000000 */
#define RTC_ALRMBSSR_MASKSS_3               (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x08000000 */
#define RTC_ALRMBSSR_MASKSS_4               (0x10UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x10000000 */
#define RTC_ALRMBSSR_MASKSS_5               (0x20UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x20000000 */
#define RTC_ALRMBSSR_SSCLR_Pos              (31U)
#define RTC_ALRMBSSR_SSCLR_Msk              (0x1UL << RTC_ALRMBSSR_SSCLR_Pos)       /*!< 0x80000000 */
#define RTC_ALRMBSSR_SSCLR                  RTC_ALRMBSSR_SSCLR_Msk                  /*!< Clear synchronous counter on alarm (Binary mode only) */

/********************  Bits definition for RTC_SR register  *******************/
#define RTC_SR_ALRAF_Pos                    (0U)
#define RTC_SR_ALRAF_Msk                    (0x1UL << RTC_SR_ALRAF_Pos)             /*!< 0x00000001 */
#define RTC_SR_ALRAF                        RTC_SR_ALRAF_Msk                        /*!< Alarm A flag */
#define RTC_SR_ALRBF_Pos                    (1U)
#define RTC_SR_ALRBF_Msk                    (0x1UL << RTC_SR_ALRBF_Pos)             /*!< 0x00000002 */
#define RTC_SR_ALRBF                        RTC_SR_ALRBF_Msk                        /*!< Alarm B flag */
#define RTC_SR_WUTF_Pos                     (2U)
#define RTC_SR_WUTF_Msk                     (0x1UL << RTC_SR_WUTF_Pos)              /*!< 0x00000004 */
#define RTC_SR_WUTF                         RTC_SR_WUTF_Msk                         /*!< Wake-up timer flag */
#define RTC_SR_TSF_Pos                      (3U)
#define RTC_SR_TSF_Msk                      (0x1UL << RTC_SR_TSF_Pos)               /*!< 0x00000008 */
#define RTC_SR_TSF                          RTC_SR_TSF_Msk                          /*!< Timestamp flag */
#define RTC_SR_TSOVF_Pos                    (4U)
#define RTC_SR_TSOVF_Msk                    (0x1UL << RTC_SR_TSOVF_Pos)             /*!< 0x00000010 */
#define RTC_SR_TSOVF                        RTC_SR_TSOVF_Msk                        /*!< Timestamp overflow flag */
#define RTC_SR_ITSF_Pos                     (5U)
#define RTC_SR_ITSF_Msk                     (0x1UL << RTC_SR_ITSF_Pos)              /*!< 0x00000020 */
#define RTC_SR_ITSF                         RTC_SR_ITSF_Msk
#define RTC_SR_SSRUF_Pos                    (6U)
#define RTC_SR_SSRUF_Msk                    (0x1UL << RTC_SR_SSRUF_Pos)             /*!< 0x00000040 */
#define RTC_SR_SSRUF                        RTC_SR_SSRUF_Msk                        /*!< SSR underflow flag */

/********************  Bits definition for RTC_MISR register  *****************/
#define RTC_MISR_ALRAMF_Pos                 (0U)
#define RTC_MISR_ALRAMF_Msk                 (0x1UL << RTC_MISR_ALRAMF_Pos)          /*!< 0x00000001 */
#define RTC_MISR_ALRAMF                     RTC_MISR_ALRAMF_Msk                     /*!< Alarm A masked flag */
#define RTC_MISR_ALRBMF_Pos                 (1U)
#define RTC_MISR_ALRBMF_Msk                 (0x1UL << RTC_MISR_ALRBMF_Pos)          /*!< 0x00000002 */
#define RTC_MISR_ALRBMF                     RTC_MISR_ALRBMF_Msk                     /*!< Alarm B masked flag */
#define RTC_MISR_WUTMF_Pos                  (2U)
#define RTC_MISR_WUTMF_Msk                  (0x1UL << RTC_MISR_WUTMF_Pos)           /*!< 0x00000004 */
#define RTC_MISR_WUTMF                      RTC_MISR_WUTMF_Msk                      /*!< Wake-up timer masked flag */
#define RTC_MISR_TSMF_Pos                   (3U)
#define RTC_MISR_TSMF_Msk                   (0x1UL << RTC_MISR_TSMF_Pos)            /*!< 0x00000008 */
#define RTC_MISR_TSMF                       RTC_MISR_TSMF_Msk                       /*!< Timestamp masked flag */
#define RTC_MISR_TSOVMF_Pos                 (4U)
#define RTC_MISR_TSOVMF_Msk                 (0x1UL << RTC_MISR_TSOVMF_Pos)          /*!< 0x00000010 */
#define RTC_MISR_TSOVMF                     RTC_MISR_TSOVMF_Msk                     /*!< Timestamp overflow masked flag */
#define RTC_MISR_ITSMF_Pos                  (5U)
#define RTC_MISR_ITSMF_Msk                  (0x1UL << RTC_MISR_ITSMF_Pos)           /*!< 0x00000020 */
#define RTC_MISR_ITSMF                      RTC_MISR_ITSMF_Msk
#define RTC_MISR_SSRUMF_Pos                 (6U)
#define RTC_MISR_SSRUMF_Msk                 (0x1UL << RTC_MISR_SSRUMF_Pos)          /*!< 0x00000040 */
#define RTC_MISR_SSRUMF                     RTC_MISR_SSRUMF_Msk                     /*!< SSR underflow masked flag */

/********************  Bits definition for RTC_SCR register  ******************/
#define RTC_SCR_CALRAF_Pos                  (0U)
#define RTC_SCR_CALRAF_Msk                  (0x1UL << RTC_SCR_CALRAF_Pos)           /*!< 0x00000001 */
#define RTC_SCR_CALRAF                      RTC_SCR_CALRAF_Msk                      /*!< Clear alarm A flag */
#define RTC_SCR_CALRBF_Pos                  (1U)
#define RTC_SCR_CALRBF_Msk                  (0x1UL << RTC_SCR_CALRBF_Pos)           /*!< 0x00000002 */
#define RTC_SCR_CALRBF                      RTC_SCR_CALRBF_Msk                      /*!< Clear alarm B flag */
#define RTC_SCR_CWUTF_Pos                   (2U)
#define RTC_SCR_CWUTF_Msk                   (0x1UL << RTC_SCR_CWUTF_Pos)            /*!< 0x00000004 */
#define RTC_SCR_CWUTF                       RTC_SCR_CWUTF_Msk                       /*!< Clear wake-up timer flag */
#define RTC_SCR_CTSF_Pos                    (3U)
#define RTC_SCR_CTSF_Msk                    (0x1UL << RTC_SCR_CTSF_Pos)             /*!< 0x00000008 */
#define RTC_SCR_CTSF                        RTC_SCR_CTSF_Msk                        /*!< Clear timestamp flag */
#define RTC_SCR_CTSOVF_Pos                  (4U)
#define RTC_SCR_CTSOVF_Msk                  (0x1UL << RTC_SCR_CTSOVF_Pos)           /*!< 0x00000010 */
#define RTC_SCR_CTSOVF                      RTC_SCR_CTSOVF_Msk                      /*!< Clear timestamp overflow flag */
#define RTC_SCR_CITSF_Pos                   (5U)
#define RTC_SCR_CITSF_Msk                   (0x1UL << RTC_SCR_CITSF_Pos)            /*!< 0x00000020 */
#define RTC_SCR_CITSF                       RTC_SCR_CITSF_Msk                       /*!< Clear timestamp overflow flag */
#define RTC_SCR_CSSRUF_Pos                  (6U)
#define RTC_SCR_CSSRUF_Msk                  (0x1UL << RTC_SCR_CSSRUF_Pos)           /*!< 0x00000040 */
#define RTC_SCR_CSSRUF                      RTC_SCR_CSSRUF_Msk                      /*!< Clear SSR underflow flag */

/********************  Bits definition for RTC_ALRABINR register  ******************/
#define RTC_ALRABINR_SS_Pos                 (0U)
#define RTC_ALRABINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos)   /*!< 0xFFFFFFFF */
#define RTC_ALRABINR_SS                     RTC_ALRABINR_SS_Msk                     /*!< Synchronous counter alarm value in Binary mode */

/********************  Bits definition for RTC_ALRBBINR register  ******************/
#define RTC_ALRBBINR_SS_Pos                 (0U)
#define RTC_ALRBBINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos)   /*!< 0xFFFFFFFF */
#define RTC_ALRBBINR_SS                     RTC_ALRBBINR_SS_Msk                     /*!< Synchronous counter alarm value in Binary mode */

/* ****************************************************************************************************************** */
/*                                                                                                                    */
/*                                   System configuration, boot and security (SBS)                                    */
/*                                                                                                                    */
/* ****************************************************************************************************************** */
/* ************************************  Bit definition for SBS_HDPLCR register  ************************************ */
#define SBS_HDPLCR_INCR_HDPL_Pos               (0U)
#define SBS_HDPLCR_INCR_HDPL_Msk               (0xFFUL << SBS_HDPLCR_INCR_HDPL_Pos)                /*!< 0x000000FF */
#define SBS_HDPLCR_INCR_HDPL                   SBS_HDPLCR_INCR_HDPL_Msk                            /*!< HDPL value
                                                                                                        increment */

/* ************************************  Bit definition for SBS_HDPLSR register  ************************************ */
#define SBS_HDPLSR_HDPL_Pos                    (0U)
#define SBS_HDPLSR_HDPL_Msk                    (0xFFUL << SBS_HDPLSR_HDPL_Pos)                     /*!< 0x000000FF */
#define SBS_HDPLSR_HDPL                        SBS_HDPLSR_HDPL_Msk                                 /*!< Temporal
                                                                                                        isolation level
                                                                                                        */

/* *************************************  Bit definition for SBS_PMCR register  ************************************* */

/* ************************************  Bit definition for SBS_FPUIMR register  ************************************ */
#define SBS_FPUIMR_FPU_IE_Pos                  (0U)
#define SBS_FPUIMR_FPU_IE_Msk                  (0x3FUL << SBS_FPUIMR_FPU_IE_Pos)                   /*!< 0x0000003F */
#define SBS_FPUIMR_FPU_IE                      SBS_FPUIMR_FPU_IE_Msk                               /*!< FPU interrupt
                                                                                                        enable */
#define SBS_FPUIMR_FPU_IE_0                    (0x1UL << SBS_FPUIMR_FPU_IE_Pos)                    /*!< 0x00000001 */
#define SBS_FPUIMR_FPU_IE_1                    (0x2UL << SBS_FPUIMR_FPU_IE_Pos)                    /*!< 0x00000002 */
#define SBS_FPUIMR_FPU_IE_2                    (0x4UL << SBS_FPUIMR_FPU_IE_Pos)                    /*!< 0x00000004 */
#define SBS_FPUIMR_FPU_IE_3                    (0x8UL << SBS_FPUIMR_FPU_IE_Pos)                    /*!< 0x00000008 */
#define SBS_FPUIMR_FPU_IE_4                    (0x10UL << SBS_FPUIMR_FPU_IE_Pos)                   /*!< 0x00000010 */
#define SBS_FPUIMR_FPU_IE_5                    (0x20UL << SBS_FPUIMR_FPU_IE_Pos)                   /*!< 0x00000020 */

/* *************************************  Bit definition for SBS_MESR register  ************************************* */
#define SBS_MESR_MCLR_Pos                      (0U)
#define SBS_MESR_MCLR_Msk                      (0x1UL << SBS_MESR_MCLR_Pos)                        /*!< 0x00000001 */
#define SBS_MESR_MCLR                          SBS_MESR_MCLR_Msk                                   /*!< Device memories
                                                                                                        erase status */
#define SBS_MESR_IPMEE_Pos                     (16U)
#define SBS_MESR_IPMEE_Msk                     (0x1UL << SBS_MESR_IPMEE_Pos)                       /*!< 0x00010000 */
#define SBS_MESR_IPMEE                         SBS_MESR_IPMEE_Msk                                  /*!< ICACHE erase
                                                                                                        status */

/* ************************************  Bit definition for SBS_CCCSR register  ************************************* */
#define SBS_CCCSR_EN1_Pos                      (0U)
#define SBS_CCCSR_EN1_Msk                      (0x1UL << SBS_CCCSR_EN1_Pos)                        /*!< 0x00000001 */
#define SBS_CCCSR_EN1                          SBS_CCCSR_EN1_Msk                                   /*!< Enable
                                                                                                        compensation
                                                                                                        cell for VDDIO
                                                                                                        power rail */
#define SBS_CCCSR_CS1_Pos                      (1U)
#define SBS_CCCSR_CS1_Msk                      (0x1UL << SBS_CCCSR_CS1_Pos)                        /*!< 0x00000002 */
#define SBS_CCCSR_CS1                          SBS_CCCSR_CS1_Msk                                   /*!< Code selection
                                                                                                        for VDDIO power
                                                                                                        rail (reset
                                                                                                        value set to 1)
                                                                                                        */
#define SBS_CCCSR_RDY1_Pos                     (8U)
#define SBS_CCCSR_RDY1_Msk                     (0x1UL << SBS_CCCSR_RDY1_Pos)                       /*!< 0x00000100 */
#define SBS_CCCSR_RDY1                         SBS_CCCSR_RDY1_Msk                                  /*!< VDDIO
                                                                                                        compensation
                                                                                                        cell ready flag
                                                                                                        */

/* ************************************  Bit definition for SBS_CCVALR register  ************************************ */
#define SBS_CCVALR_ANSRC1_Pos                  (0U)
#define SBS_CCVALR_ANSRC1_Msk                  (0xFUL << SBS_CCVALR_ANSRC1_Pos)                    /*!< 0x0000000F */
#define SBS_CCVALR_ANSRC1                      SBS_CCVALR_ANSRC1_Msk                               /*!< Compensation
                                                                                                        value for the
                                                                                                        NMOS transistor
                                                                                                        */
#define SBS_CCVALR_APSRC1_Pos                  (4U)
#define SBS_CCVALR_APSRC1_Msk                  (0xFUL << SBS_CCVALR_APSRC1_Pos)                    /*!< 0x000000F0 */
#define SBS_CCVALR_APSRC1                      SBS_CCVALR_APSRC1_Msk                               /*!< Compensation
                                                                                                        value for the
                                                                                                        PMOS transistor
                                                                                                        */

/* ************************************  Bit definition for SBS_CCSWCR register  ************************************ */
#define SBS_CCSWCR_SW_ANSRC1_Pos               (0U)
#define SBS_CCSWCR_SW_ANSRC1_Msk               (0xFUL << SBS_CCSWCR_SW_ANSRC1_Pos)                 /*!< 0x0000000F */
#define SBS_CCSWCR_SW_ANSRC1                   SBS_CCSWCR_SW_ANSRC1_Msk                            /*!< NMOS
                                                                                                        compensation
                                                                                                        code for VDD
                                                                                                        power rails */
#define SBS_CCSWCR_SW_APSRC1_Pos               (4U)
#define SBS_CCSWCR_SW_APSRC1_Msk               (0xFUL << SBS_CCSWCR_SW_APSRC1_Pos)                 /*!< 0x000000F0 */
#define SBS_CCSWCR_SW_APSRC1                   SBS_CCSWCR_SW_APSRC1_Msk                            /*!< PMOS
                                                                                                        compensation
                                                                                                        code for the VDD
                                                                                                        power rails */

/* ************************************  Bit definition for SBS_CFGR2 register  ************************************* */
#define SBS_CFGR2_CLL_Pos                      (0U)
#define SBS_CFGR2_CLL_Msk                      (0x1UL << SBS_CFGR2_CLL_Pos)                        /*!< 0x00000001 */
#define SBS_CFGR2_CLL                          SBS_CFGR2_CLL_Msk                                   /*!< Core lockup lock
                                                                                                        */
#define SBS_CFGR2_SEL_Pos                      (1U)
#define SBS_CFGR2_SEL_Msk                      (0x1UL << SBS_CFGR2_SEL_Pos)                        /*!< 0x00000002 */
#define SBS_CFGR2_SEL                          SBS_CFGR2_SEL_Msk                                   /*!< SRAM ECC error
                                                                                                        lock */
#define SBS_CFGR2_PVDL_Pos                     (2U)
#define SBS_CFGR2_PVDL_Msk                     (0x1UL << SBS_CFGR2_PVDL_Pos)                       /*!< 0x00000004 */
#define SBS_CFGR2_PVDL                         SBS_CFGR2_PVDL_Msk                                  /*!< PVD lock */
#define SBS_CFGR2_ECCL_Pos                     (3U)
#define SBS_CFGR2_ECCL_Msk                     (0x1UL << SBS_CFGR2_ECCL_Pos)                       /*!< 0x00000008 */
#define SBS_CFGR2_ECCL                         SBS_CFGR2_ECCL_Msk                                  /*!< ECC lock */

/* ************************************  Bit definition for SBS_CLCKR register  ************************************* */
#define SBS_CLCKR_LOCKVTOR_Pos                 (0U)
#define SBS_CLCKR_LOCKVTOR_Msk                 (0x1UL << SBS_CLCKR_LOCKVTOR_Pos)                   /*!< 0x00000001 */
#define SBS_CLCKR_LOCKVTOR                     SBS_CLCKR_LOCKVTOR_Msk                              /*!< VTOR register
                                                                                                        lock */
#define SBS_CLCKR_LOCKMPU_Pos                  (1U)
#define SBS_CLCKR_LOCKMPU_Msk                  (0x1UL << SBS_CLCKR_LOCKMPU_Pos)                    /*!< 0x00000002 */
#define SBS_CLCKR_LOCKMPU                      SBS_CLCKR_LOCKMPU_Msk                               /*!< MPU register
                                                                                                        lock */

/* ***********************************  Bit definition for SBS_ECCNMIR register  ************************************ */
#define SBS_ECCNMIR_ECCNMI_MASK_EN_Pos         (0U)
#define SBS_ECCNMIR_ECCNMI_MASK_EN_Msk         (0x1UL << SBS_ECCNMIR_ECCNMI_MASK_EN_Pos)           /*!< 0x00000001 */
#define SBS_ECCNMIR_ECCNMI_MASK_EN             SBS_ECCNMIR_ECCNMI_MASK_EN_Msk                      /*!< NMI behavior
                                                                                                        setup when a
                                                                                                        double ECC error
                                                                                                        occurs on FLASH
                                                                                                        data part */

/******************************************************************************/
/*                                                                            */
/*                     Serial Peripheral Interface (SPI)                      */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for SPI_CR1 register  ********************/
#define SPI_CR1_SPE_Pos                     (0U)
#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)              /*!< 0x00000001 */
#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                         /*!<Serial Peripheral Enable */
#define SPI_CR1_MASRX_Pos                   (8U)
#define SPI_CR1_MASRX_Msk                   (0x1UL << SPI_CR1_MASRX_Pos)            /*!< 0x00000100 */
#define SPI_CR1_MASRX                       SPI_CR1_MASRX_Msk                       /*!<Master automatic SUSP in Receive mode */
#define SPI_CR1_CSTART_Pos                  (9U)
#define SPI_CR1_CSTART_Msk                  (0x1UL << SPI_CR1_CSTART_Pos)           /*!< 0x00000200 */
#define SPI_CR1_CSTART                      SPI_CR1_CSTART_Msk                      /*!<Master transfer start  */
#define SPI_CR1_CSUSP_Pos                   (10U)
#define SPI_CR1_CSUSP_Msk                   (0x1UL << SPI_CR1_CSUSP_Pos)            /*!< 0x00000400 */
#define SPI_CR1_CSUSP                       SPI_CR1_CSUSP_Msk                       /*!<Master SUSPend request */
#define SPI_CR1_HDDIR_Pos                   (11U)
#define SPI_CR1_HDDIR_Msk                   (0x1UL << SPI_CR1_HDDIR_Pos)            /*!< 0x00000800 */
#define SPI_CR1_HDDIR                       SPI_CR1_HDDIR_Msk                       /*!<Rx/Tx direction at Half-duplex mode */
#define SPI_CR1_SSI_Pos                     (12U)
#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)              /*!< 0x00001000 */
#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                         /*!<Internal SS signal input level */
#define SPI_CR1_CRC33_17_Pos                (13U)
#define SPI_CR1_CRC33_17_Msk                (0x1UL << SPI_CR1_CRC33_17_Pos)         /*!< 0x00002000 */
#define SPI_CR1_CRC33_17                    SPI_CR1_CRC33_17_Msk                    /*!<32-bit CRC polynomial configuration */
#define SPI_CR1_RCRCINI_Pos                 (14U)
#define SPI_CR1_RCRCINI_Msk                 (0x1UL << SPI_CR1_RCRCINI_Pos)          /*!< 0x00004000 */
#define SPI_CR1_RCRCINI                     SPI_CR1_RCRCINI_Msk                     /*!<CRC init pattern control for receiver */
#define SPI_CR1_TCRCINI_Pos                 (15U)
#define SPI_CR1_TCRCINI_Msk                 (0x1UL << SPI_CR1_TCRCINI_Pos)          /*!< 0x00008000 */
#define SPI_CR1_TCRCINI                     SPI_CR1_TCRCINI_Msk                     /*!<CRC init pattern control for transmitter */
#define SPI_CR1_IOLOCK_Pos                  (16U)
#define SPI_CR1_IOLOCK_Msk                  (0x1UL << SPI_CR1_IOLOCK_Pos)           /*!< 0x00010000 */
#define SPI_CR1_IOLOCK                      SPI_CR1_IOLOCK_Msk                      /*!<Locking the AF configuration of associated IOs */

/*******************  Bit definition for SPI_CR2 register  ********************/
#define SPI_CR2_TSIZE_Pos                   (0U)
#define SPI_CR2_TSIZE_Msk                   (0xFFFFUL << SPI_CR2_TSIZE_Pos)         /*!< 0x0000FFFF */
#define SPI_CR2_TSIZE                       SPI_CR2_TSIZE_Msk                       /*!<Number of data at current transfer */

/*******************  Bit definition for SPI_CFG1 register  ********************/
#define SPI_CFG1_DSIZE_Pos                  (0U)
#define SPI_CFG1_DSIZE_Msk                  (0x1FUL << SPI_CFG1_DSIZE_Pos)          /*!< 0x0000001F */
#define SPI_CFG1_DSIZE                      SPI_CFG1_DSIZE_Msk                      /*!<DSIZE[4:0]: Bits number in single SPI data frame */
#define SPI_CFG1_DSIZE_0                    (0x01UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000001 */
#define SPI_CFG1_DSIZE_1                    (0x02UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000002 */
#define SPI_CFG1_DSIZE_2                    (0x04UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000004 */
#define SPI_CFG1_DSIZE_3                    (0x08UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000008 */
#define SPI_CFG1_DSIZE_4                    (0x10UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000010 */
#define SPI_CFG1_FTHLV_Pos                  (5U)
#define SPI_CFG1_FTHLV_Msk                  (0xFUL << SPI_CFG1_FTHLV_Pos)           /*!< 0x000001E0 */
#define SPI_CFG1_FTHLV                      SPI_CFG1_FTHLV_Msk                      /*!<FTHVL [3:0]: FIFO threshold level*/
#define SPI_CFG1_FTHLV_0                    (0x1UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000020 */
#define SPI_CFG1_FTHLV_1                    (0x2UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000040 */
#define SPI_CFG1_FTHLV_2                    (0x4UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000080 */
#define SPI_CFG1_FTHLV_3                    (0x8UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000100 */
#define SPI_CFG1_UDRCFG_Pos                 (9U)
#define SPI_CFG1_UDRCFG_Msk                 (0x1UL << SPI_CFG1_UDRCFG_Pos)          /*!< 0x00000600 */
#define SPI_CFG1_UDRCFG                     SPI_CFG1_UDRCFG_Msk                     /*!<Behavior of Slave transmitter at underrun */
#define SPI_CFG1_RXDMAEN_Pos                (14U)
#define SPI_CFG1_RXDMAEN_Msk                (0x1UL << SPI_CFG1_RXDMAEN_Pos)         /*!< 0x00004000 */
#define SPI_CFG1_RXDMAEN                    SPI_CFG1_RXDMAEN_Msk                    /*!<Rx DMA stream enable */
#define SPI_CFG1_TXDMAEN_Pos                (15U)
#define SPI_CFG1_TXDMAEN_Msk                (0x1UL << SPI_CFG1_TXDMAEN_Pos)         /*!< 0x00008000 */
#define SPI_CFG1_TXDMAEN                    SPI_CFG1_TXDMAEN_Msk                    /*!<Tx DMA stream enable */
#define SPI_CFG1_CRCSIZE_Pos                (16U)
#define SPI_CFG1_CRCSIZE_Msk                (0x1FUL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x001F0000 */
#define SPI_CFG1_CRCSIZE                    SPI_CFG1_CRCSIZE_Msk                    /*!<CRCSIZE [4:0]: Length of CRC frame */
#define SPI_CFG1_CRCSIZE_0                  (0x01UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00010000 */
#define SPI_CFG1_CRCSIZE_1                  (0x02UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00020000 */
#define SPI_CFG1_CRCSIZE_2                  (0x04UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00040000 */
#define SPI_CFG1_CRCSIZE_3                  (0x08UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00080000 */
#define SPI_CFG1_CRCSIZE_4                  (0x10UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00100000 */
#define SPI_CFG1_CRCEN_Pos                  (22U)
#define SPI_CFG1_CRCEN_Msk                  (0x1UL << SPI_CFG1_CRCEN_Pos)           /*!< 0x00400000 */
#define SPI_CFG1_CRCEN                      SPI_CFG1_CRCEN_Msk                      /*!<Hardware CRC computation enable */
#define SPI_CFG1_DRDS_Pos                   (24U)
#define SPI_CFG1_DRDS_Msk                   (0x1UL << SPI_CFG1_DRDS_Pos)            /*!< 0x00400000 */
#define SPI_CFG1_DRDS                       SPI_CFG1_DRDS_Msk                       /*!<Delay Read Data Sampling */
#define SPI_CFG1_MBR_Pos                    (28U)
#define SPI_CFG1_MBR_Msk                    (0x7UL << SPI_CFG1_MBR_Pos)             /*!< 0x70000000 */
#define SPI_CFG1_MBR                        SPI_CFG1_MBR_Msk                        /*!<Master baud rate */
#define SPI_CFG1_MBR_0                      (0x1UL << SPI_CFG1_MBR_Pos)             /*!< 0x10000000 */
#define SPI_CFG1_MBR_1                      (0x2UL << SPI_CFG1_MBR_Pos)             /*!< 0x20000000 */
#define SPI_CFG1_MBR_2                      (0x4UL << SPI_CFG1_MBR_Pos)             /*!< 0x40000000 */
#define SPI_CFG1_BPASS_Pos                  (31U)
#define SPI_CFG1_BPASS_Msk                  (0x1UL << SPI_CFG1_BPASS_Pos)           /*!< 0x80000000 */
#define SPI_CFG1_BPASS                      SPI_CFG1_BPASS_Msk                      /*!<Bypass of the prescaler */

/*******************  Bit definition for SPI_CFG2 register  ********************/
#define SPI_CFG2_MSSI_Pos                   (0U)
#define SPI_CFG2_MSSI_Msk                   (0xFUL << SPI_CFG2_MSSI_Pos)            /*!< 0x0000000F */
#define SPI_CFG2_MSSI                       SPI_CFG2_MSSI_Msk                       /*!<Master SS Idleness */
#define SPI_CFG2_MSSI_0                     (0x1UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000001 */
#define SPI_CFG2_MSSI_1                     (0x2UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000002 */
#define SPI_CFG2_MSSI_2                     (0x4UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000004 */
#define SPI_CFG2_MSSI_3                     (0x8UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000008 */
#define SPI_CFG2_MIDI_Pos                   (4U)
#define SPI_CFG2_MIDI_Msk                   (0xFUL << SPI_CFG2_MIDI_Pos)            /*!< 0x000000F0 */
#define SPI_CFG2_MIDI                       SPI_CFG2_MIDI_Msk                       /*!<Master Inter-Data Idleness */
#define SPI_CFG2_MIDI_0                     (0x1UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000010 */
#define SPI_CFG2_MIDI_1                     (0x2UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000020 */
#define SPI_CFG2_MIDI_2                     (0x4UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000040 */
#define SPI_CFG2_MIDI_3                     (0x8UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000080 */
#define SPI_CFG2_RDIOM_Pos                  (13U)
#define SPI_CFG2_RDIOM_Msk                  (0x1UL << SPI_CFG2_RDIOM_Pos)           /*!< 0x00002000 */
#define SPI_CFG2_RDIOM                      SPI_CFG2_RDIOM_Msk                      /*!<RDY signal input/output management */
#define SPI_CFG2_RDIOP_Pos                  (14U)
#define SPI_CFG2_RDIOP_Msk                  (0x1UL << SPI_CFG2_RDIOP_Pos)           /*!< 0x00004000 */
#define SPI_CFG2_RDIOP                      SPI_CFG2_RDIOP_Msk                      /*!<RDY signal input/output polarity */
#define SPI_CFG2_IOSWP_Pos                  (15U)
#define SPI_CFG2_IOSWP_Msk                  (0x1UL << SPI_CFG2_IOSWP_Pos)           /*!< 0x00008000 */
#define SPI_CFG2_IOSWP                      SPI_CFG2_IOSWP_Msk                      /*!<Swap functionality of MISO and MOSI pins */
#define SPI_CFG2_COMM_Pos                   (17U)
#define SPI_CFG2_COMM_Msk                   (0x3UL << SPI_CFG2_COMM_Pos)            /*!< 0x00060000 */
#define SPI_CFG2_COMM                       SPI_CFG2_COMM_Msk                       /*!<COMM [1:0]: SPI Communication Mode*/
#define SPI_CFG2_COMM_0                     (0x1UL << SPI_CFG2_COMM_Pos)            /*!< 0x00020000 */
#define SPI_CFG2_COMM_1                     (0x2UL << SPI_CFG2_COMM_Pos)            /*!< 0x00040000 */
#define SPI_CFG2_SP_Pos                     (19U)
#define SPI_CFG2_SP_Msk                     (0x7UL << SPI_CFG2_SP_Pos)              /*!< 0x00380000 */
#define SPI_CFG2_SP                         SPI_CFG2_SP_Msk                         /*!<SP[2:0]: Serial Protocol */
#define SPI_CFG2_SP_0                       (0x1UL << SPI_CFG2_SP_Pos)              /*!< 0x00080000 */
#define SPI_CFG2_SP_1                       (0x2UL << SPI_CFG2_SP_Pos)              /*!< 0x00100000 */
#define SPI_CFG2_SP_2                       (0x4UL << SPI_CFG2_SP_Pos)              /*!< 0x00200000 */
#define SPI_CFG2_MASTER_Pos                 (22U)
#define SPI_CFG2_MASTER_Msk                 (0x1UL << SPI_CFG2_MASTER_Pos)          /*!< 0x00400000 */
#define SPI_CFG2_MASTER                     SPI_CFG2_MASTER_Msk                     /*!<SPI Master */
#define SPI_CFG2_LSBFRST_Pos                (23U)
#define SPI_CFG2_LSBFRST_Msk                (0x1UL << SPI_CFG2_LSBFRST_Pos)         /*!< 0x00800000 */
#define SPI_CFG2_LSBFRST                    SPI_CFG2_LSBFRST_Msk                    /*!<Data frame format */
#define SPI_CFG2_CPHA_Pos                   (24U)
#define SPI_CFG2_CPHA_Msk                   (0x1UL << SPI_CFG2_CPHA_Pos)            /*!< 0x01000000 */
#define SPI_CFG2_CPHA                       SPI_CFG2_CPHA_Msk                       /*!<Clock Phase */
#define SPI_CFG2_CPOL_Pos                   (25U)
#define SPI_CFG2_CPOL_Msk                   (0x1UL << SPI_CFG2_CPOL_Pos)            /*!< 0x02000000 */
#define SPI_CFG2_CPOL                       SPI_CFG2_CPOL_Msk                       /*!<Clock Polarity */
#define SPI_CFG2_SSM_Pos                    (26U)
#define SPI_CFG2_SSM_Msk                    (0x1UL << SPI_CFG2_SSM_Pos)             /*!< 0x04000000 */
#define SPI_CFG2_SSM                        SPI_CFG2_SSM_Msk                        /*!<Software slave management */
#define SPI_CFG2_SSIOP_Pos                  (28U)
#define SPI_CFG2_SSIOP_Msk                  (0x1UL << SPI_CFG2_SSIOP_Pos)           /*!< 0x10000000 */
#define SPI_CFG2_SSIOP                      SPI_CFG2_SSIOP_Msk                      /*!<SS input/output polarity */
#define SPI_CFG2_SSOE_Pos                   (29U)
#define SPI_CFG2_SSOE_Msk                   (0x1UL << SPI_CFG2_SSOE_Pos)            /*!< 0x20000000 */
#define SPI_CFG2_SSOE                       SPI_CFG2_SSOE_Msk                       /*!<SS output enable */
#define SPI_CFG2_SSOM_Pos                   (30U)
#define SPI_CFG2_SSOM_Msk                   (0x1UL << SPI_CFG2_SSOM_Pos)            /*!< 0x40000000 */
#define SPI_CFG2_SSOM                       SPI_CFG2_SSOM_Msk                       /*!<SS output management in master mode */
#define SPI_CFG2_AFCNTR_Pos                 (31U)
#define SPI_CFG2_AFCNTR_Msk                 (0x1UL << SPI_CFG2_AFCNTR_Pos)          /*!< 0x80000000 */
#define SPI_CFG2_AFCNTR                     SPI_CFG2_AFCNTR_Msk                     /*!<Alternate function GPIOs control */

/*******************  Bit definition for SPI_IER register  ********************/
#define SPI_IER_RXPIE_Pos                   (0U)
#define SPI_IER_RXPIE_Msk                   (0x1UL << SPI_IER_RXPIE_Pos)            /*!< 0x00000001 */
#define SPI_IER_RXPIE                       SPI_IER_RXPIE_Msk                       /*!<RXP Interrupt Enable */
#define SPI_IER_TXPIE_Pos                   (1U)
#define SPI_IER_TXPIE_Msk                   (0x1UL << SPI_IER_TXPIE_Pos)            /*!< 0x00000002 */
#define SPI_IER_TXPIE                       SPI_IER_TXPIE_Msk                       /*!<TXP interrupt enable */
#define SPI_IER_DXPIE_Pos                   (2U)
#define SPI_IER_DXPIE_Msk                   (0x1UL << SPI_IER_DXPIE_Pos)            /*!< 0x00000004 */
#define SPI_IER_DXPIE                       SPI_IER_DXPIE_Msk                       /*!<DXP interrupt enable */
#define SPI_IER_EOTIE_Pos                   (3U)
#define SPI_IER_EOTIE_Msk                   (0x1UL << SPI_IER_EOTIE_Pos)            /*!< 0x00000008 */
#define SPI_IER_EOTIE                       SPI_IER_EOTIE_Msk                       /*!<EOT/SUSP/TXC interrupt enable */
#define SPI_IER_TXTFIE_Pos                  (4U)
#define SPI_IER_TXTFIE_Msk                  (0x1UL << SPI_IER_TXTFIE_Pos)           /*!< 0x00000010 */
#define SPI_IER_TXTFIE                      SPI_IER_TXTFIE_Msk                      /*!<TXTF interrupt enable */
#define SPI_IER_UDRIE_Pos                   (5U)
#define SPI_IER_UDRIE_Msk                   (0x1UL << SPI_IER_UDRIE_Pos)            /*!< 0x00000020 */
#define SPI_IER_UDRIE                       SPI_IER_UDRIE_Msk                       /*!<UDR interrupt enable */
#define SPI_IER_OVRIE_Pos                   (6U)
#define SPI_IER_OVRIE_Msk                   (0x1UL << SPI_IER_OVRIE_Pos)            /*!< 0x00000040 */
#define SPI_IER_OVRIE                       SPI_IER_OVRIE_Msk                       /*!<OVR interrupt enable */
#define SPI_IER_CRCEIE_Pos                  (7U)
#define SPI_IER_CRCEIE_Msk                  (0x1UL << SPI_IER_CRCEIE_Pos)           /*!< 0x00000080 */
#define SPI_IER_CRCEIE                      SPI_IER_CRCEIE_Msk                      /*!<CRCE interrupt enable */
#define SPI_IER_TIFREIE_Pos                 (8U)
#define SPI_IER_TIFREIE_Msk                 (0x1UL << SPI_IER_TIFREIE_Pos)          /*!< 0x00000100 */
#define SPI_IER_TIFREIE                     SPI_IER_TIFREIE_Msk                     /*!<TI Frame Error interrupt enable */
#define SPI_IER_MODFIE_Pos                  (9U)
#define SPI_IER_MODFIE_Msk                  (0x1UL << SPI_IER_MODFIE_Pos)           /*!< 0x00000200 */
#define SPI_IER_MODFIE                      SPI_IER_MODFIE_Msk                      /*!<MODF interrupt enable */

/*******************  Bit definition for SPI_SR register  ********************/
#define SPI_SR_RXP_Pos                      (0U)
#define SPI_SR_RXP_Msk                      (0x1UL << SPI_SR_RXP_Pos)               /*!< 0x00000001 */
#define SPI_SR_RXP                          SPI_SR_RXP_Msk                          /*!<Rx-Packet available */
#define SPI_SR_TXP_Pos                      (1U)
#define SPI_SR_TXP_Msk                      (0x1UL << SPI_SR_TXP_Pos)               /*!< 0x00000002 */
#define SPI_SR_TXP                          SPI_SR_TXP_Msk                          /*!<Tx-Packet space available */
#define SPI_SR_DXP_Pos                      (2U)
#define SPI_SR_DXP_Msk                      (0x1UL << SPI_SR_DXP_Pos)               /*!< 0x00000004 */
#define SPI_SR_DXP                          SPI_SR_DXP_Msk                          /*!<Duplex Packet available */
#define SPI_SR_EOT_Pos                      (3U)
#define SPI_SR_EOT_Msk                      (0x1UL << SPI_SR_EOT_Pos)               /*!< 0x00000008 */
#define SPI_SR_EOT                          SPI_SR_EOT_Msk                          /*!<Duplex Packet available */
#define SPI_SR_TXTF_Pos                     (4U)
#define SPI_SR_TXTF_Msk                     (0x1UL << SPI_SR_TXTF_Pos)              /*!< 0x00000010 */
#define SPI_SR_TXTF                         SPI_SR_TXTF_Msk                         /*!<Transmission Transfer Filled */
#define SPI_SR_UDR_Pos                      (5U)
#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)               /*!< 0x00000020 */
#define SPI_SR_UDR                          SPI_SR_UDR_Msk                          /*!<UDR at Slave transmission */
#define SPI_SR_OVR_Pos                      (6U)
#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)               /*!< 0x00000040 */
#define SPI_SR_OVR                          SPI_SR_OVR_Msk                          /*!<Rx-Packet available */
#define SPI_SR_CRCE_Pos                     (7U)
#define SPI_SR_CRCE_Msk                     (0x1UL << SPI_SR_CRCE_Pos)              /*!< 0x00000080 */
#define SPI_SR_CRCE                         SPI_SR_CRCE_Msk                         /*!<CRC Error Detected */
#define SPI_SR_TIFRE_Pos                    (8U)
#define SPI_SR_TIFRE_Msk                    (0x1UL << SPI_SR_TIFRE_Pos)             /*!< 0x00000100 */
#define SPI_SR_TIFRE                        SPI_SR_TIFRE_Msk                        /*!<TI frame format error Detected */
#define SPI_SR_MODF_Pos                     (9U)
#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)              /*!< 0x00000200 */
#define SPI_SR_MODF                         SPI_SR_MODF_Msk                         /*!<Mode Fault Detected */
#define SPI_SR_SUSP_Pos                     (11U)
#define SPI_SR_SUSP_Msk                     (0x1UL << SPI_SR_SUSP_Pos)              /*!< 0x00000800 */
#define SPI_SR_SUSP                         SPI_SR_SUSP_Msk                         /*!<SUSP is set by hardware */
#define SPI_SR_TXC_Pos                      (12U)
#define SPI_SR_TXC_Msk                      (0x1UL << SPI_SR_TXC_Pos)               /*!< 0x00001000 */
#define SPI_SR_TXC                          SPI_SR_TXC_Msk                          /*!<TxFIFO transmission complete */
#define SPI_SR_RXPLVL_Pos                   (13U)
#define SPI_SR_RXPLVL_Msk                   (0x3UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00006000 */
#define SPI_SR_RXPLVL                       SPI_SR_RXPLVL_Msk                       /*!<RxFIFO Packing Level */
#define SPI_SR_RXPLVL_0                     (0x1UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00002000 */
#define SPI_SR_RXPLVL_1                     (0x2UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00004000 */
#define SPI_SR_RXWNE_Pos                    (15U)
#define SPI_SR_RXWNE_Msk                    (0x1UL << SPI_SR_RXWNE_Pos)             /*!< 0x00008000 */
#define SPI_SR_RXWNE                        SPI_SR_RXWNE_Msk                        /*!<Rx FIFO Word Not Empty */
#define SPI_SR_CTSIZE_Pos                   (16U)
#define SPI_SR_CTSIZE_Msk                   (0xFFFFUL << SPI_SR_CTSIZE_Pos)         /*!< 0xFFFF0000 */
#define SPI_SR_CTSIZE                       SPI_SR_CTSIZE_Msk                       /*!<Number of data frames remaining in TSIZE */

/*******************  Bit definition for SPI_IFCR register  ********************/
#define SPI_IFCR_EOTC_Pos                   (3U)
#define SPI_IFCR_EOTC_Msk                   (0x1UL << SPI_IFCR_EOTC_Pos)            /*!< 0x00000008 */
#define SPI_IFCR_EOTC                       SPI_IFCR_EOTC_Msk                       /*!<End Of Transfer flag clear */
#define SPI_IFCR_TXTFC_Pos                  (4U)
#define SPI_IFCR_TXTFC_Msk                  (0x1UL << SPI_IFCR_TXTFC_Pos)           /*!< 0x00000010 */
#define SPI_IFCR_TXTFC                      SPI_IFCR_TXTFC_Msk                      /*!<Transmission Transfer Filled flag clear */
#define SPI_IFCR_UDRC_Pos                   (5U)
#define SPI_IFCR_UDRC_Msk                   (0x1UL << SPI_IFCR_UDRC_Pos)            /*!< 0x00000020 */
#define SPI_IFCR_UDRC                       SPI_IFCR_UDRC_Msk                       /*!<Underrun flag clear */
#define SPI_IFCR_OVRC_Pos                   (6U)
#define SPI_IFCR_OVRC_Msk                   (0x1UL << SPI_IFCR_OVRC_Pos)            /*!< 0x00000040 */
#define SPI_IFCR_OVRC                       SPI_IFCR_OVRC_Msk                       /*!<Overrun flag clear */
#define SPI_IFCR_CRCEC_Pos                  (7U)
#define SPI_IFCR_CRCEC_Msk                  (0x1UL << SPI_IFCR_CRCEC_Pos)           /*!< 0x00000080 */
#define SPI_IFCR_CRCEC                      SPI_IFCR_CRCEC_Msk                      /*!<CRC Error flag clear */
#define SPI_IFCR_TIFREC_Pos                 (8U)
#define SPI_IFCR_TIFREC_Msk                 (0x1UL << SPI_IFCR_TIFREC_Pos)          /*!< 0x00000100 */
#define SPI_IFCR_TIFREC                     SPI_IFCR_TIFREC_Msk                     /*!<TI frame format error flag clear */
#define SPI_IFCR_MODFC_Pos                  (9U)
#define SPI_IFCR_MODFC_Msk                  (0x1UL << SPI_IFCR_MODFC_Pos)           /*!< 0x00000200 */
#define SPI_IFCR_MODFC                      SPI_IFCR_MODFC_Msk                      /*!<Mode Fault flag clear */
#define SPI_IFCR_SUSPC_Pos                  (11U)
#define SPI_IFCR_SUSPC_Msk                  (0x1UL << SPI_IFCR_SUSPC_Pos)           /*!< 0x00000800 */
#define SPI_IFCR_SUSPC                      SPI_IFCR_SUSPC_Msk                      /*!<SUSPend flag clear */

/*******************  Bit definition for SPI_TXDR register  ********************/
#define SPI_TXDR_TXDR_Pos                   (0U)
#define SPI_TXDR_TXDR_Msk                   (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)     /*!< 0xFFFFFFFF */
#define SPI_TXDR_TXDR                       SPI_TXDR_TXDR_Msk                       /* Transmit Data Register */

/*******************  Bit definition for SPI_RXDR register  ********************/
#define SPI_RXDR_RXDR_Pos                   (0U)
#define SPI_RXDR_RXDR_Msk                   (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)     /*!< 0xFFFFFFFF */
#define SPI_RXDR_RXDR                       SPI_RXDR_RXDR_Msk                       /* Receive Data Register */

/*******************  Bit definition for SPI_CRCPOLY register  ********************/
#define SPI_CRCPOLY_CRCPOLY_Pos             (0U)
#define SPI_CRCPOLY_CRCPOLY_Msk             (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
#define SPI_CRCPOLY_CRCPOLY                 SPI_CRCPOLY_CRCPOLY_Msk                 /* CRC Polynomial register */

/*******************  Bit definition for SPI_TXCRC register  ********************/
#define SPI_TXCRC_TXCRC_Pos                 (0U)
#define SPI_TXCRC_TXCRC_Msk                 (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)   /*!< 0xFFFFFFFF */
#define SPI_TXCRC_TXCRC                     SPI_TXCRC_TXCRC_Msk                     /* CRCRegister for transmitter */

/*******************  Bit definition for SPI_RXCRC register  ********************/
#define SPI_RXCRC_RXCRC_Pos                 (0U)
#define SPI_RXCRC_RXCRC_Msk                 (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)   /*!< 0xFFFFFFFF */
#define SPI_RXCRC_RXCRC                     SPI_RXCRC_RXCRC_Msk                     /* CRCRegister for receiver */

/*******************  Bit definition for SPI_UDRDR register  ********************/
#define SPI_UDRDR_UDRDR_Pos                 (0U)
#define SPI_UDRDR_UDRDR_Msk                 (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)   /*!< 0xFFFFFFFF */
#define SPI_UDRDR_UDRDR                     SPI_UDRDR_UDRDR_Msk                     /* Data at slave underrun condition */

/******************  Bit definition for SPI_I2SCFGR register  *******************/
#define SPI_I2SCFGR_I2SMOD_Pos      (0U)
#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)               /*!< 0x00000001 */
#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                          /*!<I2S mode selection */
#define SPI_I2SCFGR_I2SCFG_Pos      (1U)
#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)               /*!< 0x0000000E */
#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                          /*!<I2SCFG[2:0] I2S configuration mode */
#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)               /*!< 0x00000002 */
#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)               /*!< 0x00000004 */
#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)               /*!< 0x00000008 */
#define SPI_I2SCFGR_I2SSTD_Pos      (4U)
#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)               /*!< 0x00000030 */
#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                          /*!<I2SSTD[1:0] I2S standard selection */
#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)               /*!< 0x00000010 */
#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)               /*!< 0x00000020 */
#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)              /*!< 0x00000080 */
#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                         /*!<PCM frame synchronization */
#define SPI_I2SCFGR_DATLEN_Pos      (8U)
#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)               /*!< 0x00000300 */
#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                          /*!<DATLEN[1:0] Data length to be transferred */
#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)               /*!< 0x00000100 */
#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)               /*!< 0x00000200 */
#define SPI_I2SCFGR_CHLEN_Pos       (10U)
#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)                /*!< 0x00000400 */
#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                           /*!<Channel length (number of bits per audio channel) */
#define SPI_I2SCFGR_CKPOL_Pos       (11U)
#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)                /*!< 0x00000800 */
#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                           /*!<Steady state clock polarity */
#define SPI_I2SCFGR_FIXCH_Pos       (12U)
#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)                /*!< 0x00001000 */
#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                           /*!<Fixed channel length in SLAVE */
#define SPI_I2SCFGR_WSINV_Pos       (13U)
#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)                /*!< 0x00002000 */
#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                           /*!<Word select inversion */
#define SPI_I2SCFGR_DATFMT_Pos      (14U)
#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)               /*!< 0x00004000 */
#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                          /*!<Data format */
#define SPI_I2SCFGR_I2SDIV_Pos      (16U)
#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)              /*!< 0x00FF0000 */
#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                          /*!<I2S Linear prescaler */
#define SPI_I2SCFGR_ODD_Pos         (24U)
#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)                  /*!< 0x01000000 */
#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                             /*!<Odd factor for the prescaler */
#define SPI_I2SCFGR_MCKOE_Pos       (25U)
#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)                /*!< 0x02000000 */
#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                           /*!<Master Clock Output Enable */

/******************************************************************************/
/*                                                                            */
/*                     Tamper and backup register (TAMP)                      */
/*                                                                            */
/******************************************************************************/
#define TAMP_BACKUP_NB     32U

/********************  Bits definition for TAMP_CR1 register  *****************/
#define TAMP_CR1_TAMP1E_Pos                 (0U)
#define TAMP_CR1_TAMP1E_Msk                 (0x1UL << TAMP_CR1_TAMP1E_Pos)          /*!< 0x00000001 */
#define TAMP_CR1_TAMP1E                     TAMP_CR1_TAMP1E_Msk                     /*!< Tamper detection on TAMP_IN1 enable */
#define TAMP_CR1_TAMP2E_Pos                 (1U)
#define TAMP_CR1_TAMP2E_Msk                 (0x1UL << TAMP_CR1_TAMP2E_Pos)          /*!< 0x00000002 */
#define TAMP_CR1_TAMP2E                     TAMP_CR1_TAMP2E_Msk                     /*!< Tamper detection on TAMP_IN2 enable */
#define TAMP_CR1_TAMP3E_Pos                 (2U)
#define TAMP_CR1_TAMP3E_Msk                 (0x1UL << TAMP_CR1_TAMP3E_Pos)          /*!< 0x00000004 */
#define TAMP_CR1_TAMP3E                     TAMP_CR1_TAMP3E_Msk                     /*!< Tamper detection on TAMP_IN3 enable */
#define TAMP_CR1_ITAMP3E_Pos                (18U)
#define TAMP_CR1_ITAMP3E_Msk                (0x1UL << TAMP_CR1_ITAMP3E_Pos)         /*!< 0x00040000 */
#define TAMP_CR1_ITAMP3E                    TAMP_CR1_ITAMP3E_Msk                    /*!< Internal tamper 3 enable */
#define TAMP_CR1_ITAMP4E_Pos                (19U)
#define TAMP_CR1_ITAMP4E_Msk                (0x1UL << TAMP_CR1_ITAMP4E_Pos)         /*!< 0x00080000 */
#define TAMP_CR1_ITAMP4E                    TAMP_CR1_ITAMP4E_Msk                    /*!< Internal tamper 4 enable */
#define TAMP_CR1_ITAMP5E_Pos                (20U)
#define TAMP_CR1_ITAMP5E_Msk                (0x1UL << TAMP_CR1_ITAMP5E_Pos)         /*!< 0x00100000 */
#define TAMP_CR1_ITAMP5E                    TAMP_CR1_ITAMP5E_Msk                    /*!< Internal tamper 5 enable */
#define TAMP_CR1_ITAMP6E_Pos                (21U)
#define TAMP_CR1_ITAMP6E_Msk                (0x1UL << TAMP_CR1_ITAMP6E_Pos)         /*!< 0x00200000 */
#define TAMP_CR1_ITAMP6E                    TAMP_CR1_ITAMP6E_Msk                    /*!< Internal tamper 6 enable */
#define TAMP_CR1_ITAMP9E_Pos                (24U)
#define TAMP_CR1_ITAMP9E_Msk                (0x1UL << TAMP_CR1_ITAMP9E_Pos)         /*!< 0x01000000 */
#define TAMP_CR1_ITAMP9E                    TAMP_CR1_ITAMP9E_Msk                    /*!< Internal tamper 9 enable */
#define TAMP_CR1_ITAMP11E_Pos               (26U)
#define TAMP_CR1_ITAMP11E_Msk               (0x1UL << TAMP_CR1_ITAMP11E_Pos)        /*!< 0x04000000 */
#define TAMP_CR1_ITAMP11E                   TAMP_CR1_ITAMP11E_Msk                   /*!< Internal tamper 11 enable */

/********************  Bits definition for TAMP_CR2 register  *****************/
#define TAMP_CR2_TAMP1POM_Pos               (0U)
#define TAMP_CR2_TAMP1POM_Msk               (0x1UL << TAMP_CR2_TAMP1POM_Pos)        /*!< 0x00000001 */
#define TAMP_CR2_TAMP1POM                   TAMP_CR2_TAMP1POM_Msk                   /*!< Tamper 1 potential mode */
#define TAMP_CR2_TAMP2POM_Pos               (1U)
#define TAMP_CR2_TAMP2POM_Msk               (0x1UL << TAMP_CR2_TAMP2POM_Pos)        /*!< 0x00000002 */
#define TAMP_CR2_TAMP2POM                   TAMP_CR2_TAMP2POM_Msk                   /*!< Tamper 2 potential mode */
#define TAMP_CR2_TAMP3POM_Pos               (2U)
#define TAMP_CR2_TAMP3POM_Msk               (0x1UL << TAMP_CR2_TAMP3POM_Pos)        /*!< 0x00000004 */
#define TAMP_CR2_TAMP3POM                   TAMP_CR2_TAMP3POM_Msk                   /*!< Tamper 3 potential mode */
#define TAMP_CR2_TAMP1MSK_Pos               (16U)
#define TAMP_CR2_TAMP1MSK_Msk               (0x1UL << TAMP_CR2_TAMP1MSK_Pos)        /*!< 0x00010000 */
#define TAMP_CR2_TAMP1MSK                   TAMP_CR2_TAMP1MSK_Msk                   /*!< Tamper 1 mask */
#define TAMP_CR2_TAMP2MSK_Pos               (17U)
#define TAMP_CR2_TAMP2MSK_Msk               (0x1UL << TAMP_CR2_TAMP2MSK_Pos)        /*!< 0x00020000 */
#define TAMP_CR2_TAMP2MSK                   TAMP_CR2_TAMP2MSK_Msk                   /*!< Tamper 2 mask */
#define TAMP_CR2_TAMP3MSK_Pos               (18U)
#define TAMP_CR2_TAMP3MSK_Msk               (0x1UL << TAMP_CR2_TAMP3MSK_Pos)        /*!< 0x00040000 */
#define TAMP_CR2_TAMP3MSK                   TAMP_CR2_TAMP3MSK_Msk                   /*!< Tamper 3 mask */
#define TAMP_CR2_BKBLOCK_Pos                (22U)
#define TAMP_CR2_BKBLOCK_Msk                (0x1UL << TAMP_CR2_BKBLOCK_Pos)         /*!< 0x00400000 */
#define TAMP_CR2_BKBLOCK                    TAMP_CR2_BKBLOCK_Msk                    /*!< Backup registers and device secrets access blocked */
#define TAMP_CR2_BKERASE_Pos                (23U)
#define TAMP_CR2_BKERASE_Msk                (0x1UL << TAMP_CR2_BKERASE_Pos)         /*!< 0x00800000 */
#define TAMP_CR2_BKERASE                    TAMP_CR2_BKERASE_Msk                    /*!< Backup registers and device secrets erase */
#define TAMP_CR2_TAMP1TRG_Pos               (24U)
#define TAMP_CR2_TAMP1TRG_Msk               (0x1UL << TAMP_CR2_TAMP1TRG_Pos)        /*!< 0x01000000 */
#define TAMP_CR2_TAMP1TRG                   TAMP_CR2_TAMP1TRG_Msk                   /*!< Active level for tamper 1 input */
#define TAMP_CR2_TAMP2TRG_Pos               (25U)
#define TAMP_CR2_TAMP2TRG_Msk               (0x1UL << TAMP_CR2_TAMP2TRG_Pos)        /*!< 0x02000000 */
#define TAMP_CR2_TAMP2TRG                   TAMP_CR2_TAMP2TRG_Msk                   /*!< Active level for tamper 2 input */
#define TAMP_CR2_TAMP3TRG_Pos               (26U)
#define TAMP_CR2_TAMP3TRG_Msk               (0x1UL << TAMP_CR2_TAMP3TRG_Pos)        /*!< 0x04000000 */
#define TAMP_CR2_TAMP3TRG                   TAMP_CR2_TAMP3TRG_Msk                   /*!< Active level for tamper 3 input */

/********************  Bits definition for TAMP_CR3 register  *****************/
#define TAMP_CR3_ITAMP3POM_Pos              (2U)
#define TAMP_CR3_ITAMP3POM_Msk              (0x1UL << TAMP_CR3_ITAMP3POM_Pos)       /*!< 0x00000004 */
#define TAMP_CR3_ITAMP3POM                  TAMP_CR3_ITAMP3POM_Msk                  /*!< Internal tamper 3 potential mode */
#define TAMP_CR3_ITAMP4POM_Pos              (3U)
#define TAMP_CR3_ITAMP4POM_Msk              (0x1UL << TAMP_CR3_ITAMP4POM_Pos)       /*!< 0x00000008 */
#define TAMP_CR3_ITAMP4POM                  TAMP_CR3_ITAMP4POM_Msk                  /*!< Internal tamper 4 potential mode */
#define TAMP_CR3_ITAMP5POM_Pos              (4U)
#define TAMP_CR3_ITAMP5POM_Msk              (0x1UL << TAMP_CR3_ITAMP5POM_Pos)       /*!< 0x00000010 */
#define TAMP_CR3_ITAMP5POM                  TAMP_CR3_ITAMP5POM_Msk                  /*!< Internal tamper 5 potential mode */
#define TAMP_CR3_ITAMP6POM_Pos              (5U)
#define TAMP_CR3_ITAMP6POM_Msk              (0x1UL << TAMP_CR3_ITAMP6POM_Pos)       /*!< 0x00000020 */
#define TAMP_CR3_ITAMP6POM                  TAMP_CR3_ITAMP6POM_Msk                  /*!< Internal tamper 6 potential mode */
#define TAMP_CR3_ITAMP9POM_Pos              (8U)
#define TAMP_CR3_ITAMP9POM_Msk              (0x1UL << TAMP_CR3_ITAMP9POM_Pos)       /*!< 0x00000100 */
#define TAMP_CR3_ITAMP9POM                  TAMP_CR3_ITAMP9POM_Msk                  /*!< Internal tamper 9 potential mode */
#define TAMP_CR3_ITAMP11POM_Pos             (10U)
#define TAMP_CR3_ITAMP11POM_Msk             (0x1UL << TAMP_CR3_ITAMP11POM_Pos)      /*!< 0x00000400 */
#define TAMP_CR3_ITAMP11POM                 TAMP_CR3_ITAMP11POM_Msk                 /*!< Internal tamper 11 potential mode */

/********************  Bits definition for TAMP_FLTCR register  ***************/
#define TAMP_FLTCR_TAMPFREQ_Pos             (0U)
#define TAMP_FLTCR_TAMPFREQ_Msk             (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000007 */
#define TAMP_FLTCR_TAMPFREQ                 TAMP_FLTCR_TAMPFREQ_Msk                 /*!< Tamper sampling frequency */
#define TAMP_FLTCR_TAMPFREQ_0               (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000001 */
#define TAMP_FLTCR_TAMPFREQ_1               (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000002 */
#define TAMP_FLTCR_TAMPFREQ_2               (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000004 */
#define TAMP_FLTCR_TAMPFLT_Pos              (3U)
#define TAMP_FLTCR_TAMPFLT_Msk              (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000018 */
#define TAMP_FLTCR_TAMPFLT                  TAMP_FLTCR_TAMPFLT_Msk                  /*!< TAMP_INx filter count */
#define TAMP_FLTCR_TAMPFLT_0                (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000008 */
#define TAMP_FLTCR_TAMPFLT_1                (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000010 */
#define TAMP_FLTCR_TAMPPRCH_Pos             (5U)
#define TAMP_FLTCR_TAMPPRCH_Msk             (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000060 */
#define TAMP_FLTCR_TAMPPRCH                 TAMP_FLTCR_TAMPPRCH_Msk                 /*!< TAMP_INx precharge duration */
#define TAMP_FLTCR_TAMPPRCH_0               (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000020 */
#define TAMP_FLTCR_TAMPPRCH_1               (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000040 */
#define TAMP_FLTCR_TAMPPUDIS_Pos            (7U)
#define TAMP_FLTCR_TAMPPUDIS_Msk            (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)     /*!< 0x00000080 */
#define TAMP_FLTCR_TAMPPUDIS                TAMP_FLTCR_TAMPPUDIS_Msk                /*!< TAMP_INx pull-up disable */

/********************  Bits definition for TAMP_CFGR register  *************/
#define TAMP_CFGR_BKPRW_Pos                 (0U)
#define TAMP_CFGR_BKPRW_Msk                 (0xFFUL << TAMP_CFGR_BKPRW_Pos)         /*!< 0x000000FF */
#define TAMP_CFGR_BKPRW                     TAMP_CFGR_BKPRW_Msk                     /*!< Backup registers read/write protection offset */
#define TAMP_CFGR_BKPRW_0                   (0x1UL << TAMP_CFGR_BKPRW_Pos)          /*!< 0x00000001 */
#define TAMP_CFGR_BKPRW_1                   (0x2UL << TAMP_CFGR_BKPRW_Pos)          /*!< 0x00000002 */
#define TAMP_CFGR_BKPRW_2                   (0x4UL << TAMP_CFGR_BKPRW_Pos)          /*!< 0x00000004 */
#define TAMP_CFGR_BKPRW_3                   (0x8UL << TAMP_CFGR_BKPRW_Pos)          /*!< 0x00000008 */
#define TAMP_CFGR_BKPRW_4                   (0x10UL << TAMP_CFGR_BKPRW_Pos)         /*!< 0x00000010 */
#define TAMP_CFGR_BKPRW_5                   (0x20UL << TAMP_CFGR_BKPRW_Pos)         /*!< 0x00000020 */
#define TAMP_CFGR_BKPRW_6                   (0x40UL << TAMP_CFGR_BKPRW_Pos)         /*!< 0x00000040 */
#define TAMP_CFGR_BKPRW_7                   (0x80UL << TAMP_CFGR_BKPRW_Pos)         /*!< 0x00000080 */
#define TAMP_CFGR_BKPW_Pos                  (16U)
#define TAMP_CFGR_BKPW_Msk                  (0xFFUL << TAMP_CFGR_BKPW_Pos)          /*!< 0x00FF0000 */
#define TAMP_CFGR_BKPW                      TAMP_CFGR_BKPW_Msk                      /*!< Backup registers write protection offset */
#define TAMP_CFGR_BKPW_0                    (0x1UL << TAMP_CFGR_BKPW_Pos)           /*!< 0x00010000 */
#define TAMP_CFGR_BKPW_1                    (0x2UL << TAMP_CFGR_BKPW_Pos)           /*!< 0x00020000 */
#define TAMP_CFGR_BKPW_2                    (0x4UL << TAMP_CFGR_BKPW_Pos)           /*!< 0x00040000 */
#define TAMP_CFGR_BKPW_3                    (0x8UL << TAMP_CFGR_BKPW_Pos)           /*!< 0x00080000 */
#define TAMP_CFGR_BKPW_4                    (0x10UL << TAMP_CFGR_BKPW_Pos)          /*!< 0x00100000 */
#define TAMP_CFGR_BKPW_5                    (0x20UL << TAMP_CFGR_BKPW_Pos)          /*!< 0x00200000 */
#define TAMP_CFGR_BKPW_6                    (0x40UL << TAMP_CFGR_BKPW_Pos)          /*!< 0x00400000 */
#define TAMP_CFGR_BKPW_7                    (0x80UL << TAMP_CFGR_BKPW_Pos)          /*!< 0x00800000 */

/********************  Bits definition for TAMP_PRIVCFGR register  ************/
#define TAMP_PRIVCFGR_BKPRWPRIV_Pos         (29U)
#define TAMP_PRIVCFGR_BKPRWPRIV_Msk         (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos)  /*!< 0x20000000 */
#define TAMP_PRIVCFGR_BKPRWPRIV             TAMP_PRIVCFGR_BKPRWPRIV_Msk             /*!< Backup registers zone 1 privilege protection */
#define TAMP_PRIVCFGR_BKPWPRIV_Pos          (30U)
#define TAMP_PRIVCFGR_BKPWPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos)   /*!< 0x40000000 */
#define TAMP_PRIVCFGR_BKPWPRIV              TAMP_PRIVCFGR_BKPWPRIV_Msk              /*!< Backup registers zone 2 privilege protection */
#define TAMP_PRIVCFGR_TAMPPRIV_Pos          (31U)
#define TAMP_PRIVCFGR_TAMPPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos)   /*!< 0x80000000 */
#define TAMP_PRIVCFGR_TAMPPRIV              TAMP_PRIVCFGR_TAMPPRIV_Msk              /*!< Tamper privilege protection (excluding backup registers) */

/********************  Bits definition for TAMP_IER register  *****************/
#define TAMP_IER_TAMP1IE_Pos                (0U)
#define TAMP_IER_TAMP1IE_Msk                (0x1UL << TAMP_IER_TAMP1IE_Pos)         /*!< 0x00000001 */
#define TAMP_IER_TAMP1IE                    TAMP_IER_TAMP1IE_Msk                    /*!< Tamper 1 interrupt enable */
#define TAMP_IER_TAMP2IE_Pos                (1U)
#define TAMP_IER_TAMP2IE_Msk                (0x1UL << TAMP_IER_TAMP2IE_Pos)         /*!< 0x00000002 */
#define TAMP_IER_TAMP2IE                    TAMP_IER_TAMP2IE_Msk                    /*!< Tamper 2 interrupt enable */
#define TAMP_IER_TAMP3IE_Pos                (2U)
#define TAMP_IER_TAMP3IE_Msk                (0x1UL << TAMP_IER_TAMP3IE_Pos)         /*!< 0x00000004 */
#define TAMP_IER_TAMP3IE                    TAMP_IER_TAMP3IE_Msk                    /*!< Tamper 3 interrupt enable */
#define TAMP_IER_ITAMP3IE_Pos               (18U)
#define TAMP_IER_ITAMP3IE_Msk               (0x1UL << TAMP_IER_ITAMP3IE_Pos)        /*!< 0x00040000 */
#define TAMP_IER_ITAMP3IE                   TAMP_IER_ITAMP3IE_Msk                   /*!< Internal tamper 3 interrupt enable */
#define TAMP_IER_ITAMP4IE_Pos               (19U)
#define TAMP_IER_ITAMP4IE_Msk               (0x1UL << TAMP_IER_ITAMP4IE_Pos)        /*!< 0x00080000 */
#define TAMP_IER_ITAMP4IE                   TAMP_IER_ITAMP4IE_Msk                   /*!< Internal tamper 4 interrupt enable */
#define TAMP_IER_ITAMP5IE_Pos               (20U)
#define TAMP_IER_ITAMP5IE_Msk               (0x1UL << TAMP_IER_ITAMP5IE_Pos)        /*!< 0x00100000 */
#define TAMP_IER_ITAMP5IE                   TAMP_IER_ITAMP5IE_Msk                   /*!< Internal tamper 5 interrupt enable */
#define TAMP_IER_ITAMP6IE_Pos               (21U)
#define TAMP_IER_ITAMP6IE_Msk               (0x1UL << TAMP_IER_ITAMP6IE_Pos)        /*!< 0x00200000 */
#define TAMP_IER_ITAMP6IE                   TAMP_IER_ITAMP6IE_Msk                   /*!< Internal tamper 6 interrupt enable */
#define TAMP_IER_ITAMP9IE_Pos               (24U)
#define TAMP_IER_ITAMP9IE_Msk               (0x1UL << TAMP_IER_ITAMP9IE_Pos)        /*!< 0x01000000 */
#define TAMP_IER_ITAMP9IE                   TAMP_IER_ITAMP9IE_Msk                   /*!< Internal tamper 9 interrupt enable */
#define TAMP_IER_ITAMP11IE_Pos              (26U)
#define TAMP_IER_ITAMP11IE_Msk              (0x1UL << TAMP_IER_ITAMP11IE_Pos)       /*!< 0x04000000 */
#define TAMP_IER_ITAMP11IE                  TAMP_IER_ITAMP11IE_Msk                  /*!< Internal tamper 11 interrupt enable */

/********************  Bits definition for TAMP_SR register  *****************/
#define TAMP_SR_TAMP1F_Pos                  (0U)
#define TAMP_SR_TAMP1F_Msk                  (0x1UL << TAMP_SR_TAMP1F_Pos)           /*!< 0x00000001 */
#define TAMP_SR_TAMP1F                      TAMP_SR_TAMP1F_Msk                      /*!< TAMP1 detection flag */
#define TAMP_SR_TAMP2F_Pos                  (1U)
#define TAMP_SR_TAMP2F_Msk                  (0x1UL << TAMP_SR_TAMP2F_Pos)           /*!< 0x00000002 */
#define TAMP_SR_TAMP2F                      TAMP_SR_TAMP2F_Msk                      /*!< TAMP2 detection flag */
#define TAMP_SR_TAMP3F_Pos                  (2U)
#define TAMP_SR_TAMP3F_Msk                  (0x1UL << TAMP_SR_TAMP3F_Pos)           /*!< 0x00000004 */
#define TAMP_SR_TAMP3F                      TAMP_SR_TAMP3F_Msk                      /*!< TAMP3 detection flag */
#define TAMP_SR_ITAMP3F_Pos                 (18U)
#define TAMP_SR_ITAMP3F_Msk                 (0x1UL << TAMP_SR_ITAMP3F_Pos)          /*!< 0x00040000 */
#define TAMP_SR_ITAMP3F                     TAMP_SR_ITAMP3F_Msk                     /*!< Internal tamper 3 flag */
#define TAMP_SR_ITAMP4F_Pos                 (19U)
#define TAMP_SR_ITAMP4F_Msk                 (0x1UL << TAMP_SR_ITAMP4F_Pos)          /*!< 0x00080000 */
#define TAMP_SR_ITAMP4F                     TAMP_SR_ITAMP4F_Msk                     /*!< Internal tamper 4 flag */
#define TAMP_SR_ITAMP5F_Pos                 (20U)
#define TAMP_SR_ITAMP5F_Msk                 (0x1UL << TAMP_SR_ITAMP5F_Pos)          /*!< 0x00100000 */
#define TAMP_SR_ITAMP5F                     TAMP_SR_ITAMP5F_Msk                     /*!< Internal tamper 5 flag */
#define TAMP_SR_ITAMP6F_Pos                 (21U)
#define TAMP_SR_ITAMP6F_Msk                 (0x1UL << TAMP_SR_ITAMP6F_Pos)          /*!< 0x00200000 */
#define TAMP_SR_ITAMP6F                     TAMP_SR_ITAMP6F_Msk                     /*!< Internal tamper 6 flag */
#define TAMP_SR_ITAMP9F_Pos                 (24U)
#define TAMP_SR_ITAMP9F_Msk                 (0x1UL << TAMP_SR_ITAMP9F_Pos)          /*!< 0x01000000 */
#define TAMP_SR_ITAMP9F                     TAMP_SR_ITAMP9F_Msk                     /*!< Internal tamper 9 flag */
#define TAMP_SR_ITAMP11F_Pos                (26U)
#define TAMP_SR_ITAMP11F_Msk                (0x1UL << TAMP_SR_ITAMP11F_Pos)         /*!< 0x04000000 */
#define TAMP_SR_ITAMP11F                    TAMP_SR_ITAMP11F_Msk                    /*!< Internal tamper 11 flag */

/********************  Bits definition for TAMP_MISR register  ****************/
#define TAMP_MISR_TAMP1MF_Pos               (0U)
#define TAMP_MISR_TAMP1MF_Msk               (0x1UL << TAMP_MISR_TAMP1MF_Pos)        /*!< 0x00000001 */
#define TAMP_MISR_TAMP1MF                   TAMP_MISR_TAMP1MF_Msk                   /*!< TAMP1 interrupt masked flag */
#define TAMP_MISR_TAMP2MF_Pos               (1U)
#define TAMP_MISR_TAMP2MF_Msk               (0x1UL << TAMP_MISR_TAMP2MF_Pos)        /*!< 0x00000002 */
#define TAMP_MISR_TAMP2MF                   TAMP_MISR_TAMP2MF_Msk                   /*!< TAMP2 interrupt masked flag */
#define TAMP_MISR_TAMP3MF_Pos               (2U)
#define TAMP_MISR_TAMP3MF_Msk               (0x1UL << TAMP_MISR_TAMP3MF_Pos)        /*!< 0x00000004 */
#define TAMP_MISR_TAMP3MF                   TAMP_MISR_TAMP3MF_Msk                   /*!< TAMP3 interrupt masked flag */
#define TAMP_MISR_ITAMP3MF_Pos              (18U)
#define TAMP_MISR_ITAMP3MF_Msk              (0x1UL << TAMP_MISR_ITAMP3MF_Pos)       /*!< 0x00040000 */
#define TAMP_MISR_ITAMP3MF                  TAMP_MISR_ITAMP3MF_Msk                  /*!< Internal tamper 3  interrupt masked flag */
#define TAMP_MISR_ITAMP4MF_Pos              (19U)
#define TAMP_MISR_ITAMP4MF_Msk              (0x1UL << TAMP_MISR_ITAMP4MF_Pos)       /*!< 0x00080000 */
#define TAMP_MISR_ITAMP4MF                  TAMP_MISR_ITAMP4MF_Msk                  /*!< Internal tamper 4  interrupt masked flag */
#define TAMP_MISR_ITAMP5MF_Pos              (20U)
#define TAMP_MISR_ITAMP5MF_Msk              (0x1UL << TAMP_MISR_ITAMP5MF_Pos)       /*!< 0x00100000 */
#define TAMP_MISR_ITAMP5MF                  TAMP_MISR_ITAMP5MF_Msk                  /*!< Internal tamper 5  interrupt masked flag */
#define TAMP_MISR_ITAMP6MF_Pos              (21U)
#define TAMP_MISR_ITAMP6MF_Msk              (0x1UL << TAMP_MISR_ITAMP6MF_Pos)       /*!< 0x00200000 */
#define TAMP_MISR_ITAMP6MF                  TAMP_MISR_ITAMP6MF_Msk                  /*!< Internal tamper 6  interrupt masked flag */
#define TAMP_MISR_ITAMP9MF_Pos              (24U)
#define TAMP_MISR_ITAMP9MF_Msk              (0x1UL << TAMP_MISR_ITAMP9MF_Pos)       /*!< 0x01000000 */
#define TAMP_MISR_ITAMP9MF                  TAMP_MISR_ITAMP9MF_Msk                  /*!< internal tamper 9 interrupt masked flag */
#define TAMP_MISR_ITAMP11MF_Pos             (26U)
#define TAMP_MISR_ITAMP11MF_Msk             (0x1UL << TAMP_MISR_ITAMP11MF_Pos)      /*!< 0x04000000 */
#define TAMP_MISR_ITAMP11MF                 TAMP_MISR_ITAMP11MF_Msk                 /*!< internal tamper 11 interrupt masked flag */

/********************  Bits definition for TAMP_SCR register  *****************/
#define TAMP_SCR_CTAMP1F_Pos                (0U)
#define TAMP_SCR_CTAMP1F_Msk                (0x1UL << TAMP_SCR_CTAMP1F_Pos)         /*!< 0x00000001 */
#define TAMP_SCR_CTAMP1F                    TAMP_SCR_CTAMP1F_Msk                    /*!< Clear TAMP1 detection flag */
#define TAMP_SCR_CTAMP2F_Pos                (1U)
#define TAMP_SCR_CTAMP2F_Msk                (0x1UL << TAMP_SCR_CTAMP2F_Pos)         /*!< 0x00000002 */
#define TAMP_SCR_CTAMP2F                    TAMP_SCR_CTAMP2F_Msk                    /*!< Clear TAMP2 detection flag */
#define TAMP_SCR_CTAMP3F_Pos                (2U)
#define TAMP_SCR_CTAMP3F_Msk                (0x1UL << TAMP_SCR_CTAMP3F_Pos)         /*!< 0x00000004 */
#define TAMP_SCR_CTAMP3F                    TAMP_SCR_CTAMP3F_Msk                    /*!< Clear TAMP3 detection flag */
#define TAMP_SCR_CITAMP3F_Pos               (18U)
#define TAMP_SCR_CITAMP3F_Msk               (0x1UL << TAMP_SCR_CITAMP3F_Pos)        /*!< 0x00040000 */
#define TAMP_SCR_CITAMP3F                   TAMP_SCR_CITAMP3F_Msk                   /*!< Clear ITAMP3 detection flag */
#define TAMP_SCR_CITAMP4F_Pos               (19U)
#define TAMP_SCR_CITAMP4F_Msk               (0x1UL << TAMP_SCR_CITAMP4F_Pos)        /*!< 0x00080000 */
#define TAMP_SCR_CITAMP4F                   TAMP_SCR_CITAMP4F_Msk                   /*!< Clear ITAMP4 detection flag */
#define TAMP_SCR_CITAMP5F_Pos               (20U)
#define TAMP_SCR_CITAMP5F_Msk               (0x1UL << TAMP_SCR_CITAMP5F_Pos)        /*!< 0x00100000 */
#define TAMP_SCR_CITAMP5F                   TAMP_SCR_CITAMP5F_Msk                   /*!< Clear ITAMP5 detection flag */
#define TAMP_SCR_CITAMP6F_Pos               (21U)
#define TAMP_SCR_CITAMP6F_Msk               (0x1UL << TAMP_SCR_CITAMP6F_Pos)        /*!< 0x00200000 */
#define TAMP_SCR_CITAMP6F                   TAMP_SCR_CITAMP6F_Msk                   /*!< Clear ITAMP6 detection flag */
#define TAMP_SCR_CITAMP9F_Pos               (24U)
#define TAMP_SCR_CITAMP9F_Msk               (0x1UL << TAMP_SCR_CITAMP9F_Pos)        /*!< 0x01000000 */
#define TAMP_SCR_CITAMP9F                   TAMP_SCR_CITAMP9F_Msk                   /*!< Clear ITAMP9 detection flag */
#define TAMP_SCR_CITAMP11F_Pos              (26U)
#define TAMP_SCR_CITAMP11F_Msk              (0x1UL << TAMP_SCR_CITAMP11F_Pos)       /*!< 0x04000000 */
#define TAMP_SCR_CITAMP11F                  TAMP_SCR_CITAMP11F_Msk                  /*!< Clear ITAMP11 detection flag */

/********************  Bits definition for TAMP_OR register  ***************/
#define TAMP_OR_IN2_RMP_Pos                (0U)
#define TAMP_OR_IN2_RMP_Msk                (0x1UL << TAMP_OR_IN2_RMP_Pos)          /*!< 0x00000001 */
#define TAMP_OR_IN2_RMP                    TAMP_OR_IN2_RMP_Msk                     /*!< TAMP_IN2 pin select */
#define TAMP_OR_IN3_RMP_Pos                (2U)
#define TAMP_OR_IN3_RMP_Msk                (0x1UL << TAMP_OR_IN3_RMP_Pos)          /*!< 0x00000004 */
#define TAMP_OR_IN3_RMP                    TAMP_OR_IN3_RMP_Msk                     /*!< TAMP_IN3 pin select */

/********************  Bits definition for TAMP_BKP0R register  ****************/
#define TAMP_BKP0R_BKP_Pos                 (0U)
#define TAMP_BKP0R_BKP_Msk                 (0xFFFFFFFFUL << TAMP_BKP0R_BKP_Pos)    /*!< 0xFFFFFFFF */
#define TAMP_BKP0R_BKP                     TAMP_BKP0R_BKP_Msk                      /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP1R register  ****************/
#define TAMP_BKP1R_BKP_Pos                 (0U)
#define TAMP_BKP1R_BKP_Msk                 (0xFFFFFFFFUL << TAMP_BKP1R_BKP_Pos)    /*!< 0xFFFFFFFF */
#define TAMP_BKP1R_BKP                     TAMP_BKP1R_BKP_Msk                      /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP2R register  ****************/
#define TAMP_BKP2R_BKP_Pos                 (0U)
#define TAMP_BKP2R_BKP_Msk                 (0xFFFFFFFFUL << TAMP_BKP2R_BKP_Pos)    /*!< 0xFFFFFFFF */
#define TAMP_BKP2R_BKP                     TAMP_BKP2R_BKP_Msk                      /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP3R register  ****************/
#define TAMP_BKP3R_BKP_Pos                 (0U)
#define TAMP_BKP3R_BKP_Msk                 (0xFFFFFFFFUL << TAMP_BKP3R_BKP_Pos)    /*!< 0xFFFFFFFF */
#define TAMP_BKP3R_BKP                     TAMP_BKP3R_BKP_Msk                      /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP4R register  ****************/
#define TAMP_BKP4R_BKP_Pos                 (0U)
#define TAMP_BKP4R_BKP_Msk                 (0xFFFFFFFFUL << TAMP_BKP4R_BKP_Pos)    /*!< 0xFFFFFFFF */
#define TAMP_BKP4R_BKP                     TAMP_BKP4R_BKP_Msk                      /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP5R register  ****************/
#define TAMP_BKP5R_BKP_Pos                 (0U)
#define TAMP_BKP5R_BKP_Msk                 (0xFFFFFFFFUL << TAMP_BKP5R_BKP_Pos)    /*!< 0xFFFFFFFF */
#define TAMP_BKP5R_BKP                     TAMP_BKP5R_BKP_Msk                      /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP6R register  ****************/
#define TAMP_BKP6R_BKP_Pos                 (0U)
#define TAMP_BKP6R_BKP_Msk                 (0xFFFFFFFFUL << TAMP_BKP6R_BKP_Pos)    /*!< 0xFFFFFFFF */
#define TAMP_BKP6R_BKP                     TAMP_BKP6R_BKP_Msk                      /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP7R register  ****************/
#define TAMP_BKP7R_BKP_Pos                 (0U)
#define TAMP_BKP7R_BKP_Msk                 (0xFFFFFFFFUL << TAMP_BKP7R_BKP_Pos)    /*!< 0xFFFFFFFF */
#define TAMP_BKP7R_BKP                     TAMP_BKP7R_BKP_Msk                      /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP8R register  ****************/
#define TAMP_BKP8R_BKP_Pos                 (0U)
#define TAMP_BKP8R_BKP_Msk                 (0xFFFFFFFFUL << TAMP_BKP8R_BKP_Pos)    /*!< 0xFFFFFFFF */
#define TAMP_BKP8R_BKP                     TAMP_BKP8R_BKP_Msk                      /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP9R register  ****************/
#define TAMP_BKP9R_BKP_Pos                 (0U)
#define TAMP_BKP9R_BKP_Msk                 (0xFFFFFFFFUL << TAMP_BKP9R_BKP_Pos)    /*!< 0xFFFFFFFF */
#define TAMP_BKP9R_BKP                     TAMP_BKP9R_BKP_Msk                      /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP10R register  ***************/
#define TAMP_BKP10R_BKP_Pos                (0U)
#define TAMP_BKP10R_BKP_Msk                (0xFFFFFFFFUL << TAMP_BKP10R_BKP_Pos)   /*!< 0xFFFFFFFF */
#define TAMP_BKP10R_BKP                    TAMP_BKP10R_BKP_Msk                     /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP11R register  ***************/
#define TAMP_BKP11R_BKP_Pos                (0U)
#define TAMP_BKP11R_BKP_Msk                (0xFFFFFFFFUL << TAMP_BKP11R_BKP_Pos)   /*!< 0xFFFFFFFF */
#define TAMP_BKP11R_BKP                    TAMP_BKP11R_BKP_Msk                     /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP12R register  ***************/
#define TAMP_BKP12R_BKP_Pos                (0U)
#define TAMP_BKP12R_BKP_Msk                (0xFFFFFFFFUL << TAMP_BKP12R_BKP_Pos)   /*!< 0xFFFFFFFF */
#define TAMP_BKP12R_BKP                    TAMP_BKP12R_BKP_Msk                     /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP13R register  ***************/
#define TAMP_BKP13R_BKP_Pos               (0U)
#define TAMP_BKP13R_BKP_Msk               (0xFFFFFFFFUL << TAMP_BKP13R_BKP_Pos)   /*!< 0xFFFFFFFF */
#define TAMP_BKP13R_BKP                   TAMP_BKP13R_BKP_Msk                     /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP14R register  ***************/
#define TAMP_BKP14R_BKP_Pos               (0U)
#define TAMP_BKP14R_BKP_Msk               (0xFFFFFFFFUL << TAMP_BKP14R_BKP_Pos)   /*!< 0xFFFFFFFF */
#define TAMP_BKP14R_BKP                   TAMP_BKP14R_BKP_Msk                     /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP15R register  ***************/
#define TAMP_BKP15R_BKP_Pos               (0U)
#define TAMP_BKP15R_BKP_Msk               (0xFFFFFFFFUL << TAMP_BKP15R_BKP_Pos)   /*!< 0xFFFFFFFF */
#define TAMP_BKP15R_BKP                   TAMP_BKP15R_BKP_Msk                     /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP16R register  ***************/
#define TAMP_BKP16R_BKP_Pos               (0U)
#define TAMP_BKP16R_BKP_Msk               (0xFFFFFFFFUL << TAMP_BKP16R_BKP_Pos)   /*!< 0xFFFFFFFF */
#define TAMP_BKP16R_BKP                   TAMP_BKP16R_BKP_Msk                     /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP17R register  ***************/
#define TAMP_BKP17R_BKP_Pos               (0U)
#define TAMP_BKP17R_BKP_Msk               (0xFFFFFFFFUL << TAMP_BKP17R_BKP_Pos)   /*!< 0xFFFFFFFF */
#define TAMP_BKP17R_BKP                   TAMP_BKP17R_BKP_Msk                     /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP18R register  ***************/
#define TAMP_BKP18R_BKP_Pos               (0U)
#define TAMP_BKP18R_BKP_Msk               (0xFFFFFFFFUL << TAMP_BKP18R_BKP_Pos)   /*!< 0xFFFFFFFF */
#define TAMP_BKP18R_BKP                   TAMP_BKP18R_BKP_Msk                     /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP19R register  ***************/
#define TAMP_BKP19R_BKP_Pos               (0U)
#define TAMP_BKP19R_BKP_Msk               (0xFFFFFFFFUL << TAMP_BKP19R_BKP_Pos)   /*!< 0xFFFFFFFF */
#define TAMP_BKP19R_BKP                   TAMP_BKP19R_BKP_Msk                     /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP20R register  ***************/
#define TAMP_BKP20R_BKP_Pos               (0U)
#define TAMP_BKP20R_BKP_Msk               (0xFFFFFFFFUL << TAMP_BKP20R_BKP_Pos)   /*!< 0xFFFFFFFF */
#define TAMP_BKP20R_BKP                   TAMP_BKP20R_BKP_Msk                     /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP21R register  ***************/
#define TAMP_BKP21R_BKP_Pos               (0U)
#define TAMP_BKP21R_BKP_Msk               (0xFFFFFFFFUL << TAMP_BKP21R_BKP_Pos)   /*!< 0xFFFFFFFF */
#define TAMP_BKP21R_BKP                   TAMP_BKP21R_BKP_Msk                     /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP22R register  ***************/
#define TAMP_BKP22R_BKP_Pos               (0U)
#define TAMP_BKP22R_BKP_Msk               (0xFFFFFFFFUL << TAMP_BKP22R_BKP_Pos)   /*!< 0xFFFFFFFF */
#define TAMP_BKP22R_BKP                   TAMP_BKP22R_BKP_Msk                     /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP23R register  ***************/
#define TAMP_BKP23R_BKP_Pos               (0U)
#define TAMP_BKP23R_BKP_Msk               (0xFFFFFFFFUL << TAMP_BKP23R_BKP_Pos)   /*!< 0xFFFFFFFF */
#define TAMP_BKP23R_BKP                   TAMP_BKP23R_BKP_Msk                     /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP24R register  ***************/
#define TAMP_BKP24R_BKP_Pos               (0U)
#define TAMP_BKP24R_BKP_Msk               (0xFFFFFFFFUL << TAMP_BKP24R_BKP_Pos)   /*!< 0xFFFFFFFF */
#define TAMP_BKP24R_BKP                   TAMP_BKP24R_BKP_Msk                     /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP25R register  ***************/
#define TAMP_BKP25R_BKP_Pos               (0U)
#define TAMP_BKP25R_BKP_Msk               (0xFFFFFFFFUL << TAMP_BKP25R_BKP_Pos)   /*!< 0xFFFFFFFF */
#define TAMP_BKP25R_BKP                   TAMP_BKP25R_BKP_Msk                     /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP26R register  ***************/
#define TAMP_BKP26R_BKP_Pos              (0U)
#define TAMP_BKP26R_BKP_Msk              (0xFFFFFFFFUL << TAMP_BKP26R_BKP_Pos)   /*!< 0xFFFFFFFF */
#define TAMP_BKP26R_BKP                  TAMP_BKP26R_BKP_Msk                     /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP27R register  ***************/
#define TAMP_BKP27R_BKP_Pos              (0U)
#define TAMP_BKP27R_BKP_Msk              (0xFFFFFFFFUL << TAMP_BKP27R_BKP_Pos)   /*!< 0xFFFFFFFF */
#define TAMP_BKP27R_BKP                  TAMP_BKP27R_BKP_Msk                     /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP28R register  ***************/
#define TAMP_BKP28R_BKP_Pos              (0U)
#define TAMP_BKP28R_BKP_Msk              (0xFFFFFFFFUL << TAMP_BKP28R_BKP_Pos)   /*!< 0xFFFFFFFF */
#define TAMP_BKP28R_BKP                  TAMP_BKP28R_BKP_Msk                     /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP29R register  ***************/
#define TAMP_BKP29R_BKP_Pos              (0U)
#define TAMP_BKP29R_BKP_Msk              (0xFFFFFFFFUL << TAMP_BKP29R_BKP_Pos)   /*!< 0xFFFFFFFF */
#define TAMP_BKP29R_BKP                  TAMP_BKP29R_BKP_Msk                     /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP30R register  ***************/
#define TAMP_BKP30R_BKP_Pos             (0U)
#define TAMP_BKP30R_BKP_Msk             (0xFFFFFFFFUL << TAMP_BKP30R_BKP_Pos)   /*!< 0xFFFFFFFF */
#define TAMP_BKP30R_BKP                 TAMP_BKP30R_BKP_Msk                     /*!< The application can write or read data to and from these registers. */

/********************  Bits definition for TAMP_BKP31R register  ***************/
#define TAMP_BKP31R_BKP_Pos             (0U)
#define TAMP_BKP31R_BKP_Msk             (0xFFFFFFFFUL << TAMP_BKP31R_BKP_Pos)   /*!< 0xFFFFFFFF */
#define TAMP_BKP31R_BKP                 TAMP_BKP31R_BKP_Msk                     /*!< The application can write or read data to and from these registers. */

/******************************************************************************/
/*                                                                            */
/*                                    TIM                                     */
/*                                                                            */
/******************************************************************************/
/********************  Bit definition for TIM_CR1 register  ********************/
/*!< CEN configuration */
#define TIM_CR1_CEN_Pos      (0U)
#define TIM_CR1_CEN_Msk      (0x1UL << TIM_CR1_CEN_Pos)      /*!< 0x00000001 */
#define TIM_CR1_CEN          TIM_CR1_CEN_Msk                 /*!< CEN (Counter enable) */
/*!< UDIS configuration */
#define TIM_CR1_UDIS_Pos     (1U)
#define TIM_CR1_UDIS_Msk     (0x1UL << TIM_CR1_UDIS_Pos)     /*!< 0x00000002 */
#define TIM_CR1_UDIS         TIM_CR1_UDIS_Msk                /*!< UDIS (Update disable) */
/*!< URS configuration */
#define TIM_CR1_URS_Pos      (2U)
#define TIM_CR1_URS_Msk      (0x1UL << TIM_CR1_URS_Pos)      /*!< 0x00000004 */
#define TIM_CR1_URS          TIM_CR1_URS_Msk                 /*!< URS (Update request source) */
/*!< OPM configuration */
#define TIM_CR1_OPM_Pos      (3U)
#define TIM_CR1_OPM_Msk      (0x1UL << TIM_CR1_OPM_Pos)      /*!< 0x00000008 */
#define TIM_CR1_OPM          TIM_CR1_OPM_Msk                 /*!< OPM (One-pulse mode) */
/*!< DIR configuration */
#define TIM_CR1_DIR_Pos      (4U)
#define TIM_CR1_DIR_Msk      (0x1UL << TIM_CR1_DIR_Pos)      /*!< 0x00000010 */
#define TIM_CR1_DIR          TIM_CR1_DIR_Msk                 /*!< DIR (Direction) */
/*!< CMS configuration */
#define TIM_CR1_CMS_Pos      (5U)
#define TIM_CR1_CMS_Msk      (0x3UL << TIM_CR1_CMS_Pos)      /*!< 0x00000060 */
#define TIM_CR1_CMS          TIM_CR1_CMS_Msk                 /*!< CMS[1:0] bits (Center-aligned mode selection) */
#define TIM_CR1_CMS_0        (0x1UL << TIM_CR1_CMS_Pos)      /*!< 0x00000020 */
#define TIM_CR1_CMS_1        (0x2UL << TIM_CR1_CMS_Pos)      /*!< 0x00000040 */
/*!< ARPE configuration */
#define TIM_CR1_ARPE_Pos     (7U)
#define TIM_CR1_ARPE_Msk     (0x1UL << TIM_CR1_ARPE_Pos)     /*!< 0x00000080 */
#define TIM_CR1_ARPE         TIM_CR1_ARPE_Msk                /*!< ARPE (Auto-reload preload enable) */
/*!< CKD configuration */
#define TIM_CR1_CKD_Pos      (8U)
#define TIM_CR1_CKD_Msk      (0x3UL << TIM_CR1_CKD_Pos)      /*!< 0x00000300 */
#define TIM_CR1_CKD          TIM_CR1_CKD_Msk                 /*!< CKD[1:0] bits (Clock division) */
#define TIM_CR1_CKD_0        (0x1UL << TIM_CR1_CKD_Pos)      /*!< 0x00000100 */
#define TIM_CR1_CKD_1        (0x2UL << TIM_CR1_CKD_Pos)      /*!< 0x00000200 */
/*!< UIFREMAP configuration */
#define TIM_CR1_UIFREMAP_Pos (11U)
#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
#define TIM_CR1_UIFREMAP     TIM_CR1_UIFREMAP_Msk            /*!< UIFREMAP (UIF status bit remapping) */
/*!< DITHEN configuration */
#define TIM_CR1_DITHEN_Pos   (12U)
#define TIM_CR1_DITHEN_Msk   (0x1UL << TIM_CR1_DITHEN_Pos)   /*!< 0x00001000 */
#define TIM_CR1_DITHEN       TIM_CR1_DITHEN_Msk              /*!< DITHEN (Dithering enable) */
/*!< TGO2PSC configuration */
#define TIM_CR1_TGO2PSC_Pos  (16U)
#define TIM_CR1_TGO2PSC_Msk  (0x1FUL << TIM_CR1_TGO2PSC_Pos) /*!< 0x001F0000 */
#define TIM_CR1_TGO2PSC      TIM_CR1_TGO2PSC_Msk             /*!< TGO2PSC[4:0] bits (Trigger output 2 postscaler) */
/*!< CKD2 configuration */
#define TIM_CR1_CKD2_Pos     (24U)
#define TIM_CR1_CKD2_Msk     (0xFUL << TIM_CR1_CKD2_Pos)     /*!< 0x0F000000 */
#define TIM_CR1_CKD2         TIM_CR1_CKD2_Msk                /*!< CKD2[3:0] bits (Clock division 2) */
#define TIM_CR1_CKD2_0       (0x01UL << TIM_CR1_CKD2_Pos)    /*!< 0x01000000 */
#define TIM_CR1_CKD2_1       (0x02UL << TIM_CR1_CKD2_Pos)    /*!< 0x02000000 */
#define TIM_CR1_CKD2_2       (0x04UL << TIM_CR1_CKD2_Pos)    /*!< 0x04000000 */
#define TIM_CR1_CKD2_3       (0x08UL << TIM_CR1_CKD2_Pos)    /*!< 0x08000000 */

/********************  Bit definition for TIM_CR2 register  ********************/
/*!< CCPC configuration */
#define TIM_CR2_CCPC_Pos   (0U)
#define TIM_CR2_CCPC_Msk   (0x1UL << TIM_CR2_CCPC_Pos)     /*!< 0x00000001 */
#define TIM_CR2_CCPC       TIM_CR2_CCPC_Msk                /*!< CCPC (Capture/compare preloaded control) */
/*!< CCUS configuration */
#define TIM_CR2_CCUS_Pos   (2U)
#define TIM_CR2_CCUS_Msk   (0x1UL << TIM_CR2_CCUS_Pos)     /*!< 0x00000004 */
#define TIM_CR2_CCUS       TIM_CR2_CCUS_Msk                /*!< CCUS (Capture/compare control update selection) */
/*!< CCDS configuration */
#define TIM_CR2_CCDS_Pos   (3U)
#define TIM_CR2_CCDS_Msk   (0x1UL << TIM_CR2_CCDS_Pos)     /*!< 0x00000008 */
#define TIM_CR2_CCDS       TIM_CR2_CCDS_Msk                /*!< CCDS (Capture/compare DMA selection) */
/*!< MMS configuration */
#define TIM_CR2_MMS_Pos    (4U)
#define TIM_CR2_MMS_Msk    (0x200007UL << TIM_CR2_MMS_Pos) /*!< 0x02000070 */
#define TIM_CR2_MMS        TIM_CR2_MMS_Msk                 /*!< MMS[2:0] bits (Master mode selection) */
#define TIM_CR2_MMS_0      (0x000001UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
#define TIM_CR2_MMS_1      (0x000002UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
#define TIM_CR2_MMS_2      (0x000004UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
#define TIM_CR2_MMS_3      (0x200000UL << TIM_CR2_MMS_Pos) /*!< 0x02000000 */
/*!< TI1S configuration */
#define TIM_CR2_TI1S_Pos   (7U)
#define TIM_CR2_TI1S_Msk   (0x1UL << TIM_CR2_TI1S_Pos)     /*!< 0x00000080 */
#define TIM_CR2_TI1S       TIM_CR2_TI1S_Msk                /*!< TI1S (tim_ti1 selection) */
/*!< OIS1 configuration */
#define TIM_CR2_OIS1_Pos   (8U)
#define TIM_CR2_OIS1_Msk   (0x1UL << TIM_CR2_OIS1_Pos)     /*!< 0x00000100 */
#define TIM_CR2_OIS1       TIM_CR2_OIS1_Msk                /*!< OIS1 (Output idle state 1 (tim_oc1 output)) */
/*!< OIS1N configuration */
#define TIM_CR2_OIS1N_Pos  (9U)
#define TIM_CR2_OIS1N_Msk  (0x1UL << TIM_CR2_OIS1N_Pos)    /*!< 0x00000200 */
#define TIM_CR2_OIS1N      TIM_CR2_OIS1N_Msk               /*!< OIS1N (Output idle state 1 (tim_oc1n output)) */
/*!< OIS2 configuration */
#define TIM_CR2_OIS2_Pos   (10U)
#define TIM_CR2_OIS2_Msk   (0x1UL << TIM_CR2_OIS2_Pos)     /*!< 0x00000400 */
#define TIM_CR2_OIS2       TIM_CR2_OIS2_Msk                /*!< OIS2 (Output idle state 2 (tim_oc2 output)) */
/*!< OIS2N configuration */
#define TIM_CR2_OIS2N_Pos  (11U)
#define TIM_CR2_OIS2N_Msk  (0x1UL << TIM_CR2_OIS2N_Pos)    /*!< 0x00000800 */
#define TIM_CR2_OIS2N      TIM_CR2_OIS2N_Msk               /*!< OIS2N (Output idle state 2 (tim_oc2n output)) */
/*!< OIS3 configuration */
#define TIM_CR2_OIS3_Pos   (12U)
#define TIM_CR2_OIS3_Msk   (0x1UL << TIM_CR2_OIS3_Pos)     /*!< 0x00001000 */
#define TIM_CR2_OIS3       TIM_CR2_OIS3_Msk                /*!< OIS3 (Output idle state 3 (tim_oc3 output)) */
/*!< OIS3N configuration */
#define TIM_CR2_OIS3N_Pos  (13U)
#define TIM_CR2_OIS3N_Msk  (0x1UL << TIM_CR2_OIS3N_Pos)    /*!< 0x00002000 */
#define TIM_CR2_OIS3N      TIM_CR2_OIS3N_Msk               /*!< OIS3N (Output idle state 3 (tim_oc3n output)) */
/*!< OIS4 configuration */
#define TIM_CR2_OIS4_Pos   (14U)
#define TIM_CR2_OIS4_Msk   (0x1UL << TIM_CR2_OIS4_Pos)     /*!< 0x00004000 */
#define TIM_CR2_OIS4       TIM_CR2_OIS4_Msk                /*!< OIS4 (Output idle state 4 (tim_oc4 output)) */
/*!< OIS4N configuration */
#define TIM_CR2_OIS4N_Pos  (15U)
#define TIM_CR2_OIS4N_Msk  (0x1UL << TIM_CR2_OIS4N_Pos)    /*!< 0x00008000 */
#define TIM_CR2_OIS4N      TIM_CR2_OIS4N_Msk               /*!< OIS4N (Output idle state 4 (tim_oc4n output)) */
/*!< OIS5 configuration */
#define TIM_CR2_OIS5_Pos   (16U)
#define TIM_CR2_OIS5_Msk   (0x1UL << TIM_CR2_OIS5_Pos)     /*!< 0x00010000 */
#define TIM_CR2_OIS5       TIM_CR2_OIS5_Msk                /*!< OIS5 (Output idle state 5 (tim_oc5 output)) */
/*!< OIS6 configuration */
#define TIM_CR2_OIS6_Pos   (18U)
#define TIM_CR2_OIS6_Msk   (0x1UL << TIM_CR2_OIS6_Pos)     /*!< 0x00040000 */
#define TIM_CR2_OIS6       TIM_CR2_OIS6_Msk                /*!< OIS6 (Output idle state 6 (tim_oc6 output)) */
/*!< OIS7 configuration */
#define TIM_CR2_OIS7_Pos   (19U)
#define TIM_CR2_OIS7_Msk   (0x1UL << TIM_CR2_OIS7_Pos)     /*!< 0x00080000 */
#define TIM_CR2_OIS7       TIM_CR2_OIS7_Msk                /*!< OIS7 (Output idle state 7 (tim_oc7 output)) */
/*!< MMS2 configuration */
#define TIM_CR2_MMS2_Pos   (20U)
#define TIM_CR2_MMS2_Msk   (0x1FUL << TIM_CR2_MMS2_Pos)    /*!< 0x01F00000 */
#define TIM_CR2_MMS2       TIM_CR2_MMS2_Msk                /*!< MMS2[4:0] bits (Master mode selection 2) */
#define TIM_CR2_MMS2_0     (0x01UL << TIM_CR2_MMS2_Pos)    /*!< 0x00100000 */
#define TIM_CR2_MMS2_1     (0x02UL << TIM_CR2_MMS2_Pos)    /*!< 0x00200000 */
#define TIM_CR2_MMS2_2     (0x04UL << TIM_CR2_MMS2_Pos)    /*!< 0x00400000 */
#define TIM_CR2_MMS2_3     (0x08UL << TIM_CR2_MMS2_Pos)    /*!< 0x00800000 */
#define TIM_CR2_MMS2_4     (0x10UL << TIM_CR2_MMS2_Pos)    /*!< 0x01000000 */
/*!< XORPS configuration */
#define TIM_CR2_XORPS_Pos  (27U)
#define TIM_CR2_XORPS_Msk  (0x1UL << TIM_CR2_XORPS_Pos)    /*!< 0x08000000 */
#define TIM_CR2_XORPS      TIM_CR2_XORPS_Msk               /*!< XORPS (XOR gate position selection) */
/*!< ADSYNC configuration */
#define TIM_CR2_ADSYNC_Pos (28U)
#define TIM_CR2_ADSYNC_Msk (0x1UL << TIM_CR2_ADSYNC_Pos)   /*!< 0x10000000 */
#define TIM_CR2_ADSYNC     TIM_CR2_ADSYNC_Msk              /*!< ADSYNC (ADC synchronization) */
/*!< TI1INV configuration */
#define TIM_CR2_TI1INV_Pos (29U)
#define TIM_CR2_TI1INV_Msk (0x1UL << TIM_CR2_TI1INV_Pos)   /*!< 0x20000000 */
#define TIM_CR2_TI1INV     TIM_CR2_TI1INV_Msk              /*!< TI1INV (tim_ti{1} signal inversion on XOR gate input) */
/*!< TI2INV configuration */
#define TIM_CR2_TI2INV_Pos (30U)
#define TIM_CR2_TI2INV_Msk (0x1UL << TIM_CR2_TI2INV_Pos)   /*!< 0x40000000 */
#define TIM_CR2_TI2INV     TIM_CR2_TI2INV_Msk              /*!< TI2INV (tim_ti{1} signal inversion on XOR gate input) */
/*!< TI3INV configuration */
#define TIM_CR2_TI3INV_Pos (31U)
#define TIM_CR2_TI3INV_Msk (0x1UL << TIM_CR2_TI3INV_Pos)   /*!< 0x80000000 */
#define TIM_CR2_TI3INV     TIM_CR2_TI3INV_Msk              /*!< TI3INV (tim_ti{1} signal inversion on XOR gate input) */

/********************  Bit definition for TIM_SMCR register  ********************/
/*!< SMS configuration */
#define TIM_SMCR_SMS_Pos   (0U)
#define TIM_SMCR_SMS_Msk   (0x30007UL << TIM_SMCR_SMS_Pos) /*!< 0x00030007 */
#define TIM_SMCR_SMS       TIM_SMCR_SMS_Msk                /*!< SMS[2:0] bits (Slave mode selection) */
#define TIM_SMCR_SMS_0     (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
#define TIM_SMCR_SMS_1     (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2     (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
#define TIM_SMCR_SMS_3     (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
#define TIM_SMCR_SMS_4     (0x20000UL << TIM_SMCR_SMS_Pos) /*!< 0x00020000 */
/*!< OCCS configuration */
#define TIM_SMCR_OCCS_Pos  (3U)
#define TIM_SMCR_OCCS_Msk  (0x1UL << TIM_SMCR_OCCS_Pos)    /*!< 0x00000008 */
#define TIM_SMCR_OCCS      TIM_SMCR_OCCS_Msk               /*!< OCCS (OCREF clear selection) */
/*!< TS configuration */
#define TIM_SMCR_TS_Pos    (4U)
#define TIM_SMCR_TS_Msk    (0x30007UL << TIM_SMCR_TS_Pos)  /*!< 0x00300070 */
#define TIM_SMCR_TS        TIM_SMCR_TS_Msk                 /*!< TS[2:0] bits (Trigger selection) */
#define TIM_SMCR_TS_0      (0x00001UL << TIM_SMCR_TS_Pos)  /*!< 0x00000010 */
#define TIM_SMCR_TS_1      (0x00002UL << TIM_SMCR_TS_Pos)  /*!< 0x00000020 */
#define TIM_SMCR_TS_2      (0x00004UL << TIM_SMCR_TS_Pos)  /*!< 0x00000040 */
#define TIM_SMCR_TS_3      (0x10000UL << TIM_SMCR_TS_Pos)  /*!< 0x00100000 */
#define TIM_SMCR_TS_4      (0x20000UL << TIM_SMCR_TS_Pos)  /*!< 0x00200000 */
/*!< MSM configuration */
#define TIM_SMCR_MSM_Pos   (7U)
#define TIM_SMCR_MSM_Msk   (0x1UL << TIM_SMCR_MSM_Pos)     /*!< 0x00000080 */
#define TIM_SMCR_MSM       TIM_SMCR_MSM_Msk                /*!< MSM (Master/slave mode) */
/*!< ETF configuration */
#define TIM_SMCR_ETF_Pos   (8U)
#define TIM_SMCR_ETF_Msk   (0xFUL << TIM_SMCR_ETF_Pos)     /*!< 0x00000F00 */
#define TIM_SMCR_ETF       TIM_SMCR_ETF_Msk                /*!< ETF[3:0] bits (External trigger filter) */
#define TIM_SMCR_ETF_0     (0x01UL << TIM_SMCR_ETF_Pos)    /*!< 0x00000100 */
#define TIM_SMCR_ETF_1     (0x02UL << TIM_SMCR_ETF_Pos)    /*!< 0x00000200 */
#define TIM_SMCR_ETF_2     (0x04UL << TIM_SMCR_ETF_Pos)    /*!< 0x00000400 */
#define TIM_SMCR_ETF_3     (0x08UL << TIM_SMCR_ETF_Pos)    /*!< 0x00000800 */
/*!< ETPS configuration */
#define TIM_SMCR_ETPS_Pos  (12U)
#define TIM_SMCR_ETPS_Msk  (0x3UL << TIM_SMCR_ETPS_Pos)    /*!< 0x00003000 */
#define TIM_SMCR_ETPS      TIM_SMCR_ETPS_Msk               /*!< ETPS[1:0] bits (External trigger prescaler) */
#define TIM_SMCR_ETPS_0    (0x1UL << TIM_SMCR_ETPS_Pos)    /*!< 0x00001000 */
#define TIM_SMCR_ETPS_1    (0x2UL << TIM_SMCR_ETPS_Pos)    /*!< 0x00002000 */
/*!< ECE configuration */
#define TIM_SMCR_ECE_Pos   (14U)
#define TIM_SMCR_ECE_Msk   (0x1UL << TIM_SMCR_ECE_Pos)     /*!< 0x00004000 */
#define TIM_SMCR_ECE       TIM_SMCR_ECE_Msk                /*!< ECE (External clock enable) */
/*!< ETP configuration */
#define TIM_SMCR_ETP_Pos   (15U)
#define TIM_SMCR_ETP_Msk   (0x1UL << TIM_SMCR_ETP_Pos)     /*!< 0x00008000 */
#define TIM_SMCR_ETP       TIM_SMCR_ETP_Msk                /*!< ETP (External trigger polarity) */
/*!< SMSPE configuration */
#define TIM_SMCR_SMSPE_Pos (24U)
#define TIM_SMCR_SMSPE_Msk (0x1UL << TIM_SMCR_SMSPE_Pos)   /*!< 0x01000000 */
#define TIM_SMCR_SMSPE     TIM_SMCR_SMSPE_Msk              /*!< SMSPE (SMS preload enable) */
/*!< SMSPS configuration */
#define TIM_SMCR_SMSPS_Pos (25U)
#define TIM_SMCR_SMSPS_Msk (0x1UL << TIM_SMCR_SMSPS_Pos)   /*!< 0x02000000 */
#define TIM_SMCR_SMSPS     TIM_SMCR_SMSPS_Msk              /*!< SMSPS (SMS preload source) */
/*!< SETPS configuration */
#define TIM_SMCR_SETPS_Pos (26U)
#define TIM_SMCR_SETPS_Msk (0xFUL << TIM_SMCR_SETPS_Pos)   /*!< 0x3C000000 */
#define TIM_SMCR_SETPS     TIM_SMCR_SETPS_Msk              /*!< SETPS[3:0] bits (Synchronous External Trigger Prescaler) */
#define TIM_SMCR_SETPS_0   (0x01UL << TIM_SMCR_SETPS_Pos)  /*!< 0x04000000 */
#define TIM_SMCR_SETPS_1   (0x02UL << TIM_SMCR_SETPS_Pos)  /*!< 0x08000000 */
#define TIM_SMCR_SETPS_2   (0x04UL << TIM_SMCR_SETPS_Pos)  /*!< 0x10000000 */
#define TIM_SMCR_SETPS_3   (0x08UL << TIM_SMCR_SETPS_Pos)  /*!< 0x20000000 */

/********************  Bit definition for TIM_DIER register  ********************/
/*!< UIE configuration */
#define TIM_DIER_UIE_Pos    (0U)
#define TIM_DIER_UIE_Msk    (0x1UL << TIM_DIER_UIE_Pos)    /*!< 0x00000001 */
#define TIM_DIER_UIE        TIM_DIER_UIE_Msk               /*!< UIE (Update interrupt enable) */
/*!< CC1IE configuration */
#define TIM_DIER_CC1IE_Pos  (1U)
#define TIM_DIER_CC1IE_Msk  (0x1UL << TIM_DIER_CC1IE_Pos)  /*!< 0x00000002 */
#define TIM_DIER_CC1IE      TIM_DIER_CC1IE_Msk             /*!< CC1IE (Capture/compare 1 interrupt enable) */
/*!< CC2IE configuration */
#define TIM_DIER_CC2IE_Pos  (2U)
#define TIM_DIER_CC2IE_Msk  (0x1UL << TIM_DIER_CC2IE_Pos)  /*!< 0x00000004 */
#define TIM_DIER_CC2IE      TIM_DIER_CC2IE_Msk             /*!< CC2IE (Capture/compare 2 interrupt enable) */
/*!< CC3IE configuration */
#define TIM_DIER_CC3IE_Pos  (3U)
#define TIM_DIER_CC3IE_Msk  (0x1UL << TIM_DIER_CC3IE_Pos)  /*!< 0x00000008 */
#define TIM_DIER_CC3IE      TIM_DIER_CC3IE_Msk             /*!< CC3IE (Capture/compare 3 interrupt enable) */
/*!< CC4IE configuration */
#define TIM_DIER_CC4IE_Pos  (4U)
#define TIM_DIER_CC4IE_Msk  (0x1UL << TIM_DIER_CC4IE_Pos)  /*!< 0x00000010 */
#define TIM_DIER_CC4IE      TIM_DIER_CC4IE_Msk             /*!< CC4IE (Capture/compare 4 interrupt enable) */
/*!< COMIE configuration */
#define TIM_DIER_COMIE_Pos  (5U)
#define TIM_DIER_COMIE_Msk  (0x1UL << TIM_DIER_COMIE_Pos)  /*!< 0x00000020 */
#define TIM_DIER_COMIE      TIM_DIER_COMIE_Msk             /*!< COMIE (COM interrupt enable) */
/*!< TIE configuration */
#define TIM_DIER_TIE_Pos    (6U)
#define TIM_DIER_TIE_Msk    (0x1UL << TIM_DIER_TIE_Pos)    /*!< 0x00000040 */
#define TIM_DIER_TIE        TIM_DIER_TIE_Msk               /*!< TIE (Trigger interrupt enable) */
/*!< BIE configuration */
#define TIM_DIER_BIE_Pos    (7U)
#define TIM_DIER_BIE_Msk    (0x1UL << TIM_DIER_BIE_Pos)    /*!< 0x00000080 */
#define TIM_DIER_BIE        TIM_DIER_BIE_Msk               /*!< BIE (Break interrupt enable) */
/*!< UDE configuration */
#define TIM_DIER_UDE_Pos    (8U)
#define TIM_DIER_UDE_Msk    (0x1UL << TIM_DIER_UDE_Pos)    /*!< 0x00000100 */
#define TIM_DIER_UDE        TIM_DIER_UDE_Msk               /*!< UDE (Update DMA request enable) */
/*!< CC1DE configuration */
#define TIM_DIER_CC1DE_Pos  (9U)
#define TIM_DIER_CC1DE_Msk  (0x1UL << TIM_DIER_CC1DE_Pos)  /*!< 0x00000200 */
#define TIM_DIER_CC1DE      TIM_DIER_CC1DE_Msk             /*!< CC1DE (Capture/compare 1 DMA request enable) */
/*!< CC2DE configuration */
#define TIM_DIER_CC2DE_Pos  (10U)
#define TIM_DIER_CC2DE_Msk  (0x1UL << TIM_DIER_CC2DE_Pos)  /*!< 0x00000400 */
#define TIM_DIER_CC2DE      TIM_DIER_CC2DE_Msk             /*!< CC2DE (Capture/compare 2 DMA request enable) */
/*!< CC3DE configuration */
#define TIM_DIER_CC3DE_Pos  (11U)
#define TIM_DIER_CC3DE_Msk  (0x1UL << TIM_DIER_CC3DE_Pos)  /*!< 0x00000800 */
#define TIM_DIER_CC3DE      TIM_DIER_CC3DE_Msk             /*!< CC3DE (Capture/compare 3 DMA request enable) */
/*!< CC4DE configuration */
#define TIM_DIER_CC4DE_Pos  (12U)
#define TIM_DIER_CC4DE_Msk  (0x1UL << TIM_DIER_CC4DE_Pos)  /*!< 0x00001000 */
#define TIM_DIER_CC4DE      TIM_DIER_CC4DE_Msk             /*!< CC4DE (Capture/compare 4 DMA request enable) */
/*!< COMDE configuration */
#define TIM_DIER_COMDE_Pos  (13U)
#define TIM_DIER_COMDE_Msk  (0x1UL << TIM_DIER_COMDE_Pos)  /*!< 0x00002000 */
#define TIM_DIER_COMDE      TIM_DIER_COMDE_Msk             /*!< COMDE (COM DMA request enable) */
/*!< TDE configuration */
#define TIM_DIER_TDE_Pos    (14U)
#define TIM_DIER_TDE_Msk    (0x1UL << TIM_DIER_TDE_Pos)    /*!< 0x00004000 */
#define TIM_DIER_TDE        TIM_DIER_TDE_Msk               /*!< TDE (Trigger DMA request enable) */
/*!< IDXIE configuration */
#define TIM_DIER_IDXIE_Pos  (20U)
#define TIM_DIER_IDXIE_Msk  (0x1UL << TIM_DIER_IDXIE_Pos)  /*!< 0x00100000 */
#define TIM_DIER_IDXIE      TIM_DIER_IDXIE_Msk             /*!< IDXIE (Index interrupt enable) */
/*!< DIRIE configuration */
#define TIM_DIER_DIRIE_Pos  (21U)
#define TIM_DIER_DIRIE_Msk  (0x1UL << TIM_DIER_DIRIE_Pos)  /*!< 0x00200000 */
#define TIM_DIER_DIRIE      TIM_DIER_DIRIE_Msk             /*!< DIRIE (Direction change interrupt enable) */
/*!< IERRIE configuration */
#define TIM_DIER_IERRIE_Pos (22U)
#define TIM_DIER_IERRIE_Msk (0x1UL << TIM_DIER_IERRIE_Pos) /*!< 0x00400000 */
#define TIM_DIER_IERRIE     TIM_DIER_IERRIE_Msk            /*!< IERRIE (Index error interrupt enable) */
/*!< TERRIE configuration */
#define TIM_DIER_TERRIE_Pos (23U)
#define TIM_DIER_TERRIE_Msk (0x1UL << TIM_DIER_TERRIE_Pos) /*!< 0x00800000 */
#define TIM_DIER_TERRIE     TIM_DIER_TERRIE_Msk            /*!< TERRIE (Transition error interrupt enable) */

/********************  Bit definition for TIM_SR register  ********************/
/*!< UIF configuration */
#define TIM_SR_UIF_Pos    (0U)
#define TIM_SR_UIF_Msk    (0x1UL << TIM_SR_UIF_Pos)    /*!< 0x00000001 */
#define TIM_SR_UIF        TIM_SR_UIF_Msk               /*!< UIF (Update interrupt flag) */
/*!< CC1IF configuration */
#define TIM_SR_CC1IF_Pos  (1U)
#define TIM_SR_CC1IF_Msk  (0x1UL << TIM_SR_CC1IF_Pos)  /*!< 0x00000002 */
#define TIM_SR_CC1IF      TIM_SR_CC1IF_Msk             /*!< CC1IF (Capture/compare 1 interrupt flag) */
/*!< CC2IF configuration */
#define TIM_SR_CC2IF_Pos  (2U)
#define TIM_SR_CC2IF_Msk  (0x1UL << TIM_SR_CC2IF_Pos)  /*!< 0x00000004 */
#define TIM_SR_CC2IF      TIM_SR_CC2IF_Msk             /*!< CC2IF (Capture/compare 2 interrupt flag) */
/*!< CC3IF configuration */
#define TIM_SR_CC3IF_Pos  (3U)
#define TIM_SR_CC3IF_Msk  (0x1UL << TIM_SR_CC3IF_Pos)  /*!< 0x00000008 */
#define TIM_SR_CC3IF      TIM_SR_CC3IF_Msk             /*!< CC3IF (Capture/compare 3 interrupt flag) */
/*!< CC4IF configuration */
#define TIM_SR_CC4IF_Pos  (4U)
#define TIM_SR_CC4IF_Msk  (0x1UL << TIM_SR_CC4IF_Pos)  /*!< 0x00000010 */
#define TIM_SR_CC4IF      TIM_SR_CC4IF_Msk             /*!< CC4IF (Capture/compare 4 interrupt flag) */
/*!< COMIF configuration */
#define TIM_SR_COMIF_Pos  (5U)
#define TIM_SR_COMIF_Msk  (0x1UL << TIM_SR_COMIF_Pos)  /*!< 0x00000020 */
#define TIM_SR_COMIF      TIM_SR_COMIF_Msk             /*!< COMIF (COM interrupt flag) */
/*!< TIF configuration */
#define TIM_SR_TIF_Pos    (6U)
#define TIM_SR_TIF_Msk    (0x1UL << TIM_SR_TIF_Pos)    /*!< 0x00000040 */
#define TIM_SR_TIF        TIM_SR_TIF_Msk               /*!< TIF (Trigger interrupt flag) */
/*!< BIF configuration */
#define TIM_SR_BIF_Pos    (7U)
#define TIM_SR_BIF_Msk    (0x1UL << TIM_SR_BIF_Pos)    /*!< 0x00000080 */
#define TIM_SR_BIF        TIM_SR_BIF_Msk               /*!< BIF (Break interrupt flag) */
/*!< B2IF configuration */
#define TIM_SR_B2IF_Pos   (8U)
#define TIM_SR_B2IF_Msk   (0x1UL << TIM_SR_B2IF_Pos)   /*!< 0x00000100 */
#define TIM_SR_B2IF       TIM_SR_B2IF_Msk              /*!< B2IF (Break 2 interrupt flag) */
/*!< CC1OF configuration */
#define TIM_SR_CC1OF_Pos  (9U)
#define TIM_SR_CC1OF_Msk  (0x1UL << TIM_SR_CC1OF_Pos)  /*!< 0x00000200 */
#define TIM_SR_CC1OF      TIM_SR_CC1OF_Msk             /*!< CC1OF (Capture/compare 1 overcapture flag) */
/*!< CC2OF configuration */
#define TIM_SR_CC2OF_Pos  (10U)
#define TIM_SR_CC2OF_Msk  (0x1UL << TIM_SR_CC2OF_Pos)  /*!< 0x00000400 */
#define TIM_SR_CC2OF      TIM_SR_CC2OF_Msk             /*!< CC2OF (Capture/compare 2 overcapture flag) */
/*!< CC3OF configuration */
#define TIM_SR_CC3OF_Pos  (11U)
#define TIM_SR_CC3OF_Msk  (0x1UL << TIM_SR_CC3OF_Pos)  /*!< 0x00000800 */
#define TIM_SR_CC3OF      TIM_SR_CC3OF_Msk             /*!< CC3OF (Capture/compare 3 overcapture flag) */
/*!< CC4OF configuration */
#define TIM_SR_CC4OF_Pos  (12U)
#define TIM_SR_CC4OF_Msk  (0x1UL << TIM_SR_CC4OF_Pos)  /*!< 0x00001000 */
#define TIM_SR_CC4OF      TIM_SR_CC4OF_Msk             /*!< CC4OF (Capture/compare 4 overcapture flag) */
/*!< SBIF configuration */
#define TIM_SR_SBIF_Pos   (13U)
#define TIM_SR_SBIF_Msk   (0x1UL << TIM_SR_SBIF_Pos)   /*!< 0x00002000 */
#define TIM_SR_SBIF       TIM_SR_SBIF_Msk              /*!< SBIF (System break interrupt flag) */
/*!< BGF configuration */
#define TIM_SR_BGF_Pos    (14U)
#define TIM_SR_BGF_Msk    (0x1UL << TIM_SR_BGF_Pos)    /*!< 0x00004000 */
#define TIM_SR_BGF        TIM_SR_BGF_Msk               /*!< BGF (Break generation flag) */
/*!< B2GF configuration */
#define TIM_SR_B2GF_Pos   (15U)
#define TIM_SR_B2GF_Msk   (0x1UL << TIM_SR_B2GF_Pos)   /*!< 0x00008000 */
#define TIM_SR_B2GF       TIM_SR_B2GF_Msk              /*!< B2GF (Break 2 generation flag) */
/*!< CC5IF configuration */
#define TIM_SR_CC5IF_Pos  (16U)
#define TIM_SR_CC5IF_Msk  (0x1UL << TIM_SR_CC5IF_Pos)  /*!< 0x00010000 */
#define TIM_SR_CC5IF      TIM_SR_CC5IF_Msk             /*!< CC5IF (Compare 5 interrupt flag) */
/*!< CC6IF configuration */
#define TIM_SR_CC6IF_Pos  (17U)
#define TIM_SR_CC6IF_Msk  (0x1UL << TIM_SR_CC6IF_Pos)  /*!< 0x00020000 */
#define TIM_SR_CC6IF      TIM_SR_CC6IF_Msk             /*!< CC6IF (Compare 6 interrupt flag) */
/*!< CC7IF configuration */
#define TIM_SR_CC7IF_Pos  (18U)
#define TIM_SR_CC7IF_Msk  (0x1UL << TIM_SR_CC7IF_Pos)  /*!< 0x00040000 */
#define TIM_SR_CC7IF      TIM_SR_CC7IF_Msk             /*!< CC7IF (Compare 7 interrupt flag) */
/*!< IDXF configuration */
#define TIM_SR_IDXF_Pos   (20U)
#define TIM_SR_IDXF_Msk   (0x1UL << TIM_SR_IDXF_Pos)   /*!< 0x00100000 */
#define TIM_SR_IDXF       TIM_SR_IDXF_Msk              /*!< IDXF (Index interrupt flag) */
/*!< DIRF configuration */
#define TIM_SR_DIRF_Pos   (21U)
#define TIM_SR_DIRF_Msk   (0x1UL << TIM_SR_DIRF_Pos)   /*!< 0x00200000 */
#define TIM_SR_DIRF       TIM_SR_DIRF_Msk              /*!< DIRF (Direction change interrupt flag) */
/*!< IERRF configuration */
#define TIM_SR_IERRF_Pos  (22U)
#define TIM_SR_IERRF_Msk  (0x1UL << TIM_SR_IERRF_Pos)  /*!< 0x00400000 */
#define TIM_SR_IERRF      TIM_SR_IERRF_Msk             /*!< IERRF (Index error interrupt flag) */
/*!< TERRF configuration */
#define TIM_SR_TERRF_Pos  (23U)
#define TIM_SR_TERRF_Msk  (0x1UL << TIM_SR_TERRF_Pos)  /*!< 0x00800000 */
#define TIM_SR_TERRF      TIM_SR_TERRF_Msk             /*!< TERRF (Transition error interrupt flag) */
/*!< UIOVRF configuration */
#define TIM_SR_UIOVRF_Pos (24U)
#define TIM_SR_UIOVRF_Msk (0x1UL << TIM_SR_UIOVRF_Pos) /*!< 0x01000000 */
#define TIM_SR_UIOVRF     TIM_SR_UIOVRF_Msk            /*!< UIOVRF (Update Interrupt Overrun flag) */
/*!< ODS configuration */
#define TIM_SR_ODS_Pos    (25U)
#define TIM_SR_ODS_Msk    (0x1UL << TIM_SR_ODS_Pos)    /*!< 0x02000000 */
#define TIM_SR_ODS        TIM_SR_ODS_Msk               /*!< ODS (Output disable status) */
/*!< TI1FS configuration */
#define TIM_SR_TI1FS_Pos  (28U)
#define TIM_SR_TI1FS_Msk  (0x1UL << TIM_SR_TI1FS_Pos)  /*!< 0x10000000 */
#define TIM_SR_TI1FS      TIM_SR_TI1FS_Msk             /*!< TI1FS (tim_in1f status) */
/*!< TI2FS configuration */
#define TIM_SR_TI2FS_Pos  (29U)
#define TIM_SR_TI2FS_Msk  (0x1UL << TIM_SR_TI2FS_Pos)  /*!< 0x20000000 */
#define TIM_SR_TI2FS      TIM_SR_TI2FS_Msk             /*!< TI2FS (tim_in2f status) */
/*!< TI3FS configuration */
#define TIM_SR_TI3FS_Pos  (30U)
#define TIM_SR_TI3FS_Msk  (0x1UL << TIM_SR_TI3FS_Pos)  /*!< 0x40000000 */
#define TIM_SR_TI3FS      TIM_SR_TI3FS_Msk             /*!< TI3FS (tim_in3f status) */
/*!< TI4FS configuration */
#define TIM_SR_TI4FS_Pos  (31U)
#define TIM_SR_TI4FS_Msk  (0x1UL << TIM_SR_TI4FS_Pos)  /*!< 0x80000000 */
#define TIM_SR_TI4FS      TIM_SR_TI4FS_Msk             /*!< TI4FS (tim_in4f status) */

/********************  Bit definition for TIM_EGR register  ********************/
/*!< UG configuration */
#define TIM_EGR_UG_Pos   (0U)
#define TIM_EGR_UG_Msk   (0x1UL << TIM_EGR_UG_Pos)   /*!< 0x00000001 */
#define TIM_EGR_UG       TIM_EGR_UG_Msk              /*!< UG (Update generation) */
/*!< CC1G configuration */
#define TIM_EGR_CC1G_Pos (1U)
#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
#define TIM_EGR_CC1G     TIM_EGR_CC1G_Msk            /*!< CC1G (Capture/compare 1  generation) */
/*!< CC2G configuration */
#define TIM_EGR_CC2G_Pos (2U)
#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
#define TIM_EGR_CC2G     TIM_EGR_CC2G_Msk            /*!< CC2G (Capture/compare 2  generation) */
/*!< CC3G configuration */
#define TIM_EGR_CC3G_Pos (3U)
#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
#define TIM_EGR_CC3G     TIM_EGR_CC3G_Msk            /*!< CC3G (Capture/compare 3  generation) */
/*!< CC4G configuration */
#define TIM_EGR_CC4G_Pos (4U)
#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
#define TIM_EGR_CC4G     TIM_EGR_CC4G_Msk            /*!< CC4G (Capture/compare 4  generation) */
/*!< COMG configuration */
#define TIM_EGR_COMG_Pos (5U)
#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
#define TIM_EGR_COMG     TIM_EGR_COMG_Msk            /*!< COMG (Capture/compare control update generation) */
/*!< TG configuration */
#define TIM_EGR_TG_Pos   (6U)
#define TIM_EGR_TG_Msk   (0x1UL << TIM_EGR_TG_Pos)   /*!< 0x00000040 */
#define TIM_EGR_TG       TIM_EGR_TG_Msk              /*!< TG (Trigger generation) */
/*!< BG configuration */
#define TIM_EGR_BG_Pos   (7U)
#define TIM_EGR_BG_Msk   (0x1UL << TIM_EGR_BG_Pos)   /*!< 0x00000080 */
#define TIM_EGR_BG       TIM_EGR_BG_Msk              /*!< BG (Break generation) */
/*!< B2G configuration */
#define TIM_EGR_B2G_Pos  (8U)
#define TIM_EGR_B2G_Msk  (0x1UL << TIM_EGR_B2G_Pos)  /*!< 0x00000100 */
#define TIM_EGR_B2G      TIM_EGR_B2G_Msk             /*!< B2G (Break 2 generation) */

/********************  Bit definition for TIM_CCMR1 register  ********************/
/*!< CC1S configuration */
#define TIM_CCMR1_CC1S_Pos   (0U)
#define TIM_CCMR1_CC1S_Msk   (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
#define TIM_CCMR1_CC1S       TIM_CCMR1_CC1S_Msk                  /*!< CC1S[1:0] bits (Capture/compare 1 selection) */
#define TIM_CCMR1_CC1S_0     (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
#define TIM_CCMR1_CC1S_1     (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
/*!< IC1PSC configuration */
#define TIM_CCMR1_IC1PSC_Pos (2U)
#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
#define TIM_CCMR1_IC1PSC     TIM_CCMR1_IC1PSC_Msk                /*!< IC1PSC[1:0] bits (Input capture 1 prescaler) */
#define TIM_CCMR1_IC1PSC_0   (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
#define TIM_CCMR1_IC1PSC_1   (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
/*!< IC1F configuration */
#define TIM_CCMR1_IC1F_Pos   (4U)
#define TIM_CCMR1_IC1F_Msk   (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
#define TIM_CCMR1_IC1F       TIM_CCMR1_IC1F_Msk                  /*!< IC1F[3:0] bits (Input capture 1 filter) */
#define TIM_CCMR1_IC1F_0     (0x01UL << TIM_CCMR1_IC1F_Pos)      /*!< 0x00000010 */
#define TIM_CCMR1_IC1F_1     (0x02UL << TIM_CCMR1_IC1F_Pos)      /*!< 0x00000020 */
#define TIM_CCMR1_IC1F_2     (0x04UL << TIM_CCMR1_IC1F_Pos)      /*!< 0x00000040 */
#define TIM_CCMR1_IC1F_3     (0x08UL << TIM_CCMR1_IC1F_Pos)      /*!< 0x00000080 */
/*!< CC2S configuration */
#define TIM_CCMR1_CC2S_Pos   (8U)
#define TIM_CCMR1_CC2S_Msk   (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
#define TIM_CCMR1_CC2S       TIM_CCMR1_CC2S_Msk                  /*!< CC2S[1:0] bits (Capture/compare 2 selection) */
#define TIM_CCMR1_CC2S_0     (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
#define TIM_CCMR1_CC2S_1     (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
/*!< IC2PSC configuration */
#define TIM_CCMR1_IC2PSC_Pos (10U)
#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
#define TIM_CCMR1_IC2PSC     TIM_CCMR1_IC2PSC_Msk                /*!< IC2PSC[1:0] bits (Input capture 2 prescaler) */
#define TIM_CCMR1_IC2PSC_0   (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
#define TIM_CCMR1_IC2PSC_1   (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
/*!< IC2F configuration */
#define TIM_CCMR1_IC2F_Pos   (12U)
#define TIM_CCMR1_IC2F_Msk   (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
#define TIM_CCMR1_IC2F       TIM_CCMR1_IC2F_Msk                  /*!< IC2F[3:0] bits (Input capture 2 filter) */
#define TIM_CCMR1_IC2F_0     (0x01UL << TIM_CCMR1_IC2F_Pos)      /*!< 0x00001000 */
#define TIM_CCMR1_IC2F_1     (0x02UL << TIM_CCMR1_IC2F_Pos)      /*!< 0x00002000 */
#define TIM_CCMR1_IC2F_2     (0x04UL << TIM_CCMR1_IC2F_Pos)      /*!< 0x00004000 */
#define TIM_CCMR1_IC2F_3     (0x08UL << TIM_CCMR1_IC2F_Pos)      /*!< 0x00008000 */

/*-------------------------------------------------------------------------------*/
/*!< OC1FE configuration */
#define TIM_CCMR1_OC1FE_Pos  (2U)
#define TIM_CCMR1_OC1FE_Msk  (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
#define TIM_CCMR1_OC1FE      TIM_CCMR1_OC1FE_Msk                 /*!< OC1FE (Output compare 1 fast enable) */
/*!< OC1PE configuration */
#define TIM_CCMR1_OC1PE_Pos  (3U)
#define TIM_CCMR1_OC1PE_Msk  (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
#define TIM_CCMR1_OC1PE      TIM_CCMR1_OC1PE_Msk                 /*!< OC1PE (Output compare 1 preload enable) */
/*!< OC1M configuration */
#define TIM_CCMR1_OC1M_Pos   (4U)
#define TIM_CCMR1_OC1M_Msk   (0x3007UL << TIM_CCMR1_OC1M_Pos)    /*!< 0x00030070 */
#define TIM_CCMR1_OC1M       TIM_CCMR1_OC1M_Msk                  /*!< OC1M[2:0] bits (Output compare 1 mode) */
#define TIM_CCMR1_OC1M_0     (0x0001UL << TIM_CCMR1_OC1M_Pos)    /*!< 0x00000010 */
#define TIM_CCMR1_OC1M_1     (0x0002UL << TIM_CCMR1_OC1M_Pos)    /*!< 0x00000020 */
#define TIM_CCMR1_OC1M_2     (0x0004UL << TIM_CCMR1_OC1M_Pos)    /*!< 0x00000040 */
#define TIM_CCMR1_OC1M_3     (0x1000UL << TIM_CCMR1_OC1M_Pos)    /*!< 0x00010000 */
#define TIM_CCMR1_OC1M_4     (0x2000UL << TIM_CCMR1_OC1M_Pos)    /*!< 0x00020000 */
/*!< OC1CE configuration */
#define TIM_CCMR1_OC1CE_Pos  (7U)
#define TIM_CCMR1_OC1CE_Msk  (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
#define TIM_CCMR1_OC1CE      TIM_CCMR1_OC1CE_Msk                 /*!< OC1CE (Output compare 1 clear enable) */
/*!< OC2FE configuration */
#define TIM_CCMR1_OC2FE_Pos  (10U)
#define TIM_CCMR1_OC2FE_Msk  (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
#define TIM_CCMR1_OC2FE      TIM_CCMR1_OC2FE_Msk                 /*!< OC2FE (Output compare 2 fast enable) */
/*!< OC2PE configuration */
#define TIM_CCMR1_OC2PE_Pos  (11U)
#define TIM_CCMR1_OC2PE_Msk  (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
#define TIM_CCMR1_OC2PE      TIM_CCMR1_OC2PE_Msk                 /*!< OC2PE (Output compare 2 preload enable) */
/*!< OC2M configuration */
#define TIM_CCMR1_OC2M_Pos   (12U)
#define TIM_CCMR1_OC2M_Msk   (0x3007UL << TIM_CCMR1_OC2M_Pos)    /*!< 0x03007000 */
#define TIM_CCMR1_OC2M       TIM_CCMR1_OC2M_Msk                  /*!< OC2M[2:0] bits (Output compare 2 mode) */
#define TIM_CCMR1_OC2M_0     (0x0001UL << TIM_CCMR1_OC2M_Pos)    /*!< 0x00001000 */
#define TIM_CCMR1_OC2M_1     (0x0002UL << TIM_CCMR1_OC2M_Pos)    /*!< 0x00002000 */
#define TIM_CCMR1_OC2M_2     (0x0004UL << TIM_CCMR1_OC2M_Pos)    /*!< 0x00004000 */
#define TIM_CCMR1_OC2M_3     (0x1000UL << TIM_CCMR1_OC2M_Pos)    /*!< 0x01000000 */
#define TIM_CCMR1_OC2M_4     (0x2000UL << TIM_CCMR1_OC2M_Pos)    /*!< 0x02000000 */
/*!< OC2CE configuration */
#define TIM_CCMR1_OC2CE_Pos  (15U)
#define TIM_CCMR1_OC2CE_Msk  (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
#define TIM_CCMR1_OC2CE      TIM_CCMR1_OC2CE_Msk                 /*!< OC2CE (Output compare 2 clear enable) */

/********************  Bit definition for TIM_CCMR2 register  ********************/
/*!< CC3S configuration */
#define TIM_CCMR2_CC3S_Pos   (0U)
#define TIM_CCMR2_CC3S_Msk   (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
#define TIM_CCMR2_CC3S       TIM_CCMR2_CC3S_Msk                  /*!< CC3S[1:0] bits (Capture/compare 3 selection) */
#define TIM_CCMR2_CC3S_0     (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
#define TIM_CCMR2_CC3S_1     (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
/*!< IC3PSC configuration */
#define TIM_CCMR2_IC3PSC_Pos (2U)
#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
#define TIM_CCMR2_IC3PSC     TIM_CCMR2_IC3PSC_Msk                /*!< IC3PSC[1:0] bits (Input capture 3 prescaler) */
#define TIM_CCMR2_IC3PSC_0   (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
#define TIM_CCMR2_IC3PSC_1   (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
/*!< IC3F configuration */
#define TIM_CCMR2_IC3F_Pos   (4U)
#define TIM_CCMR2_IC3F_Msk   (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
#define TIM_CCMR2_IC3F       TIM_CCMR2_IC3F_Msk                  /*!< IC3F[3:0] bits (Input capture 3 filter) */
#define TIM_CCMR2_IC3F_0     (0x01UL << TIM_CCMR2_IC3F_Pos)      /*!< 0x00000010 */
#define TIM_CCMR2_IC3F_1     (0x02UL << TIM_CCMR2_IC3F_Pos)      /*!< 0x00000020 */
#define TIM_CCMR2_IC3F_2     (0x04UL << TIM_CCMR2_IC3F_Pos)      /*!< 0x00000040 */
#define TIM_CCMR2_IC3F_3     (0x08UL << TIM_CCMR2_IC3F_Pos)      /*!< 0x00000080 */
/*!< IC4PSC configuration */
#define TIM_CCMR2_IC4PSC_Pos (10U)
#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
#define TIM_CCMR2_IC4PSC     TIM_CCMR2_IC4PSC_Msk                /*!< IC4PSC[1:0] bits (Input capture 4 prescaler) */
#define TIM_CCMR2_IC4PSC_0   (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
#define TIM_CCMR2_IC4PSC_1   (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
/*!< IC4F configuration */
#define TIM_CCMR2_IC4F_Pos   (12U)
#define TIM_CCMR2_IC4F_Msk   (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
#define TIM_CCMR2_IC4F       TIM_CCMR2_IC4F_Msk                  /*!< IC4F[3:0] bits (Input capture 4 filter) */
#define TIM_CCMR2_IC4F_0     (0x01UL << TIM_CCMR2_IC4F_Pos)      /*!< 0x00001000 */
#define TIM_CCMR2_IC4F_1     (0x02UL << TIM_CCMR2_IC4F_Pos)      /*!< 0x00002000 */
#define TIM_CCMR2_IC4F_2     (0x04UL << TIM_CCMR2_IC4F_Pos)      /*!< 0x00004000 */
#define TIM_CCMR2_IC4F_3     (0x08UL << TIM_CCMR2_IC4F_Pos)      /*!< 0x00008000 */

/*-------------------------------------------------------------------------------*/
/*!< OC3FE configuration */
#define TIM_CCMR2_OC3FE_Pos  (2U)
#define TIM_CCMR2_OC3FE_Msk  (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
#define TIM_CCMR2_OC3FE      TIM_CCMR2_OC3FE_Msk                 /*!< OC3FE (Output compare 3 fast enable) */
/*!< OC3PE configuration */
#define TIM_CCMR2_OC3PE_Pos  (3U)
#define TIM_CCMR2_OC3PE_Msk  (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
#define TIM_CCMR2_OC3PE      TIM_CCMR2_OC3PE_Msk                 /*!< OC3PE (Output compare 3 preload enable) */
/*!< OC3M configuration */
#define TIM_CCMR2_OC3M_Pos   (4U)
#define TIM_CCMR2_OC3M_Msk   (0x3007UL << TIM_CCMR2_OC3M_Pos)    /*!< 0x00030070 */
#define TIM_CCMR2_OC3M       TIM_CCMR2_OC3M_Msk                  /*!< OC3M[2:0] bits (Output compare 3 mode) */
#define TIM_CCMR2_OC3M_0     (0x0001UL << TIM_CCMR2_OC3M_Pos)    /*!< 0x00000010 */
#define TIM_CCMR2_OC3M_1     (0x0002UL << TIM_CCMR2_OC3M_Pos)    /*!< 0x00000020 */
#define TIM_CCMR2_OC3M_2     (0x0004UL << TIM_CCMR2_OC3M_Pos)    /*!< 0x00000040 */
#define TIM_CCMR2_OC3M_3     (0x1000UL << TIM_CCMR2_OC3M_Pos)    /*!< 0x00010000 */
#define TIM_CCMR2_OC3M_4     (0x2000UL << TIM_CCMR2_OC3M_Pos)    /*!< 0x00020000 */
/*!< OC3CE configuration */
#define TIM_CCMR2_OC3CE_Pos  (7U)
#define TIM_CCMR2_OC3CE_Msk  (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
#define TIM_CCMR2_OC3CE      TIM_CCMR2_OC3CE_Msk                 /*!< OC3CE (Output compare 3 clear enable) */
/*!< CC4S configuration */
#define TIM_CCMR2_CC4S_Pos   (8U)
#define TIM_CCMR2_CC4S_Msk   (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
#define TIM_CCMR2_CC4S       TIM_CCMR2_CC4S_Msk                  /*!< CC4S[1:0] bits (Capture/compare 4 selection) */
#define TIM_CCMR2_CC4S_0     (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
#define TIM_CCMR2_CC4S_1     (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
/*!< OC4FE configuration */
#define TIM_CCMR2_OC4FE_Pos  (10U)
#define TIM_CCMR2_OC4FE_Msk  (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
#define TIM_CCMR2_OC4FE      TIM_CCMR2_OC4FE_Msk                 /*!< OC4FE (Output compare 4 fast enable) */
/*!< OC4PE configuration */
#define TIM_CCMR2_OC4PE_Pos  (11U)
#define TIM_CCMR2_OC4PE_Msk  (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
#define TIM_CCMR2_OC4PE      TIM_CCMR2_OC4PE_Msk                 /*!< OC4PE (Output compare 4 preload enable) */
/*!< OC4M configuration */
#define TIM_CCMR2_OC4M_Pos   (12U)
#define TIM_CCMR2_OC4M_Msk   (0x3007UL << TIM_CCMR2_OC4M_Pos)    /*!< 0x03007000 */
#define TIM_CCMR2_OC4M       TIM_CCMR2_OC4M_Msk                  /*!< OC4M[2:0] bits (Output compare 4 mode) */
#define TIM_CCMR2_OC4M_0     (0x0001UL << TIM_CCMR2_OC4M_Pos)    /*!< 0x00001000 */
#define TIM_CCMR2_OC4M_1     (0x0002UL << TIM_CCMR2_OC4M_Pos)    /*!< 0x00002000 */
#define TIM_CCMR2_OC4M_2     (0x0004UL << TIM_CCMR2_OC4M_Pos)    /*!< 0x00004000 */
#define TIM_CCMR2_OC4M_3     (0x1000UL << TIM_CCMR2_OC4M_Pos)    /*!< 0x01000000 */
#define TIM_CCMR2_OC4M_4     (0x2000UL << TIM_CCMR2_OC4M_Pos)    /*!< 0x02000000 */
/*!< OC4CE configuration */
#define TIM_CCMR2_OC4CE_Pos  (15U)
#define TIM_CCMR2_OC4CE_Msk  (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
#define TIM_CCMR2_OC4CE      TIM_CCMR2_OC4CE_Msk                 /*!< OC4CE (Output compare 4 clear enable) */

/********************  Bit definition for TIM_CCER register  ********************/
/*!< CC1E configuration */
#define TIM_CCER_CC1E_Pos  (0U)
#define TIM_CCER_CC1E_Msk  (0x1UL << TIM_CCER_CC1E_Pos)  /*!< 0x00000001 */
#define TIM_CCER_CC1E      TIM_CCER_CC1E_Msk             /*!< CC1E (Capture/compare  1 output enable) */
/*!< CC1P configuration */
#define TIM_CCER_CC1P_Pos  (1U)
#define TIM_CCER_CC1P_Msk  (0x1UL << TIM_CCER_CC1P_Pos)  /*!< 0x00000002 */
#define TIM_CCER_CC1P      TIM_CCER_CC1P_Msk             /*!< CC1P (Capture/compare 1 output polarity) */
/*!< CC1NE configuration */
#define TIM_CCER_CC1NE_Pos (2U)
#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
#define TIM_CCER_CC1NE     TIM_CCER_CC1NE_Msk            /*!< CC1NE (Capture/compare 1 complementary output enable) */
/*!< CC1NP configuration */
#define TIM_CCER_CC1NP_Pos (3U)
#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
#define TIM_CCER_CC1NP     TIM_CCER_CC1NP_Msk            /*!< CC1NP (Capture/compare 1 complementary output polarity) */
/*!< CC2E configuration */
#define TIM_CCER_CC2E_Pos  (4U)
#define TIM_CCER_CC2E_Msk  (0x1UL << TIM_CCER_CC2E_Pos)  /*!< 0x00000010 */
#define TIM_CCER_CC2E      TIM_CCER_CC2E_Msk             /*!< CC2E (Capture/compare  2 output enable) */
/*!< CC2P configuration */
#define TIM_CCER_CC2P_Pos  (5U)
#define TIM_CCER_CC2P_Msk  (0x1UL << TIM_CCER_CC2P_Pos)  /*!< 0x00000020 */
#define TIM_CCER_CC2P      TIM_CCER_CC2P_Msk             /*!< CC2P (Capture/compare 2 output polarity) */
/*!< CC2NE configuration */
#define TIM_CCER_CC2NE_Pos (6U)
#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
#define TIM_CCER_CC2NE     TIM_CCER_CC2NE_Msk            /*!< CC2NE (Capture/compare 2 complementary output enable) */
/*!< CC2NP configuration */
#define TIM_CCER_CC2NP_Pos (7U)
#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
#define TIM_CCER_CC2NP     TIM_CCER_CC2NP_Msk            /*!< CC2NP (Capture/compare 2 complementary output polarity) */
/*!< CC3E configuration */
#define TIM_CCER_CC3E_Pos  (8U)
#define TIM_CCER_CC3E_Msk  (0x1UL << TIM_CCER_CC3E_Pos)  /*!< 0x00000100 */
#define TIM_CCER_CC3E      TIM_CCER_CC3E_Msk             /*!< CC3E (Capture/compare  3 output enable) */
/*!< CC3P configuration */
#define TIM_CCER_CC3P_Pos  (9U)
#define TIM_CCER_CC3P_Msk  (0x1UL << TIM_CCER_CC3P_Pos)  /*!< 0x00000200 */
#define TIM_CCER_CC3P      TIM_CCER_CC3P_Msk             /*!< CC3P (Capture/compare 3 output polarity) */
/*!< CC3NE configuration */
#define TIM_CCER_CC3NE_Pos (10U)
#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
#define TIM_CCER_CC3NE     TIM_CCER_CC3NE_Msk            /*!< CC3NE (Capture/compare 3 complementary output enable) */
/*!< CC3NP configuration */
#define TIM_CCER_CC3NP_Pos (11U)
#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
#define TIM_CCER_CC3NP     TIM_CCER_CC3NP_Msk            /*!< CC3NP (Capture/compare 3 complementary output polarity) */
/*!< CC4E configuration */
#define TIM_CCER_CC4E_Pos  (12U)
#define TIM_CCER_CC4E_Msk  (0x1UL << TIM_CCER_CC4E_Pos)  /*!< 0x00001000 */
#define TIM_CCER_CC4E      TIM_CCER_CC4E_Msk             /*!< CC4E (Capture/compare  4 output enable) */
/*!< CC4P configuration */
#define TIM_CCER_CC4P_Pos  (13U)
#define TIM_CCER_CC4P_Msk  (0x1UL << TIM_CCER_CC4P_Pos)  /*!< 0x00002000 */
#define TIM_CCER_CC4P      TIM_CCER_CC4P_Msk             /*!< CC4P (Capture/compare 4 output polarity) */
/*!< CC4NE configuration */
#define TIM_CCER_CC4NE_Pos (14U)
#define TIM_CCER_CC4NE_Msk (0x1UL << TIM_CCER_CC4NE_Pos) /*!< 0x00004000 */
#define TIM_CCER_CC4NE     TIM_CCER_CC4NE_Msk            /*!< CC4NE (Capture/compare 4 complementary output enable) */
/*!< CC4NP configuration */
#define TIM_CCER_CC4NP_Pos (15U)
#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
#define TIM_CCER_CC4NP     TIM_CCER_CC4NP_Msk            /*!< CC4NP (Capture/compare 4 complementary output polarity) */
/*!< CC5E configuration */
#define TIM_CCER_CC5E_Pos  (16U)
#define TIM_CCER_CC5E_Msk  (0x1UL << TIM_CCER_CC5E_Pos)  /*!< 0x00010000 */
#define TIM_CCER_CC5E      TIM_CCER_CC5E_Msk             /*!< CC5E (Capture/compare  5 output enable) */
/*!< CC5P configuration */
#define TIM_CCER_CC5P_Pos  (17U)
#define TIM_CCER_CC5P_Msk  (0x1UL << TIM_CCER_CC5P_Pos)  /*!< 0x00020000 */
#define TIM_CCER_CC5P      TIM_CCER_CC5P_Msk             /*!< CC5P (Capture/compare 5 output polarity) */
/*!< CC6E configuration */
#define TIM_CCER_CC6E_Pos  (20U)
#define TIM_CCER_CC6E_Msk  (0x1UL << TIM_CCER_CC6E_Pos)  /*!< 0x00100000 */
#define TIM_CCER_CC6E      TIM_CCER_CC6E_Msk             /*!< CC6E (Capture/compare  6 output enable) */
/*!< CC6P configuration */
#define TIM_CCER_CC6P_Pos  (21U)
#define TIM_CCER_CC6P_Msk  (0x1UL << TIM_CCER_CC6P_Pos)  /*!< 0x00200000 */
#define TIM_CCER_CC6P      TIM_CCER_CC6P_Msk             /*!< CC6P (Capture/compare 6 output polarity) */
/*!< CC7E configuration */
#define TIM_CCER_CC7E_Pos  (24U)
#define TIM_CCER_CC7E_Msk  (0x1UL << TIM_CCER_CC7E_Pos)  /*!< 0x01000000 */
#define TIM_CCER_CC7E      TIM_CCER_CC7E_Msk             /*!< CC7E (Capture/compare  7 output enable) */
/*!< CC7P configuration */
#define TIM_CCER_CC7P_Pos  (25U)
#define TIM_CCER_CC7P_Msk  (0x1UL << TIM_CCER_CC7P_Pos)  /*!< 0x02000000 */
#define TIM_CCER_CC7P      TIM_CCER_CC7P_Msk             /*!< CC7P (Capture/compare 7 output polarity) */

/********************  Bit definition for TIM_CNT register  ********************/
/*!< CNT configuration */
#define TIM_CNT_CNT_Pos    (0U)
#define TIM_CNT_CNT_Msk    (0x7FFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0x7FFFFFFF */
#define TIM_CNT_CNT        TIM_CNT_CNT_Msk                   /*!< CNT[30:0] bits (Counter value) */
/*!< UIFCPY configuration */
#define TIM_CNT_UIFCPY_Pos (31U)
#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)     /*!< 0x80000000 */
#define TIM_CNT_UIFCPY     TIM_CNT_UIFCPY_Msk                /*!< UIFCPY (UIF copy) */

/********************  Bit definition for TIM_PSC register  ********************/
/*!< PSC configuration */
#define TIM_PSC_PSC_Pos (0U)
#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
#define TIM_PSC_PSC     TIM_PSC_PSC_Msk               /*!< PSC[15:0] bits (Prescaler value) */

/********************  Bit definition for TIM_ARR register  ********************/
/*!< ARR configuration */
#define TIM_ARR_ARR_Pos (0U)
#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
#define TIM_ARR_ARR     TIM_ARR_ARR_Msk                   /*!< ARR[31:0] bits (Auto-reload value) */

/********************  Bit definition for TIM_RCR register  ********************/
/*!< REP configuration */
#define TIM_RCR_REP_Pos (0U)
#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
#define TIM_RCR_REP     TIM_RCR_REP_Msk               /*!< REP[15:0] bits (Repetition counter reload value) */

/********************  Bit definition for TIM_CCR1 register  ********************/
/*!< CCR1 configuration */
#define TIM_CCR1_CCR1_Pos (0U)
#define TIM_CCR1_CCR1_Msk (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR1_CCR1     TIM_CCR1_CCR1_Msk                   /*!< CCR1[31:0] bits (Capture/compare 1 value) */

/********************  Bit definition for TIM_CCR2 register  ********************/
/*!< CCR2 configuration */
#define TIM_CCR2_CCR2_Pos (0U)
#define TIM_CCR2_CCR2_Msk (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR2_CCR2     TIM_CCR2_CCR2_Msk                   /*!< CCR2[31:0] bits (Capture/compare 2 value) */

/********************  Bit definition for TIM_CCR3 register  ********************/
/*!< CCR3 configuration */
#define TIM_CCR3_CCR3_Pos (0U)
#define TIM_CCR3_CCR3_Msk (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR3_CCR3     TIM_CCR3_CCR3_Msk                   /*!< CCR3[31:0] bits (Capture/compare 3 value) */

/********************  Bit definition for TIM_CCR4 register  ********************/
/*!< CCR4 configuration */
#define TIM_CCR4_CCR4_Pos (0U)
#define TIM_CCR4_CCR4_Msk (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR4_CCR4     TIM_CCR4_CCR4_Msk                   /*!< CCR4[19:0] bits (Capture/compare 4 value) */

/********************  Bit definition for TIM_BDTR register  ********************/
/*!< DTG configuration */
#define TIM_BDTR_DTG_Pos     (0U)
#define TIM_BDTR_DTG_Msk     (0xFFUL << TIM_BDTR_DTG_Pos)    /*!< 0x000000FF */
#define TIM_BDTR_DTG         TIM_BDTR_DTG_Msk                /*!< DTG[7:0] bits (Dead-time generator setup) */
#define TIM_BDTR_DTG_0       (0x001UL << TIM_BDTR_DTG_Pos)   /*!< 0x00000001 */
#define TIM_BDTR_DTG_1       (0x002UL << TIM_BDTR_DTG_Pos)   /*!< 0x00000002 */
#define TIM_BDTR_DTG_2       (0x004UL << TIM_BDTR_DTG_Pos)   /*!< 0x00000004 */
#define TIM_BDTR_DTG_3       (0x008UL << TIM_BDTR_DTG_Pos)   /*!< 0x00000008 */
#define TIM_BDTR_DTG_4       (0x010UL << TIM_BDTR_DTG_Pos)   /*!< 0x00000010 */
#define TIM_BDTR_DTG_5       (0x020UL << TIM_BDTR_DTG_Pos)   /*!< 0x00000020 */
#define TIM_BDTR_DTG_6       (0x040UL << TIM_BDTR_DTG_Pos)   /*!< 0x00000040 */
#define TIM_BDTR_DTG_7       (0x080UL << TIM_BDTR_DTG_Pos)   /*!< 0x00000080 */
/*!< LOCK configuration */
#define TIM_BDTR_LOCK_Pos    (8U)
#define TIM_BDTR_LOCK_Msk    (0x3UL << TIM_BDTR_LOCK_Pos)    /*!< 0x00000300 */
#define TIM_BDTR_LOCK        TIM_BDTR_LOCK_Msk               /*!< LOCK[1:0] bits (Lock configuration) */
#define TIM_BDTR_LOCK_0      (0x1UL << TIM_BDTR_LOCK_Pos)    /*!< 0x00000100 */
#define TIM_BDTR_LOCK_1      (0x2UL << TIM_BDTR_LOCK_Pos)    /*!< 0x00000200 */
/*!< OSSI configuration */
#define TIM_BDTR_OSSI_Pos    (10U)
#define TIM_BDTR_OSSI_Msk    (0x1UL << TIM_BDTR_OSSI_Pos)    /*!< 0x00000400 */
#define TIM_BDTR_OSSI        TIM_BDTR_OSSI_Msk               /*!< OSSI (Off-state selection for idle mode) */
/*!< OSSR configuration */
#define TIM_BDTR_OSSR_Pos    (11U)
#define TIM_BDTR_OSSR_Msk    (0x1UL << TIM_BDTR_OSSR_Pos)    /*!< 0x00000800 */
#define TIM_BDTR_OSSR        TIM_BDTR_OSSR_Msk               /*!< OSSR (Off-state selection for Run mode) */
/*!< BKE configuration */
#define TIM_BDTR_BKE_Pos     (12U)
#define TIM_BDTR_BKE_Msk     (0x1UL << TIM_BDTR_BKE_Pos)     /*!< 0x00001000 */
#define TIM_BDTR_BKE         TIM_BDTR_BKE_Msk                /*!< BKE (Break enable) */
/*!< BKP configuration */
#define TIM_BDTR_BKP_Pos     (13U)
#define TIM_BDTR_BKP_Msk     (0x1UL << TIM_BDTR_BKP_Pos)     /*!< 0x00002000 */
#define TIM_BDTR_BKP         TIM_BDTR_BKP_Msk                /*!< BKP (Break polarity) */
/*!< AOE configuration */
#define TIM_BDTR_AOE_Pos     (14U)
#define TIM_BDTR_AOE_Msk     (0x1UL << TIM_BDTR_AOE_Pos)     /*!< 0x00004000 */
#define TIM_BDTR_AOE         TIM_BDTR_AOE_Msk                /*!< AOE (Automatic output enable) */
/*!< MOE configuration */
#define TIM_BDTR_MOE_Pos     (15U)
#define TIM_BDTR_MOE_Msk     (0x1UL << TIM_BDTR_MOE_Pos)     /*!< 0x00008000 */
#define TIM_BDTR_MOE         TIM_BDTR_MOE_Msk                /*!< MOE (Main output enable) */
/*!< BKF configuration */
#define TIM_BDTR_BKF_Pos     (16U)
#define TIM_BDTR_BKF_Msk     (0xFUL << TIM_BDTR_BKF_Pos)     /*!< 0x000F0000 */
#define TIM_BDTR_BKF         TIM_BDTR_BKF_Msk                /*!< BKF[3:0] bits (Break filter) */
#define TIM_BDTR_BKF_0       (0x01UL << TIM_BDTR_BKF_Pos)    /*!< 0x00010000 */
#define TIM_BDTR_BKF_1       (0x02UL << TIM_BDTR_BKF_Pos)    /*!< 0x00020000 */
#define TIM_BDTR_BKF_2       (0x04UL << TIM_BDTR_BKF_Pos)    /*!< 0x00040000 */
#define TIM_BDTR_BKF_3       (0x08UL << TIM_BDTR_BKF_Pos)    /*!< 0x00080000 */
/*!< BK2F configuration */
#define TIM_BDTR_BK2F_Pos    (20U)
#define TIM_BDTR_BK2F_Msk    (0xFUL << TIM_BDTR_BK2F_Pos)    /*!< 0x00F00000 */
#define TIM_BDTR_BK2F        TIM_BDTR_BK2F_Msk               /*!< BK2F[3:0] bits (Break 2 filter) */
#define TIM_BDTR_BK2F_0      (0x01UL << TIM_BDTR_BK2F_Pos)   /*!< 0x00100000 */
#define TIM_BDTR_BK2F_1      (0x02UL << TIM_BDTR_BK2F_Pos)   /*!< 0x00200000 */
#define TIM_BDTR_BK2F_2      (0x04UL << TIM_BDTR_BK2F_Pos)   /*!< 0x00400000 */
#define TIM_BDTR_BK2F_3      (0x08UL << TIM_BDTR_BK2F_Pos)   /*!< 0x00800000 */
/*!< BK2E configuration */
#define TIM_BDTR_BK2E_Pos    (24U)
#define TIM_BDTR_BK2E_Msk    (0x1UL << TIM_BDTR_BK2E_Pos)    /*!< 0x01000000 */
#define TIM_BDTR_BK2E        TIM_BDTR_BK2E_Msk               /*!< BK2E (Break 2 enable) */
/*!< BK2P configuration */
#define TIM_BDTR_BK2P_Pos    (25U)
#define TIM_BDTR_BK2P_Msk    (0x1UL << TIM_BDTR_BK2P_Pos)    /*!< 0x02000000 */
#define TIM_BDTR_BK2P        TIM_BDTR_BK2P_Msk               /*!< BK2P (Break 2 polarity) */
/*!< BKDSRM configuration */
#define TIM_BDTR_BKDSRM_Pos  (26U)
#define TIM_BDTR_BKDSRM_Msk  (0x1UL << TIM_BDTR_BKDSRM_Pos)  /*!< 0x04000000 */
#define TIM_BDTR_BKDSRM      TIM_BDTR_BKDSRM_Msk             /*!< BKDSRM (Break disarm) */
/*!< BK2DSRM configuration */
#define TIM_BDTR_BK2DSRM_Pos (27U)
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
#define TIM_BDTR_BK2DSRM     TIM_BDTR_BK2DSRM_Msk            /*!< BK2DSRM (Break2 disarm) */
/*!< BKBID configuration */
#define TIM_BDTR_BKBID_Pos   (28U)
#define TIM_BDTR_BKBID_Msk   (0x1UL << TIM_BDTR_BKBID_Pos)   /*!< 0x10000000 */
#define TIM_BDTR_BKBID       TIM_BDTR_BKBID_Msk              /*!< BKBID (Break bidirectional) */
/*!< BK2BID configuration */
#define TIM_BDTR_BK2BID_Pos  (29U)
#define TIM_BDTR_BK2BID_Msk  (0x1UL << TIM_BDTR_BK2BID_Pos)  /*!< 0x20000000 */
#define TIM_BDTR_BK2BID      TIM_BDTR_BK2BID_Msk             /*!< BK2BID (Break2 bidirectional) */

/********************  Bit definition for TIM_CCR5 register  ********************/
/*!< CCR5 configuration */
#define TIM_CCR5_CCR5_Pos   (0U)
#define TIM_CCR5_CCR5_Msk   (0x000FFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0x000FFFFF */
#define TIM_CCR5_CCR5       TIM_CCR5_CCR5_Msk                   /*!< CCR5[19:0] bits (Capture/compare 5 value) */
/*!< GC5C1O configuration */
#define TIM_CCR5_GC5C1O_Pos (24U)
#define TIM_CCR5_GC5C1O_Msk (0x1UL << TIM_CCR5_GC5C1O_Pos)      /*!< 0x01000000 */
#define TIM_CCR5_GC5C1O     TIM_CCR5_GC5C1O_Msk                 /*!< GC5C1O (Group channel 5 and channel 1 (ORed)) */
/*!< GC5C2O configuration */
#define TIM_CCR5_GC5C2O_Pos (25U)
#define TIM_CCR5_GC5C2O_Msk (0x1UL << TIM_CCR5_GC5C2O_Pos)      /*!< 0x02000000 */
#define TIM_CCR5_GC5C2O     TIM_CCR5_GC5C2O_Msk                 /*!< GC5C2O (Group channel 5 and channel 2 (ORed)) */
/*!< GC5C3O configuration */
#define TIM_CCR5_GC5C3O_Pos (26U)
#define TIM_CCR5_GC5C3O_Msk (0x1UL << TIM_CCR5_GC5C3O_Pos)      /*!< 0x04000000 */
#define TIM_CCR5_GC5C3O     TIM_CCR5_GC5C3O_Msk                 /*!< GC5C3O (Group channel 5 and channel 3 (ORed)) */
/*!< GC5C4O configuration */
#define TIM_CCR5_GC5C4O_Pos (27U)
#define TIM_CCR5_GC5C4O_Msk (0x1UL << TIM_CCR5_GC5C4O_Pos)      /*!< 0x08000000 */
#define TIM_CCR5_GC5C4O     TIM_CCR5_GC5C4O_Msk                 /*!< GC5C4O (Group channel 5 and channel 4 (ORed)) */
/*!< GC5C4 configuration */
#define TIM_CCR5_GC5C4_Pos  (28U)
#define TIM_CCR5_GC5C4_Msk  (0x1UL << TIM_CCR5_GC5C4_Pos)       /*!< 0x10000000 */
#define TIM_CCR5_GC5C4      TIM_CCR5_GC5C4_Msk                  /*!< GC5C4 (Group channel 5 and channel 4) */
/*!< GC5C1 configuration */
#define TIM_CCR5_GC5C1_Pos  (29U)
#define TIM_CCR5_GC5C1_Msk  (0x1UL << TIM_CCR5_GC5C1_Pos)       /*!< 0x20000000 */
#define TIM_CCR5_GC5C1      TIM_CCR5_GC5C1_Msk                  /*!< GC5C1 (Group channel 5 and channel 1) */
/*!< GC5C2 configuration */
#define TIM_CCR5_GC5C2_Pos  (30U)
#define TIM_CCR5_GC5C2_Msk  (0x1UL << TIM_CCR5_GC5C2_Pos)       /*!< 0x40000000 */
#define TIM_CCR5_GC5C2      TIM_CCR5_GC5C2_Msk                  /*!< GC5C2 (Group channel 5 and channel 2) */
/*!< GC5C3 configuration */
#define TIM_CCR5_GC5C3_Pos  (31U)
#define TIM_CCR5_GC5C3_Msk  (0x1UL << TIM_CCR5_GC5C3_Pos)       /*!< 0x80000000 */
#define TIM_CCR5_GC5C3      TIM_CCR5_GC5C3_Msk                  /*!< GC5C3 (Group channel 5 and channel 3) */

/********************  Bit definition for TIM_CCR6 register  ********************/
/*!< CCR6 configuration */
#define TIM_CCR6_CCR6_Pos    (0U)
#define TIM_CCR6_CCR6_Msk    (0x000FFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x000FFFFF */
#define TIM_CCR6_CCR6        TIM_CCR6_CCR6_Msk                   /*!< CCR6[19:0] bits (Capture/compare 6 value) */

/********************  Bit definition for TIM_CCMR3 register  ********************/
/*!< OC5FE configuration */
#define TIM_CCMR3_OC5FE_Pos  (2U)
#define TIM_CCMR3_OC5FE_Msk  (0x1UL << TIM_CCMR3_OC5FE_Pos)      /*!< 0x00000004 */
#define TIM_CCMR3_OC5FE      TIM_CCMR3_OC5FE_Msk                 /*!< OC5FE (Output compare 5 fast enable) */
/*!< OC5PE configuration */
#define TIM_CCMR3_OC5PE_Pos  (3U)
#define TIM_CCMR3_OC5PE_Msk  (0x1UL << TIM_CCMR3_OC5PE_Pos)      /*!< 0x00000008 */
#define TIM_CCMR3_OC5PE      TIM_CCMR3_OC5PE_Msk                 /*!< OC5PE (Output compare 5 preload enable) */
/*!< OC5M configuration */
#define TIM_CCMR3_OC5M_Pos   (4U)
#define TIM_CCMR3_OC5M_Msk   (0x3007UL << TIM_CCMR3_OC5M_Pos)    /*!< 0x00030070 */
#define TIM_CCMR3_OC5M       TIM_CCMR3_OC5M_Msk                  /*!< OC5M[2:0] bits (Output compare 5 mode) */
#define TIM_CCMR3_OC5M_0     (0x0001UL << TIM_CCMR3_OC5M_Pos)    /*!< 0x00000010 */
#define TIM_CCMR3_OC5M_1     (0x0002UL << TIM_CCMR3_OC5M_Pos)    /*!< 0x00000020 */
#define TIM_CCMR3_OC5M_2     (0x0004UL << TIM_CCMR3_OC5M_Pos)    /*!< 0x00000040 */
#define TIM_CCMR3_OC5M_3     (0x1000UL << TIM_CCMR3_OC5M_Pos)    /*!< 0x00010000 */
#define TIM_CCMR3_OC5M_4     (0x2000UL << TIM_CCMR3_OC5M_Pos)    /*!< 0x00020000 */
/*!< OC5CE configuration */
#define TIM_CCMR3_OC5CE_Pos  (7U)
#define TIM_CCMR3_OC5CE_Msk  (0x1UL << TIM_CCMR3_OC5CE_Pos)      /*!< 0x00000080 */
#define TIM_CCMR3_OC5CE      TIM_CCMR3_OC5CE_Msk                 /*!< OC5CE (Output compare 5 clear enable) */
/*!< OC6FE configuration */
#define TIM_CCMR3_OC6FE_Pos  (10U)
#define TIM_CCMR3_OC6FE_Msk  (0x1UL << TIM_CCMR3_OC6FE_Pos)      /*!< 0x00000400 */
#define TIM_CCMR3_OC6FE      TIM_CCMR3_OC6FE_Msk                 /*!< OC6FE (Output compare 6 fast enable) */
/*!< OC6PE configuration */
#define TIM_CCMR3_OC6PE_Pos  (11U)
#define TIM_CCMR3_OC6PE_Msk  (0x1UL << TIM_CCMR3_OC6PE_Pos)      /*!< 0x00000800 */
#define TIM_CCMR3_OC6PE      TIM_CCMR3_OC6PE_Msk                 /*!< OC6PE (Output compare 6 preload enable) */
/*!< OC6M configuration */
#define TIM_CCMR3_OC6M_Pos   (12U)
#define TIM_CCMR3_OC6M_Msk   (0x3007UL << TIM_CCMR3_OC6M_Pos)    /*!< 0x03007000 */
#define TIM_CCMR3_OC6M       TIM_CCMR3_OC6M_Msk                  /*!< OC6M[2:0] bits (Output compare 6 mode) */
#define TIM_CCMR3_OC6M_0     (0x0001UL << TIM_CCMR3_OC6M_Pos)    /*!< 0x00001000 */
#define TIM_CCMR3_OC6M_1     (0x0002UL << TIM_CCMR3_OC6M_Pos)    /*!< 0x00002000 */
#define TIM_CCMR3_OC6M_2     (0x0004UL << TIM_CCMR3_OC6M_Pos)    /*!< 0x00004000 */
#define TIM_CCMR3_OC6M_3     (0x1000UL << TIM_CCMR3_OC6M_Pos)    /*!< 0x01000000 */
#define TIM_CCMR3_OC6M_4     (0x2000UL << TIM_CCMR3_OC6M_Pos)    /*!< 0x02000000 */
/*!< OC6CE configuration */
#define TIM_CCMR3_OC6CE_Pos  (15U)
#define TIM_CCMR3_OC6CE_Msk  (0x1UL << TIM_CCMR3_OC6CE_Pos)      /*!< 0x00008000 */
#define TIM_CCMR3_OC6CE      TIM_CCMR3_OC6CE_Msk                 /*!< OC6CE (Output compare 6 clear enable) */

/********************  Bit definition for TIM_DTR2 register  ********************/
/*!< DTGF configuration */
#define TIM_DTR2_DTGF_Pos     (0U)
#define TIM_DTR2_DTGF_Msk     (0xFFUL << TIM_DTR2_DTGF_Pos)  /*!< 0x000000FF */
#define TIM_DTR2_DTGF         TIM_DTR2_DTGF_Msk              /*!< DTGF[7:0] bits (Dead-time falling edge generator setup) */
#define TIM_DTR2_DTGF_0       (0x001UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
#define TIM_DTR2_DTGF_1       (0x002UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
#define TIM_DTR2_DTGF_2       (0x004UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
#define TIM_DTR2_DTGF_3       (0x008UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
#define TIM_DTR2_DTGF_4       (0x010UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
#define TIM_DTR2_DTGF_5       (0x020UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
#define TIM_DTR2_DTGF_6       (0x040UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
#define TIM_DTR2_DTGF_7       (0x080UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
/*!< DTAE configuration */
#define TIM_DTR2_DTAE_Pos     (16U)
#define TIM_DTR2_DTAE_Msk     (0x1UL << TIM_DTR2_DTAE_Pos)   /*!< 0x00010000 */
#define TIM_DTR2_DTAE         TIM_DTR2_DTAE_Msk              /*!< DTAE (Deadtime asymmetric enable) */
/*!< DTPE configuration */
#define TIM_DTR2_DTPE_Pos     (17U)
#define TIM_DTR2_DTPE_Msk     (0x1UL << TIM_DTR2_DTPE_Pos)   /*!< 0x00020000 */
#define TIM_DTR2_DTPE         TIM_DTR2_DTPE_Msk              /*!< DTPE (Deadtime preload enable) */

/********************  Bit definition for TIM_ECR register  ********************/
/*!< IE configuration */
#define TIM_ECR_IE_Pos        (0U)
#define TIM_ECR_IE_Msk        (0x1UL << TIM_ECR_IE_Pos)     /*!< 0x00000001 */
#define TIM_ECR_IE            TIM_ECR_IE_Msk                /*!< IE (Index enable) */
/*!< IDIR configuration */
#define TIM_ECR_IDIR_Pos      (1U)
#define TIM_ECR_IDIR_Msk      (0x3UL << TIM_ECR_IDIR_Pos)   /*!< 0x00000006 */
#define TIM_ECR_IDIR          TIM_ECR_IDIR_Msk              /*!< IDIR[1:0] bits (Index direction) */
#define TIM_ECR_IDIR_0        (0x1UL << TIM_ECR_IDIR_Pos)   /*!< 0x00000002 */
#define TIM_ECR_IDIR_1        (0x2UL << TIM_ECR_IDIR_Pos)   /*!< 0x00000004 */
/*!< IBLK configuration */
#define TIM_ECR_IBLK_Pos      (3U)
#define TIM_ECR_IBLK_Msk      (0x3UL << TIM_ECR_IBLK_Pos)   /*!< 0x00000018 */
#define TIM_ECR_IBLK          TIM_ECR_IBLK_Msk              /*!< IBLK[1:0] bits (Index blanking) */
#define TIM_ECR_IBLK_0        (0x1UL << TIM_ECR_IBLK_Pos)   /*!< 0x00000008 */
#define TIM_ECR_IBLK_1        (0x2UL << TIM_ECR_IBLK_Pos)   /*!< 0x00000010 */
/*!< FIDX configuration */
#define TIM_ECR_FIDX_Pos      (5U)
#define TIM_ECR_FIDX_Msk      (0x1UL << TIM_ECR_FIDX_Pos)   /*!< 0x00000020 */
#define TIM_ECR_FIDX          TIM_ECR_FIDX_Msk              /*!< FIDX (First index) */
/*!< IPOS configuration */
#define TIM_ECR_IPOS_Pos      (6U)
#define TIM_ECR_IPOS_Msk      (0x3UL << TIM_ECR_IPOS_Pos)   /*!< 0x000000C0 */
#define TIM_ECR_IPOS          TIM_ECR_IPOS_Msk              /*!< IPOS[1:0] bits (Index positioning) */
#define TIM_ECR_IPOS_0        (0x1UL << TIM_ECR_IPOS_Pos)   /*!< 0x00000040 */
#define TIM_ECR_IPOS_1        (0x2UL << TIM_ECR_IPOS_Pos)   /*!< 0x00000080 */
/*!< PW configuration */
#define TIM_ECR_PW_Pos        (16U)
#define TIM_ECR_PW_Msk        (0xFFUL << TIM_ECR_PW_Pos)    /*!< 0x00FF0000 */
#define TIM_ECR_PW            TIM_ECR_PW_Msk                /*!< PW[7:0] bits (Pulse width) */
#define TIM_ECR_PW_0          (0x001UL << TIM_ECR_PW_Pos)   /*!< 0x00010000 */
#define TIM_ECR_PW_1          (0x002UL << TIM_ECR_PW_Pos)   /*!< 0x00020000 */
#define TIM_ECR_PW_2          (0x004UL << TIM_ECR_PW_Pos)   /*!< 0x00040000 */
#define TIM_ECR_PW_3          (0x008UL << TIM_ECR_PW_Pos)   /*!< 0x00080000 */
#define TIM_ECR_PW_4          (0x010UL << TIM_ECR_PW_Pos)   /*!< 0x00100000 */
#define TIM_ECR_PW_5          (0x020UL << TIM_ECR_PW_Pos)   /*!< 0x00200000 */
#define TIM_ECR_PW_6          (0x040UL << TIM_ECR_PW_Pos)   /*!< 0x00400000 */
#define TIM_ECR_PW_7          (0x080UL << TIM_ECR_PW_Pos)   /*!< 0x00800000 */
/*!< PWPRSC configuration */
#define TIM_ECR_PWPRSC_Pos    (24U)
#define TIM_ECR_PWPRSC_Msk    (0x7UL << TIM_ECR_PWPRSC_Pos) /*!< 0x07000000 */
#define TIM_ECR_PWPRSC        TIM_ECR_PWPRSC_Msk            /*!< PWPRSC[2:0] bits (Pulse width prescaler) */
#define TIM_ECR_PWPRSC_0      (0x1UL << TIM_ECR_PWPRSC_Pos) /*!< 0x01000000 */
#define TIM_ECR_PWPRSC_1      (0x2UL << TIM_ECR_PWPRSC_Pos) /*!< 0x02000000 */
#define TIM_ECR_PWPRSC_2      (0x4UL << TIM_ECR_PWPRSC_Pos) /*!< 0x04000000 */

/********************  Bit definition for TIM_TISEL register  ********************/
/*!< TI1SEL configuration */
#define TIM_TISEL_TI1SEL_Pos  (0U)
#define TIM_TISEL_TI1SEL_Msk  (0xFUL << TIM_TISEL_TI1SEL_Pos)  /*!< 0x0000000F */
#define TIM_TISEL_TI1SEL      TIM_TISEL_TI1SEL_Msk             /*!< TI1SEL[3:0] bits (Selects tim_ti1[0..15] input) */
#define TIM_TISEL_TI1SEL_0    (0x01UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM_TISEL_TI1SEL_1    (0x02UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM_TISEL_TI1SEL_2    (0x04UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM_TISEL_TI1SEL_3    (0x08UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
/*!< TI2SEL configuration */
#define TIM_TISEL_TI2SEL_Pos  (8U)
#define TIM_TISEL_TI2SEL_Msk  (0xFUL << TIM_TISEL_TI2SEL_Pos)  /*!< 0x00000F00 */
#define TIM_TISEL_TI2SEL      TIM_TISEL_TI2SEL_Msk             /*!< TI2SEL[3:0] bits (Selects tim_ti2[0..15] input) */
#define TIM_TISEL_TI2SEL_0    (0x01UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM_TISEL_TI2SEL_1    (0x02UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM_TISEL_TI2SEL_2    (0x04UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM_TISEL_TI2SEL_3    (0x08UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
/*!< TI3SEL configuration */
#define TIM_TISEL_TI3SEL_Pos  (16U)
#define TIM_TISEL_TI3SEL_Msk  (0xFUL << TIM_TISEL_TI3SEL_Pos)  /*!< 0x000F0000 */
#define TIM_TISEL_TI3SEL      TIM_TISEL_TI3SEL_Msk             /*!< TI3SEL[3:0] bits (Selects tim_ti3[0..15] input) */
#define TIM_TISEL_TI3SEL_0    (0x01UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
#define TIM_TISEL_TI3SEL_1    (0x02UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
#define TIM_TISEL_TI3SEL_2    (0x04UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
#define TIM_TISEL_TI3SEL_3    (0x08UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
/*!< TI4SEL configuration */
#define TIM_TISEL_TI4SEL_Pos  (24U)
#define TIM_TISEL_TI4SEL_Msk  (0xFUL << TIM_TISEL_TI4SEL_Pos)  /*!< 0x0F000000 */
#define TIM_TISEL_TI4SEL      TIM_TISEL_TI4SEL_Msk             /*!< TI4SEL[3:0] bits (Selects tim_ti4[0..15] input) */
#define TIM_TISEL_TI4SEL_0    (0x01UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
#define TIM_TISEL_TI4SEL_1    (0x02UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
#define TIM_TISEL_TI4SEL_2    (0x04UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
#define TIM_TISEL_TI4SEL_3    (0x08UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */

/********************  Bit definition for TIM_AF1 register  ********************/
/*!< BKINE configuration */
#define TIM_AF1_BKINE_Pos     (0U)
#define TIM_AF1_BKINE_Msk     (0x1UL << TIM_AF1_BKINE_Pos)    /*!< 0x00000001 */
#define TIM_AF1_BKINE         TIM_AF1_BKINE_Msk               /*!< BKINE (TIMx_BKIN input enable) */
/*!< BKCMP1E configuration */
#define TIM_AF1_BKCMP1E_Pos   (1U)
#define TIM_AF1_BKCMP1E_Msk   (0x1UL << TIM_AF1_BKCMP1E_Pos)  /*!< 0x00000002 */
#define TIM_AF1_BKCMP1E       TIM_AF1_BKCMP1E_Msk             /*!< BKCMP1E (tim_brk_cmp1 enable) */
/*!< BKCMP2E configuration */
#define TIM_AF1_BKCMP2E_Pos   (2U)
#define TIM_AF1_BKCMP2E_Msk   (0x1UL << TIM_AF1_BKCMP2E_Pos)  /*!< 0x00000004 */
#define TIM_AF1_BKCMP2E       TIM_AF1_BKCMP2E_Msk             /*!< tim_brk_cmp2 enable */
/*!< BKCMP3E configuration */
#define TIM_AF1_BKCMP3E_Pos   (3U)
#define TIM_AF1_BKCMP3E_Msk   (0x1UL << TIM_AF1_BKCMP3E_Pos)  /*!< 0x00000008 */
#define TIM_AF1_BKCMP3E       TIM_AF1_BKCMP3E_Msk             /*!< tim_brk_cmp3 enable */
/*!< BKCMP4E configuration */
#define TIM_AF1_BKCMP4E_Pos   (4U)
#define TIM_AF1_BKCMP4E_Msk   (0x1UL << TIM_AF1_BKCMP4E_Pos)  /*!< 0x00000010 */
#define TIM_AF1_BKCMP4E       TIM_AF1_BKCMP4E_Msk             /*!< tim_brk_cmp4 enable */
/*!< BKCMP5E configuration */
#define TIM_AF1_BKCMP5E_Pos   (5U)
#define TIM_AF1_BKCMP5E_Msk   (0x1UL << TIM_AF1_BKCMP5E_Pos)  /*!< 0x00000020 */
#define TIM_AF1_BKCMP5E       TIM_AF1_BKCMP5E_Msk             /*!< BKCMP5E (tim_brk_cmp5 enable) */
/*!< BKCMP6E configuration */
#define TIM_AF1_BKCMP6E_Pos   (6U)
#define TIM_AF1_BKCMP6E_Msk   (0x1UL << TIM_AF1_BKCMP6E_Pos)  /*!< 0x00000040 */
#define TIM_AF1_BKCMP6E       TIM_AF1_BKCMP6E_Msk             /*!< BKCMP6E (tim_brk_cmp6 enable) */
/*!< BKCMP7E configuration */
#define TIM_AF1_BKCMP7E_Pos   (7U)
#define TIM_AF1_BKCMP7E_Msk   (0x1UL << TIM_AF1_BKCMP7E_Pos)  /*!< 0x00000080 */
#define TIM_AF1_BKCMP7E       TIM_AF1_BKCMP7E_Msk             /*!< tim_brk_cmp7 enable */
/*!< BKCMP8E configuration */
#define TIM_AF1_BKCMP8E_Pos   (8U)
#define TIM_AF1_BKCMP8E_Msk   (0x1UL << TIM_AF1_BKCMP8E_Pos)  /*!< 0x00000100 */
#define TIM_AF1_BKCMP8E       TIM_AF1_BKCMP8E_Msk             /*!< BKCMP8E (tim_brk_cmp8 enable) */
/*!< BKINP configuration */
#define TIM_AF1_BKINP_Pos     (9U)
#define TIM_AF1_BKINP_Msk     (0x1UL << TIM_AF1_BKINP_Pos)    /*!< 0x00000200 */
#define TIM_AF1_BKINP         TIM_AF1_BKINP_Msk               /*!< BKINP (TIMx_BKIN input polarity) */
/*!< BKCMP1P configuration */
#define TIM_AF1_BKCMP1P_Pos   (10U)
#define TIM_AF1_BKCMP1P_Msk   (0x1UL << TIM_AF1_BKCMP1P_Pos)  /*!< 0x00000400 */
#define TIM_AF1_BKCMP1P       TIM_AF1_BKCMP1P_Msk             /*!< BKCMP1P (tim_brk_cmp1 input polarity) */
/*!< BKCMP2P configuration */
#define TIM_AF1_BKCMP2P_Pos   (11U)
#define TIM_AF1_BKCMP2P_Msk   (0x1UL << TIM_AF1_BKCMP2P_Pos)  /*!< 0x00000800 */
#define TIM_AF1_BKCMP2P       TIM_AF1_BKCMP2P_Msk             /*!< tim_brk_cmp2 input polarity */
/*!< BKCMP3P configuration */
#define TIM_AF1_BKCMP3P_Pos   (12U)
#define TIM_AF1_BKCMP3P_Msk   (0x1UL << TIM_AF1_BKCMP3P_Pos)  /*!< 0x00001000 */
#define TIM_AF1_BKCMP3P       TIM_AF1_BKCMP3P_Msk             /*!< tim_brk_cmp3 input polarity */
/*!< BKCMP4P configuration */
#define TIM_AF1_BKCMP4P_Pos   (13U)
#define TIM_AF1_BKCMP4P_Msk   (0x1UL << TIM_AF1_BKCMP4P_Pos)  /*!< 0x00002000 */
#define TIM_AF1_BKCMP4P       TIM_AF1_BKCMP4P_Msk             /*!< tim_brk_cmp4 input polarity */
/*!< ETRSEL configuration */
#define TIM_AF1_ETRSEL_Pos    (14U)
#define TIM_AF1_ETRSEL_Msk    (0x1FUL << TIM_AF1_ETRSEL_Pos)  /*!< 0x0007C000 */
#define TIM_AF1_ETRSEL        TIM_AF1_ETRSEL_Msk              /*!< ETRSEL[4:0] bits (etr_in source selection) */
#define TIM_AF1_ETRSEL_0      (0x01UL << TIM_AF1_ETRSEL_Pos)  /*!< 0x00004000 */
#define TIM_AF1_ETRSEL_1      (0x02UL << TIM_AF1_ETRSEL_Pos)  /*!< 0x00008000 */
#define TIM_AF1_ETRSEL_2      (0x04UL << TIM_AF1_ETRSEL_Pos)  /*!< 0x00010000 */
#define TIM_AF1_ETRSEL_3      (0x08UL << TIM_AF1_ETRSEL_Pos)  /*!< 0x00020000 */
#define TIM_AF1_ETRSEL_4      (0x10UL << TIM_AF1_ETRSEL_Pos)  /*!< 0x00040000 */
/*!< BKCMP9E configuration */
#define TIM_AF1_BKCMP9E_Pos   (20U)
#define TIM_AF1_BKCMP9E_Msk   (0x1UL << TIM_AF1_BKCMP9E_Pos)  /*!< 0x00100000 */
#define TIM_AF1_BKCMP9E       TIM_AF1_BKCMP9E_Msk             /*!< BKCMP9E (tim_brk_cmp9 enable) */
/*!< BKCMP10E configuration */
#define TIM_AF1_BKCMP10E_Pos  (21U)
#define TIM_AF1_BKCMP10E_Msk  (0x1UL << TIM_AF1_BKCMP10E_Pos)  /*!< 0x00200000 */
#define TIM_AF1_BKCMP10E      TIM_AF1_BKCMP10E_Msk             /*!< BKCMP10E (tim_brk_cmp10 enable) */
/*!< BKCMP11E configuration */
#define TIM_AF1_BKCMP11E_Pos  (22U)
#define TIM_AF1_BKCMP11E_Msk  (0x1UL << TIM_AF1_BKCMP11E_Pos)  /*!< 0x00400000 */
#define TIM_AF1_BKCMP11E      TIM_AF1_BKCMP11E_Msk             /*!< tim_brk_cmp11 enable */
/*!< BKCMP12E configuration */
#define TIM_AF1_BKCMP12E_Pos  (23U)
#define TIM_AF1_BKCMP12E_Msk  (0x1UL << TIM_AF1_BKCMP12E_Pos)  /*!< 0x00800000 */
#define TIM_AF1_BKCMP12E      TIM_AF1_BKCMP12E_Msk             /*!< tim_brk_cmp12 enable */
/*!< BKCMP13E configuration */
#define TIM_AF1_BKCMP13E_Pos  (24U)
#define TIM_AF1_BKCMP13E_Msk  (0x1UL << TIM_AF1_BKCMP13E_Pos)  /*!< 0x01000000 */
#define TIM_AF1_BKCMP13E      TIM_AF1_BKCMP13E_Msk             /*!< tim_brk_cmp13 enable */
/*!< BKCMP14E configuration */
#define TIM_AF1_BKCMP14E_Pos  (25U)
#define TIM_AF1_BKCMP14E_Msk  (0x1UL << TIM_AF1_BKCMP14E_Pos)  /*!< 0x02000000 */
#define TIM_AF1_BKCMP14E      TIM_AF1_BKCMP14E_Msk             /*!< tim_brk_cmp14 enable */
/*!< BKCMP15E configuration */
#define TIM_AF1_BKCMP15E_Pos  (26U)
#define TIM_AF1_BKCMP15E_Msk  (0x1UL << TIM_AF1_BKCMP15E_Pos)  /*!< 0x04000000 */
#define TIM_AF1_BKCMP15E      TIM_AF1_BKCMP15E_Msk             /*!< tim_brk_cmp15 enable */
/*!< BKCMP16E configuration */
#define TIM_AF1_BKCMP16E_Pos  (27U)
#define TIM_AF1_BKCMP16E_Msk  (0x1UL << TIM_AF1_BKCMP16E_Pos)  /*!< 0x08000000 */
#define TIM_AF1_BKCMP16E      TIM_AF1_BKCMP16E_Msk             /*!< tim_brk_cmp16 enable */
/*!< BKCMP17E configuration */
#define TIM_AF1_BKCMP17E_Pos  (28U)
#define TIM_AF1_BKCMP17E_Msk  (0x1UL << TIM_AF1_BKCMP17E_Pos)  /*!< 0x10000000 */
#define TIM_AF1_BKCMP17E      TIM_AF1_BKCMP17E_Msk             /*!< tim_brk_cmp17 enable */
/*!< BKCMP18E configuration */
#define TIM_AF1_BKCMP18E_Pos  (29U)
#define TIM_AF1_BKCMP18E_Msk  (0x1UL << TIM_AF1_BKCMP18E_Pos)  /*!< 0x20000000 */
#define TIM_AF1_BKCMP18E      TIM_AF1_BKCMP18E_Msk             /*!< tim_brk_cmp18 enable */
/*!< BKCMP19E configuration */
#define TIM_AF1_BKCMP19E_Pos  (30U)
#define TIM_AF1_BKCMP19E_Msk  (0x1UL << TIM_AF1_BKCMP19E_Pos)  /*!< 0x40000000 */
#define TIM_AF1_BKCMP19E      TIM_AF1_BKCMP19E_Msk             /*!< tim_brk_cmp19 enable */
/*!< BKCMP20E configuration */
#define TIM_AF1_BKCMP20E_Pos  (31U)
#define TIM_AF1_BKCMP20E_Msk  (0x1UL << TIM_AF1_BKCMP20E_Pos)  /*!< 0x80000000 */
#define TIM_AF1_BKCMP20E      TIM_AF1_BKCMP20E_Msk             /*!< tim_brk_cmp20 enable */

/********************  Bit definition for TIM_AF2 register  ********************/
/*!< BK2INE configuration */
#define TIM_AF2_BK2INE_Pos    (0U)
#define TIM_AF2_BK2INE_Msk    (0x1UL << TIM_AF2_BK2INE_Pos)    /*!< 0x00000001 */
#define TIM_AF2_BK2INE        TIM_AF2_BK2INE_Msk               /*!< BK2INE (TIMx_BKIN2 input enable) */
/*!< BK2CMP1E configuration */
#define TIM_AF2_BK2CMP1E_Pos  (1U)
#define TIM_AF2_BK2CMP1E_Msk  (0x1UL << TIM_AF2_BK2CMP1E_Pos)  /*!< 0x00000002 */
#define TIM_AF2_BK2CMP1E      TIM_AF2_BK2CMP1E_Msk             /*!< BK2CMP1E (tim_brk2_cmp8 enable) */
/*!< BK2CMP2E configuration */
#define TIM_AF2_BK2CMP2E_Pos  (2U)
#define TIM_AF2_BK2CMP2E_Msk  (0x1UL << TIM_AF2_BK2CMP2E_Pos)  /*!< 0x00000004 */
#define TIM_AF2_BK2CMP2E      TIM_AF2_BK2CMP2E_Msk             /*!< tim_brk2_cmp2 enable */
/*!< BK2CMP3E configuration */
#define TIM_AF2_BK2CMP3E_Pos  (3U)
#define TIM_AF2_BK2CMP3E_Msk  (0x1UL << TIM_AF2_BK2CMP3E_Pos)  /*!< 0x00000008 */
#define TIM_AF2_BK2CMP3E      TIM_AF2_BK2CMP3E_Msk             /*!< tim_brk2_cmp3 enable */
/*!< BK2CMP4E configuration */
#define TIM_AF2_BK2CMP4E_Pos  (4U)
#define TIM_AF2_BK2CMP4E_Msk  (0x1UL << TIM_AF2_BK2CMP4E_Pos)  /*!< 0x00000010 */
#define TIM_AF2_BK2CMP4E      TIM_AF2_BK2CMP4E_Msk             /*!< tim_brk2_cmp4 enable */
/*!< BK2CMP5E configuration */
#define TIM_AF2_BK2CMP5E_Pos  (5U)
#define TIM_AF2_BK2CMP5E_Msk  (0x1UL << TIM_AF2_BK2CMP5E_Pos)  /*!< 0x00000020 */
#define TIM_AF2_BK2CMP5E      TIM_AF2_BK2CMP5E_Msk             /*!< BK2CMP5E (tim_brk2_cmp8 enable) */
/*!< BK2CMP6E configuration */
#define TIM_AF2_BK2CMP6E_Pos  (6U)
#define TIM_AF2_BK2CMP6E_Msk  (0x1UL << TIM_AF2_BK2CMP6E_Pos)  /*!< 0x00000040 */
#define TIM_AF2_BK2CMP6E      TIM_AF2_BK2CMP6E_Msk             /*!< BK2CMP6E (tim_brk2_cmp8 enable) */
/*!< BK2CMP7E configuration */
#define TIM_AF2_BK2CMP7E_Pos  (7U)
#define TIM_AF2_BK2CMP7E_Msk  (0x1UL << TIM_AF2_BK2CMP7E_Pos)  /*!< 0x00000080 */
#define TIM_AF2_BK2CMP7E      TIM_AF2_BK2CMP7E_Msk             /*!< tim_brk2_cmp7 enable */
/*!< BK2CMP8E configuration */
#define TIM_AF2_BK2CMP8E_Pos  (8U)
#define TIM_AF2_BK2CMP8E_Msk  (0x1UL << TIM_AF2_BK2CMP8E_Pos)  /*!< 0x00000100 */
#define TIM_AF2_BK2CMP8E      TIM_AF2_BK2CMP8E_Msk             /*!< tim_brk2_cmp8 enable */
/*!< BK2INP configuration */
#define TIM_AF2_BK2INP_Pos    (9U)
#define TIM_AF2_BK2INP_Msk    (0x1UL << TIM_AF2_BK2INP_Pos)    /*!< 0x00000200 */
#define TIM_AF2_BK2INP        TIM_AF2_BK2INP_Msk               /*!< BK2INP (TIMx_BKIN2 input polarity) */
/*!< BK2CMP1P configuration */
#define TIM_AF2_BK2CMP1P_Pos  (10U)
#define TIM_AF2_BK2CMP1P_Msk  (0x1UL << TIM_AF2_BK2CMP1P_Pos)  /*!< 0x00000400 */
#define TIM_AF2_BK2CMP1P      TIM_AF2_BK2CMP1P_Msk             /*!< BK2CMP1P (tim_brk2_cmp1 input polarity) */
/*!< BK2CMP2P configuration */
#define TIM_AF2_BK2CMP2P_Pos  (11U)
#define TIM_AF2_BK2CMP2P_Msk  (0x1UL << TIM_AF2_BK2CMP2P_Pos)  /*!< 0x00000800 */
#define TIM_AF2_BK2CMP2P      TIM_AF2_BK2CMP2P_Msk             /*!< tim_brk2_cmp2 input polarity */
/*!< BK2CMP3P configuration */
#define TIM_AF2_BK2CMP3P_Pos  (12U)
#define TIM_AF2_BK2CMP3P_Msk  (0x1UL << TIM_AF2_BK2CMP3P_Pos)  /*!< 0x00001000 */
#define TIM_AF2_BK2CMP3P      TIM_AF2_BK2CMP3P_Msk             /*!< tim_brk2_cmp3 input polarity */
/*!< BK2CMP4P configuration */
#define TIM_AF2_BK2CMP4P_Pos  (13U)
#define TIM_AF2_BK2CMP4P_Msk  (0x1UL << TIM_AF2_BK2CMP4P_Pos)  /*!< 0x00002000 */
#define TIM_AF2_BK2CMP4P      TIM_AF2_BK2CMP4P_Msk             /*!< tim_brk2_cmp4 input polarity */
/*!< OCRSEL configuration */
#define TIM_AF2_OCRSEL_Pos     (16U)
#define TIM_AF2_OCRSEL_Msk     (0xFUL << TIM_AF2_OCRSEL_Pos)    /*!< 0x000F0000 */
#define TIM_AF2_OCRSEL         TIM_AF2_OCRSEL_Msk               /*!< OCRSEL[3:0] bits (ocref_clr source selection) */
#define TIM_AF2_OCRSEL_0       (0x01UL << TIM_AF2_OCRSEL_Pos)   /*!< 0x00010000 */
#define TIM_AF2_OCRSEL_1       (0x02UL << TIM_AF2_OCRSEL_Pos)   /*!< 0x00020000 */
#define TIM_AF2_OCRSEL_2       (0x04UL << TIM_AF2_OCRSEL_Pos)   /*!< 0x00040000 */
#define TIM_AF2_OCRSEL_3       (0x08UL << TIM_AF2_OCRSEL_Pos)   /*!< 0x00080000 */
/*!< BK2CMP9E configuration */
#define TIM_AF2_BK2CMP9E_Pos   (20U)
#define TIM_AF2_BK2CMP9E_Msk   (0x1UL << TIM_AF2_BK2CMP9E_Pos)  /*!< 0x00100000 */
#define TIM_AF2_BK2CMP9E       TIM_AF2_BK2CMP9E_Msk             /*!< tim_brk2_cmp9 enable */
/*!< BK2CMP10E configuration */
#define TIM_AF2_BK2CMP10E_Pos  (21U)
#define TIM_AF2_BK2CMP10E_Msk  (0x1UL << TIM_AF2_BK2CMP10E_Pos) /*!< 0x00200000 */
#define TIM_AF2_BK2CMP10E      TIM_AF2_BK2CMP10E_Msk            /*!< tim_brk2_cmp10 enable */
/*!< BK2CMP11P configuration */
#define TIM_AF2_BK2CMP11E_Pos  (22U)
#define TIM_AF2_BK2CMP11E_Msk  (0x1UL << TIM_AF2_BK2CMP11E_Pos) /*!< 0x00400000 */
#define TIM_AF2_BK2CMP11E      TIM_AF2_BK2CMP11E_Msk            /*!< tim_brk2_cmp11 enable */
/*!< BK2CMP12P configuration */
#define TIM_AF2_BK2CMP12E_Pos  (23U)
#define TIM_AF2_BK2CMP12E_Msk  (0x1UL << TIM_AF2_BK2CMP12E_Pos) /*!< 0x00800000 */
#define TIM_AF2_BK2CMP12E      TIM_AF2_BK2CMP12E_Msk            /*!< tim_brk2_cmp12 enable */
/*!< BK2CMP13P configuration */
#define TIM_AF2_BK2CMP13E_Pos  (24U)
#define TIM_AF2_BK2CMP13E_Msk  (0x1UL << TIM_AF2_BK2CMP13E_Pos) /*!< 0x01000000 */
#define TIM_AF2_BK2CMP13E      TIM_AF2_BK2CMP13E_Msk            /*!< tim_brk2_cmp13 enable */
/*!< BK2CMP14P configuration */
#define TIM_AF2_BK2CMP14E_Pos  (25U)
#define TIM_AF2_BK2CMP14E_Msk  (0x1UL << TIM_AF2_BK2CMP14E_Pos) /*!< 0x02000000 */
#define TIM_AF2_BK2CMP14E      TIM_AF2_BK2CMP14E_Msk            /*!< tim_brk2_cmp14 enable */
/*!< BK2CMP15P configuration */
#define TIM_AF2_BK2CMP15E_Pos  (26U)
#define TIM_AF2_BK2CMP15E_Msk  (0x1UL << TIM_AF2_BK2CMP15E_Pos) /*!< 0x04000000 */
#define TIM_AF2_BK2CMP15E      TIM_AF2_BK2CMP15E_Msk            /*!< tim_brk2_cmp15 enable */
/*!< BK2CMP16P configuration */
#define TIM_AF2_BK2CMP16E_Pos  (27U)
#define TIM_AF2_BK2CMP16E_Msk  (0x1UL << TIM_AF2_BK2CMP16E_Pos) /*!< 0x08000000 */
#define TIM_AF2_BK2CMP16E      TIM_AF2_BK2CMP16E_Msk            /*!< tim_brk2_cmp16 enable */
/*!< BK2CMP17P configuration */
#define TIM_AF2_BK2CMP17E_Pos  (28U)
#define TIM_AF2_BK2CMP17E_Msk  (0x1UL << TIM_AF2_BK2CMP17E_Pos) /*!< 0x10000000 */
#define TIM_AF2_BK2CMP17E      TIM_AF2_BK2CMP17E_Msk            /*!< tim_brk2_cmp17 enable */
/*!< BK2CMP18P configuration */
#define TIM_AF2_BK2CMP18E_Pos  (29U)
#define TIM_AF2_BK2CMP18E_Msk  (0x1UL << TIM_AF2_BK2CMP18E_Pos) /*!< 0x20000000 */
#define TIM_AF2_BK2CMP18E      TIM_AF2_BK2CMP18E_Msk            /*!< tim_brk2_cmp18 enable */
/*!< BK2CMP19P configuration */
#define TIM_AF2_BK2CMP19E_Pos  (30U)
#define TIM_AF2_BK2CMP19E_Msk  (0x1UL << TIM_AF2_BK2CMP19E_Pos) /*!< 0x40000000 */
#define TIM_AF2_BK2CMP19E      TIM_AF2_BK2CMP19E_Msk            /*!< tim_brk2_cmp19 enable */
/*!< BK2CMP20P configuration */
#define TIM_AF2_BK2CMP20E_Pos  (31U)
#define TIM_AF2_BK2CMP20E_Msk  (0x1UL << TIM_AF2_BK2CMP20E_Pos) /*!< 0x80000000 */
#define TIM_AF2_BK2CMP20E      TIM_AF2_BK2CMP20E_Msk            /*!< tim_brk2_cmp20 enable */

/********************  Bit definition for TIM_CCR7 register  ********************/
/*!< CCR7 configuration */
#define TIM_CCR7_CCR7_Pos      (0U)
#define TIM_CCR7_CCR7_Msk      (0x000FFFFFUL << TIM_CCR7_CCR7_Pos) /*!< 0x000FFFFF */
#define TIM_CCR7_CCR7          TIM_CCR7_CCR7_Msk                   /*!< CCR7[19:0] bits (Capture/compare 7 value) */

/********************  Bit definition for TIM_CCMR4 register  ********************/
/*!< OC7FE configuration */
#define TIM_CCMR4_OC7FE_Pos    (2U)
#define TIM_CCMR4_OC7FE_Msk    (0x1UL << TIM_CCMR4_OC7FE_Pos)    /*!< 0x00000004 */
#define TIM_CCMR4_OC7FE        TIM_CCMR4_OC7FE_Msk               /*!< OC7FE (Output compare 7 fast enable) */
/*!< OC7PE configuration */
#define TIM_CCMR4_OC7PE_Pos    (3U)
#define TIM_CCMR4_OC7PE_Msk    (0x1UL << TIM_CCMR4_OC7PE_Pos)    /*!< 0x00000008 */
#define TIM_CCMR4_OC7PE        TIM_CCMR4_OC7PE_Msk               /*!< OC7PE (Output compare 7 preload enable) */
/*!< OC7M configuration */
#define TIM_CCMR4_OC7M_Pos     (4U)
#define TIM_CCMR4_OC7M_Msk     (0x3007UL << TIM_CCMR4_OC7M_Pos)  /*!< 0x00030070 */
#define TIM_CCMR4_OC7M         TIM_CCMR4_OC7M_Msk                /*!< OC7M[2:0] bits (Output compare 7 mode) */
#define TIM_CCMR4_OC7M_0       (0x0001UL << TIM_CCMR4_OC7M_Pos)  /*!< 0x00000010 */
#define TIM_CCMR4_OC7M_1       (0x0002UL << TIM_CCMR4_OC7M_Pos)  /*!< 0x00000020 */
#define TIM_CCMR4_OC7M_2       (0x0004UL << TIM_CCMR4_OC7M_Pos)  /*!< 0x00000040 */
#define TIM_CCMR4_OC7M_3       (0x1000UL << TIM_CCMR4_OC7M_Pos)  /*!< 0x00010000 */
#define TIM_CCMR4_OC7M_4       (0x2000UL << TIM_CCMR4_OC7M_Pos)  /*!< 0x00020000 */
/*!< OC7CE configuration */
#define TIM_CCMR4_OC7CE_Pos    (7U)
#define TIM_CCMR4_OC7CE_Msk    (0x1UL << TIM_CCMR4_OC7CE_Pos)    /*!< 0x00000080 */
#define TIM_CCMR4_OC7CE        TIM_CCMR4_OC7CE_Msk               /*!< OC7CE (Output compare 7 clear enable) */

/********************  Bit definition for TIM_MPR1 register  ********************/
/*!< BK1M configuration */
#define TIM_MPR1_BK1M_Pos      (0U)
#define TIM_MPR1_BK1M_Msk      (0x3UL << TIM_MPR1_BK1M_Pos)  /*!< 0x00000003 */
#define TIM_MPR1_BK1M          TIM_MPR1_BK1M_Msk             /*!< BK1M[1:0] bits (Break mode for tim_oc1 output) */
#define TIM_MPR1_BK1M_0        (0x1UL << TIM_MPR1_BK1M_Pos)  /*!< 0x00000001 */
#define TIM_MPR1_BK1M_1        (0x2UL << TIM_MPR1_BK1M_Pos)  /*!< 0x00000002 */
/*!< BK1NM configuration */
#define TIM_MPR1_BK1NM_Pos     (2U)
#define TIM_MPR1_BK1NM_Msk     (0x3UL << TIM_MPR1_BK1NM_Pos) /*!< 0x0000000C */
#define TIM_MPR1_BK1NM         TIM_MPR1_BK1NM_Msk            /*!< BK1NM[1:0] bits (Break mode for tim_oc1n output) */
#define TIM_MPR1_BK1NM_0       (0x1UL << TIM_MPR1_BK1NM_Pos) /*!< 0x00000004 */
#define TIM_MPR1_BK1NM_1       (0x2UL << TIM_MPR1_BK1NM_Pos) /*!< 0x00000008 */
/*!< BK2M configuration */
#define TIM_MPR1_BK2M_Pos      (4U)
#define TIM_MPR1_BK2M_Msk      (0x3UL << TIM_MPR1_BK2M_Pos)  /*!< 0x00000030 */
#define TIM_MPR1_BK2M          TIM_MPR1_BK2M_Msk             /*!< BK2M[1:0] bits (Break mode for tim_oc2 output) */
#define TIM_MPR1_BK2M_0        (0x1UL << TIM_MPR1_BK2M_Pos)  /*!< 0x00000010 */
#define TIM_MPR1_BK2M_1        (0x2UL << TIM_MPR1_BK2M_Pos)  /*!< 0x00000020 */
/*!< BK2NM configuration */
#define TIM_MPR1_BK2NM_Pos     (6U)
#define TIM_MPR1_BK2NM_Msk     (0x3UL << TIM_MPR1_BK2NM_Pos) /*!< 0x000000C0 */
#define TIM_MPR1_BK2NM         TIM_MPR1_BK2NM_Msk            /*!< BK2NM[1:0] bits (Break mode for tim_oc2n output) */
#define TIM_MPR1_BK2NM_0       (0x1UL << TIM_MPR1_BK2NM_Pos) /*!< 0x00000040 */
#define TIM_MPR1_BK2NM_1       (0x2UL << TIM_MPR1_BK2NM_Pos) /*!< 0x00000080 */
/*!< BK3M configuration */
#define TIM_MPR1_BK3M_Pos      (8U)
#define TIM_MPR1_BK3M_Msk      (0x3UL << TIM_MPR1_BK3M_Pos)  /*!< 0x00000300 */
#define TIM_MPR1_BK3M          TIM_MPR1_BK3M_Msk             /*!< BK3M[1:0] bits (Break mode for tim_oc3 output) */
#define TIM_MPR1_BK3M_0        (0x1UL << TIM_MPR1_BK3M_Pos)  /*!< 0x00000100 */
#define TIM_MPR1_BK3M_1        (0x2UL << TIM_MPR1_BK3M_Pos)  /*!< 0x00000200 */
/*!< BK3NM configuration */
#define TIM_MPR1_BK3NM_Pos     (10U)
#define TIM_MPR1_BK3NM_Msk     (0x3UL << TIM_MPR1_BK3NM_Pos) /*!< 0x00000C00 */
#define TIM_MPR1_BK3NM         TIM_MPR1_BK3NM_Msk            /*!< BK3NM[1:0] bits (Break mode for tim_oc3n output) */
#define TIM_MPR1_BK3NM_0       (0x1UL << TIM_MPR1_BK3NM_Pos) /*!< 0x00000400 */
#define TIM_MPR1_BK3NM_1       (0x2UL << TIM_MPR1_BK3NM_Pos) /*!< 0x00000800 */
/*!< BK4M configuration */
#define TIM_MPR1_BK4M_Pos      (12U)
#define TIM_MPR1_BK4M_Msk      (0x3UL << TIM_MPR1_BK4M_Pos)  /*!< 0x00003000 */
#define TIM_MPR1_BK4M          TIM_MPR1_BK4M_Msk             /*!< BK4M[1:0] bits (Break mode for tim_oc4 output) */
#define TIM_MPR1_BK4M_0        (0x1UL << TIM_MPR1_BK4M_Pos)  /*!< 0x00001000 */
#define TIM_MPR1_BK4M_1        (0x2UL << TIM_MPR1_BK4M_Pos)  /*!< 0x00002000 */
/*!< BK4NM configuration */
#define TIM_MPR1_BK4NM_Pos     (14U)
#define TIM_MPR1_BK4NM_Msk     (0x3UL << TIM_MPR1_BK4NM_Pos) /*!< 0x0000C000 */
#define TIM_MPR1_BK4NM         TIM_MPR1_BK4NM_Msk            /*!< BK4NM[1:0] bits (Break mode for tim_oc4n output) */
#define TIM_MPR1_BK4NM_0       (0x1UL << TIM_MPR1_BK4NM_Pos) /*!< 0x00004000 */
#define TIM_MPR1_BK4NM_1       (0x2UL << TIM_MPR1_BK4NM_Pos) /*!< 0x00008000 */

/********************  Bit definition for TIM_MPR2 register  ********************/
/*!< DBK1 configuration */
#define TIM_MPR2_DBK1_Pos      (0U)
#define TIM_MPR2_DBK1_Msk      (0xFFUL << TIM_MPR2_DBK1_Pos)  /*!< 0x000000FF */
#define TIM_MPR2_DBK1          TIM_MPR2_DBK1_Msk              /*!< DBK1[7:0] bits (Delayed 1 Break duration) */
/*!< DBK2 configuration */
#define TIM_MPR2_DBK2_Pos      (16U)
#define TIM_MPR2_DBK2_Msk      (0xFFUL << TIM_MPR2_DBK2_Pos)  /*!< 0x00FF0000 */
#define TIM_MPR2_DBK2          TIM_MPR2_DBK2_Msk              /*!< DBK2[7:0] bits (Delayed 2 Break duration) */

/********************  Bit definition for TIM_OOR register  ********************/
#define TIM_OOR_OOS1_Pos       (0U)
#define TIM_OOR_OOS1_Msk       (0x1UL << TIM_OOR_OOS1_Pos)  /*!< 0x00000001 */
#define TIM_OOR_OOS1           TIM_OOR_OOS1_Msk             /*!< OOS1 (Output override state for output tim_oc1n) */
/*!< OOS1N configuration */
#define TIM_OOR_OOS1N_Pos      (1U)
#define TIM_OOR_OOS1N_Msk      (0x1UL << TIM_OOR_OOS1N_Pos) /*!< 0x00000002 */
#define TIM_OOR_OOS1N          TIM_OOR_OOS1N_Msk            /*!< OOS1N (Output override state for output tim_oc1n) */
/*!< OOS2 configuration */
#define TIM_OOR_OOS2_Pos       (2U)
#define TIM_OOR_OOS2_Msk       (0x1UL << TIM_OOR_OOS2_Pos)  /*!< 0x00000004 */
#define TIM_OOR_OOS2           TIM_OOR_OOS2_Msk             /*!< OOS2 (Output override state for output tim_oc2n) */
/*!< OOS2N configuration */
#define TIM_OOR_OOS2N_Pos      (3U)
#define TIM_OOR_OOS2N_Msk      (0x1UL << TIM_OOR_OOS2N_Pos) /*!< 0x00000008 */
#define TIM_OOR_OOS2N          TIM_OOR_OOS2N_Msk            /*!< OOS2N (Output override state for output tim_oc2n) */
/*!< OOS3 configuration */
#define TIM_OOR_OOS3_Pos       (4U)
#define TIM_OOR_OOS3_Msk       (0x1UL << TIM_OOR_OOS3_Pos)  /*!< 0x00000010 */
#define TIM_OOR_OOS3           TIM_OOR_OOS3_Msk             /*!< OOS3 (Output override state for output tim_oc3n) */
/*!< OOS3N configuration */
#define TIM_OOR_OOS3N_Pos      (5U)
#define TIM_OOR_OOS3N_Msk      (0x1UL << TIM_OOR_OOS3N_Pos) /*!< 0x00000020 */
#define TIM_OOR_OOS3N          TIM_OOR_OOS3N_Msk            /*!< OOS3N (Output override state for output tim_oc3n) */
/*!< OOS4 configuration */
#define TIM_OOR_OOS4_Pos       (6U)
#define TIM_OOR_OOS4_Msk       (0x1UL << TIM_OOR_OOS4_Pos)  /*!< 0x00000040 */
#define TIM_OOR_OOS4           TIM_OOR_OOS4_Msk             /*!< OOS4 (Output override state for output tim_oc4n) */
/*!< OOS4N configuration */
#define TIM_OOR_OOS4N_Pos      (7U)
#define TIM_OOR_OOS4N_Msk      (0x1UL << TIM_OOR_OOS4N_Pos) /*!< 0x00000080 */
#define TIM_OOR_OOS4N          TIM_OOR_OOS4N_Msk            /*!< OOS4N (Output override state for output tim_oc4n) */
/*!< OOC configuration */
#define TIM_OOR_OOC_Pos        (12U)
#define TIM_OOR_OOC_Msk        (0x1UL << TIM_OOR_OOC_Pos)   /*!< 0x00001000 */
#define TIM_OOR_OOC            TIM_OOR_OOC_Msk              /*!< OOC (Output override control) */

/********************  Bit definition for TIM_DCR register  ********************/
/*!< DBA configuration */
#define TIM_DCR_DBA_Pos        (0U)
#define TIM_DCR_DBA_Msk        (0x1FUL << TIM_DCR_DBA_Pos)  /*!< 0x0000001F */
#define TIM_DCR_DBA            TIM_DCR_DBA_Msk              /*!< DBA[4:0] bits (DMA base address) */
#define TIM_DCR_DBA_0          (0x01UL << TIM_DCR_DBA_Pos)  /*!< 0x00000001 */
#define TIM_DCR_DBA_1          (0x02UL << TIM_DCR_DBA_Pos)  /*!< 0x00000002 */
#define TIM_DCR_DBA_2          (0x04UL << TIM_DCR_DBA_Pos)  /*!< 0x00000004 */
#define TIM_DCR_DBA_3          (0x08UL << TIM_DCR_DBA_Pos)  /*!< 0x00000008 */
#define TIM_DCR_DBA_4          (0x10UL << TIM_DCR_DBA_Pos)  /*!< 0x00000010 */
/*!< DBL configuration */
#define TIM_DCR_DBL_Pos        (8U)
#define TIM_DCR_DBL_Msk        (0x1FUL << TIM_DCR_DBL_Pos)  /*!< 0x00001F00 */
#define TIM_DCR_DBL            TIM_DCR_DBL_Msk              /*!< DBL[4:0] bits (DMA burst length) */
#define TIM_DCR_DBL_0          (0x01UL << TIM_DCR_DBL_Pos)  /*!< 0x00000100 */
#define TIM_DCR_DBL_1          (0x02UL << TIM_DCR_DBL_Pos)  /*!< 0x00000200 */
#define TIM_DCR_DBL_2          (0x04UL << TIM_DCR_DBL_Pos)  /*!< 0x00000400 */
#define TIM_DCR_DBL_3          (0x08UL << TIM_DCR_DBL_Pos)  /*!< 0x00000800 */
#define TIM_DCR_DBL_4          (0x10UL << TIM_DCR_DBL_Pos)  /*!< 0x00001000 */
/*!< DBSS configuration */
#define TIM_DCR_DBSS_Pos       (16U)
#define TIM_DCR_DBSS_Msk       (0xFUL << TIM_DCR_DBSS_Pos)  /*!< 0x000F0000 */
#define TIM_DCR_DBSS           TIM_DCR_DBSS_Msk             /*!< DBSS[3:0] bits (DMA burst source selection) */
#define TIM_DCR_DBSS_0         (0x01UL << TIM_DCR_DBSS_Pos) /*!< 0x00010000 */
#define TIM_DCR_DBSS_1         (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000 */
#define TIM_DCR_DBSS_2         (0x04UL << TIM_DCR_DBSS_Pos) /*!< 0x00040000 */
#define TIM_DCR_DBSS_3         (0x08UL << TIM_DCR_DBSS_Pos) /*!< 0x00080000 */

/********************  Bit definition for TIM_DMAR register  ********************/
/*!< DMAB configuration */
#define TIM_DMAR_DMAB_Pos      (0U)
#define TIM_DMAR_DMAB_Msk      (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0xFFFFFFFF */
#define TIM_DMAR_DMAB          TIM_DMAR_DMAB_Msk                   /*!< DMAB[31:0] bits (DMA register for burst accesses) */

/******************************************************************************/
/*                                                                            */
/*                         Low Power Timer (LPTIM)                            */
/*                                                                            */
/******************************************************************************/
/******************  Bit definition for LPTIM_ISR register  *******************/
#define LPTIM_ISR_CC1IF_Pos                 (0U)
#define LPTIM_ISR_CC1IF_Msk                 (0x1UL << LPTIM_ISR_CC1IF_Pos)            /*!< 0x00000001 */
#define LPTIM_ISR_CC1IF                     LPTIM_ISR_CC1IF_Msk                       /*!< Capture/Compare 1 interrupt flag */
#define LPTIM_ISR_ARRM_Pos                  (1U)
#define LPTIM_ISR_ARRM_Msk                  (0x1UL << LPTIM_ISR_ARRM_Pos)           /*!< 0x00000002 */
#define LPTIM_ISR_ARRM                      LPTIM_ISR_ARRM_Msk                      /*!< Autoreload match */
#define LPTIM_ISR_EXTTRIG_Pos               (2U)
#define LPTIM_ISR_EXTTRIG_Msk               (0x1UL << LPTIM_ISR_EXTTRIG_Pos)        /*!< 0x00000004 */
#define LPTIM_ISR_EXTTRIG                   LPTIM_ISR_EXTTRIG_Msk                   /*!< External trigger edge event */
#define LPTIM_ISR_CMP1OK_Pos                (3U)
#define LPTIM_ISR_CMP1OK_Msk                (0x1UL << LPTIM_ISR_CMP1OK_Pos)         /*!< 0x00000008 */
#define LPTIM_ISR_CMP1OK                    LPTIM_ISR_CMP1OK_Msk                    /*!< Compare register 1 update OK */
#define LPTIM_ISR_ARROK_Pos                 (4U)
#define LPTIM_ISR_ARROK_Msk                 (0x1UL << LPTIM_ISR_ARROK_Pos)          /*!< 0x00000010 */
#define LPTIM_ISR_ARROK                     LPTIM_ISR_ARROK_Msk                     /*!< Autoreload register update OK */
#define LPTIM_ISR_UP_Pos                    (5U)
#define LPTIM_ISR_UP_Msk                    (0x1UL << LPTIM_ISR_UP_Pos)             /*!< 0x00000020 */
#define LPTIM_ISR_UP                        LPTIM_ISR_UP_Msk                        /*!< Counter direction change down to up */
#define LPTIM_ISR_DOWN_Pos                  (6U)
#define LPTIM_ISR_DOWN_Msk                  (0x1UL << LPTIM_ISR_DOWN_Pos)           /*!< 0x00000040 */
#define LPTIM_ISR_DOWN                      LPTIM_ISR_DOWN_Msk                      /*!< Counter direction change up to down */
#define LPTIM_ISR_UE_Pos                    (7U)
#define LPTIM_ISR_UE_Msk                    (0x1UL << LPTIM_ISR_UE_Pos)             /*!< 0x00000080 */
#define LPTIM_ISR_UE                        LPTIM_ISR_UE_Msk                        /*!< Update event */
#define LPTIM_ISR_REPOK_Pos                 (8U)
#define LPTIM_ISR_REPOK_Msk                 (0x1UL << LPTIM_ISR_REPOK_Pos)          /*!< 0x00000100 */
#define LPTIM_ISR_REPOK                     LPTIM_ISR_REPOK_Msk                     /*!< Repetition register update OK */
#define LPTIM_ISR_CC2IF_Pos                 (9U)
#define LPTIM_ISR_CC2IF_Msk                 (0x1UL << LPTIM_ISR_CC2IF_Pos)          /*!< 0x00000200 */
#define LPTIM_ISR_CC2IF                     LPTIM_ISR_CC2IF_Msk                     /*!< Capture/Compare 2 interrupt flag */
#define LPTIM_ISR_CC1OF_Pos                 (12U)
#define LPTIM_ISR_CC1OF_Msk                 (0x1UL << LPTIM_ISR_CC1OF_Pos)          /*!< 0x00001000 */
#define LPTIM_ISR_CC1OF                     LPTIM_ISR_CC1OF_Msk                     /*!< Capture/Compare 1 over-capture flag */
#define LPTIM_ISR_CC2OF_Pos                 (13U)
#define LPTIM_ISR_CC2OF_Msk                 (0x1UL << LPTIM_ISR_CC2OF_Pos)          /*!< 0x00002000 */
#define LPTIM_ISR_CC2OF                     LPTIM_ISR_CC2OF_Msk                     /*!< Capture/Compare 2 over-capture flag */
#define LPTIM_ISR_CMP2OK_Pos                (19U)
#define LPTIM_ISR_CMP2OK_Msk                (0x1UL << LPTIM_ISR_CMP2OK_Pos)         /*!< 0x00080000 */
#define LPTIM_ISR_CMP2OK                    LPTIM_ISR_CMP2OK_Msk                    /*!< Compare register 2 update OK */
#define LPTIM_ISR_DIEROK_Pos                (24U)
#define LPTIM_ISR_DIEROK_Msk                (0x1UL << LPTIM_ISR_DIEROK_Pos)         /*!< 0x01000000 */
#define LPTIM_ISR_DIEROK                    LPTIM_ISR_DIEROK_Msk                    /*!< DMA & interrupt enable update OK */

/******************  Bit definition for LPTIM_ICR register  *******************/
#define LPTIM_ICR_CC1CF_Pos                 (0U)
#define LPTIM_ICR_CC1CF_Msk                 (0x1UL << LPTIM_ICR_CC1CF_Pos)          /*!< 0x00000001 */
#define LPTIM_ICR_CC1CF                     LPTIM_ICR_CC1CF_Msk                     /*!< Capture/Compare 1 clear flag  */
#define LPTIM_ICR_ARRMCF_Pos                (1U)
#define LPTIM_ICR_ARRMCF_Msk                (0x1UL << LPTIM_ICR_ARRMCF_Pos)         /*!< 0x00000002 */
#define LPTIM_ICR_ARRMCF                    LPTIM_ICR_ARRMCF_Msk                    /*!< Autoreload match clear flag */
#define LPTIM_ICR_EXTTRIGCF_Pos             (2U)
#define LPTIM_ICR_EXTTRIGCF_Msk             (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)      /*!< 0x00000004 */
#define LPTIM_ICR_EXTTRIGCF                 LPTIM_ICR_EXTTRIGCF_Msk                 /*!< External trigger edge event clear flag */
#define LPTIM_ICR_CMP1OKCF_Pos              (3U)
#define LPTIM_ICR_CMP1OKCF_Msk              (0x1UL << LPTIM_ICR_CMP1OKCF_Pos)       /*!< 0x00000008 */
#define LPTIM_ICR_CMP1OKCF                  LPTIM_ICR_CMP1OKCF_Msk                  /*!< Compare register 1 update OK clear flag */
#define LPTIM_ICR_ARROKCF_Pos               (4U)
#define LPTIM_ICR_ARROKCF_Msk               (0x1UL << LPTIM_ICR_ARROKCF_Pos)        /*!< 0x00000010 */
#define LPTIM_ICR_ARROKCF                   LPTIM_ICR_ARROKCF_Msk                   /*!< Autoreload register update OK clear flag */
#define LPTIM_ICR_UPCF_Pos                  (5U)
#define LPTIM_ICR_UPCF_Msk                  (0x1UL << LPTIM_ICR_UPCF_Pos)           /*!< 0x00000020 */
#define LPTIM_ICR_UPCF                      LPTIM_ICR_UPCF_Msk                      /*!< Counter direction change down to up clear flag */
#define LPTIM_ICR_DOWNCF_Pos                (6U)
#define LPTIM_ICR_DOWNCF_Msk                (0x1UL << LPTIM_ICR_DOWNCF_Pos)         /*!< 0x00000040 */
#define LPTIM_ICR_DOWNCF                    LPTIM_ICR_DOWNCF_Msk                    /*!< Counter direction change up to down clear flag */
#define LPTIM_ICR_UECF_Pos                  (7U)
#define LPTIM_ICR_UECF_Msk                  (0x1UL << LPTIM_ICR_UECF_Pos)           /*!< 0x00000080 */
#define LPTIM_ICR_UECF                      LPTIM_ICR_UECF_Msk                      /*!< Update event clear flag */
#define LPTIM_ICR_REPOKCF_Pos               (8U)
#define LPTIM_ICR_REPOKCF_Msk               (0x1UL << LPTIM_ICR_REPOKCF_Pos)        /*!< 0x00000100 */
#define LPTIM_ICR_REPOKCF                   LPTIM_ICR_REPOKCF_Msk                   /*!< Repetition register update OK clear flag */
#define LPTIM_ICR_CC2CF_Pos                 (9U)
#define LPTIM_ICR_CC2CF_Msk                 (0x1UL << LPTIM_ICR_CC2CF_Pos)          /*!< 0x00000200 */
#define LPTIM_ICR_CC2CF                     LPTIM_ICR_CC2CF_Msk                     /*!< Capture/Compare 2 clear flag  */
#define LPTIM_ICR_CC1OCF_Pos                (12U)
#define LPTIM_ICR_CC1OCF_Msk                (0x1UL << LPTIM_ICR_CC1OCF_Pos)         /*!< 0x00001000 */
#define LPTIM_ICR_CC1OCF                    LPTIM_ICR_CC1OCF_Msk                    /*!< Capture/Compare 1 over-capture clear flag */
#define LPTIM_ICR_CC2OCF_Pos                (13U)
#define LPTIM_ICR_CC2OCF_Msk                (0x1UL << LPTIM_ICR_CC2OCF_Pos)         /*!< 0x00002000 */
#define LPTIM_ICR_CC2OCF                    LPTIM_ICR_CC2OCF_Msk                    /*!< Capture/Compare 2 over-capture clear flag */
#define LPTIM_ICR_CMP2OKCF_Pos              (19U)
#define LPTIM_ICR_CMP2OKCF_Msk              (0x1UL << LPTIM_ICR_CMP2OKCF_Pos)       /*!< 0x00080000 */
#define LPTIM_ICR_CMP2OKCF                  LPTIM_ICR_CMP2OKCF_Msk                  /*!< Compare register 2 update OK clear flag */
#define LPTIM_ICR_DIEROKCF_Pos              (24U)
#define LPTIM_ICR_DIEROKCF_Msk              (0x1UL << LPTIM_ICR_DIEROKCF_Pos)       /*!< 0x01000000 */
#define LPTIM_ICR_DIEROKCF                  LPTIM_ICR_DIEROKCF_Msk                  /*!< Interrupt enable register update OK clear flag */
/******************  Bit definition for LPTIM_DIER register *******************/
#define LPTIM_DIER_CC1IE_Pos                (0U)
#define LPTIM_DIER_CC1IE_Msk                (0x1UL << LPTIM_DIER_CC1IE_Pos)         /*!< 0x00000001 */
#define LPTIM_DIER_CC1IE                    LPTIM_DIER_CC1IE_Msk                    /*!< Compare/Compare interrupt enable */
#define LPTIM_DIER_ARRMIE_Pos               (1U)
#define LPTIM_DIER_ARRMIE_Msk               (0x1UL << LPTIM_DIER_ARRMIE_Pos)        /*!< 0x00000002 */
#define LPTIM_DIER_ARRMIE                   LPTIM_DIER_ARRMIE_Msk                   /*!< Autoreload match interrupt enable */
#define LPTIM_DIER_EXTTRIGIE_Pos            (2U)
#define LPTIM_DIER_EXTTRIGIE_Msk            (0x1UL << LPTIM_DIER_EXTTRIGIE_Pos)     /*!< 0x00000004 */
#define LPTIM_DIER_EXTTRIGIE                LPTIM_DIER_EXTTRIGIE_Msk                /*!< External trigger edge event interrupt enable */
#define LPTIM_DIER_CMP1OKIE_Pos             (3U)
#define LPTIM_DIER_CMP1OKIE_Msk             (0x1UL << LPTIM_DIER_CMP1OKIE_Pos)      /*!< 0x00000008 */
#define LPTIM_DIER_CMP1OKIE                 LPTIM_DIER_CMP1OKIE_Msk                 /*!< Compare register 1 update OK interrupt enable */
#define LPTIM_DIER_ARROKIE_Pos              (4U)
#define LPTIM_DIER_ARROKIE_Msk              (0x1UL << LPTIM_DIER_ARROKIE_Pos)       /*!< 0x00000010 */
#define LPTIM_DIER_ARROKIE                  LPTIM_DIER_ARROKIE_Msk                  /*!< Autoreload register update OK interrupt enable */
#define LPTIM_DIER_UPIE_Pos                 (5U)
#define LPTIM_DIER_UPIE_Msk                 (0x1UL << LPTIM_DIER_UPIE_Pos)          /*!< 0x00000020 */
#define LPTIM_DIER_UPIE                     LPTIM_DIER_UPIE_Msk                     /*!< Counter direction change down to up interrupt enable */
#define LPTIM_DIER_DOWNIE_Pos               (6U)
#define LPTIM_DIER_DOWNIE_Msk               (0x1UL << LPTIM_DIER_DOWNIE_Pos)        /*!< 0x00000040 */
#define LPTIM_DIER_DOWNIE                   LPTIM_DIER_DOWNIE_Msk                   /*!< Counter direction change up to down interrupt enable */
#define LPTIM_DIER_UEIE_Pos                 (7U)
#define LPTIM_DIER_UEIE_Msk                 (0x1UL << LPTIM_DIER_UEIE_Pos)          /*!< 0x00000080 */
#define LPTIM_DIER_UEIE                     LPTIM_DIER_UEIE_Msk                     /*!< Update event interrupt enable */
#define LPTIM_DIER_REPOKIE_Pos              (8U)
#define LPTIM_DIER_REPOKIE_Msk              (0x1UL << LPTIM_DIER_REPOKIE_Pos)       /*!< 0x00000100 */
#define LPTIM_DIER_REPOKIE                  LPTIM_DIER_REPOKIE_Msk                  /*!< Repetition register update OK interrupt enable */
#define LPTIM_DIER_CC2IE_Pos                (9U)
#define LPTIM_DIER_CC2IE_Msk                (0x1UL << LPTIM_DIER_CC2IE_Pos)         /*!< 0x00000200 */
#define LPTIM_DIER_CC2IE                    LPTIM_DIER_CC2IE_Msk                    /*!< Capture/Compare 2 interrupt interrupt enable */
#define LPTIM_DIER_CC1OIE_Pos               (12U)
#define LPTIM_DIER_CC1OIE_Msk               (0x1UL << LPTIM_DIER_CC1OIE_Pos)        /*!< 0x00001000 */
#define LPTIM_DIER_CC1OIE                   LPTIM_DIER_CC1OIE_Msk                   /*!< Capture/Compare 1 over-capture interrupt enable */
#define LPTIM_DIER_CC2OIE_Pos               (13U)
#define LPTIM_DIER_CC2OIE_Msk               (0x1UL << LPTIM_DIER_CC2OIE_Pos)        /*!< 0x00002000 */
#define LPTIM_DIER_CC2OIE                   LPTIM_DIER_CC2OIE_Msk                   /*!< Capture/Compare 2 over-capture interrupt enable */
#define LPTIM_DIER_CC1DE_Pos                (16U)
#define LPTIM_DIER_CC1DE_Msk                (0x1UL << LPTIM_DIER_CC1DE_Pos)         /*!< 0x00010000 */
#define LPTIM_DIER_CC1DE                    LPTIM_DIER_CC1DE_Msk                    /*!< Capture/Compare 1 DMA request enable */
#define LPTIM_DIER_CMP2OKIE_Pos             (19U)
#define LPTIM_DIER_CMP2OKIE_Msk             (0x1UL << LPTIM_DIER_CMP2OKIE_Pos)      /*!< 0x00080000 */
#define LPTIM_DIER_CMP2OKIE                 LPTIM_DIER_CMP2OKIE_Msk                 /*!< Compare register 2 update OK interrupt enable */
#define LPTIM_DIER_UEDE_Pos                 (23U)
#define LPTIM_DIER_UEDE_Msk                 (0x1UL << LPTIM_DIER_UEDE_Pos)          /*!< 0x00800000 */
#define LPTIM_DIER_UEDE                     LPTIM_DIER_UEDE_Msk                     /*!< Update event DMA request enable */
#define LPTIM_DIER_CC2DE_Pos                (25U)
#define LPTIM_DIER_CC2DE_Msk                (0x1UL << LPTIM_DIER_CC2DE_Pos)         /*!< 0x02000000 */
#define LPTIM_DIER_CC2DE                    LPTIM_DIER_CC2DE_Msk                    /*!< Capture/Compare 2 DMA request enable */

/******************  Bit definition for LPTIM_CFGR register *******************/
#define LPTIM_CFGR_CKSEL_Pos                (0U)
#define LPTIM_CFGR_CKSEL_Msk                (0x1UL << LPTIM_CFGR_CKSEL_Pos)         /*!< 0x00000001 */
#define LPTIM_CFGR_CKSEL                    LPTIM_CFGR_CKSEL_Msk                    /*!< Clock selector */
#define LPTIM_CFGR_CKPOL_Pos                (1U)
#define LPTIM_CFGR_CKPOL_Msk                (0x3UL << LPTIM_CFGR_CKPOL_Pos)         /*!< 0x00000006 */
#define LPTIM_CFGR_CKPOL                    LPTIM_CFGR_CKPOL_Msk                    /*!< CKPOL[1:0] bits (Clock polarity) */
#define LPTIM_CFGR_CKPOL_0                  (0x1UL << LPTIM_CFGR_CKPOL_Pos)         /*!< 0x00000002 */
#define LPTIM_CFGR_CKPOL_1                  (0x2UL << LPTIM_CFGR_CKPOL_Pos)         /*!< 0x00000004 */
#define LPTIM_CFGR_CKFLT_Pos                (3U)
#define LPTIM_CFGR_CKFLT_Msk                (0x3UL << LPTIM_CFGR_CKFLT_Pos)         /*!< 0x00000018 */
#define LPTIM_CFGR_CKFLT                    LPTIM_CFGR_CKFLT_Msk                    /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
#define LPTIM_CFGR_CKFLT_0                  (0x1UL << LPTIM_CFGR_CKFLT_Pos)         /*!< 0x00000008 */
#define LPTIM_CFGR_CKFLT_1                  (0x2UL << LPTIM_CFGR_CKFLT_Pos)         /*!< 0x00000010 */
#define LPTIM_CFGR_TRGFLT_Pos               (6U)
#define LPTIM_CFGR_TRGFLT_Msk               (0x3UL << LPTIM_CFGR_TRGFLT_Pos)        /*!< 0x000000C0 */
#define LPTIM_CFGR_TRGFLT                   LPTIM_CFGR_TRGFLT_Msk                   /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
#define LPTIM_CFGR_TRGFLT_0                 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)        /*!< 0x00000040 */
#define LPTIM_CFGR_TRGFLT_1                 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)        /*!< 0x00000080 */
#define LPTIM_CFGR_PRESC_Pos                (9U)
#define LPTIM_CFGR_PRESC_Msk                (0x7UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000E00 */
#define LPTIM_CFGR_PRESC                    LPTIM_CFGR_PRESC_Msk                    /*!< PRESC[2:0] bits (Clock prescaler) */
#define LPTIM_CFGR_PRESC_0                  (0x1UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000200 */
#define LPTIM_CFGR_PRESC_1                  (0x2UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000400 */
#define LPTIM_CFGR_PRESC_2                  (0x4UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000800 */
#define LPTIM_CFGR_TRIGSEL_Pos              (13U)
#define LPTIM_CFGR_TRIGSEL_Msk              (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x0000E000 */
#define LPTIM_CFGR_TRIGSEL                  LPTIM_CFGR_TRIGSEL_Msk                  /*!< TRIGSEL[2:0]] bits (Trigger selector) */
#define LPTIM_CFGR_TRIGSEL_0                (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x00002000 */
#define LPTIM_CFGR_TRIGSEL_1                (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x00004000 */
#define LPTIM_CFGR_TRIGSEL_2                (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x00008000 */
#define LPTIM_CFGR_TRIGEN_Pos               (17U)
#define LPTIM_CFGR_TRIGEN_Msk               (0x3UL << LPTIM_CFGR_TRIGEN_Pos)        /*!< 0x00060000 */
#define LPTIM_CFGR_TRIGEN                   LPTIM_CFGR_TRIGEN_Msk                   /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
#define LPTIM_CFGR_TRIGEN_0                 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)        /*!< 0x00020000 */
#define LPTIM_CFGR_TRIGEN_1                 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)        /*!< 0x00040000 */
#define LPTIM_CFGR_TIMOUT_Pos               (19U)
#define LPTIM_CFGR_TIMOUT_Msk               (0x1UL << LPTIM_CFGR_TIMOUT_Pos)        /*!< 0x00080000 */
#define LPTIM_CFGR_TIMOUT                   LPTIM_CFGR_TIMOUT_Msk                   /*!< Timout enable */
#define LPTIM_CFGR_WAVE_Pos                 (20U)
#define LPTIM_CFGR_WAVE_Msk                 (0x1UL << LPTIM_CFGR_WAVE_Pos)          /*!< 0x00100000 */
#define LPTIM_CFGR_WAVE                     LPTIM_CFGR_WAVE_Msk                     /*!< Waveform shape */
#define LPTIM_CFGR_WAVPOL_Pos               (21U)
#define LPTIM_CFGR_WAVPOL_Msk               (0x1UL << LPTIM_CFGR_WAVPOL_Pos)        /*!< 0x00200000 */
#define LPTIM_CFGR_WAVPOL                   LPTIM_CFGR_WAVPOL_Msk                   /*!< Waveform shape */
#define LPTIM_CFGR_PRELOAD_Pos              (22U)
#define LPTIM_CFGR_PRELOAD_Msk              (0x1UL << LPTIM_CFGR_PRELOAD_Pos)       /*!< 0x00400000 */
#define LPTIM_CFGR_PRELOAD                  LPTIM_CFGR_PRELOAD_Msk                  /*!< Reg update mode */
#define LPTIM_CFGR_COUNTMODE_Pos            (23U)
#define LPTIM_CFGR_COUNTMODE_Msk            (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)     /*!< 0x00800000 */
#define LPTIM_CFGR_COUNTMODE                LPTIM_CFGR_COUNTMODE_Msk                /*!< Counter mode enable */
#define LPTIM_CFGR_ENC_Pos                  (24U)
#define LPTIM_CFGR_ENC_Msk                  (0x1UL << LPTIM_CFGR_ENC_Pos)           /*!< 0x01000000 */
#define LPTIM_CFGR_ENC                      LPTIM_CFGR_ENC_Msk                      /*!< Encoder mode enable */

/******************  Bit definition for LPTIM_CR register  ********************/
#define LPTIM_CR_ENABLE_Pos                 (0U)
#define LPTIM_CR_ENABLE_Msk                 (0x1UL << LPTIM_CR_ENABLE_Pos)          /*!< 0x00000001 */
#define LPTIM_CR_ENABLE                     LPTIM_CR_ENABLE_Msk                     /*!< LPTIMer enable */
#define LPTIM_CR_SNGSTRT_Pos                (1U)
#define LPTIM_CR_SNGSTRT_Msk                (0x1UL << LPTIM_CR_SNGSTRT_Pos)         /*!< 0x00000002 */
#define LPTIM_CR_SNGSTRT                    LPTIM_CR_SNGSTRT_Msk                    /*!< Timer start in single mode */
#define LPTIM_CR_CNTSTRT_Pos                (2U)
#define LPTIM_CR_CNTSTRT_Msk                (0x1UL << LPTIM_CR_CNTSTRT_Pos)         /*!< 0x00000004 */
#define LPTIM_CR_CNTSTRT                    LPTIM_CR_CNTSTRT_Msk                    /*!< Timer start in continuous mode */
#define LPTIM_CR_COUNTRST_Pos               (3U)
#define LPTIM_CR_COUNTRST_Msk               (0x1UL << LPTIM_CR_COUNTRST_Pos)        /*!< 0x00000008 */
#define LPTIM_CR_COUNTRST                   LPTIM_CR_COUNTRST_Msk                   /*!< Timer Counter reset in synchronous mode*/
#define LPTIM_CR_RSTARE_Pos                 (4U)
#define LPTIM_CR_RSTARE_Msk                 (0x1UL << LPTIM_CR_RSTARE_Pos)          /*!< 0x00000010 */
#define LPTIM_CR_RSTARE                     LPTIM_CR_RSTARE_Msk                     /*!< Timer Counter reset after read enable (asynchronously)*/

/******************  Bit definition for LPTIM_CCR1 register  ******************/
#define LPTIM_CCR1_CCR1_Pos                 (0U)
#define LPTIM_CCR1_CCR1_Msk                 (0xFFFFUL << LPTIM_CCR1_CCR1_Pos)       /*!< 0x0000FFFF */
#define LPTIM_CCR1_CCR1                     LPTIM_CCR1_CCR1_Msk                     /*!< Compare register 1 */

/******************  Bit definition for LPTIM_ARR register  *******************/
#define LPTIM_ARR_ARR_Pos                   (0U)
#define LPTIM_ARR_ARR_Msk                   (0xFFFFUL << LPTIM_ARR_ARR_Pos)         /*!< 0x0000FFFF */
#define LPTIM_ARR_ARR                       LPTIM_ARR_ARR_Msk                       /*!< Auto reload register */

/******************  Bit definition for LPTIM_CNT register  *******************/
#define LPTIM_CNT_CNT_Pos                   (0U)
#define LPTIM_CNT_CNT_Msk                   (0xFFFFUL << LPTIM_CNT_CNT_Pos)         /*!< 0x0000FFFF */
#define LPTIM_CNT_CNT                       LPTIM_CNT_CNT_Msk                       /*!< Counter register */

/******************  Bit definition for LPTIM_CFGR2 register  *****************/
#define LPTIM_CFGR2_IN1SEL_Pos              (0U)
#define LPTIM_CFGR2_IN1SEL_Msk              (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)       /*!< 0x00000003 */
#define LPTIM_CFGR2_IN1SEL                  LPTIM_CFGR2_IN1SEL_Msk                  /*!< IN1SEL[1:0] bits (Remap selection) */
#define LPTIM_CFGR2_IN1SEL_0                (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)       /*!< 0x00000001 */
#define LPTIM_CFGR2_IN1SEL_1                (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)       /*!< 0x00000002 */
#define LPTIM_CFGR2_IN2SEL_Pos              (4U)
#define LPTIM_CFGR2_IN2SEL_Msk              (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)       /*!< 0x00000030 */
#define LPTIM_CFGR2_IN2SEL                  LPTIM_CFGR2_IN2SEL_Msk                  /*!< IN2SEL[5:4] bits (Remap selection) */
#define LPTIM_CFGR2_IN2SEL_0                (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)       /*!< 0x00000010 */
#define LPTIM_CFGR2_IN2SEL_1                (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)       /*!< 0x00000020 */
#define LPTIM_CFGR2_IC1SEL_Pos              (16U)
#define LPTIM_CFGR2_IC1SEL_Msk              (0x3UL << LPTIM_CFGR2_IC1SEL_Pos)       /*!< 0x00000003 */
#define LPTIM_CFGR2_IC1SEL                  LPTIM_CFGR2_IC1SEL_Msk                  /*!< IC1SEL[17:16] bits */
#define LPTIM_CFGR2_IC1SEL_0                (0x1UL << LPTIM_CFGR2_IC1SEL_Pos)       /*!< 0x00010000 */
#define LPTIM_CFGR2_IC1SEL_1                (0x2UL << LPTIM_CFGR2_IC1SEL_Pos)       /*!< 0x00020000 */
#define LPTIM_CFGR2_IC2SEL_Pos              (20U)
#define LPTIM_CFGR2_IC2SEL_Msk              (0x3UL << LPTIM_CFGR2_IC2SEL_Pos)       /*!< 0x00000030 */
#define LPTIM_CFGR2_IC2SEL                  LPTIM_CFGR2_IC2SEL_Msk                  /*!< IC2SEL[21:20] bits */
#define LPTIM_CFGR2_IC2SEL_0                (0x1UL << LPTIM_CFGR2_IC2SEL_Pos)       /*!< 0x00100000 */
#define LPTIM_CFGR2_IC2SEL_1                (0x2UL << LPTIM_CFGR2_IC2SEL_Pos)       /*!< 0x00200000 */

/******************  Bit definition for LPTIM_RCR register  *******************/
#define LPTIM_RCR_REP_Pos                   (0U)
#define LPTIM_RCR_REP_Msk                   (0xFFUL << LPTIM_RCR_REP_Pos)           /*!< 0x000000FF */
#define LPTIM_RCR_REP                       LPTIM_RCR_REP_Msk                       /*!< Repetition register value */

/*****************  Bit definition for LPTIM_CCMR1 register  ******************/
#define LPTIM_CCMR1_CC1SEL_Pos              (0U)
#define LPTIM_CCMR1_CC1SEL_Msk              (0x1UL << LPTIM_CCMR1_CC1SEL_Pos)       /*!< 0x00000001 */
#define LPTIM_CCMR1_CC1SEL                  LPTIM_CCMR1_CC1SEL_Msk                  /*!< Capture/Compare 1 selection */
#define LPTIM_CCMR1_CC1E_Pos                (1U)
#define LPTIM_CCMR1_CC1E_Msk                (0x1UL << LPTIM_CCMR1_CC1E_Pos)         /*!< 0x00000002 */
#define LPTIM_CCMR1_CC1E                    LPTIM_CCMR1_CC1E_Msk                    /*!< Capture/Compare 1 output enable */
#define LPTIM_CCMR1_CC1P_Pos                (2U)
#define LPTIM_CCMR1_CC1P_Msk                (0x3UL << LPTIM_CCMR1_CC1P_Pos)         /*!< 0x0000000C */
#define LPTIM_CCMR1_CC1P                    LPTIM_CCMR1_CC1P_Msk                    /*!< Capture/Compare 1 output polarity */
#define LPTIM_CCMR1_CC1P_0                  (0x1UL << LPTIM_CCMR1_CC1P_Pos)         /*!< 0x00000004 */
#define LPTIM_CCMR1_CC1P_1                  (0x2UL << LPTIM_CCMR1_CC1P_Pos)         /*!< 0x00000008 */
#define LPTIM_CCMR1_IC1PSC_Pos              (8U)
#define LPTIM_CCMR1_IC1PSC_Msk              (0x3UL << LPTIM_CCMR1_IC1PSC_Pos)       /*!< 0x00000300 */
#define LPTIM_CCMR1_IC1PSC                  LPTIM_CCMR1_IC1PSC_Msk                  /*!< Input capture 1 prescaler */
#define LPTIM_CCMR1_IC1PSC_0                (0x1UL << LPTIM_CCMR1_IC1PSC_Pos)       /*!< 0x00000100 */
#define LPTIM_CCMR1_IC1PSC_1                (0x2UL << LPTIM_CCMR1_IC1PSC_Pos)       /*!< 0x00000200 */
#define LPTIM_CCMR1_IC1F_Pos                (12U)
#define LPTIM_CCMR1_IC1F_Msk                (0x3UL << LPTIM_CCMR1_IC1F_Pos)         /*!< 0x00003000 */
#define LPTIM_CCMR1_IC1F                    LPTIM_CCMR1_IC1F_Msk                    /*!< Input capture 1 filter */
#define LPTIM_CCMR1_IC1F_0                  (0x1UL << LPTIM_CCMR1_IC1F_Pos)         /*!< 0x00001000 */
#define LPTIM_CCMR1_IC1F_1                  (0x2UL << LPTIM_CCMR1_IC1F_Pos)         /*!< 0x00002000 */
#define LPTIM_CCMR1_CC2SEL_Pos              (16U)
#define LPTIM_CCMR1_CC2SEL_Msk              (0x1UL << LPTIM_CCMR1_CC2SEL_Pos)       /*!< 0x00010000 */
#define LPTIM_CCMR1_CC2SEL                  LPTIM_CCMR1_CC2SEL_Msk                  /*!< Capture/Compare 2 selection */
#define LPTIM_CCMR1_CC2E_Pos                (17U)
#define LPTIM_CCMR1_CC2E_Msk                (0x1UL << LPTIM_CCMR1_CC2E_Pos)         /*!< 0x00020000 */
#define LPTIM_CCMR1_CC2E                    LPTIM_CCMR1_CC2E_Msk                    /*!< Capture/Compare 2 output enable */
#define LPTIM_CCMR1_CC2P_Pos                (18U)
#define LPTIM_CCMR1_CC2P_Msk                (0x3UL << LPTIM_CCMR1_CC2P_Pos)         /*!< 0x000C0000 */
#define LPTIM_CCMR1_CC2P                    LPTIM_CCMR1_CC2P_Msk                    /*!< Capture/Compare 2 output polarity */
#define LPTIM_CCMR1_CC2P_0                  (0x1UL << LPTIM_CCMR1_CC2P_Pos)         /*!< 0x00040000 */
#define LPTIM_CCMR1_CC2P_1                  (0x2UL << LPTIM_CCMR1_CC2P_Pos)         /*!< 0x00080000 */
#define LPTIM_CCMR1_IC2PSC_Pos              (24U)
#define LPTIM_CCMR1_IC2PSC_Msk              (0x3UL << LPTIM_CCMR1_IC2PSC_Pos)       /*!< 0x03000000 */
#define LPTIM_CCMR1_IC2PSC                  LPTIM_CCMR1_IC2PSC_Msk                  /*!< Input capture 2 prescaler */
#define LPTIM_CCMR1_IC2PSC_0                (0x1UL << LPTIM_CCMR1_IC2PSC_Pos)       /*!< 0x01000000 */
#define LPTIM_CCMR1_IC2PSC_1                (0x2UL << LPTIM_CCMR1_IC2PSC_Pos)       /*!< 0x02000000 */
#define LPTIM_CCMR1_IC2F_Pos                (28U)
#define LPTIM_CCMR1_IC2F_Msk                (0x3UL << LPTIM_CCMR1_IC2F_Pos)         /*!< 0x30000000 */
#define LPTIM_CCMR1_IC2F                    LPTIM_CCMR1_IC2F_Msk                    /*!< Input capture 2 filter */
#define LPTIM_CCMR1_IC2F_0                  (0x1UL << LPTIM_CCMR1_IC2F_Pos)         /*!< 0x10000000 */
#define LPTIM_CCMR1_IC2F_1                  (0x2UL << LPTIM_CCMR1_IC2F_Pos)         /*!< 0x20000000 */

/******************  Bit definition for LPTIM_CCR2 register  ******************/
#define LPTIM_CCR2_CCR2_Pos                 (0U)
#define LPTIM_CCR2_CCR2_Msk                 (0xFFFFUL << LPTIM_CCR2_CCR2_Pos)       /*!< 0x0000FFFF */
#define LPTIM_CCR2_CCR2                     LPTIM_CCR2_CCR2_Msk                     /*!< Compare register 2 */

/******************************************************************************/
/*                                                                            */
/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
/*                                                                            */
/******************************************************************************/
/******************  Bit definition for USART_CR1 register  *******************/
#define USART_CR1_UE_Pos                    (0U)
#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)             /*!< 0x00000001 */
#define USART_CR1_UE                        USART_CR1_UE_Msk                        /*!< USART Enable */
#define USART_CR1_UESM_Pos                  (1U)
#define USART_CR1_UESM_Msk                  (0x1UL << USART_CR1_UESM_Pos)           /*!< 0x00000002 */
#define USART_CR1_UESM                      USART_CR1_UESM_Msk                      /*!< USART Enable in STOP Mode */
#define USART_CR1_RE_Pos                    (2U)
#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)             /*!< 0x00000004 */
#define USART_CR1_RE                        USART_CR1_RE_Msk                        /*!< Receiver Enable */
#define USART_CR1_TE_Pos                    (3U)
#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)             /*!< 0x00000008 */
#define USART_CR1_TE                        USART_CR1_TE_Msk                        /*!< Transmitter Enable */
#define USART_CR1_IDLEIE_Pos                (4U)
#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)         /*!< 0x00000010 */
#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk                    /*!< IDLE Interrupt Enable */
#define USART_CR1_RXNEIE_Pos                (5U)
#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)         /*!< 0x00000020 */
#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk                    /*!< RXNE Interrupt Enable */
#define USART_CR1_RXNEIE_RXFNEIE_Pos        USART_CR1_RXNEIE_Pos
#define USART_CR1_RXNEIE_RXFNEIE_Msk        USART_CR1_RXNEIE_Msk                    /*!< 0x00000020 */
#define USART_CR1_RXNEIE_RXFNEIE            USART_CR1_RXNEIE_Msk                    /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
#define USART_CR1_TCIE_Pos                  (6U)
#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)           /*!< 0x00000040 */
#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                      /*!< Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE_Pos                 (7U)
#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                     /*!< TXE Interrupt Enable */
#define USART_CR1_TXEIE_TXFNFIE_Pos         (7U)
#define USART_CR1_TXEIE_TXFNFIE_Msk         (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
#define USART_CR1_TXEIE_TXFNFIE             USART_CR1_TXEIE                         /*!< TXE and TX FIFO Not Full Interrupt Enable */
#define USART_CR1_PEIE_Pos                  (8U)
#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)           /*!< 0x00000100 */
#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                      /*!< PE Interrupt Enable */
#define USART_CR1_PS_Pos                    (9U)
#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)             /*!< 0x00000200 */
#define USART_CR1_PS                        USART_CR1_PS_Msk                        /*!< Parity Selection */
#define USART_CR1_PCE_Pos                   (10U)
#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)            /*!< 0x00000400 */
#define USART_CR1_PCE                       USART_CR1_PCE_Msk                       /*!< Parity Control Enable */
#define USART_CR1_WAKE_Pos                  (11U)
#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)           /*!< 0x00000800 */
#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                      /*!< Receiver Wakeup method */
#define USART_CR1_M_Pos                     (12U)
#define USART_CR1_M_Msk                     (0x10001UL << USART_CR1_M_Pos)          /*!< 0x10001000 */
#define USART_CR1_M                         USART_CR1_M_Msk                         /*!< Word length */
#define USART_CR1_M0_Pos                    (12U)
#define USART_CR1_M0_Msk                    (0x1UL << USART_CR1_M0_Pos)             /*!< 0x00001000 */
#define USART_CR1_M0                        USART_CR1_M0_Msk                        /*!< Word length - Bit 0 */
#define USART_CR1_MME_Pos                   (13U)
#define USART_CR1_MME_Msk                   (0x1UL << USART_CR1_MME_Pos)            /*!< 0x00002000 */
#define USART_CR1_MME                       USART_CR1_MME_Msk                       /*!< Mute Mode Enable */
#define USART_CR1_CMIE_Pos                  (14U)
#define USART_CR1_CMIE_Msk                  (0x1UL << USART_CR1_CMIE_Pos)           /*!< 0x00004000 */
#define USART_CR1_CMIE                      USART_CR1_CMIE_Msk                      /*!< Character match Interrupt Enable */
#define USART_CR1_OVER8_Pos                 (15U)
#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)          /*!< 0x00008000 */
#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                     /*!< Oversampling by 8-bit or 16-bit mode */
#define USART_CR1_DEDT_Pos                  (16U)
#define USART_CR1_DEDT_Msk                  (0x1FUL << USART_CR1_DEDT_Pos)          /*!< 0x001F0000 */
#define USART_CR1_DEDT                      USART_CR1_DEDT_Msk                      /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
#define USART_CR1_DEDT_0                    (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */
#define USART_CR1_DEDT_1                    (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */
#define USART_CR1_DEDT_2                    (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */
#define USART_CR1_DEDT_3                    (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */
#define USART_CR1_DEDT_4                    (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */
#define USART_CR1_DEAT_Pos                  (21U)
#define USART_CR1_DEAT_Msk                  (0x1FUL << USART_CR1_DEAT_Pos)          /*!< 0x03E00000 */
#define USART_CR1_DEAT                      USART_CR1_DEAT_Msk                      /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
#define USART_CR1_DEAT_0                    (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */
#define USART_CR1_DEAT_1                    (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */
#define USART_CR1_DEAT_2                    (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */
#define USART_CR1_DEAT_3                    (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */
#define USART_CR1_DEAT_4                    (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */
#define USART_CR1_RTOIE_Pos                 (26U)
#define USART_CR1_RTOIE_Msk                 (0x1UL << USART_CR1_RTOIE_Pos)          /*!< 0x04000000 */
#define USART_CR1_RTOIE                     USART_CR1_RTOIE_Msk                     /*!< Receive Time Out Interrupt Enable */
#define USART_CR1_EOBIE_Pos                 (27U)
#define USART_CR1_EOBIE_Msk                 (0x1UL << USART_CR1_EOBIE_Pos)          /*!< 0x08000000 */
#define USART_CR1_EOBIE                     USART_CR1_EOBIE_Msk                     /*!< End of Block Interrupt Enable */
#define USART_CR1_M1_Pos                    (28U)
#define USART_CR1_M1_Msk                    (0x1UL << USART_CR1_M1_Pos)             /*!< 0x10000000 */
#define USART_CR1_M1                        USART_CR1_M1_Msk                        /*!< Word length - Bit 1 */
#define USART_CR1_FIFOEN_Pos                (29U)
#define USART_CR1_FIFOEN_Msk                (0x1UL << USART_CR1_FIFOEN_Pos)         /*!< 0x20000000 */
#define USART_CR1_FIFOEN                    USART_CR1_FIFOEN_Msk                    /*!< FIFO mode enable */
#define USART_CR1_TXFEIE_Pos                (30U)
#define USART_CR1_TXFEIE_Msk                (0x1UL << USART_CR1_TXFEIE_Pos)         /*!< 0x40000000 */
#define USART_CR1_TXFEIE                    USART_CR1_TXFEIE_Msk                    /*!< TX FIFO Empty Interrupt Enable */
#define USART_CR1_RXFFIE_Pos                (31U)
#define USART_CR1_RXFFIE_Msk                (0x1UL << USART_CR1_RXFFIE_Pos)         /*!< 0x80000000 */
#define USART_CR1_RXFFIE                    USART_CR1_RXFFIE_Msk                    /*!< RX FIFO Full Interrupt Enable */

/******************  Bit definition for USART_CR2 register  *******************/
#define USART_CR2_SLVEN_Pos                 (0U)
#define USART_CR2_SLVEN_Msk                 (0x1UL << USART_CR2_SLVEN_Pos)          /*!< 0x00000001 */
#define USART_CR2_SLVEN                     USART_CR2_SLVEN_Msk                     /*!< Synchronous Slave mode enable */
#define USART_CR2_DIS_NSS_Pos               (3U)
#define USART_CR2_DIS_NSS_Msk               (0x1UL << USART_CR2_DIS_NSS_Pos)        /*!< 0x00000008 */
#define USART_CR2_DIS_NSS                   USART_CR2_DIS_NSS_Msk                   /*!< Slave Select (NSS) pin management */
#define USART_CR2_ADDM7_Pos                 (4U)
#define USART_CR2_ADDM7_Msk                 (0x1UL << USART_CR2_ADDM7_Pos)          /*!< 0x00000010 */
#define USART_CR2_ADDM7                     USART_CR2_ADDM7_Msk                     /*!< 7-bit or 4-bit Address Detection */
#define USART_CR2_LBDL_Pos                  (5U)
#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)           /*!< 0x00000020 */
#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                      /*!< LIN Break Detection Length */
#define USART_CR2_LBDIE_Pos                 (6U)
#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)          /*!< 0x00000040 */
#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                     /*!< LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL_Pos                  (8U)
#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)           /*!< 0x00000100 */
#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                      /*!< Last Bit Clock pulse */
#define USART_CR2_CPHA_Pos                  (9U)
#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)           /*!< 0x00000200 */
#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                      /*!< Clock Phase */
#define USART_CR2_CPOL_Pos                  (10U)
#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)           /*!< 0x00000400 */
#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                      /*!< Clock Polarity */
#define USART_CR2_CLKEN_Pos                 (11U)
#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)          /*!< 0x00000800 */
#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                     /*!< Clock Enable */
#define USART_CR2_STOP_Pos                  (12U)
#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)           /*!< 0x00003000 */
#define USART_CR2_STOP                      USART_CR2_STOP_Msk                      /*!< STOP[1:0] bits (STOP bits) */
#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */
#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */
#define USART_CR2_LINEN_Pos                 (14U)
#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)          /*!< 0x00004000 */
#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                     /*!< LIN mode enable */
#define USART_CR2_SWAP_Pos                  (15U)
#define USART_CR2_SWAP_Msk                  (0x1UL << USART_CR2_SWAP_Pos)           /*!< 0x00008000 */
#define USART_CR2_SWAP                      USART_CR2_SWAP_Msk                      /*!< SWAP TX/RX pins */
#define USART_CR2_RXINV_Pos                 (16U)
#define USART_CR2_RXINV_Msk                 (0x1UL << USART_CR2_RXINV_Pos)          /*!< 0x00010000 */
#define USART_CR2_RXINV                     USART_CR2_RXINV_Msk                     /*!< RX pin active level inversion */
#define USART_CR2_TXINV_Pos                 (17U)
#define USART_CR2_TXINV_Msk                 (0x1UL << USART_CR2_TXINV_Pos)          /*!< 0x00020000 */
#define USART_CR2_TXINV                     USART_CR2_TXINV_Msk                     /*!< TX pin active level inversion */
#define USART_CR2_DATAINV_Pos               (18U)
#define USART_CR2_DATAINV_Msk               (0x1UL << USART_CR2_DATAINV_Pos)        /*!< 0x00040000 */
#define USART_CR2_DATAINV                   USART_CR2_DATAINV_Msk                   /*!< Binary data inversion */
#define USART_CR2_MSBFIRST_Pos              (19U)
#define USART_CR2_MSBFIRST_Msk              (0x1UL << USART_CR2_MSBFIRST_Pos)       /*!< 0x00080000 */
#define USART_CR2_MSBFIRST                  USART_CR2_MSBFIRST_Msk                  /*!< Most Significant Bit First */
#define USART_CR2_ABREN_Pos                 (20U)
#define USART_CR2_ABREN_Msk                 (0x1UL << USART_CR2_ABREN_Pos)          /*!< 0x00100000 */
#define USART_CR2_ABREN                     USART_CR2_ABREN_Msk                     /*!< Auto Baud-Rate Enable*/
#define USART_CR2_ABRMOD_Pos                (21U)
#define USART_CR2_ABRMOD_Msk                (0x3UL << USART_CR2_ABRMOD_Pos)         /*!< 0x00600000 */
#define USART_CR2_ABRMOD                    USART_CR2_ABRMOD_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
#define USART_CR2_ABRMOD_0                  (0x1UL << USART_CR2_ABRMOD_Pos)         /*!< 0x00200000 */
#define USART_CR2_ABRMOD_1                  (0x2UL << USART_CR2_ABRMOD_Pos)         /*!< 0x00400000 */
#define USART_CR2_RTOEN_Pos                 (23U)
#define USART_CR2_RTOEN_Msk                 (0x1UL << USART_CR2_RTOEN_Pos)          /*!< 0x00800000 */
#define USART_CR2_RTOEN                     USART_CR2_RTOEN_Msk                     /*!< Receiver Time-Out enable */
#define USART_CR2_ADD_Pos                   (24U)
#define USART_CR2_ADD_Msk                   (0xFFUL << USART_CR2_ADD_Pos)           /*!< 0xFF000000 */
#define USART_CR2_ADD                       USART_CR2_ADD_Msk                       /*!< Address of the USART node */

/******************  Bit definition for USART_CR3 register  *******************/
#define USART_CR3_EIE_Pos                   (0U)
#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)            /*!< 0x00000001 */
#define USART_CR3_EIE                       USART_CR3_EIE_Msk                       /*!< Error Interrupt Enable */
#define USART_CR3_IREN_Pos                  (1U)
#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)           /*!< 0x00000002 */
#define USART_CR3_IREN                      USART_CR3_IREN_Msk                      /*!< IrDA mode Enable */
#define USART_CR3_IRLP_Pos                  (2U)
#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)           /*!< 0x00000004 */
#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                      /*!< IrDA Low-Power */
#define USART_CR3_HDSEL_Pos                 (3U)
#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)          /*!< 0x00000008 */
#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                     /*!< Half-Duplex Selection */
#define USART_CR3_NACK_Pos                  (4U)
#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)           /*!< 0x00000010 */
#define USART_CR3_NACK                      USART_CR3_NACK_Msk                      /*!< SmartCard NACK enable */
#define USART_CR3_SCEN_Pos                  (5U)
#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)           /*!< 0x00000020 */
#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                      /*!< SmartCard mode enable */
#define USART_CR3_DMAR_Pos                  (6U)
#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)           /*!< 0x00000040 */
#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                      /*!< DMA Enable Receiver */
#define USART_CR3_DMAT_Pos                  (7U)
#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)           /*!< 0x00000080 */
#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                      /*!< DMA Enable Transmitter */
#define USART_CR3_RTSE_Pos                  (8U)
#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)           /*!< 0x00000100 */
#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                      /*!< RTS Enable */
#define USART_CR3_CTSE_Pos                  (9U)
#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)           /*!< 0x00000200 */
#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                      /*!< CTS Enable */
#define USART_CR3_CTSIE_Pos                 (10U)
#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)          /*!< 0x00000400 */
#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                     /*!< CTS Interrupt Enable */
#define USART_CR3_ONEBIT_Pos                (11U)
#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)         /*!< 0x00000800 */
#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk                    /*!< One sample bit method enable */
#define USART_CR3_OVRDIS_Pos                (12U)
#define USART_CR3_OVRDIS_Msk                (0x1UL << USART_CR3_OVRDIS_Pos)         /*!< 0x00001000 */
#define USART_CR3_OVRDIS                    USART_CR3_OVRDIS_Msk                    /*!< Overrun Disable */
#define USART_CR3_DDRE_Pos                  (13U)
#define USART_CR3_DDRE_Msk                  (0x1UL << USART_CR3_DDRE_Pos)           /*!< 0x00002000 */
#define USART_CR3_DDRE                      USART_CR3_DDRE_Msk                      /*!< DMA Disable on Reception Error */
#define USART_CR3_DEM_Pos                   (14U)
#define USART_CR3_DEM_Msk                   (0x1UL << USART_CR3_DEM_Pos)            /*!< 0x00004000 */
#define USART_CR3_DEM                       USART_CR3_DEM_Msk                       /*!< Driver Enable Mode */
#define USART_CR3_DEP_Pos                   (15U)
#define USART_CR3_DEP_Msk                   (0x1UL << USART_CR3_DEP_Pos)            /*!< 0x00008000 */
#define USART_CR3_DEP                       USART_CR3_DEP_Msk                       /*!< Driver Enable Polarity Selection */
#define USART_CR3_SCARCNT_Pos               (17U)
#define USART_CR3_SCARCNT_Msk               (0x7UL << USART_CR3_SCARCNT_Pos)        /*!< 0x000E0000 */
#define USART_CR3_SCARCNT                   USART_CR3_SCARCNT_Msk                   /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
#define USART_CR3_SCARCNT_0                 (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */
#define USART_CR3_SCARCNT_1                 (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */
#define USART_CR3_SCARCNT_2                 (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */
#define USART_CR3_WUS_Pos                   (20U)
#define USART_CR3_WUS_Msk                   (0x3UL << USART_CR3_WUS_Pos)            /*!< 0x00300000 */
#define USART_CR3_WUS                       USART_CR3_WUS_Msk                       /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
#define USART_CR3_WUS_0                     (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */
#define USART_CR3_WUS_1                     (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */
#define USART_CR3_WUFIE_Pos                 (22U)
#define USART_CR3_WUFIE_Msk                 (0x1UL << USART_CR3_WUFIE_Pos)          /*!< 0x00400000 */
#define USART_CR3_WUFIE                     USART_CR3_WUFIE_Msk                     /*!< Wake Up Interrupt Enable */
#define USART_CR3_TXFTIE_Pos                (23U)
#define USART_CR3_TXFTIE_Msk                (0x1UL << USART_CR3_TXFTIE_Pos)         /*!< 0x00800000 */
#define USART_CR3_TXFTIE                    USART_CR3_TXFTIE_Msk                    /*!< TX FIFO Threshold Interrupt Enable */
#define USART_CR3_TCBGTIE_Pos               (24U)
#define USART_CR3_TCBGTIE_Msk               (0x1UL << USART_CR3_TCBGTIE_Pos)        /*!< 0x01000000 */
#define USART_CR3_TCBGTIE                   USART_CR3_TCBGTIE_Msk                   /*!< Transmission Complete Before Guard Time Interrupt Enable */
#define USART_CR3_RXFTCFG_Pos               (25U)
#define USART_CR3_RXFTCFG_Msk               (0x7UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x0E000000 */
#define USART_CR3_RXFTCFG                   USART_CR3_RXFTCFG_Msk                   /*!< RX FIFO Threshold Configuration */
#define USART_CR3_RXFTCFG_0                 (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */
#define USART_CR3_RXFTCFG_1                 (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */
#define USART_CR3_RXFTCFG_2                 (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */
#define USART_CR3_RXFTIE_Pos                (28U)
#define USART_CR3_RXFTIE_Msk                (0x1UL << USART_CR3_RXFTIE_Pos)         /*!< 0x10000000 */
#define USART_CR3_RXFTIE                    USART_CR3_RXFTIE_Msk                    /*!< RX FIFO Threshold Interrupt Enable */
#define USART_CR3_TXFTCFG_Pos               (29U)
#define USART_CR3_TXFTCFG_Msk               (0x7UL << USART_CR3_TXFTCFG_Pos)        /*!< 0xE0000000 */
#define USART_CR3_TXFTCFG                   USART_CR3_TXFTCFG_Msk                   /*!< TX FIFO Threshold configuration */
#define USART_CR3_TXFTCFG_0                 (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */
#define USART_CR3_TXFTCFG_1                 (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */
#define USART_CR3_TXFTCFG_2                 (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */

/******************  Bit definition for USART_BRR register  *******************/
#define USART_BRR_LPUART_Pos                (0U)
#define USART_BRR_LPUART_Msk                (0xFFFFFUL << USART_BRR_LPUART_Pos)     /*!< 0x000FFFFF */
#define USART_BRR_LPUART                    USART_BRR_LPUART_Msk                    /*!< LPUART Baud rate register [19:0] */
#define USART_BRR_BRR                       ((uint16_t)0xFFFF)                      /*!< USART  Baud rate register [15:0] */

/******************  Bit definition for USART_GTPR register  ******************/
#define USART_GTPR_PSC_Pos                  (0U)
#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)          /*!< 0x000000FF */
#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                      /*!< PSC[7:0] bits (Prescaler value) */
#define USART_GTPR_GT_Pos                   (8U)
#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)           /*!< 0x0000FF00 */
#define USART_GTPR_GT                       USART_GTPR_GT_Msk                       /*!< GT[7:0] bits (Guard time value) */

/*******************  Bit definition for USART_RTOR register  *****************/
#define USART_RTOR_RTO_Pos                  (0U)
#define USART_RTOR_RTO_Msk                  (0xFFFFFFUL << USART_RTOR_RTO_Pos)      /*!< 0x00FFFFFF */
#define USART_RTOR_RTO                      USART_RTOR_RTO_Msk                      /*!< Receiver Time Out Value */
#define USART_RTOR_BLEN_Pos                 (24U)
#define USART_RTOR_BLEN_Msk                 (0xFFUL << USART_RTOR_BLEN_Pos)         /*!< 0xFF000000 */
#define USART_RTOR_BLEN                     USART_RTOR_BLEN_Msk                     /*!< Block Length */

/*******************  Bit definition for USART_RQR register  ******************/
#define USART_RQR_ABRRQ                     ((uint16_t)0x0001)                      /*!< Auto-Baud Rate Request */
#define USART_RQR_SBKRQ                     ((uint16_t)0x0002)                      /*!< Send Break Request */
#define USART_RQR_MMRQ                      ((uint16_t)0x0004)                      /*!< Mute Mode Request */
#define USART_RQR_RXFRQ                     ((uint16_t)0x0008)                      /*!< Receive Data flush Request */
#define USART_RQR_TXFRQ                     ((uint16_t)0x0010)                      /*!< Transmit data flush Request */

/*******************  Bit definition for USART_ISR register  ******************/
#define USART_ISR_PE_Pos                    (0U)
#define USART_ISR_PE_Msk                    (0x1UL << USART_ISR_PE_Pos)             /*!< 0x00000001 */
#define USART_ISR_PE                        USART_ISR_PE_Msk                        /*!< Parity Error */
#define USART_ISR_FE_Pos                    (1U)
#define USART_ISR_FE_Msk                    (0x1UL << USART_ISR_FE_Pos)             /*!< 0x00000002 */
#define USART_ISR_FE                        USART_ISR_FE_Msk                        /*!< Framing Error */
#define USART_ISR_NE_Pos                    (2U)
#define USART_ISR_NE_Msk                    (0x1UL << USART_ISR_NE_Pos)             /*!< 0x00000004 */
#define USART_ISR_NE                        USART_ISR_NE_Msk                        /*!< Noise Error detection Flag */
#define USART_ISR_ORE_Pos                   (3U)
#define USART_ISR_ORE_Msk                   (0x1UL << USART_ISR_ORE_Pos)            /*!< 0x00000008 */
#define USART_ISR_ORE                       USART_ISR_ORE_Msk                       /*!< OverRun Error */
#define USART_ISR_IDLE_Pos                  (4U)
#define USART_ISR_IDLE_Msk                  (0x1UL << USART_ISR_IDLE_Pos)           /*!< 0x00000010 */
#define USART_ISR_IDLE                      USART_ISR_IDLE_Msk                      /*!< IDLE line detected */
#define USART_ISR_RXNE_Pos                  (5U)
#define USART_ISR_RXNE_Msk                  (0x1UL << USART_ISR_RXNE_Pos)           /*!< 0x00000020 */
#define USART_ISR_RXNE                      USART_ISR_RXNE_Msk                      /*!< Read Data Register Not Empty */
#define USART_ISR_RXNE_RXFNE_Pos            USART_ISR_RXNE_Pos
#define USART_ISR_RXNE_RXFNE_Msk            USART_ISR_RXNE_Msk                      /*!< 0x00000020 */
#define USART_ISR_RXNE_RXFNE                USART_ISR_RXNE_Msk                      /*!< Read Data Register or RX FIFO Not Empty */
#define USART_ISR_TC_Pos                    (6U)
#define USART_ISR_TC_Msk                    (0x1UL << USART_ISR_TC_Pos)             /*!< 0x00000040 */
#define USART_ISR_TC                        USART_ISR_TC_Msk                        /*!< Transmission Complete */
#define USART_ISR_TXE_Pos                   (7U)
#define USART_ISR_TXE_Msk                   (0x1UL << USART_ISR_TXE_Pos)            /*!< 0x00000080 */
#define USART_ISR_TXE                       USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty */
#define USART_ISR_TXE_TXFNF_Pos             USART_ISR_TXE_Pos
#define USART_ISR_TXE_TXFNF_Msk             USART_ISR_TXE_Msk                       /*!< 0x00000080 */
#define USART_ISR_TXE_TXFNF                 USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
#define USART_ISR_LBDF_Pos                  (8U)
#define USART_ISR_LBDF_Msk                  (0x1UL << USART_ISR_LBDF_Pos)           /*!< 0x00000100 */
#define USART_ISR_LBDF                      USART_ISR_LBDF_Msk                      /*!< LIN Break Detection Flag */
#define USART_ISR_CTSIF_Pos                 (9U)
#define USART_ISR_CTSIF_Msk                 (0x1UL << USART_ISR_CTSIF_Pos)          /*!< 0x00000200 */
#define USART_ISR_CTSIF                     USART_ISR_CTSIF_Msk                     /*!< CTS interrupt Flag */
#define USART_ISR_CTS_Pos                   (10U)
#define USART_ISR_CTS_Msk                   (0x1UL << USART_ISR_CTS_Pos)            /*!< 0x00000400 */
#define USART_ISR_CTS                       USART_ISR_CTS_Msk                       /*!< CTS Flag */
#define USART_ISR_RTOF_Pos                  (11U)
#define USART_ISR_RTOF_Msk                  (0x1UL << USART_ISR_RTOF_Pos)           /*!< 0x00000800 */
#define USART_ISR_RTOF                      USART_ISR_RTOF_Msk                      /*!< Receiver Time Out */
#define USART_ISR_EOBF_Pos                  (12U)
#define USART_ISR_EOBF_Msk                  (0x1UL << USART_ISR_EOBF_Pos)           /*!< 0x00001000 */
#define USART_ISR_EOBF                      USART_ISR_EOBF_Msk                      /*!< End Of Block Flag */
#define USART_ISR_UDR_Pos                   (13U)
#define USART_ISR_UDR_Msk                   (0x1UL << USART_ISR_UDR_Pos)            /*!< 0x00002000 */
#define USART_ISR_UDR                       USART_ISR_UDR_Msk                       /*!< SPI Slave Underrun error Flag */
#define USART_ISR_ABRE_Pos                  (14U)
#define USART_ISR_ABRE_Msk                  (0x1UL << USART_ISR_ABRE_Pos)           /*!< 0x00004000 */
#define USART_ISR_ABRE                      USART_ISR_ABRE_Msk                      /*!< Auto-Baud Rate Error */
#define USART_ISR_ABRF_Pos                  (15U)
#define USART_ISR_ABRF_Msk                  (0x1UL << USART_ISR_ABRF_Pos)           /*!< 0x00008000 */
#define USART_ISR_ABRF                      USART_ISR_ABRF_Msk                      /*!< Auto-Baud Rate Flag */
#define USART_ISR_BUSY_Pos                  (16U)
#define USART_ISR_BUSY_Msk                  (0x1UL << USART_ISR_BUSY_Pos)           /*!< 0x00010000 */
#define USART_ISR_BUSY                      USART_ISR_BUSY_Msk                      /*!< Busy Flag */
#define USART_ISR_CMF_Pos                   (17U)
#define USART_ISR_CMF_Msk                   (0x1UL << USART_ISR_CMF_Pos)            /*!< 0x00020000 */
#define USART_ISR_CMF                       USART_ISR_CMF_Msk                       /*!< Character Match Flag */
#define USART_ISR_SBKF_Pos                  (18U)
#define USART_ISR_SBKF_Msk                  (0x1UL << USART_ISR_SBKF_Pos)           /*!< 0x00040000 */
#define USART_ISR_SBKF                      USART_ISR_SBKF_Msk                      /*!< Send Break Flag */
#define USART_ISR_RWU_Pos                   (19U)
#define USART_ISR_RWU_Msk                   (0x1UL << USART_ISR_RWU_Pos)            /*!< 0x00080000 */
#define USART_ISR_RWU                       USART_ISR_RWU_Msk                       /*!< Receive Wake Up from mute mode Flag */
#define USART_ISR_WUF_Pos                   (20U)
#define USART_ISR_WUF_Msk                   (0x1UL << USART_ISR_WUF_Pos)            /*!< 0x00100000 */
#define USART_ISR_WUF                       USART_ISR_WUF_Msk                       /*!< Wake Up from low power mode Flag */
#define USART_ISR_TEACK_Pos                 (21U)
#define USART_ISR_TEACK_Msk                 (0x1UL << USART_ISR_TEACK_Pos)          /*!< 0x00200000 */
#define USART_ISR_TEACK                     USART_ISR_TEACK_Msk                     /*!< Transmit Enable Acknowledge Flag */
#define USART_ISR_REACK_Pos                 (22U)
#define USART_ISR_REACK_Msk                 (0x1UL << USART_ISR_REACK_Pos)          /*!< 0x00400000 */
#define USART_ISR_REACK                     USART_ISR_REACK_Msk                     /*!< Receive Enable Acknowledge Flag */
#define USART_ISR_TXFE_Pos                  (23U)
#define USART_ISR_TXFE_Msk                  (0x1UL << USART_ISR_TXFE_Pos)           /*!< 0x00800000 */
#define USART_ISR_TXFE                      USART_ISR_TXFE_Msk                      /*!< TX FIFO Empty Flag */
#define USART_ISR_RXFF_Pos                  (24U)
#define USART_ISR_RXFF_Msk                  (0x1UL << USART_ISR_RXFF_Pos)           /*!< 0x01000000 */
#define USART_ISR_RXFF                      USART_ISR_RXFF_Msk                      /*!< RX FIFO Full Flag */
#define USART_ISR_TCBGT_Pos                 (25U)
#define USART_ISR_TCBGT_Msk                 (0x1UL << USART_ISR_TCBGT_Pos)          /*!< 0x02000000 */
#define USART_ISR_TCBGT                     USART_ISR_TCBGT_Msk                     /*!< Transmission Complete Before Guard Time completion */
#define USART_ISR_RXFT_Pos                  (26U)
#define USART_ISR_RXFT_Msk                  (0x1UL << USART_ISR_RXFT_Pos)           /*!< 0x04000000 */
#define USART_ISR_RXFT                      USART_ISR_RXFT_Msk                      /*!< RX FIFO Threshold Flag */
#define USART_ISR_TXFT_Pos                  (27U)
#define USART_ISR_TXFT_Msk                  (0x1UL << USART_ISR_TXFT_Pos)           /*!< 0x08000000 */
#define USART_ISR_TXFT                      USART_ISR_TXFT_Msk                      /*!< TX FIFO Threshold Flag */

/*******************  Bit definition for USART_ICR register  ******************/
#define USART_ICR_PECF_Pos                  (0U)
#define USART_ICR_PECF_Msk                  (0x1UL << USART_ICR_PECF_Pos)           /*!< 0x00000001 */
#define USART_ICR_PECF                      USART_ICR_PECF_Msk                      /*!< Parity Error Clear Flag */
#define USART_ICR_FECF_Pos                  (1U)
#define USART_ICR_FECF_Msk                  (0x1UL << USART_ICR_FECF_Pos)           /*!< 0x00000002 */
#define USART_ICR_FECF                      USART_ICR_FECF_Msk                      /*!< Framing Error Clear Flag */
#define USART_ICR_NECF_Pos                  (2U)
#define USART_ICR_NECF_Msk                  (0x1UL << USART_ICR_NECF_Pos)           /*!< 0x00000004 */
#define USART_ICR_NECF                      USART_ICR_NECF_Msk                      /*!< Noise Error detected Clear Flag */
#define USART_ICR_ORECF_Pos                 (3U)
#define USART_ICR_ORECF_Msk                 (0x1UL << USART_ICR_ORECF_Pos)          /*!< 0x00000008 */
#define USART_ICR_ORECF                     USART_ICR_ORECF_Msk                     /*!< OverRun Error Clear Flag */
#define USART_ICR_IDLECF_Pos                (4U)
#define USART_ICR_IDLECF_Msk                (0x1UL << USART_ICR_IDLECF_Pos)         /*!< 0x00000010 */
#define USART_ICR_IDLECF                    USART_ICR_IDLECF_Msk                    /*!< IDLE line detected Clear Flag */
#define USART_ICR_TXFECF_Pos                (5U)
#define USART_ICR_TXFECF_Msk                (0x1UL << USART_ICR_TXFECF_Pos)         /*!< 0x00000020 */
#define USART_ICR_TXFECF                    USART_ICR_TXFECF_Msk                    /*!< TX FIFO Empty Clear Flag */
#define USART_ICR_TCCF_Pos                  (6U)
#define USART_ICR_TCCF_Msk                  (0x1UL << USART_ICR_TCCF_Pos)           /*!< 0x00000040 */
#define USART_ICR_TCCF                      USART_ICR_TCCF_Msk                      /*!< Transmission Complete Clear Flag */
#define USART_ICR_TCBGTCF_Pos               (7U)
#define USART_ICR_TCBGTCF_Msk               (0x1UL << USART_ICR_TCBGTCF_Pos)        /*!< 0x00000080 */
#define USART_ICR_TCBGTCF                   USART_ICR_TCBGTCF_Msk                   /*!< Transmission Complete Before Guard Time Clear Flag */
#define USART_ICR_LBDCF_Pos                 (8U)
#define USART_ICR_LBDCF_Msk                 (0x1UL << USART_ICR_LBDCF_Pos)          /*!< 0x00000100 */
#define USART_ICR_LBDCF                     USART_ICR_LBDCF_Msk                     /*!< LIN Break Detection Clear Flag */
#define USART_ICR_CTSCF_Pos                 (9U)
#define USART_ICR_CTSCF_Msk                 (0x1UL << USART_ICR_CTSCF_Pos)          /*!< 0x00000200 */
#define USART_ICR_CTSCF                     USART_ICR_CTSCF_Msk                     /*!< CTS Interrupt Clear Flag */
#define USART_ICR_RTOCF_Pos                 (11U)
#define USART_ICR_RTOCF_Msk                 (0x1UL << USART_ICR_RTOCF_Pos)          /*!< 0x00000800 */
#define USART_ICR_RTOCF                     USART_ICR_RTOCF_Msk                     /*!< Receiver Time Out Clear Flag */
#define USART_ICR_EOBCF_Pos                 (12U)
#define USART_ICR_EOBCF_Msk                 (0x1UL << USART_ICR_EOBCF_Pos)          /*!< 0x00001000 */
#define USART_ICR_EOBCF                     USART_ICR_EOBCF_Msk                     /*!< End Of Block Clear Flag */
#define USART_ICR_UDRCF_Pos                 (13U)
#define USART_ICR_UDRCF_Msk                 (0x1UL << USART_ICR_UDRCF_Pos)          /*!< 0x00002000 */
#define USART_ICR_UDRCF                     USART_ICR_UDRCF_Msk                     /*!< SPI Slave Underrun Clear Flag */
#define USART_ICR_CMCF_Pos                  (17U)
#define USART_ICR_CMCF_Msk                  (0x1UL << USART_ICR_CMCF_Pos)           /*!< 0x00020000 */
#define USART_ICR_CMCF                      USART_ICR_CMCF_Msk                      /*!< Character Match Clear Flag */
#define USART_ICR_WUCF_Pos                  (20U)
#define USART_ICR_WUCF_Msk                  (0x1UL << USART_ICR_WUCF_Pos)           /*!< 0x00100000 */
#define USART_ICR_WUCF                      USART_ICR_WUCF_Msk                      /*!< Wake Up from stop mode Clear Flag */

/*******************  Bit definition for USART_RDR register  ******************/
#define USART_RDR_RDR                       ((uint16_t)0x01FF)                      /*!< RDR[8:0] bits (Receive Data value) */

/*******************  Bit definition for USART_TDR register  ******************/
#define USART_TDR_TDR                       ((uint16_t)0x01FF)                      /*!< TDR[8:0] bits (Transmit Data value) */

/*******************  Bit definition for USART_PRESC register  ****************/
#define USART_PRESC_PRESCALER_Pos           (0U)
#define USART_PRESC_PRESCALER_Msk           (0xFUL << USART_PRESC_PRESCALER_Pos)    /*!< 0x0000000F */
#define USART_PRESC_PRESCALER               USART_PRESC_PRESCALER_Msk               /*!< PRESCALER[3:0] bits (Clock prescaler) */
#define USART_PRESC_PRESCALER_0             (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */
#define USART_PRESC_PRESCALER_1             (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */
#define USART_PRESC_PRESCALER_2             (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3             (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */

/* ****************************************************************************************************************** */
/*                                                                                                                    */
/*                            Universal serial bus full-speed host/device interface (USB)                             */
/*                                                                                                                    */
/* ****************************************************************************************************************** */

/* *************************************  Bit definition for USB_CHEP register  ************************************* */
#define USB_CHEP_EA_Pos           (0U)
#define USB_CHEP_EA_Msk           (0xFUL << USB_CHEP_EA_Pos)             /*!< 0x0000000F */
#define USB_CHEP_EA               USB_CHEP_EA_Msk                        /*!< endpoint/channel address */
#define USB_CHEP_STATTX_Pos       (4U)
#define USB_CHEP_STATTX_Msk       (0x3UL << USB_CHEP_STATTX_Pos)         /*!< 0x00000030 */
#define USB_CHEP_STATTX           USB_CHEP_STATTX_Msk                    /*!< Status bits, for transmission transfers */
#define USB_CHEP_DTOGTX_Pos       (6U)
#define USB_CHEP_DTOGTX_Msk       (0x1UL << USB_CHEP_DTOGTX_Pos)         /*!< 0x00000040 */
#define USB_CHEP_DTOGTX           USB_CHEP_DTOGTX_Msk                    /*!< Data toggle, for transmission transfers */
#define USB_CHEP_VTTX_Pos         (7U)
#define USB_CHEP_VTTX_Msk         (0x1UL << USB_CHEP_VTTX_Pos)           /*!< 0x00000080 */
#define USB_CHEP_VTTX             USB_CHEP_VTTX_Msk                      /*!< Valid USB transaction transmitted */
#define USB_CHEP_EPKIND_Pos       (8U)
#define USB_CHEP_EPKIND_Msk       (0x1UL << USB_CHEP_EPKIND_Pos)         /*!< 0x00000100 */
#define USB_CHEP_EPKIND           USB_CHEP_EPKIND_Msk                    /*!< endpoint/channel kind */
#define USB_CHEP_UTYPE_Pos        (9U)
#define USB_CHEP_UTYPE_Msk        (0x3UL << USB_CHEP_UTYPE_Pos)          /*!< 0x00000600 */
#define USB_CHEP_UTYPE            USB_CHEP_UTYPE_Msk                     /*!< USB type of transaction */
#define USB_CHEP_SETUP_Pos        (11U)
#define USB_CHEP_SETUP_Msk        (0x1UL << USB_CHEP_SETUP_Pos)          /*!< 0x00000800 */
#define USB_CHEP_SETUP            USB_CHEP_SETUP_Msk                     /*!< Setup transaction completed */
#define USB_CHEP_STATRX_Pos       (12U)
#define USB_CHEP_STATRX_Msk       (0x3UL << USB_CHEP_STATRX_Pos)         /*!< 0x00003000 */
#define USB_CHEP_STATRX           USB_CHEP_STATRX_Msk                    /*!< Status bits, for reception transfers */
#define USB_CHEP_DTOGRX_Pos       (14U)
#define USB_CHEP_DTOGRX_Msk       (0x1UL << USB_CHEP_DTOGRX_Pos)         /*!< 0x00004000 */
#define USB_CHEP_DTOGRX           USB_CHEP_DTOGRX_Msk                    /*!< Data Toggle, for reception transfers */
#define USB_CHEP_VTRX_Pos         (15U)
#define USB_CHEP_VTRX_Msk         (0x1UL << USB_CHEP_VTRX_Pos)           /*!< 0x00008000 */
#define USB_CHEP_VTRX             USB_CHEP_VTRX_Msk                      /*!< USB valid transaction received */
#define USB_CHEP_DEVADDR_Pos      (16U)
#define USB_CHEP_DEVADDR_Msk      (0x7FUL << USB_CHEP_DEVADDR_Pos)       /*!< 0x007F0000 */
#define USB_CHEP_DEVADDR          USB_CHEP_DEVADDR_Msk                   /*!< Host mode */
#define USB_CHEP_NAK_Pos          (23U)
#define USB_CHEP_NAK_Msk          (0x1UL << USB_CHEP_NAK_Pos)            /*!< 0x00800000 */
#define USB_CHEP_NAK              USB_CHEP_NAK_Msk                       /*!< Host mode */
#define USB_CHEP_LS_EP_Pos        (24U)
#define USB_CHEP_LS_EP_Msk        (0x1UL << USB_CHEP_LS_EP_Pos)          /*!< 0x01000000 */
#define USB_CHEP_LS_EP            USB_CHEP_LS_EP_Msk                     /*!< Low speed endpoint host with HUB only */
#define USB_CHEP_ERR_TX_Pos       (25U)
#define USB_CHEP_ERR_TX_Msk       (0x1UL << USB_CHEP_ERR_TX_Pos)         /*!< 0x02000000 */
#define USB_CHEP_ERR_TX           USB_CHEP_ERR_TX_Msk                    /*!< Received error for an OUT/SETUP
                                                                              transaction */
#define USB_CHEP_ERR_RX_Pos       (26U)
#define USB_CHEP_ERR_RX_Msk       (0x1UL << USB_CHEP_ERR_RX_Pos)         /*!< 0x04000000 */
#define USB_CHEP_ERR_RX           USB_CHEP_ERR_RX_Msk                    /*!< Received error for an IN transaction */
#define USB_CHEP_THREE_ERR_TX_Pos (27U)
#define USB_CHEP_THREE_ERR_TX_Msk (0x3UL << USB_CHEP_THREE_ERR_TX_Pos)   /*!< 0x18000000 */
#define USB_CHEP_THREE_ERR_TX     USB_CHEP_THREE_ERR_TX_Msk              /*!< Three errors for an OUT or SETUP
                                                                              transaction */
#define USB_CHEP_THREE_ERR_RX_Pos (29U)
#define USB_CHEP_THREE_ERR_RX_Msk (0x3UL << USB_CHEP_THREE_ERR_RX_Pos)   /*!< 0x60000000 */
#define USB_CHEP_THREE_ERR_RX     USB_CHEP_THREE_ERR_RX_Msk              /*!< Three errors for an IN transaction */

/* *************************************  Bit definition for USB_CNTR register  ************************************* */
#define USB_CNTR_USBRST_Pos       (0U)
#define USB_CNTR_USBRST_Msk       (0x1UL << USB_CNTR_USBRST_Pos)         /*!< 0x00000001 */
#define USB_CNTR_USBRST           USB_CNTR_USBRST_Msk                    /*!< USB Reset */
#define USB_CNTR_PDWN_Pos         (1U)
#define USB_CNTR_PDWN_Msk         (0x1UL << USB_CNTR_PDWN_Pos)           /*!< 0x00000002 */
#define USB_CNTR_PDWN             USB_CNTR_PDWN_Msk                      /*!< Power down */
#define USB_CNTR_SUSPRDY_Pos      (2U)
#define USB_CNTR_SUSPRDY_Msk      (0x1UL << USB_CNTR_SUSPRDY_Pos)        /*!< 0x00000004 */
#define USB_CNTR_SUSPRDY          USB_CNTR_SUSPRDY_Msk                   /*!< Suspend state effective */
#define USB_CNTR_SUSPEN_Pos       (3U)
#define USB_CNTR_SUSPEN_Msk       (0x1UL << USB_CNTR_SUSPEN_Pos)         /*!< 0x00000008 */
#define USB_CNTR_SUSPEN           USB_CNTR_SUSPEN_Msk                    /*!< Suspend state enable */
#define USB_CNTR_L2RES_Pos        (4U)
#define USB_CNTR_L2RES_Msk        (0x1UL << USB_CNTR_L2RES_Pos)          /*!< 0x00000010 */
#define USB_CNTR_L2RES            USB_CNTR_L2RES_Msk                     /*!< L2 remote wake-up / resume driver */
#define USB_CNTR_L1RES_Pos        (5U)
#define USB_CNTR_L1RES_Msk        (0x1UL << USB_CNTR_L1RES_Pos)          /*!< 0x00000020 */
#define USB_CNTR_L1RES            USB_CNTR_L1RES_Msk                     /*!< L1 remote wake-up / resume driver */
#define USB_CNTR_L1REQM_Pos       (7U)
#define USB_CNTR_L1REQM_Msk       (0x1UL << USB_CNTR_L1REQM_Pos)         /*!< 0x00000080 */
#define USB_CNTR_L1REQM           USB_CNTR_L1REQM_Msk                    /*!< LPM L1 state request interrupt mask */
#define USB_CNTR_ESOFM_Pos        (8U)
#define USB_CNTR_ESOFM_Msk        (0x1UL << USB_CNTR_ESOFM_Pos)          /*!< 0x00000100 */
#define USB_CNTR_ESOFM            USB_CNTR_ESOFM_Msk                     /*!< Expected start of frame interrupt mask */
#define USB_CNTR_SOFM_Pos         (9U)
#define USB_CNTR_SOFM_Msk         (0x1UL << USB_CNTR_SOFM_Pos)           /*!< 0x00000200 */
#define USB_CNTR_SOFM             USB_CNTR_SOFM_Msk                      /*!< Start of frame interrupt mask */
#define USB_CNTR_RST_DCONM_Pos    (10U)
#define USB_CNTR_RST_DCONM_Msk    (0x1UL << USB_CNTR_RST_DCONM_Pos)      /*!< 0x00000400 */
#define USB_CNTR_RST_DCONM        USB_CNTR_RST_DCONM_Msk                 /*!< USB reset request (Device mode) or device
                                                                              connect/disconnect (Host mode) interrupt
                                                                              mask */
#define USB_CNTR_SUSPM_Pos        (11U)
#define USB_CNTR_SUSPM_Msk        (0x1UL << USB_CNTR_SUSPM_Pos)          /*!< 0x00000800 */
#define USB_CNTR_SUSPM            USB_CNTR_SUSPM_Msk                     /*!< Suspend mode interrupt mask */
#define USB_CNTR_WKUPM_Pos        (12U)
#define USB_CNTR_WKUPM_Msk        (0x1UL << USB_CNTR_WKUPM_Pos)          /*!< 0x00001000 */
#define USB_CNTR_WKUPM            USB_CNTR_WKUPM_Msk                     /*!< Wake-up interrupt mask */
#define USB_CNTR_ERRM_Pos         (13U)
#define USB_CNTR_ERRM_Msk         (0x1UL << USB_CNTR_ERRM_Pos)           /*!< 0x00002000 */
#define USB_CNTR_ERRM             USB_CNTR_ERRM_Msk                      /*!< Error interrupt mask */
#define USB_CNTR_PMAOVRM_Pos      (14U)
#define USB_CNTR_PMAOVRM_Msk      (0x1UL << USB_CNTR_PMAOVRM_Pos)        /*!< 0x00004000 */
#define USB_CNTR_PMAOVRM          USB_CNTR_PMAOVRM_Msk                   /*!< Packet memory area over / underrun
                                                                              interrupt mask */
#define USB_CNTR_CTRM_Pos         (15U)
#define USB_CNTR_CTRM_Msk         (0x1UL << USB_CNTR_CTRM_Pos)           /*!< 0x00008000 */
#define USB_CNTR_CTRM             USB_CNTR_CTRM_Msk                      /*!< Correct transfer interrupt mask */
#define USB_CNTR_THR512M_Pos      (16U)
#define USB_CNTR_THR512M_Msk      (0x1UL << USB_CNTR_THR512M_Pos)        /*!< 0x00010000 */
#define USB_CNTR_THR512M          USB_CNTR_THR512M_Msk                   /*!< 512 byte threshold interrupt mask */
#define USB_CNTR_DDISCM_Pos       (17U)
#define USB_CNTR_DDISCM_Msk       (0x1UL << USB_CNTR_DDISCM_Pos)         /*!< 0x00020000 */
#define USB_CNTR_DDISCM           USB_CNTR_DDISCM_Msk                    /*!< Device disconnection mask */
#define USB_CNTR_HOST_Pos         (31U)
#define USB_CNTR_HOST_Msk         (0x1UL << USB_CNTR_HOST_Pos)           /*!< 0x80000000 */
#define USB_CNTR_HOST             USB_CNTR_HOST_Msk                      /*!< HOST mode */

/* *************************************  Bit definition for USB_ISTR register  ************************************* */
#define USB_ISTR_IDN_Pos          (0U)
#define USB_ISTR_IDN_Msk          (0xFUL << USB_ISTR_IDN_Pos)            /*!< 0x0000000F */
#define USB_ISTR_IDN              USB_ISTR_IDN_Msk                       /*!< Device Endpoint / host channel
                                                                              identification number */
#define USB_ISTR_DIR_Pos          (4U)
#define USB_ISTR_DIR_Msk          (0x1UL << USB_ISTR_DIR_Pos)            /*!< 0x00000010 */
#define USB_ISTR_DIR              USB_ISTR_DIR_Msk                       /*!< Direction of transaction */
#define USB_ISTR_L1REQ_Pos        (7U)
#define USB_ISTR_L1REQ_Msk        (0x1UL << USB_ISTR_L1REQ_Pos)          /*!< 0x00000080 */
#define USB_ISTR_L1REQ            USB_ISTR_L1REQ_Msk                     /*!< LPM L1 state request */
#define USB_ISTR_ESOF_Pos         (8U)
#define USB_ISTR_ESOF_Msk         (0x1UL << USB_ISTR_ESOF_Pos)           /*!< 0x00000100 */
#define USB_ISTR_ESOF             USB_ISTR_ESOF_Msk                      /*!< Expected start of frame */
#define USB_ISTR_SOF_Pos          (9U)
#define USB_ISTR_SOF_Msk          (0x1UL << USB_ISTR_SOF_Pos)            /*!< 0x00000200 */
#define USB_ISTR_SOF              USB_ISTR_SOF_Msk                       /*!< Start of frame */
#define USB_ISTR_RST_DCON_Pos     (10U)
#define USB_ISTR_RST_DCON_Msk     (0x1UL << USB_ISTR_RST_DCON_Pos)       /*!< 0x00000400 */
#define USB_ISTR_RST_DCON         USB_ISTR_RST_DCON_Msk                  /*!< USB reset request (Device mode) or device
                                                                              connect/disconnect (Host mode) */
#define USB_ISTR_SUSP_Pos         (11U)
#define USB_ISTR_SUSP_Msk         (0x1UL << USB_ISTR_SUSP_Pos)           /*!< 0x00000800 */
#define USB_ISTR_SUSP             USB_ISTR_SUSP_Msk                      /*!< Suspend mode request */
#define USB_ISTR_WKUP_Pos         (12U)
#define USB_ISTR_WKUP_Msk         (0x1UL << USB_ISTR_WKUP_Pos)           /*!< 0x00001000 */
#define USB_ISTR_WKUP             USB_ISTR_WKUP_Msk                      /*!< Wake-up */
#define USB_ISTR_ERR_Pos          (13U)
#define USB_ISTR_ERR_Msk          (0x1UL << USB_ISTR_ERR_Pos)            /*!< 0x00002000 */
#define USB_ISTR_ERR              USB_ISTR_ERR_Msk                       /*!< Error */
#define USB_ISTR_PMAOVR_Pos       (14U)
#define USB_ISTR_PMAOVR_Msk       (0x1UL << USB_ISTR_PMAOVR_Pos)         /*!< 0x00004000 */
#define USB_ISTR_PMAOVR           USB_ISTR_PMAOVR_Msk                    /*!< Packet memory area over / underrun */
#define USB_ISTR_CTR_Pos          (15U)
#define USB_ISTR_CTR_Msk          (0x1UL << USB_ISTR_CTR_Pos)            /*!< 0x00008000 */
#define USB_ISTR_CTR              USB_ISTR_CTR_Msk                       /*!< Completed transfer in host mode */
#define USB_ISTR_THR512_Pos       (16U)
#define USB_ISTR_THR512_Msk       (0x1UL << USB_ISTR_THR512_Pos)         /*!< 0x00010000 */
#define USB_ISTR_THR512           USB_ISTR_THR512_Msk                    /*!< 512 byte threshold interrupt */
#define USB_ISTR_DDISC_Pos        (17U)
#define USB_ISTR_DDISC_Msk        (0x1UL << USB_ISTR_DDISC_Pos)          /*!< 0x00020000 */
#define USB_ISTR_DDISC            USB_ISTR_DDISC_Msk                     /*!< Device connection */
#define USB_ISTR_DCON_STAT_Pos    (29U)
#define USB_ISTR_DCON_STAT_Msk    (0x1UL << USB_ISTR_DCON_STAT_Pos)      /*!< 0x20000000 */
#define USB_ISTR_DCON_STAT        USB_ISTR_DCON_STAT_Msk                 /*!< Device connection status */
#define USB_ISTR_LS_DCON_Pos      (30U)
#define USB_ISTR_LS_DCON_Msk      (0x1UL << USB_ISTR_LS_DCON_Pos)        /*!< 0x40000000 */
#define USB_ISTR_LS_DCON          USB_ISTR_LS_DCON_Msk                   /*!< Low speed device connected */

/* *************************************  Bit definition for USB_FNR register  ************************************** */
#define USB_FNR_FN_Pos            (0U)
#define USB_FNR_FN_Msk            (0x7FFUL << USB_FNR_FN_Pos)            /*!< 0x000007FF */
#define USB_FNR_FN                USB_FNR_FN_Msk                         /*!< Frame number */
#define USB_FNR_LSOF_Pos          (11U)
#define USB_FNR_LSOF_Msk          (0x3UL << USB_FNR_LSOF_Pos)            /*!< 0x00001800 */
#define USB_FNR_LSOF              USB_FNR_LSOF_Msk                       /*!< Lost SOF */
#define USB_FNR_LCK_Pos           (13U)
#define USB_FNR_LCK_Msk           (0x1UL << USB_FNR_LCK_Pos)             /*!< 0x00002000 */
#define USB_FNR_LCK               USB_FNR_LCK_Msk                        /*!< Locked */
#define USB_FNR_RXDM_Pos          (14U)
#define USB_FNR_RXDM_Msk          (0x1UL << USB_FNR_RXDM_Pos)            /*!< 0x00004000 */
#define USB_FNR_RXDM              USB_FNR_RXDM_Msk                       /*!< Receive data - line status */
#define USB_FNR_RXDP_Pos          (15U)
#define USB_FNR_RXDP_Msk          (0x1UL << USB_FNR_RXDP_Pos)            /*!< 0x00008000 */
#define USB_FNR_RXDP              USB_FNR_RXDP_Msk                       /*!< Receive data + line status */

/* ************************************  Bit definition for USB_DADDR register  ************************************* */
#define USB_DADDR_ADD_Pos         (0U)
#define USB_DADDR_ADD_Msk         (0x7FUL << USB_DADDR_ADD_Pos)          /*!< 0x0000007F */
#define USB_DADDR_ADD             USB_DADDR_ADD_Msk                      /*!< Device address */
#define USB_DADDR_EF_Pos          (7U)
#define USB_DADDR_EF_Msk          (0x1UL << USB_DADDR_EF_Pos)            /*!< 0x00000080 */
#define USB_DADDR_EF              USB_DADDR_EF_Msk                       /*!< Enable function */

/* ************************************  Bit definition for USB_LPMCSR register  ************************************ */
#define USB_LPMCSR_LPMEN_Pos      (0U)
#define USB_LPMCSR_LPMEN_Msk      (0x1UL << USB_LPMCSR_LPMEN_Pos)        /*!< 0x00000001 */
#define USB_LPMCSR_LPMEN          USB_LPMCSR_LPMEN_Msk                   /*!< LPM support enable */
#define USB_LPMCSR_LPMACK_Pos     (1U)
#define USB_LPMCSR_LPMACK_Msk     (0x1UL << USB_LPMCSR_LPMACK_Pos)       /*!< 0x00000002 */
#define USB_LPMCSR_LPMACK         USB_LPMCSR_LPMACK_Msk                  /*!< LPM token acknowledge enable */
#define USB_LPMCSR_REMWAKE_Pos    (3U)
#define USB_LPMCSR_REMWAKE_Msk    (0x1UL << USB_LPMCSR_REMWAKE_Pos)      /*!< 0x00000008 */
#define USB_LPMCSR_REMWAKE        USB_LPMCSR_REMWAKE_Msk                 /*!< bRemoteWake value */
#define USB_LPMCSR_BESL_Pos       (4U)
#define USB_LPMCSR_BESL_Msk       (0xFUL << USB_LPMCSR_BESL_Pos)         /*!< 0x000000F0 */
#define USB_LPMCSR_BESL           USB_LPMCSR_BESL_Msk                    /*!< BESL value */

/* *************************************  Bit definition for USB_BCDR register  ************************************* */
#define USB_BCDR_BCDEN_Pos        (0U)
#define USB_BCDR_BCDEN_Msk        (0x1UL << USB_BCDR_BCDEN_Pos)          /*!< 0x00000001 */
#define USB_BCDR_BCDEN            USB_BCDR_BCDEN_Msk                     /*!< Battery charging detector (BCD) enable */
#define USB_BCDR_DCDEN_Pos        (1U)
#define USB_BCDR_DCDEN_Msk        (0x1UL << USB_BCDR_DCDEN_Pos)          /*!< 0x00000002 */
#define USB_BCDR_DCDEN            USB_BCDR_DCDEN_Msk                     /*!< Data contact detection (DCD) mode enable
                                                                              */
#define USB_BCDR_PDEN_Pos         (2U)
#define USB_BCDR_PDEN_Msk         (0x1UL << USB_BCDR_PDEN_Pos)           /*!< 0x00000004 */
#define USB_BCDR_PDEN             USB_BCDR_PDEN_Msk                      /*!< Primary detection (PD) mode enable */
#define USB_BCDR_SDEN_Pos         (3U)
#define USB_BCDR_SDEN_Msk         (0x1UL << USB_BCDR_SDEN_Pos)           /*!< 0x00000008 */
#define USB_BCDR_SDEN             USB_BCDR_SDEN_Msk                      /*!< Secondary detection (SD) mode enable */
#define USB_BCDR_DCDET_Pos        (4U)
#define USB_BCDR_DCDET_Msk        (0x1UL << USB_BCDR_DCDET_Pos)          /*!< 0x00000010 */
#define USB_BCDR_DCDET            USB_BCDR_DCDET_Msk                     /*!< Data contact detection (DCD) status */
#define USB_BCDR_PDET_Pos         (5U)
#define USB_BCDR_PDET_Msk         (0x1UL << USB_BCDR_PDET_Pos)           /*!< 0x00000020 */
#define USB_BCDR_PDET             USB_BCDR_PDET_Msk                      /*!< Primary detection (PD) status */
#define USB_BCDR_SDET_Pos         (6U)
#define USB_BCDR_SDET_Msk         (0x1UL << USB_BCDR_SDET_Pos)           /*!< 0x00000040 */
#define USB_BCDR_SDET             USB_BCDR_SDET_Msk                      /*!< Secondary detection (SD) status */
#define USB_BCDR_PS2DET_Pos       (7U)
#define USB_BCDR_PS2DET_Msk       (0x1UL << USB_BCDR_PS2DET_Pos)         /*!< 0x00000080 */
#define USB_BCDR_PS2DET           USB_BCDR_PS2DET_Msk                    /*!< DM pull-up detection status */
#define USB_BCDR_DPPU_DPD_Pos     (15U)
#define USB_BCDR_DPPU_DPD_Msk     (0x1UL << USB_BCDR_DPPU_DPD_Pos)       /*!< 0x00008000 */
#define USB_BCDR_DPPU_DPD         USB_BCDR_DPPU_DPD_Msk                  /*!< DP pull-up / DPDM pull-down */


/* EndPoint Register MASK (no toggle fields) */
#define USB_CHEP_REG_MASK                          (USB_CHEP_ERR_RX | USB_CHEP_ERR_TX | USB_CHEP_LS_EP | \
                                                    USB_CHEP_DEVADDR | USB_CHEP_VTRX | USB_CHEP_SETUP | \
                                                    USB_CHEP_UTYPE | USB_CHEP_EPKIND | USB_CHEP_VTTX | USB_CHEP_EA | \
                                                    USB_CHEP_NAK) /* 0x07FF8F8F */

#define USB_CHEP_TX_DTOGMASK                       (USB_CHEP_STATTX | USB_CHEP_REG_MASK)
#define USB_CHEP_RX_DTOGMASK                       (USB_CHEP_STATRX | USB_CHEP_REG_MASK)

#define USB_CHEP_TX_DTOG1                          (0x00000010UL)           /*!< Channel/EndPoint TX Data Toggle bit1 */
#define USB_CHEP_TX_DTOG2                          (0x00000020UL)           /*!< Channel/EndPoint TX Data Toggle bit2 */
#define USB_CHEP_RX_DTOG1                          (0x00001000UL)           /*!< Channel/EndPoint RX Data Toggle bit1 */
#define USB_CHEP_RX_DTOG2                          (0x00002000UL)           /*!< Channel/EndPoint RX Data Toggle bit2 */

/*!< EP_TYPE[1:0] Channel/EndPoint TYPE */
#define USB_EP_TYPE_MASK                           (0x00000600UL)           /*!< Channel/EndPoint TYPE Mask */
#define USB_EP_BULK                                (0x00000000UL)           /*!< Channel/EndPoint BULK */
#define USB_EP_CONTROL                             (0x00000200UL)           /*!< Channel/EndPoint CONTROL */
#define USB_EP_ISOCHRONOUS                         (0x00000400UL)           /*!< Channel/EndPoint ISOCHRONOUS */
#define USB_EP_INTERRUPT                           (0x00000600UL)           /*!< Channel/EndPoint INTERRUPT */

#define USB_EP_T_MASK                              ((~USB_EP_UTYPE) & USB_CHEP_REG_MASK) /* =0x898F */
#define USB_CH_T_MASK                              ((~USB_CH_UTYPE) & USB_CHEP_REG_MASK) /* =0x898F */

#define USB_EP_KIND_MASK                           ((~USB_EP_EPKIND) & USB_CHEP_REG_MASK) /*!< EP_KIND EndPoint KIND */
#define USB_CH_KIND_MASK                           ((~USB_CH_EPKIND) & USB_CHEP_REG_MASK) /*!< EP_KIND EndPoint KIND */

/*!< STAT_TX[1:0] STATus for TX transfer */
#define USB_EP_TX_DIS                              (0x00000000UL)           /*!< EndPoint TX Disabled */
#define USB_EP_TX_STALL                            (0x00000010UL)           /*!< EndPoint TX STALLed */
#define USB_EP_TX_NAK                              (0x00000020UL)           /*!< EndPoint TX NAKed */
#define USB_EP_TX_VALID                            (0x00000030UL)           /*!< EndPoint TX VALID */

#define USB_CH_TX_DIS                              (0x00000000UL)           /*!< Channel TX Disabled */
#define USB_CH_TX_STALL                            (0x00000010UL)           /*!< Channel TX STALLed */
#define USB_CH_TX_NAK                              (0x00000020UL)           /*!< Channel TX NAKed */
#define USB_CH_TX_VALID                            (0x00000030UL)           /*!< Channel TX VALID */

#define USB_EP_TX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
#define USB_EP_TX_ACK_DBUF                         (0x00000030UL)           /*!< ACK Double buffer mode */

#define USB_CH_TX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
#define USB_CH_TX_ACK_DBUF                         (0x00000030UL)           /*!< ACK Double buffer mode */

/*!< STAT_RX[1:0] STATus for RX transfer */
#define USB_EP_RX_DIS                              (0x00000000UL)           /*!< EndPoint RX Disabled */
#define USB_EP_RX_STALL                            (0x00001000UL)           /*!< EndPoint RX STALLed */
#define USB_EP_RX_NAK                              (0x00002000UL)           /*!< EndPoint RX NAKed */
#define USB_EP_RX_VALID                            (0x00003000UL)           /*!< EndPoint RX VALID */

#define USB_EP_RX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
#define USB_EP_RX_ACK_DBUF                         (0x00003000UL)           /*!< ACK Double buffer mode */

#define USB_CH_RX_DIS                              (0x00000000UL)           /*!< EndPoint RX Disabled */
#define USB_CH_RX_STALL                            (0x00001000UL)           /*!< EndPoint RX STALLed */
#define USB_CH_RX_NAK                              (0x00002000UL)           /*!< Channel RX NAKed */
#define USB_CH_RX_VALID                            (0x00003000UL)           /*!< Channel RX VALID */

#define USB_CH_RX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
#define USB_CH_RX_ACK_DBUF                         (0x00003000UL)           /*!< ACK Double buffer mode */

/*! <used For Double Buffer Enable Disable */
#define USB_CHEP_DB_MSK                            (0xFFFF0F0FUL)

/*!< Buffer Descriptor Mask */
#define USB_PMA_TXBD_ADDMSK                        (0xFFFF0000UL)
#define USB_PMA_TXBD_COUNTMSK                      (0x0000FFFFUL)
#define USB_PMA_RXBD_ADDMSK                        (0xFFFF0000UL)

/*!< USB PMA SIZE */
#define USB_DRD_PMA_SIZE                           (2048U)                  /*!< USB PMA Size 2Kbyte */

#define USB_DRD_FS_EP_NBR                          (8U)                     /*!< Number of USB Device endpoints */
#define USB_DRD_FS_CH_NBR                          (8U)                     /*!< Number of USB Host channels */

/* legacy defines */
/* USB_CHEP register legacy aliases */
#define USB_CHEP_ADDR_Pos          USB_CHEP_EA_Pos
#define USB_CHEP_ADDR_Msk          USB_CHEP_EA_Msk
#define USB_CHEP_ADDR              USB_CHEP_EA

#define USB_CHEP_TX_STTX_Pos       USB_CHEP_STATTX_Pos
#define USB_CHEP_TX_STTX_Msk       USB_CHEP_STATTX_Msk
#define USB_CHEP_TX_STTX           USB_CHEP_STATTX
#define USB_EP_TX_STTX             USB_CHEP_STATTX
#define USB_CH_TX_STTX             USB_CHEP_STATTX

#define USB_CHEP_DTOG_TX_Pos       USB_CHEP_DTOGTX_Pos
#define USB_CHEP_DTOG_TX_Msk       USB_CHEP_DTOGTX_Msk
#define USB_CHEP_DTOG_TX           USB_CHEP_DTOGTX
#define USB_EP_DTOG_TX             USB_CHEP_DTOGTX
#define USB_CH_DTOG_TX             USB_CHEP_DTOGTX

#define USB_CHEP_RX_STRX_Pos       USB_CHEP_STATRX_Pos
#define USB_CHEP_RX_STRX_Msk       USB_CHEP_STATRX_Msk
#define USB_CHEP_RX_STRX           USB_CHEP_STATRX
#define USB_EP_RX_STRX             USB_CHEP_STATRX
#define USB_CH_RX_STRX             USB_CHEP_STATRX

#define USB_CHEP_DTOG_RX_Pos       USB_CHEP_DTOGRX_Pos
#define USB_CHEP_DTOG_RX_Msk       USB_CHEP_DTOGRX_Msk
#define USB_CHEP_DTOG_RX           USB_CHEP_DTOGRX
#define USB_EP_DTOG_RX             USB_CHEP_DTOGRX
#define USB_CH_DTOG_RX             USB_CHEP_DTOGRX

#define USB_CHEP_LSEP_Pos          USB_CHEP_LS_EP_Pos
#define USB_CHEP_LSEP_Msk          USB_CHEP_LS_EP_Msk
#define USB_CHEP_LSEP              USB_CHEP_LS_EP

#define USB_CHEP_ERRTX_Pos         USB_CHEP_ERR_TX_Pos
#define USB_CHEP_ERRTX_Msk         USB_CHEP_ERR_TX_Msk
#define USB_CHEP_ERRTX             USB_CHEP_ERR_TX
#define USB_EP_ERRTX               USB_CHEP_ERR_TX
#define USB_CH_ERRTX               USB_CHEP_ERR_TX

#define USB_CHEP_ERRRX_Pos         USB_CHEP_ERR_RX_Pos
#define USB_CHEP_ERRRX_Msk         USB_CHEP_ERR_RX_Msk
#define USB_CHEP_ERRRX             USB_CHEP_ERR_RX
#define USB_EP_ERRRX               USB_CHEP_ERR_RX
#define USB_CH_ERRRX               USB_CHEP_ERR_RX

#define USB_CHEP_KIND_Pos          USB_CHEP_EPKIND_Pos
#define USB_CHEP_KIND_Msk          USB_CHEP_EPKIND_Msk
#define USB_CHEP_KIND              USB_CHEP_EPKIND

/* Provide EP/CH KIND aliases based on new EPKIND field */
#define USB_EP_EPKIND              USB_CHEP_EPKIND
#define USB_CH_EPKIND              USB_CHEP_EPKIND
#define USB_EP_KIND                USB_EP_EPKIND
#define USB_CH_KIND                USB_CH_EPKIND

/* USB_CNTR register legacy aliases */
#define USB_CNTR_RESETM_Pos        USB_CNTR_RST_DCONM_Pos
#define USB_CNTR_RESETM_Msk        USB_CNTR_RST_DCONM_Msk
#define USB_CNTR_RESETM            USB_CNTR_RST_DCONM
#define USB_CNTR_DCON              USB_CNTR_RST_DCONM

/* USB_ISTR register legacy aliases */
#define USB_ISTR_RESET_Pos         USB_ISTR_RST_DCON_Pos
#define USB_ISTR_RESET_Msk         USB_ISTR_RST_DCON_Msk
#define USB_ISTR_RESET             USB_ISTR_RST_DCON
#define USB_ISTR_DCON              USB_ISTR_RST_DCON

#define USB_ISTR_LS_DCONN_Pos      USB_ISTR_LS_DCON_Pos
#define USB_ISTR_LS_DCONN_Msk      USB_ISTR_LS_DCON_Msk
#define USB_ISTR_LS_DCONN          USB_ISTR_LS_DCON

/* USB_LPMCSR register legacy aliases */
#define USB_LPMCSR_LMPEN_Pos       USB_LPMCSR_LPMEN_Pos
#define USB_LPMCSR_LMPEN_Msk       USB_LPMCSR_LPMEN_Msk
#define USB_LPMCSR_LMPEN           USB_LPMCSR_LPMEN

/* USB_BCDR register legacy aliases */
#define USB_BCDR_DPPU_Pos          USB_BCDR_DPPU_DPD_Pos
#define USB_BCDR_DPPU_Msk          USB_BCDR_DPPU_DPD_Msk
#define USB_BCDR_DPPU              USB_BCDR_DPPU_DPD
#define USB_BCDR_DPPD_Pos          USB_BCDR_DPPU_DPD_Pos
#define USB_BCDR_DPPD_Msk          USB_BCDR_DPPU_DPD_Msk
#define USB_BCDR_DPPD              USB_BCDR_DPPU_DPD

/******************************************************************************/
/*                                                                            */
/*                            Independent WATCHDOG                            */
/*                                                                            */
/******************************************************************************/

/*******************  Bit definition for IWDG_KR register  ********************/
#define IWDG_KR_KEY_Pos                     (0U)
#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)           /*!< 0x0000FFFF */
#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                         /*!<Key value (write only, read 0000h)  */

/*******************  Bit definition for IWDG_PR register  ********************/
#define IWDG_PR_PR_Pos                      (0U)
#define IWDG_PR_PR_Msk                      (0xFUL << IWDG_PR_PR_Pos)               /*!< 0x0000000F */
#define IWDG_PR_PR                          IWDG_PR_PR_Msk                          /*!<PR[3:0] (Prescaler divider)         */
#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)               /*!< 0x00000001 */
#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)               /*!< 0x00000002 */
#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)               /*!< 0x00000004 */
#define IWDG_PR_PR_3                        (0x8UL << IWDG_PR_PR_Pos)               /*!< 0x00000008 */

/*******************  Bit definition for IWDG_RLR register  *******************/
#define IWDG_RLR_RL_Pos                     (0U)
#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)            /*!< 0x00000FFF */
#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                         /*!<Watchdog counter reload value        */

/*******************  Bit definition for IWDG_SR register  ********************/
#define IWDG_SR_PVU_Pos                     (0U)
#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)              /*!< 0x00000001 */
#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                         /*!< Watchdog prescaler value update */
#define IWDG_SR_RVU_Pos                     (1U)
#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)              /*!< 0x00000002 */
#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                         /*!< Watchdog counter reload value update */
#define IWDG_SR_WVU_Pos                     (2U)
#define IWDG_SR_WVU_Msk                     (0x1UL << IWDG_SR_WVU_Pos)              /*!< 0x00000004 */
#define IWDG_SR_WVU                         IWDG_SR_WVU_Msk                         /*!< Watchdog counter window value update */
#define IWDG_SR_EWU_Pos                     (3U)
#define IWDG_SR_EWU_Msk                     (0x1UL << IWDG_SR_EWU_Pos)              /*!< 0x00000008 */
#define IWDG_SR_EWU                         IWDG_SR_EWU_Msk                         /*!< Watchdog interrupt comparator value update */
#define IWDG_SR_ONF_Pos                     (8U)
#define IWDG_SR_ONF_Msk                     (0x1UL << IWDG_SR_ONF_Pos)              /*!< 0x00000100 */
#define IWDG_SR_ONF                         IWDG_SR_ONF_Msk                         /*!< Watchdog enable flag */
#define IWDG_SR_EWIF_Pos                    (15U)
#define IWDG_SR_EWIF_Msk                    (0x1UL << IWDG_SR_EWIF_Pos)             /*!< 0x00004000 */
#define IWDG_SR_EWIF                        IWDG_SR_EWIF_Msk                        /*!< Watchdog early interrupt flag */

/******************  Bit definition for IWDG_WINR register  *******************/
#define IWDG_WINR_WIN_Pos                   (0U)
#define IWDG_WINR_WIN_Msk                   (0xFFFUL << IWDG_WINR_WIN_Pos)          /*!< 0x00000FFF */
#define IWDG_WINR_WIN                       IWDG_WINR_WIN_Msk                       /*!< Watchdog counter window value */

/******************  Bit definition for IWDG_EWCR register  *******************/
#define IWDG_EWCR_EWIT_Pos                  (0U)
#define IWDG_EWCR_EWIT_Msk                  (0xFFFUL << IWDG_EWCR_EWIT_Pos)         /*!< 0x00000FFF */
#define IWDG_EWCR_EWIT                      IWDG_EWCR_EWIT_Msk                      /*!< Watchdog early wakeup comparator value */
#define IWDG_EWCR_EWIE_Pos                  (15U)
#define IWDG_EWCR_EWIE_Msk                  (0x1UL << IWDG_EWCR_EWIE_Pos)           /*!< 0x00000FFF */
#define IWDG_EWCR_EWIE                      IWDG_EWCR_EWIE_Msk                      /*!< Watchdog early wakeup comparator value */

/******************  Bit definition for IWDG_ICR register  *******************/
#define IWDG_ICR_EWIC_Pos              (15U)
#define IWDG_ICR_EWIC_Msk              (0x1UL << IWDG_ICR_EWIC_Pos)                  /*!< 0x00008000 */
#define IWDG_ICR_EWIC                  IWDG_ICR_EWIC_Msk                             /*!< Watchdog early interrupt acknowledge */

/******************************************************************************/
/*                                                                            */
/*                              Window WATCHDOG                               */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for WWDG_CR register  ********************/
#define WWDG_CR_T_Pos                       (0U)
#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)               /*!< 0x0000007F */
#define WWDG_CR_T                           WWDG_CR_T_Msk                           /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)               /*!< 0x00000001 */
#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)               /*!< 0x00000002 */
#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)               /*!< 0x00000004 */
#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)               /*!< 0x00000008 */
#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)               /*!< 0x00000010 */
#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)               /*!< 0x00000020 */
#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)               /*!< 0x00000040 */
#define WWDG_CR_WDGA_Pos                    (7U)
#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)             /*!< 0x00000080 */
#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                        /*!<Activation bit */

/*******************  Bit definition for WWDG_CFR register  *******************/
#define WWDG_CFR_W_Pos                      (0U)
#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)              /*!< 0x0000007F */
#define WWDG_CFR_W                          WWDG_CFR_W_Msk                          /*!<W[6:0] bits (7-bit window value) */
#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)              /*!< 0x00000001 */
#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)              /*!< 0x00000002 */
#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)              /*!< 0x00000004 */
#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)              /*!< 0x00000008 */
#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)              /*!< 0x00000010 */
#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)              /*!< 0x00000020 */
#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)              /*!< 0x00000040 */
#define WWDG_CFR_WDGTB_Pos                  (11U)
#define WWDG_CFR_WDGTB_Msk                  (0x7UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00003800 */
#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                      /*!<WDGTB[2:0] bits (Timer Base) */
#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00000800 */
#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00001000 */
#define WWDG_CFR_WDGTB_2                    (0x4UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00002000 */
#define WWDG_CFR_EWI_Pos                    (9U)
#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)             /*!< 0x00000200 */
#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                        /*!<Early Wakeup Interrupt */

/*******************  Bit definition for WWDG_SR register  ********************/
#define WWDG_SR_EWIF_Pos                    (0U)
#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)             /*!< 0x00000001 */
#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                        /*!<Early Wakeup Interrupt Flag */


/** @addtogroup STM32C5xx_Peripheral_Exported_macros
  * @{
  */

/******************************* AES Instances ********************************/
#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)

/******************************* ADC Instances ********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) \
                                       || ((INSTANCE) == ADC2))

#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)

/* Select the ADC common instance to which belongs the selected ADC instance */
#define ADC_COMMON_INSTANCE(adc_instance) (ADC12_COMMON)

/* Select the ADC multimode instance master corresponding to the selected ADC instance */
#define ADC_MULTI_INSTANCE_MASTER(adc_instance) (((adc_instance) == ADC2) ? (ADC1) : (adc_instance))

/******************************* COMP Instances *******************************/
#define IS_COMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)

/****************************** CORDIC Instances ******************************/
#define IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC)

/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

/******************************* CRS Instances ********************************/
#define IS_CRS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRS)

/*************************************** DAC Instances *******************************/
#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)

/******************************** DMA Instances *******************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == LPDMA1_CH0)  || \
                                       ((INSTANCE) == LPDMA1_CH1)  || \
                                       ((INSTANCE) == LPDMA1_CH2)  || \
                                       ((INSTANCE) == LPDMA1_CH3)  || \
                                       ((INSTANCE) == LPDMA1_CH4)  || \
                                       ((INSTANCE) == LPDMA1_CH5)  || \
                                       ((INSTANCE) == LPDMA1_CH6)  || \
                                       ((INSTANCE) == LPDMA1_CH7)  || \
                                       ((INSTANCE) == LPDMA2_CH0)  || \
                                       ((INSTANCE) == LPDMA2_CH1)  || \
                                       ((INSTANCE) == LPDMA2_CH2)  || \
                                       ((INSTANCE) == LPDMA2_CH3))

#define IS_LPDMA1_INSTANCE(INSTANCE)   (((INSTANCE) == LPDMA1_CH0)  || \
                                        ((INSTANCE) == LPDMA1_CH1)  || \
                                        ((INSTANCE) == LPDMA1_CH2)  || \
                                        ((INSTANCE) == LPDMA1_CH3)  || \
                                        ((INSTANCE) == LPDMA1_CH4)  || \
                                        ((INSTANCE) == LPDMA1_CH5)  || \
                                        ((INSTANCE) == LPDMA1_CH6)  || \
                                        ((INSTANCE) == LPDMA1_CH7))

#define IS_LPDMA2_INSTANCE(INSTANCE)   (((INSTANCE) == LPDMA2_CH0)  || \
                                        ((INSTANCE) == LPDMA2_CH1)  || \
                                        ((INSTANCE) == LPDMA2_CH2)  || \
                                        ((INSTANCE) == LPDMA2_CH3))

#define IS_DMA_PFREQ_INSTANCE(INSTANCE)   (((INSTANCE) == LPDMA1_CH0)  || \
                                           ((INSTANCE) == LPDMA1_CH7)  || \
                                           ((INSTANCE) == LPDMA2_CH0)  || \
                                           ((INSTANCE) == LPDMA2_CH3))

/* ************************************************* FLASH Instances ************************************************ */
#define IS_FLASH_INSTANCE(INSTANCE)    (((INSTANCE) == FLASH))

/* ************************************************* FDCAN Instances ************************************************ */
#define IS_FDCAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN1)

#define FDCAN_MULTI_INSTANCE_CONFIG(INSTANCE) (IS_FDCAN_ALL_INSTANCE(INSTANCE) ? \
                                               (FDCAN_CONFIG) : (NULL))


/* ************************************************* GPIO Instances ************************************************* */
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA)     \
                                        || ((INSTANCE) == GPIOB)  \
                                        || ((INSTANCE) == GPIOC)  \
                                        || ((INSTANCE) == GPIOD)  \
                                        || ((INSTANCE) == GPIOE)  \
                                        || ((INSTANCE) == GPIOH))

/**************************** HASH Instances ********************************/
#define IS_HASH_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HASH)

/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
                                       ((INSTANCE) == I2C2))
/****************** I2C Instances : wakeup capability from stop modes *********/
#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)

/******************************** SMBUS Instances *******************************/
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
                                         ((INSTANCE) == I2C2))

/******************************** I3C Instances *******************************/
#define IS_I3C_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == I3C1))

/****************************** ICACHE Instances ******************************/
#define IS_ICACHE_ALL_INSTANCE(INSTANCE)    (((INSTANCE) == ICACHE))

/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == IWDG))

/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)

/******************** LPUART Instance *****************************************/
#define IS_LPUART_INSTANCE(INSTANCE)    (((INSTANCE) == LPUART1))


/* *************************************************** RAMCFG Instances ********************************************* */
#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1)  || ((INSTANCE) == RAMCFG_SRAM2))

/* ********************************************* RAMCFG Mass Erase Instances **************************************** */
#define IS_RAMCFG_MASS_ERASE_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1)  || ((INSTANCE) == RAMCFG_SRAM2))

/* ********************************************* RAMCFG ECC Instances *********************************************** */
#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) ((INSTANCE) == RAMCFG_SRAM2)

/* ****************************************** RAMCFG Write Protection Instances ************************************* */
#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1)  || ((INSTANCE) == RAMCFG_SRAM2))

/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)

/******************************* RTC Instances ********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE)   ((INSTANCE) == RTC)

/******************************** LPTIM Instances *****************************/
#define IS_LPTIM_INSTANCE(INSTANCE)     ((INSTANCE) == LPTIM1)

/****************** LPTIM Instances : DMA supported instances *****************/
#define IS_LPTIM_DMA_INSTANCE(INSTANCE)  ((INSTANCE) == LPTIM1)

/************* LPTIM Instances : at least 1 capture/compare channel ***********/
#define IS_LPTIM_CC1_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)

/************* LPTIM Instances : at least 2 capture/compare channel ***********/
#define IS_LPTIM_CC2_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)

/****************** LPTIM Instances : supporting encoder interface ************/
#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  ((INSTANCE) == LPTIM1)

/****************** LPTIM Instances : supporting Input Capture ****************/
#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE)  ((INSTANCE) == LPTIM1)

/****************** LPTIM Instances : supporting Input1 ***********************/
#define IS_LPTIM_INPUT1_INSTANCE(INSTANCE)  ((INSTANCE) == LPTIM1)

/******************************* SPI Instances ********************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE)     (((INSTANCE) == SPI1) || \
                                           ((INSTANCE) == SPI2) || \
                                           ((INSTANCE) == SPI3))

/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \
                                         ((INSTANCE) == SPI2) || \
                                         ((INSTANCE) == SPI3))

/***************************** TAMP Instances  ********************************/
#define IS_TAMP_INSTANCE(INSTANCE)  ((INSTANCE) == TAMP)

/****************** TIM Instances : All supported instances *******************/
#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)  || \
                                         ((INSTANCE) == TIM2)  || \
                                         ((INSTANCE) == TIM5)  || \
                                         ((INSTANCE) == TIM6)  || \
                                         ((INSTANCE) == TIM7)  || \
                                         ((INSTANCE) == TIM8)  || \
                                         ((INSTANCE) == TIM12) || \
                                         ((INSTANCE) == TIM15) || \
                                         ((INSTANCE) == TIM16) || \
                                         ((INSTANCE) == TIM17))
/****************** TIM Instances : supporting 32 bits counter ****************/
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
                                               ((INSTANCE) == TIM5))
/****************** TIM Instances : supporting the break function *************/
#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
                                            ((INSTANCE) == TIM8)  || \
                                            ((INSTANCE) == TIM15) || \
                                            ((INSTANCE) == TIM16) || \
                                            ((INSTANCE) == TIM17))
/************** TIM Instances : supporting Break source selection *************/
#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
                                               ((INSTANCE) == TIM8)  || \
                                               ((INSTANCE) == TIM15) || \
                                               ((INSTANCE) == TIM16) || \
                                               ((INSTANCE) == TIM17))
/****************** TIM Instances : supporting 2 break inputs *****************/
#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
                                            ((INSTANCE) == TIM8))

/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
                                         ((INSTANCE) == TIM2)  || \
                                         ((INSTANCE) == TIM5)  || \
                                         ((INSTANCE) == TIM8)  || \
                                         ((INSTANCE) == TIM12) || \
                                         ((INSTANCE) == TIM15) || \
                                         ((INSTANCE) == TIM16) || \
                                         ((INSTANCE) == TIM17))
/************ TIM Instances : at least 2 capture/compare channels *************/
#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
                                         ((INSTANCE) == TIM2)  || \
                                         ((INSTANCE) == TIM5)  || \
                                         ((INSTANCE) == TIM8)  || \
                                         ((INSTANCE) == TIM12) || \
                                         ((INSTANCE) == TIM15))
/************ TIM Instances : at least 3 capture/compare channels *************/
#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
                                         ((INSTANCE) == TIM2)  || \
                                         ((INSTANCE) == TIM5)  || \
                                         ((INSTANCE) == TIM8))
/************ TIM Instances : at least 4 capture/compare channels *************/
#define IS_TIM_CC4_INSTANCE(INSTANCE)   IS_TIM_CC3_INSTANCE(INSTANCE)

/****************** TIM Instances : at least 5 capture/compare channels *******/
#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
                                         ((INSTANCE) == TIM8))

/****************** TIM Instances : at least 6 capture/compare channels *******/
#define IS_TIM_CC6_INSTANCE(INSTANCE)   IS_TIM_CC5_INSTANCE(INSTANCE)

/****************** TIM Instances : at least 7 capture/compare channels *******/
#define IS_TIM_CC7_INSTANCE(INSTANCE)   IS_TIM_CC6_INSTANCE(INSTANCE)

/****** TIM Instances : at least 1 capture/compare complementary channel ******/
#define IS_TIM_CC1N_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
                                         ((INSTANCE) == TIM8)  || \
                                         ((INSTANCE) == TIM15) || \
                                         ((INSTANCE) == TIM16) || \
                                         ((INSTANCE) == TIM17))
/****** TIM Instances : at least 2 capture/compare complementary channel ******/
#define IS_TIM_CC2N_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
                                         ((INSTANCE) == TIM8))

/****** TIM Instances : at least 3 capture/compare complementary channel ******/
#define IS_TIM_CC3N_INSTANCE(INSTANCE) IS_TIM_CC2N_INSTANCE(INSTANCE)

/****** TIM Instances : at least 4 capture/compare complementary channel ******/
#define IS_TIM_CC4N_INSTANCE(INSTANCE) IS_TIM_CC3N_INSTANCE(INSTANCE)

/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
                                            ((INSTANCE) == TIM2)  || \
                                            ((INSTANCE) == TIM5)  || \
                                            ((INSTANCE) == TIM6)  || \
                                            ((INSTANCE) == TIM7)  || \
                                            ((INSTANCE) == TIM8)  || \
                                            ((INSTANCE) == TIM15) || \
                                            ((INSTANCE) == TIM16) || \
                                            ((INSTANCE) == TIM17))
/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
                                            ((INSTANCE) == TIM2)  || \
                                            ((INSTANCE) == TIM5)  || \
                                            ((INSTANCE) == TIM8)  || \
                                            ((INSTANCE) == TIM15) || \
                                            ((INSTANCE) == TIM16) || \
                                            ((INSTANCE) == TIM17))
/******************** TIM Instances : DMA burst feature ***********************/
#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
                                            ((INSTANCE) == TIM2)  || \
                                            ((INSTANCE) == TIM5)  || \
                                            ((INSTANCE) == TIM8)  || \
                                            ((INSTANCE) == TIM15) || \
                                            ((INSTANCE) == TIM16) || \
                                            ((INSTANCE) == TIM17))
/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
                                                    ((INSTANCE) == TIM2)  || \
                                                    ((INSTANCE) == TIM5)  || \
                                                    ((INSTANCE) == TIM8)  || \
                                                    ((INSTANCE) == TIM12) || \
                                                    ((INSTANCE) == TIM15) || \
                                                    ((INSTANCE) == TIM16) || \
                                                    ((INSTANCE) == TIM17))
/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
                                                     ((INSTANCE) == TIM8)  || \
                                                     ((INSTANCE) == TIM15) || \
                                                     ((INSTANCE) == TIM16) || \
                                                     ((INSTANCE) == TIM17))
/****************** TIM Instances : supporting counting mode selection ********/
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
                                                        ((INSTANCE) == TIM2)  || \
                                                        ((INSTANCE) == TIM5)  || \
                                                        ((INSTANCE) == TIM8)  || \
                                                        ((INSTANCE) == TIM15) || \
                                                        ((INSTANCE) == TIM16) || \
                                                        ((INSTANCE) == TIM17))
/****************** TIM Instances : supporting encoder interface **************/
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
                                                      ((INSTANCE) == TIM2)  || \
                                                      ((INSTANCE) == TIM5)  || \
                                                      ((INSTANCE) == TIM8)  || \
                                                      ((INSTANCE) == TIM15))
/**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
                                            ((INSTANCE) == TIM2)  || \
                                            ((INSTANCE) == TIM5)  || \
                                            ((INSTANCE) == TIM8))
/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
                                            ((INSTANCE) == TIM2)  || \
                                            ((INSTANCE) == TIM5)  || \
                                            ((INSTANCE) == TIM6)  || \
                                            ((INSTANCE) == TIM7)  || \
                                            ((INSTANCE) == TIM8)  || \
                                            ((INSTANCE) == TIM12) || \
                                            ((INSTANCE) == TIM15))
/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
                                            ((INSTANCE) == TIM2)  || \
                                            ((INSTANCE) == TIM5)  || \
                                            ((INSTANCE) == TIM8)  || \
                                            ((INSTANCE) == TIM12) || \
                                            ((INSTANCE) == TIM15))
/****************** TIM Instances : supporting OCxREF clear *******************/
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1)  || \
                                                       ((INSTANCE) == TIM2)  || \
                                                       ((INSTANCE) == TIM5)  || \
                                                       ((INSTANCE) == TIM8)  || \
                                                       ((INSTANCE) == TIM15) || \
                                                       ((INSTANCE) == TIM16) || \
                                                       ((INSTANCE) == TIM17))
/**************** TIM Instances : supporting 16 bits repetition counter *******/
#define IS_TIM_16B_REPETITION_COUNTER_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
                                                             ((INSTANCE) == TIM8))

/**************** TIM Instances : supporting 8 bits repetition counter ********/
#define IS_TIM_8B_REPETITION_COUNTER_INSTANCE(INSTANCE)     (((INSTANCE) == TIM15) || \
                                                             ((INSTANCE) == TIM16) || \
                                                             ((INSTANCE) == TIM17))
/****************** TIM Instances : supporting repetition counter *************/
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)   (IS_TIM_16B_REPETITION_COUNTER_INSTANCE(INSTANCE) || \
                                                        IS_TIM_8B_REPETITION_COUNTER_INSTANCE(INSTANCE))

/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1) || \
                                            ((INSTANCE) == TIM8))

/******************* TIM Instances : Timer input XOR function *****************/
#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
                                            ((INSTANCE) == TIM2)  || \
                                            ((INSTANCE) == TIM5)  || \
                                            ((INSTANCE) == TIM8)  || \
                                            ((INSTANCE) == TIM12) || \
                                            ((INSTANCE) == TIM15))

/* *********************************************** TIM APB1 Instances *********************************************** */
#define IS_TIM_APB1_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)   || \
                                             ((INSTANCE) == TIM5)   || \
                                             ((INSTANCE) == TIM6)   || \
                                             ((INSTANCE) == TIM7)   || \
                                             ((INSTANCE) == TIM12))

/* *********************************************** TIM APB2 Instances *********************************************** */
#define IS_TIM_APB2_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
                                             ((INSTANCE) == TIM8)   || \
                                             ((INSTANCE) == TIM15)  || \
                                             ((INSTANCE) == TIM16)  || \
                                             ((INSTANCE) == TIM17))

/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1)  || \
                                     ((INSTANCE) == USART2)  || \
                                     ((INSTANCE) == USART3))

/******************** UART Instances : Asynchronous mode **********************/
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1)  || \
                                    ((INSTANCE) == USART2)  || \
                                    ((INSTANCE) == USART3)  || \
                                    ((INSTANCE) == UART4)   || \
                                    ((INSTANCE) == UART5))

/*********************** UART Instances : FIFO mode ***************************/
#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1)  || \
                                         ((INSTANCE) == USART2)  || \
                                         ((INSTANCE) == USART3)  || \
                                         ((INSTANCE) == UART4)   || \
                                         ((INSTANCE) == UART5)   || \
                                         ((INSTANCE) == LPUART1))

/*********************** UART Instances : SPI Slave mode **********************/
#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1)  || \
                                              ((INSTANCE) == USART2)  || \
                                              ((INSTANCE) == USART3))

/****************** UART Instances : Auto Baud Rate detection ****************/
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1)  || \
                                                            ((INSTANCE) == USART2)  || \
                                                            ((INSTANCE) == USART3)  || \
                                                            ((INSTANCE) == UART4)   || \
                                                            ((INSTANCE) == UART5))

/****************** UART Instances : Driver Enable *****************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1)  || \
                                                      ((INSTANCE) == USART2)  || \
                                                      ((INSTANCE) == USART3)  || \
                                                      ((INSTANCE) == UART4)   || \
                                                      ((INSTANCE) == UART5)   || \
                                                      ((INSTANCE) == LPUART1))

/******************** UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1)  || \
                                                 ((INSTANCE) == USART2)  || \
                                                 ((INSTANCE) == USART3)  || \
                                                 ((INSTANCE) == UART4)   || \
                                                 ((INSTANCE) == UART5)   || \
                                                 ((INSTANCE) == LPUART1))

/****************** UART Instances : Hardware Flow control ********************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1)  || \
                                           ((INSTANCE) == USART2)  || \
                                           ((INSTANCE) == USART3)  || \
                                           ((INSTANCE) == UART4)   || \
                                           ((INSTANCE) == UART5)   || \
                                           ((INSTANCE) == LPUART1))

/* **************************************  UART Instances : Receiver timeout **************************************** */
#define IS_UART_RECEIVER_TIMEOUT_INSTANCE(INSTANCE)   (((INSTANCE) == USART1)  || \
                                                       ((INSTANCE) == USART2)  || \
                                                       ((INSTANCE) == USART3)  || \
                                                       ((INSTANCE) == UART4)   || \
                                                       ((INSTANCE) == UART5))

/******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1)  || \
                                          ((INSTANCE) == USART2)  || \
                                          ((INSTANCE) == USART3)  || \
                                          ((INSTANCE) == UART4)   || \
                                          ((INSTANCE) == UART5))

/******************** UART Instances : Wake-up from Stop mode **********************/
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1)  || \
                                                      ((INSTANCE) == USART2)  || \
                                                      ((INSTANCE) == USART3)  || \
                                                      ((INSTANCE) == UART4)   || \
                                                      ((INSTANCE) == UART5)   || \
                                                      ((INSTANCE) == LPUART1))

/*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1)  || \
                                    ((INSTANCE) == USART2)  || \
                                    ((INSTANCE) == USART3)  || \
                                    ((INSTANCE) == UART4)   || \
                                    ((INSTANCE) == UART5))

/********************* USART Instances : Smard card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1)  || \
                                         ((INSTANCE) == USART2)  || \
                                         ((INSTANCE) == USART3))

/******************************* USB DRD FS HCD Instances *********************/
#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_DRD_FS)

/******************************* USB DRD FS PCD Instances *********************/
#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_DRD_FS)

/** @} */ /* End of group STM32C5xx_Peripheral_Exported_macros */

/** @} */ /* End of group STM32C562xx */

/** @} */ /* End of group ST */

#ifdef __cplusplus
}
#endif

#endif  /* STM32C562xx_H */
