library ieee; use ieee.std_logic_1164.all; entity upcount is port( resb : in std_logic; pulse : in std_logic; down : in std_logic; O : out std_logic_vector(3 downto 0) ); end upcount; architecture behav of upcount is signal counter : std_logic_vector(3 downto 0); signal wires : std_logic_vector(3 downto 0); signal down_int : std_logic; signal switch : std_logic; begin wires(3 downto 1) <= not(counter(2 downto 0)) when down_int = '0' else counter(2 downto 0); wires(0) <= pulse; -- es sollen nur steigende Pulseflanken ausgewertet werden -- asynchroner Counter count_i : for i in 0 to 3 generate process(resb, wires) begin if resb = '0' then counter(i) <= '0'; elsif rising_edge(wires(i)) then if switch = '0' then -- Unterdrückung bei Up/Down-Umschaltung counter(i) <= not(counter(i)); end if; end if; end process; end generate; -- zusätzliche Logic für das saubere Umschalten zwischen Up und Down -- die Rückschaltung von switch ist von pulse (wires(0)) abhängig process(resb, pulse, down, down_int) begin if resb = '0' then down_int <= '0'; switch <= '0'; elsif down /= down_int then down_int <= down; switch <= '1'; elsif rising_edge(pulse) then -- pulse == wires(0) switch <= '0'; end if; end process; O <= counter; end behav;