00001 /************************************************************************* 00002 Author: $Author: dennis $ 00003 File: $HeadURL: file:///home/dennis/svn-store/avr-source/mptry-1/spi.c $ 00004 Date: $Date: 2008-09-06 10:51:00 +0200 (Sa, 06 Sep 2008) $ 00005 Revision: $Revision: 94 $ 00006 Id: $Id: spi.c 94 2008-09-06 08:51:00Z dennis $ 00007 Licence: GNU General Public License 00008 *************************************************************************/ 00009 00010 #include "vs1011.h" 00011 #include "spi.h" 00012 00013 #include "delay.h" 00014 #include <util/delay.h> 00015 00016 /* SCI read write values */ 00017 #define VS_WRITE 0x02 00018 #define VS_READ 0x03 00019 00020 /* SCI register addresses */ 00021 #define SCI_MODE 0x00 00022 #define SCI_STATUS 0x01 00023 #define SCI_BASS 0x02 00024 #define SCI_CLOCKF 0x03 00025 #define SCI_DECODE_TIME 0x04 00026 #define SCI_HDAT0 0x08 00027 #define SCI_HDAT0 0x09 00028 #define SCI_VOL 0x0b 00029 00030 /* SCI_MODE register bit names */ 00031 #define SM_DIFF 0 00032 #define SM_LAYER12 1 00033 #define SM_RESET 2 00034 #define SM_OUTOFWAV 3 00035 #define SM_SETTOZERO1 4 00036 #define SM_TESTS 5 00037 #define SM_STREAM 6 00038 #define SM_SETTOZERO2 7 00039 #define SM_DACT 8 00040 #define SM_SDIORD 9 00041 #define SM_SDISHARE 10 00042 #define SM_SDINEW 11 00043 #define SM_SETTOZERO3 12 00044 #define SM_SETTOZERO4 13 00045 00046 00053 uint8_t vs1011_port_init( void ) { 00054 DDRA &= ~(1 << VS1011_DREQ); // input 00055 DDRA |= (1 << VS1011_XCS); // output 00056 DDRA |= (1 << VS1011_XRESET); // output 00057 #ifdef NON_SHARED 00058 // for non shared, XDCS is also uses 00059 DDRA |= (1 << VS1011_XDCS); 00060 #endif 00061 return 0; 00062 } 00063 00064 static void _vs1011_init( void ) { 00065 // set clock value 00066 vs1011_xcs_select(); 00067 spi_write_byte(VS_WRITE); 00068 spi_write_byte(SCI_CLOCKF); 00069 spi_write_byte(0x98); // 12.288 Mhz and clock doubler 00070 spi_write_byte(0x00); 00071 vs1011_xcs_deselect(); 00072 00073 // set operating mode 00074 vs1011_xcs_select(); 00075 spi_write_byte(VS_WRITE); 00076 spi_write_byte(SCI_MODE); 00077 //spi_write_byte(0x0c); // SM_SDINEW + SM_SDISHARE 00078 spi_write_byte(0x08); // SM_SDINEW 00079 spi_write_byte(0x00); // 00080 vs1011_xcs_deselect(); // end SCI cycle 00081 } 00082 00089 uint8_t vs1011_sw_reset( void ) { 00090 00091 //uart_puts("before sw init vs\n\r"); 00092 vs1011_xcs_select(); 00093 spi_write_byte(VS_WRITE); 00094 spi_write_byte(SCI_MODE); // address mode register 00095 spi_write_byte(0x00); 00096 spi_write_byte(1 << SM_RESET); 00097 vs1011_xcs_deselect(); 00098 00099 // wait until DREQ goes high 00100 loop_until_bit_is_set(PINA,VS1011_DREQ); 00101 //uart_puts("after sw init vs\n\r"); 00102 00103 _vs1011_init(); 00104 00105 return 0; 00106 } 00107 00114 uint8_t vs1011_init( void ) { 00115 00116 // clear xreset pin -> hardware reset 00117 PORTA &= ~(1 << VS1011_XRESET); 00118 // set xreset pin -> vs1011 will go out of hardware reset state 00119 PORTA |= (1 << VS1011_XRESET); 00120 00121 // wait until DREQ goes high 00122 loop_until_bit_is_set(PINA,VS1011_DREQ); 00123 00124 _vs1011_init(); 00125 00126 return 0; 00127 } 00128 00134 void vs1011_xcs_select( void ) { 00135 PORTA &= ~(1 << VS1011_XCS); 00136 } 00137 00143 void vs1011_xcs_deselect( void ) { 00144 PORTA |= (1 << VS1011_XCS); 00145 } 00146 00152 void vs1011_xdcs_select( void ) { 00153 PORTA &= ~(1 << VS1011_XDCS); // activate XDCS 00154 } 00155 00161 void vs1011_xdcs_deselect( void ) { 00162 PORTA |= (1 << VS1011_XDCS); 00163 } 00164 00172 uint8_t vs1011_dim_volume( uint8_t v ) { 00173 // write volume value ; the lower the louder, 0xff is quiet! 00174 vs1011_xcs_select(); 00175 spi_write_byte(VS_WRITE); 00176 spi_write_byte(SCI_VOL); 00177 spi_write_byte(v); // left 00178 spi_write_byte(v); // right 00179 vs1011_xcs_deselect(); 00180 00181 return 0; 00182 } 00183 00184 uint8_t vs1011_test_vol( void ) { 00185 //uart_puts("before vol vs\n\r"); 00186 for (;;) { 00187 // test routine 00188 vs1011_xcs_select(); 00189 spi_write_byte(VS_WRITE); 00190 spi_write_byte(SCI_VOL); 00191 spi_write_byte(0x00); 00192 spi_write_byte(0x00); 00193 vs1011_xcs_deselect(); 00194 _delay_loop_2(1000); 00195 00196 vs1011_xcs_select(); 00197 spi_write_byte(VS_WRITE); 00198 spi_write_byte(SCI_VOL); 00199 spi_write_byte(0xff); 00200 spi_write_byte(0xff); 00201 vs1011_xcs_deselect(); 00202 _delay_loop_2(1000); 00203 } 00204 return 0; 00205 } 00206 00207 00208 uint8_t vs1011_test_vol_rw( void ) { 00209 uint8_t b; 00210 00211 // write volume value 0xa2, 0xf5 00212 vs1011_xcs_select(); 00213 spi_write_byte(VS_WRITE); 00214 spi_write_byte(SCI_VOL); 00215 spi_write_byte(0xa2); 00216 spi_write_byte(0xf5); 00217 vs1011_xcs_deselect(); 00218 00219 // try to read back volume value; should be 0xa2, 0xf5 00220 vs1011_xcs_select(); 00221 spi_write_byte(VS_READ); 00222 spi_write_byte(SCI_VOL); 00223 b = spi_write_byte(0x00); 00224 uart_putc_hex(b); 00225 b = spi_write_byte(0x00); 00226 uart_putc_hex(b); 00227 vs1011_xcs_deselect(); 00228 return 0; 00229 } 00230 00231 uint8_t vs1011_test_sine_on_off( void ) { 00232 vs1011_xcs_select(); // start SCI cycle 00233 spi_write_byte(VS_WRITE); 00234 spi_write_byte(SCI_MODE); 00235 #ifdef NON_SHARED 00236 spi_write_byte(0x08); // SD_SDINEW 00237 spi_write_byte(1<<SM_TESTS); // SM_TESTS 00238 vs1011_xcs_deselect(); // end SCI cycle 00239 PORTA &= ~(1 << VS1011_XDCS); // activate XDCS 00240 #else 00241 00242 spi_write_byte(0x0c); // SM_SDINEW + SM_SDISHARE 00243 spi_write_byte(1<<SM_TESTS); // SM_TESTS 00244 vs1011_xcs_deselect(); // end SCI cycle 00245 #endif 00246 00247 for (;;) { 00248 //uart_puts("sine on\n\r"); 00249 spi_write_byte(0x53); 00250 spi_write_byte(0xef); 00251 spi_write_byte(0x6e); 00252 spi_write_byte(0x44); 00253 spi_write_byte(0x00); 00254 spi_write_byte(0x00); 00255 spi_write_byte(0x00); 00256 spi_write_byte(0x00); 00257 dd_delay(10); 00258 00259 //uart_puts("sine off\n\r"); 00260 spi_write_byte(0x45); 00261 spi_write_byte(0x78); 00262 spi_write_byte(0x69); 00263 spi_write_byte(0x74); 00264 spi_write_byte(0x00); 00265 spi_write_byte(0x00); 00266 spi_write_byte(0x00); 00267 spi_write_byte(0x00); 00268 dd_delay(10); 00269 } 00270 return 0; 00271 }