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00026 #include <avr/io.h>
00027 #include <avr/interrupt.h>
00028
00029 #include <avr/pgmspace.h>
00030 #include "uart.h"
00031
00032
00033
00034
00035
00036
00037
00038 #define UART_RX_BUFFER_MASK ( UART_RX_BUFFER_SIZE - 1)
00039 #define UART_TX_BUFFER_MASK ( UART_TX_BUFFER_SIZE - 1)
00040
00041 #if ( UART_RX_BUFFER_SIZE & UART_RX_BUFFER_MASK )
00042 #error RX buffer size is not a power of 2
00043 #endif
00044 #if ( UART_TX_BUFFER_SIZE & UART_TX_BUFFER_MASK )
00045 #error TX buffer size is not a power of 2
00046 #endif
00047
00048 #if defined(__AVR_AT90S2313__) \
00049 || defined(__AVR_AT90S4414__) || defined(__AVR_AT90S4434__) \
00050 || defined(__AVR_AT90S8515__) || defined(__AVR_AT90S8535__) \
00051 || defined(__AVR_ATmega103__)
00052
00053 #define AT90_UART
00054 #define UART0_RECEIVE_INTERRUPT SIG_UART_RECV
00055 #define UART0_TRANSMIT_INTERRUPT SIG_UART_DATA
00056 #define UART0_STATUS USR
00057 #define UART0_CONTROL UCR
00058 #define UART0_DATA UDR
00059 #define UART0_UDRIE UDRIE
00060 #elif defined(__AVR_AT90S2333__) || defined(__AVR_AT90S4433__)
00061
00062 #define AT90_UART
00063 #define UART0_RECEIVE_INTERRUPT SIG_UART_RECV
00064 #define UART0_TRANSMIT_INTERRUPT SIG_UART_DATA
00065 #define UART0_STATUS UCSRA
00066 #define UART0_CONTROL UCSRB
00067 #define UART0_DATA UDR
00068 #define UART0_UDRIE UDRIE
00069 #elif defined(__AVR_ATmega8__) || defined(__AVR_ATmega16__) || defined(__AVR_ATmega32__) \
00070 || defined(__AVR_ATmega8515__) || defined(__AVR_ATmega8535__) \
00071 || defined(__AVR_ATmega323__)
00072
00073 #define ATMEGA_USART
00074 #define UART0_RECEIVE_INTERRUPT SIG_UART_RECV
00075 #define UART0_TRANSMIT_INTERRUPT SIG_UART_DATA
00076 #define UART0_STATUS UCSRA
00077 #define UART0_CONTROL UCSRB
00078 #define UART0_DATA UDR
00079 #define UART0_UDRIE UDRIE
00080 #elif defined(__AVR_ATmega163__)
00081
00082 #define ATMEGA_UART
00083 #define UART0_RECEIVE_INTERRUPT SIG_UART_RECV
00084 #define UART0_TRANSMIT_INTERRUPT SIG_UART_DATA
00085 #define UART0_STATUS UCSRA
00086 #define UART0_CONTROL UCSRB
00087 #define UART0_DATA UDR
00088 #define UART0_UDRIE UDRIE
00089 #elif defined(__AVR_ATmega162__)
00090
00091 #define ATMEGA_USART0
00092 #define ATMEGA_USART1
00093 #define UART0_RECEIVE_INTERRUPT SIG_USART0_RECV
00094 #define UART1_RECEIVE_INTERRUPT SIG_USART1_RECV
00095 #define UART0_TRANSMIT_INTERRUPT SIG_USART0_DATA
00096 #define UART1_TRANSMIT_INTERRUPT SIG_USART1_DATA
00097 #define UART0_STATUS UCSR0A
00098 #define UART0_CONTROL UCSR0B
00099 #define UART0_DATA UDR0
00100 #define UART0_UDRIE UDRIE0
00101 #define UART1_STATUS UCSR1A
00102 #define UART1_CONTROL UCSR1B
00103 #define UART1_DATA UDR1
00104 #define UART1_UDRIE UDRIE1
00105 #elif defined(__AVR_ATmega64__) || defined(__AVR_ATmega128__)
00106
00107 #define ATMEGA_USART0
00108 #define ATMEGA_USART1
00109 #define UART0_RECEIVE_INTERRUPT SIG_UART0_RECV
00110 #define UART1_RECEIVE_INTERRUPT SIG_UART1_RECV
00111 #define UART0_TRANSMIT_INTERRUPT SIG_UART0_DATA
00112 #define UART1_TRANSMIT_INTERRUPT SIG_UART1_DATA
00113 #define UART0_STATUS UCSR0A
00114 #define UART0_CONTROL UCSR0B
00115 #define UART0_DATA UDR0
00116 #define UART0_UDRIE UDRIE0
00117 #define UART1_STATUS UCSR1A
00118 #define UART1_CONTROL UCSR1B
00119 #define UART1_DATA UDR1
00120 #define UART1_UDRIE UDRIE1
00121 #elif defined(__AVR_ATmega161__)
00122
00123 #error "AVR ATmega161 currently not supported by this libaray !"
00124 #elif defined(__AVR_ATmega169__)
00125
00126 #define ATMEGA_USART0
00127 #define UART0_RECEIVE_INTERRUPT SIG_UART0_RECV
00128 #define UART0_TRANSMIT_INTERRUPT SIG_UART0_DATA
00129 #define UART0_STATUS UCSR0A
00130 #define UART0_CONTROL UCSR0B
00131 #define UART0_DATA UDR0
00132 #define UART0_UDRIE UDRIE0
00133 #endif
00134
00135
00136
00137
00138
00139 static volatile unsigned char UART_TxBuf[UART_TX_BUFFER_SIZE];
00140 static volatile unsigned char UART_RxBuf[UART_RX_BUFFER_SIZE];
00141 static volatile unsigned char UART_TxHead;
00142 static volatile unsigned char UART_TxTail;
00143 static volatile unsigned char UART_RxHead;
00144 static volatile unsigned char UART_RxTail;
00145 static volatile unsigned char UART_LastRxError;
00146
00147 #if defined( ATMEGA_USART1 )
00148 static volatile unsigned char UART1_TxBuf[UART_TX_BUFFER_SIZE];
00149 static volatile unsigned char UART1_RxBuf[UART_RX_BUFFER_SIZE];
00150 static volatile unsigned char UART1_TxHead;
00151 static volatile unsigned char UART1_TxTail;
00152 static volatile unsigned char UART1_RxHead;
00153 static volatile unsigned char UART1_RxTail;
00154 static volatile unsigned char UART1_LastRxError;
00155 #endif
00156
00157
00158
00159 SIGNAL(UART0_RECEIVE_INTERRUPT)
00160
00161
00162
00163
00164 {
00165 unsigned char tmphead;
00166 unsigned char data;
00167 unsigned char usr;
00168 unsigned char lastRxError;
00169
00170
00171
00172 usr = UART0_STATUS;
00173 data = UART0_DATA;
00174
00175
00176 #if defined( AT90_UART )
00177 lastRxError = (usr & (_BV(FE)|_BV(DOR)) );
00178 #elif defined( ATMEGA_USART )
00179 lastRxError = (usr & (_BV(FE)|_BV(DOR)) );
00180 #elif defined( ATMEGA_USART0 )
00181 lastRxError = (usr & (_BV(FE0)|_BV(DOR0)) );
00182 #elif defined ( ATMEGA_UART )
00183 lastRxError = (usr & (_BV(FE)|_BV(DOR)) );
00184 #endif
00185
00186
00187 tmphead = ( UART_RxHead + 1) & UART_RX_BUFFER_MASK;
00188
00189 if ( tmphead == UART_RxTail ) {
00190
00191 lastRxError = UART_BUFFER_OVERFLOW >> 8;
00192 }else{
00193
00194 UART_RxHead = tmphead;
00195
00196 UART_RxBuf[tmphead] = data;
00197 }
00198 UART_LastRxError = lastRxError;
00199 }
00200
00201
00202 SIGNAL(UART0_TRANSMIT_INTERRUPT)
00203
00204
00205
00206
00207 {
00208 unsigned char tmptail;
00209
00210
00211 if ( UART_TxHead != UART_TxTail) {
00212
00213 tmptail = (UART_TxTail + 1) & UART_TX_BUFFER_MASK;
00214 UART_TxTail = tmptail;
00215
00216 UART0_DATA = UART_TxBuf[tmptail];
00217 }else{
00218
00219 UART0_CONTROL &= ~_BV(UART0_UDRIE);
00220 }
00221 }
00222
00223
00224
00225
00226
00227
00228
00229
00230 void uart_init(unsigned int baudrate)
00231 {
00232 UART_TxHead = 0;
00233 UART_TxTail = 0;
00234 UART_RxHead = 0;
00235 UART_RxTail = 0;
00236
00237 #if defined( AT90_UART )
00238
00239 UBRR = (unsigned char)baudrate;
00240
00241
00242 UART0_CONTROL = _BV(RXCIE)|_BV(RXEN)|_BV(TXEN);
00243
00244 #elif defined (ATMEGA_USART)
00245
00246 UBRRH = (unsigned char)(baudrate>>8);
00247 UBRRL = (unsigned char) baudrate;
00248
00249
00250 UART0_CONTROL = _BV(RXCIE)|(1<<RXEN)|(1<<TXEN);
00251
00252
00253 #ifdef URSEL
00254 UCSRC = (1<<URSEL)|(3<<UCSZ0);
00255 #else
00256 UCSRC = (3<<UCSZ0);
00257 #endif
00258
00259 #elif defined (ATMEGA_USART0 )
00260
00261 UBRR0H = (unsigned char)(baudrate>>8);
00262 UBRR0L = (unsigned char) baudrate;
00263
00264
00265 UART0_CONTROL = _BV(RXCIE0)|(1<<RXEN0)|(1<<TXEN0);
00266
00267
00268 #ifdef URSEL0
00269 UCSR0C = (1<<URSEL0)|(3<<UCSZ00);
00270 #else
00271 UCSR0C = (3<<UCSZ00);
00272 #endif
00273
00274 #elif defined ( ATMEGA_UART )
00275
00276 UBRRHI = (unsigned char)(baudrate>>8);
00277 UBRR = (unsigned char) baudrate;
00278
00279
00280 UART0_CONTROL = _BV(RXCIE)|(1<<RXEN)|(1<<TXEN);
00281
00282 #endif
00283
00284 }
00285
00286
00287
00288
00289
00290
00291
00292
00293 unsigned int uart_getc(void)
00294 {
00295 unsigned char tmptail;
00296 unsigned char data;
00297
00298
00299 if ( UART_RxHead == UART_RxTail ) {
00300 return UART_NO_DATA;
00301 }
00302
00303
00304 tmptail = (UART_RxTail + 1) & UART_RX_BUFFER_MASK;
00305 UART_RxTail = tmptail;
00306
00307
00308 data = UART_RxBuf[tmptail];
00309
00310 return (UART_LastRxError << 8) + data;
00311
00312 }
00313
00314
00315
00316
00317
00318
00319
00320
00321 void uart_putc(unsigned char data)
00322 {
00323 unsigned char tmphead;
00324
00325
00326 tmphead = (UART_TxHead + 1) & UART_TX_BUFFER_MASK;
00327
00328 while ( tmphead == UART_TxTail ){
00329 ;
00330 }
00331
00332 UART_TxBuf[tmphead] = data;
00333 UART_TxHead = tmphead;
00334
00335
00336 UART0_CONTROL |= _BV(UART0_UDRIE);
00337
00338 }
00339
00340 void uart_putc_hex(unsigned char b)
00341 {
00342
00343 if((b >> 4) < 0x0a)
00344 uart_putc((b >> 4) + '0');
00345 else
00346 uart_putc((b >> 4) - 0x0a + 'a');
00347
00348
00349 if((b & 0x0f) < 0x0a)
00350 uart_putc((b & 0x0f) + '0');
00351 else
00352 uart_putc((b & 0x0f) - 0x0a + 'a');
00353 }
00354
00355 void uart_putw_dec(uint16_t w)
00356 {
00357 uint16_t num = 10000;
00358 uint8_t started = 0;
00359
00360 while(num > 0)
00361 {
00362 uint8_t b = w / num;
00363 if(b > 0 || started || num == 1)
00364 {
00365 uart_putc('0' + b);
00366 started = 1;
00367 }
00368 w -= b * num;
00369
00370 num /= 10;
00371 }
00372 }
00373
00374 void uart_putdw_dec(uint32_t dw)
00375 {
00376 uint32_t num = 1000000000;
00377 uint8_t started = 0;
00378
00379 while(num > 0)
00380 {
00381 uint8_t b = dw / num;
00382 if(b > 0 || started || num == 1)
00383 {
00384 uart_putc('0' + b);
00385 started = 1;
00386 }
00387 dw -= b * num;
00388
00389 num /= 10;
00390 }
00391 }
00392
00393
00394
00395
00396
00397
00398
00399 void uart_puts(const char *s )
00400 {
00401 while (*s)
00402 uart_putc(*s++);
00403
00404 }
00405
00406
00407
00408
00409
00410
00411
00412
00413 void uart_puts_p(const char *progmem_s )
00414 {
00415 register char c;
00416
00417 while ( (c = pgm_read_byte(progmem_s++)) )
00418 uart_putc(c);
00419
00420 }
00421
00422
00423
00424
00425
00426 #if defined( ATMEGA_USART1 )
00427
00428 SIGNAL(UART1_RECEIVE_INTERRUPT)
00429
00430
00431
00432
00433 {
00434 unsigned char tmphead;
00435 unsigned char data;
00436 unsigned char usr;
00437 unsigned char lastRxError;
00438
00439
00440
00441 usr = UART1_STATUS;
00442 data = UART1_DATA;
00443
00444
00445 lastRxError = (usr & (_BV(FE1)|_BV(DOR1)) );
00446
00447
00448 tmphead = ( UART1_RxHead + 1) & UART_RX_BUFFER_MASK;
00449
00450 if ( tmphead == UART1_RxTail ) {
00451
00452 lastRxError = UART_BUFFER_OVERFLOW >> 8;
00453 }else{
00454
00455 UART1_RxHead = tmphead;
00456
00457 UART1_RxBuf[tmphead] = data;
00458 }
00459 UART1_LastRxError = lastRxError;
00460 }
00461
00462
00463 SIGNAL(UART1_TRANSMIT_INTERRUPT)
00464
00465
00466
00467
00468 {
00469 unsigned char tmptail;
00470
00471
00472 if ( UART1_TxHead != UART1_TxTail) {
00473
00474 tmptail = (UART1_TxTail + 1) & UART_TX_BUFFER_MASK;
00475 UART1_TxTail = tmptail;
00476
00477 UART1_DATA = UART1_TxBuf[tmptail];
00478 }else{
00479
00480 UART1_CONTROL &= ~_BV(UART1_UDRIE);
00481 }
00482 }
00483
00484
00485
00486
00487
00488
00489
00490
00491 void uart1_init(unsigned int baudrate)
00492 {
00493 UART1_TxHead = 0;
00494 UART1_TxTail = 0;
00495 UART1_RxHead = 0;
00496 UART1_RxTail = 0;
00497
00498
00499
00500 UBRR1H = (unsigned char)(baudrate>>8);
00501 UBRR1L = (unsigned char) baudrate;
00502
00503
00504 UART1_CONTROL = _BV(RXCIE1)|(1<<RXEN1)|(1<<TXEN1);
00505
00506
00507 #ifdef URSEL1
00508 UCSR1C = (1<<URSEL1)|(3<<UCSZ10);
00509 #else
00510 UCSR1C = (3<<UCSZ10);
00511 #endif
00512 }
00513
00514
00515
00516
00517
00518
00519
00520
00521 unsigned int uart1_getc(void)
00522 {
00523 unsigned char tmptail;
00524 unsigned char data;
00525
00526
00527 if ( UART1_RxHead == UART1_RxTail ) {
00528 return UART_NO_DATA;
00529 }
00530
00531
00532 tmptail = (UART1_RxTail + 1) & UART_RX_BUFFER_MASK;
00533 UART1_RxTail = tmptail;
00534
00535
00536 data = UART1_RxBuf[tmptail];
00537
00538 return (UART1_LastRxError << 8) + data;
00539
00540 }
00541
00542
00543
00544
00545
00546
00547
00548
00549 void uart1_putc(unsigned char data)
00550 {
00551 unsigned char tmphead;
00552
00553
00554 tmphead = (UART1_TxHead + 1) & UART_TX_BUFFER_MASK;
00555
00556 while ( tmphead == UART1_TxTail ){
00557 ;
00558 }
00559
00560 UART1_TxBuf[tmphead] = data;
00561 UART1_TxHead = tmphead;
00562
00563
00564 UART1_CONTROL |= _BV(UART1_UDRIE);
00565
00566 }
00567
00568
00569
00570
00571
00572
00573
00574
00575 void uart1_puts(const char *s )
00576 {
00577 while (*s)
00578 uart1_putc(*s++);
00579
00580 }
00581
00582
00583
00584
00585
00586
00587
00588
00589 void uart1_puts_p(const char *progmem_s )
00590 {
00591 register char c;
00592
00593 while ( (c = pgm_read_byte(progmem_s++)) )
00594 uart1_putc(c);
00595
00596 }
00597
00598
00599 #endif