-- WARNING: Do NOT edit the input and output ports in this file in a text -- editor if you plan to continue editing the block that represents it in -- the Block Editor! File corruption is VERY likely to occur. -- Copyright (C) 1991-2010 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. -- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010) -- Created on Wed Apr 14 15:05:45 2010 LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.numeric_std.all; -- Entity Declaration entity Broke is port( cardsum:in std_logic_vector(4 downto 0) broke : out std_logic); end Broke; architecture verhalten of Broke is begin with cardsum select broke <= '1' when "10110", '1' when "10111", '1' when "11000", '1' when "11001", '1' when "11010", '1' when "11011", '1' when "11100", '1' when "11101", '1' when "11110", '1' when "11111", '0'when others; end verhalten; entity Stand is port( cardsum:in std_logic_vector(4 downto 0) stand : out std_logic); end Stand; architecture verhalten_2 of Stand is begin with cardsum select stand <= '1' when "10110", '1' when "10111", '1' when "11000", '1' when "11001", '1' when "11010", '1' when "11011", '1' when "11100", '1' when "11101", '1' when "11110", '1' when "11111", '1' when "10001", '1' when "10010", '1' when "10011", '1' when "10100", '1' when "10101", '0' when others; end verhalten_2; entity bcd_7seg is port (bcd: in std_logic_vector (3 downto 0); sslines: out std_logic_vector (0 to 6)); end bcd_7seg; architecture verhalten_3 of bcd_7seg is begin with bcd select sslines <= "0000001" when "00000", "1001111" when "00001", "0010010" when "00010", "0000110" when "00011", "1001100" when "00100", "0100100" when "00101", "0100000" when "00110", "0001111" when "00111", "0000000" when "01000", "0000100" when "01001", "1111111" when others; END verhalten_3; entity card_z is port(cardsum :in std_logic_vector(4 downto 0); digit_1: out std_logic_vector(0 to 3)); end card_z; architecture verhalten_4 of card_z is begin ENTITY DISPLAY IS -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! PORT ( cardsum : IN STD_LOGIC_VECTOR(4 downto 0); digit_1 : OUT STD_LOGIC_VECTOR(0 to 6); digit_0 : OUT STD_LOGIC_VECTOR(0 to 6); digit_2 : OUT STD_LOGIC_VECTOR(0 to 6); digit_3 : OUT STD_LOGIC_VECTOR(0 to 6) ); -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! END DISPLAY; -- Architecture Body ARCHITECTURE DISPLAY_architecture OF DISPLAY IS BEGIN END DISPLAY_architecture;