Ctrl-Opcodes : 0000 0000 0000 0000 0000 Nop 001x 0000 0000 0001 xxxx SW-Interrupt x 002x 0000 0000 0010 xxxx Push Reg x on Stack 003x 0000 0000 0011 xxxx Pop Reg x from Stack 0040 0000 0000 0100 0000 Push Reg ACC on Stack 0041 0000 0000 0100 0001 Push Reg PC on Stack 0042 0000 0000 0100 0010 Push Reg SR on Stack 0050 0000 0000 0101 0000 Pop Reg ACC from Stack 0051 0000 0000 0101 0001 Pop Reg PC from Stack 0052 0000 0000 0101 0010 Pop Reg SR from Stack 00c0 0000 0000 1ccc 0000 Conditionally Return From Subroutine 00c1 0000 0000 1ccc 0001 Conditionally Return From Interrupt 01cx 0000 0001 0ccc xxxx Conditionally Jump To Addr [Register x (lo) + Register x+1 (hi)] 01cx 0000 0001 1ccc xxxx Conditionally Jump To Subroutine Addr [Register x (lo) + Register x+1 (hi)] 02dd 0000 0010 dddd dddd Push Lo Byte d on Stack 03dd 0000 0011 dddd dddd Push Hi Byte d on Stack 04xy 0000 0100 xxxx yyyy Writes Lo-Byte of Register y to IO-Reg [Register x] 05xy 0000 0101 xxxx yyyy Reads to Lo-Byte of Register y from IO-Reg [Register x] 060x 0000 0110 0000 xxxx Writes Register x (Lo-Byte) to Debug-Uart (Data-Register) 061x 0000 0110 0001 xxxx Reads Debug-Uart (Data-Register) to Register x (Lo-Byte) 062x 0000 0110 0010 xxxx Writes Register x (Lo-Byte) to Debug-Uart (Status-Register) 063x 0000 0110 0011 xxxx Reads Debug-Uart (Status-Register) to Register x (Lo-Byte) 064x 0000 0110 0100 xxxx Writes Register x (Lo-Byte) to Debug-Uart (Baudrate-Register) 065x 0000 0110 0101 xxxx Reads Debug-Uart (Baudrate-Register) to Register x (Lo-Byte) 066x 0000 0110 0110 xxxx Writes Register x (Lo-Byte) to Debug-Uart (Aux IO-Register) 067x 0000 0110 0111 xxxx Reads Debug-Uart (Aux IO-Register) to Register x (Lo-Byte) 08xy 0000 1000 xxxx yyyy Writes Lo-Word of SW-Int-Vect x with Register y 09xy 0000 1001 xxxx yyyy Writes Hi-Word of SW-Int-Vect x with Register y 0axy 0000 1010 xxxx yyyy Reads SW-Int-Vect x to Lo-Word of Register y 0bxy 0000 1011 xxxx yyyy Reads SW-Int-Vect x to Hi-Word of Register y 1dab 0001 00dd xaaa ybbb AND-Condition aaa/bbb = Condition, x/y = Invert Condition, dd -> Destination User Con. 1dab 0001 01dd aaaa bbbb OR-Condition aaa/bbb = Condition, x/y = Invert Condition, dd -> Destination User Con. 1dab 0001 10dd aaaa bbbb XOR-Condition aaa/bbb = Condition, x/y = Invert Condition, dd -> Destination User Con. Move-Opcodes : 40xy 0100 0000 xxxx yyyy Move Register x -> Register y 41xy 0100 0001 xxxx yyyy Move Register x -> Addr [Register y (lo) + Register y+1 (hi)] 42xy 0100 0010 xxxx yyyy Move Addr [Register x (lo) + Register x+1 (hi)] -> Register y 430x 0100 0011 0000 xxxx Move ACC-Lo -> Register x 431x 0100 0011 0001 xxxx Move ACC-Hi -> Register x 432x 0100 0011 0010 xxxx Move Register x -> ACC-Lo 433x 0100 0011 0011 xxxx Move Register x -> ACC-Hi 434x 0100 0011 0100 xxxx Move PC-Lo -> Register x 435x 0100 0011 0101 xxxx Move PC-Hi -> Register x 436x 0100 0011 0110 xxxx Move Register x -> PC-Lo 437x 0100 0011 0111 xxxx Move Register x -> PC-Hi 438x 0100 0011 1000 xxxx Move SP-Lo -> Register x 439x 0100 0011 1001 xxxx Move SP-Hi -> Register x 43Ax 0100 0011 1010 xxxx Move Register x -> SP-Lo 43Bx 0100 0011 1011 xxxx Move Register x -> SP-Hi 6xdd 0110 xxxx dddd dddd Move Lo-Byte d -> Register x 7xdd 0111 xxxx dddd dddd Move Hi-Byte d -> Register x ALU-Opcodes : 8cxy 1000 0ccc xxxx yyyy Conditionally Add Reg x & Reg y -> Store in acc 8cxy 1000 1ccc xxxx yyyy Conditionally Sub Reg x & Reg y -> Store in acc 9cxy 1001 0ccc xxxx yyyy Conditionally Mul Reg x & Reg y -> Store in acc, acc + 1 9cxy 1001 1ccc xxxx yyyy Conditionally And Reg x & Reg y -> Store in acc Acxy 1010 0ccc xxxx yyyy Conditionally Or Reg x & Reg y -> Store in acc Acxy 1010 1ccc xxxx yyyy Conditionally Xor Reg x & Reg y -> Store in acc Bcxy 1011 aacc xxxx yyyy Compare X & Y upon Condition a store it in C-Reg c ccc -> Condition 000 -> always 001 -> zero-flag 010 -> negative-flag 011 -> carry-flag 100-111 -> user-flags (compare) aa -> Compare 00 -> EQ 01 -> GR 10 -> LS 11 -> NE