---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:19:31 05/20/2010 -- Design Name: -- Module Name: Counter - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_arith.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Counter is Port ( CLK : in std_logic; TASTER : in std_logic; LED : out std_logic_vector (5 downto 0)); end Counter; architecture Behavioral of Counter is constant XTAL : integer := 50000000; signal DEBOUNCE_CNT : integer range 0 to 100; signal STATE : std_logic := '0'; signal OLD_STATE : std_logic := '0'; signal TIMER_COUNTER : integer range 0 to XTAL := 0; signal COUNTERX : integer range 0 to 63 := 0; signal DIRECTION : std_logic := '0'; begin -- Tasten entprellung DEBOUNCE : process begin wait until rising_edge(CLK); if (STATE /= TASTER) then -- Flanken Erkennung DEBOUNCE_CNT <= DEBOUNCE_CNT + 1; -- 50 Taktzyklen muss ein neuer Tastenzustand andauern else DEBOUNCE_CNT <= 0; end if; if (DEBOUNCE_CNT = 50) then STATE <= TASTER; -- 0 ist gedrückt / 1 ist losgelassen end if; end process DEBOUNCE; -------------------------------------------------------------------------------- process (CLK, STATE) begin if rising_edge(CLK) then if (STATE = '0' and OLD_STATE /= STATE) then -- Taster wurde gedrückt DIRECTION <= not DIRECTION; end if; OLD_STATE <= STATE; end if; end process; --------------------------------------------------------------------------------- TIMER : process (CLK) begin if rising_edge(CLK) then if (TIMER_COUNTER = XTAL - 1) then -- TIMER_COUNTER erzeugt Sek. Takt TIMER_COUNTER <= 0; case DIRECTION is when '0' => if (COUNTERX = 63) then -- Überlauf COUNTERX <= 0; else COUNTERX <= COUNTERX + 1; end if; when others => if (COUNTERX = 0) then -- Überlauf COUNTERX <= 63; else COUNTERX <= COUNTERX - 1; end if; end case; else TIMER_COUNTER <= TIMER_COUNTER + 1; end if; end if; end process TIMER; LED <= not (conv_std_logic_vector (COUNTERX,6)); --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- end Behavioral;