library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity counter is port( clk : in std_logic; clear : in std_logic; count : in std_logic; countst : out std_logic_vector(31 downto 0) ); end counter; architecture verhalten of counter is signal ce : std_logic; signal cnt : integer range 0 to 15; signal Q : std_logic_vector(31 downto 0); begin COUNTERPRO: process(ce, clear, count) begin if ce = '1' then if clear = '1' then Q <= (others => '0'); end if; if count = '1' then if Q = x"7FFFFFFF" then Q <= (others => '0'); end if; Q <= Q + '1'; else Q <= Q; end if; end if; end process COUNTERPRO; countst <= Q; TIMER: process(clk) begin if rising_edge(clk) then if cnt=15 then ce <= '1'; cnt <= 0; else ce <= '0'; cnt <= cnt + 1; end if; end if; end process TIMER; end verhalten;