ENTITY rotate IS
  PORT(
	res, clock: IN bit;
	n: IN integer range 0 to 15;
	high_byte, low_byte: INOUT bitvector (7 DOWNTO 0)
       );



ARCHITECTURE arch OF rotate IS
BEGIN
PROCESS(res, clock)
VARIABLE tmpl, tmph : std_logic;
BEGIN

IF (res = '1') THEN
	high_byte <= "00000000";
	low_byte  <= "00000000";

ELSIF(rising_edge(clock)) THEN

	FOR a IN 0 TO n LOOP
	  tmph:=high_byte(7);
	  tmpl:=low_byte(7);
	  
	  FOR i IN 6 DOWNTO 0 LOOP
	    high_byte(i+1) <=high_byte(i);
	    low_byte(i+1) <=low_byte(i);
	  END LOOP;
	  
	   high_byte(0) := tmpl;
	   low_byte(0) := tmph;

	END LOOP;
END IF;
END PROCESS;
END arch;