********** Mapped Logic ********** |
FTCPE_ADR0: FTCPE port map (ADR(0),'1',NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0'); |
FTCPE_ADR1: FTCPE port map (ADR(1),ADR_0_OBUF.LFBK,NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0'); |
FTCPE_ADR2: FTCPE port map (ADR(2),ADR_T(2),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(2) <= (ADR_0_OBUF.LFBK AND ADR_1_OBUF.LFBK); |
FTCPE_ADR3: FTCPE port map (ADR(3),ADR_T(3),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(3) <= (ADR(0).PIN AND ADR(1).PIN AND ADR(2).PIN); |
FTCPE_ADR4: FTCPE port map (ADR(4),ADR_T(4),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(4) <= (ADR(0).PIN AND ADR(1).PIN AND ADR(2).PIN AND ADR(3).PIN); |
FTCPE_ADR5: FTCPE port map (ADR(5),ADR_T(5),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(5) <= (ADR_4_OBUF.LFBK AND ADR(0).PIN AND ADR(1).PIN AND ADR(2).PIN AND ADR(3).PIN); |
FTCPE_ADR6: FTCPE port map (ADR(6),ADR_T(6),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(6) <= (ADR_4_OBUF.LFBK AND ADR_5_OBUF.LFBK AND ADR(0).PIN AND ADR(1).PIN AND ADR(2).PIN AND ADR(3).PIN); |
FTCPE_ADR7: FTCPE port map (ADR(7),ADR_T(7),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(7) <= (ADR_4_OBUF.LFBK AND ADR_5_OBUF.LFBK AND ADR_6_OBUF.LFBK AND ADR(0).PIN AND ADR(1).PIN AND ADR(2).PIN AND ADR(3).PIN); |
FTCPE_ADR8: FTCPE port map (ADR(8),ADR_T(8),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(8) <= (ADR_4_OBUF.LFBK AND ADR_5_OBUF.LFBK AND ADR_6_OBUF.LFBK AND ADR_7_OBUF.LFBK AND ADR(0).PIN AND ADR(1).PIN AND ADR(2).PIN AND ADR(3).PIN); |
FTCPE_ADR9: FTCPE port map (ADR(9),ADR_T(9),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(9) <= (ADR_3_OBUF.LFBK AND ADR(0).PIN AND ADR(4).PIN AND ADR(8).PIN AND ADR(1).PIN AND ADR(5).PIN AND ADR(2).PIN AND ADR(6).PIN AND ADR(7).PIN); |
FTCPE_ADR10: FTCPE port map (ADR(10),ADR_T(10),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(10) <= (ADR_3_OBUF.LFBK AND ADR_9_OBUF.LFBK AND ADR(0).PIN AND ADR(4).PIN AND ADR(8).PIN AND ADR(1).PIN AND ADR(5).PIN AND ADR(2).PIN AND ADR(6).PIN AND ADR(7).PIN); |
FTCPE_ADR11: FTCPE port map (ADR(11),ADR_T(11),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(11) <= (ADR_3_OBUF.LFBK AND ADR_9_OBUF.LFBK AND ADR_10_OBUF.LFBK AND ADR(0).PIN AND ADR(4).PIN AND ADR(8).PIN AND ADR(1).PIN AND ADR(5).PIN AND ADR(2).PIN AND ADR(6).PIN AND ADR(7).PIN); |
FTCPE_ADR12: FTCPE port map (ADR(12),ADR_T(12),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(12) <= (ADR_4_OBUF.LFBK AND ADR_5_OBUF.LFBK AND ADR_6_OBUF.LFBK AND ADR_7_OBUF.LFBK AND ADR_8_OBUF.LFBK AND ADR(0).PIN AND ADR(1).PIN AND ADR(9).PIN AND ADR(10).PIN AND ADR(2).PIN AND ADR(11).PIN AND ADR(3).PIN); |
FTCPE_ADR13: FTCPE port map (ADR(13),ADR_T(13),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0');
ADR_T(13) <= (ADR_3_OBUF.LFBK AND ADR_9_OBUF.LFBK AND ADR_10_OBUF.LFBK AND ADR_11_OBUF.LFBK AND ADR(0).PIN AND ADR(4).PIN AND ADR(8).PIN AND ADR(12).PIN AND ADR(1).PIN AND ADR(5).PIN AND ADR(2).PIN AND ADR(6).PIN AND ADR(7).PIN); |
FTCPE_ADR14: FTCPE port map (ADR(14),ADR_T(14),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT.LFBK,RESET,'0');
ADR_T(14) <= (ADR(0).PIN AND ADR(4).PIN AND ADR(8).PIN AND ADR(12).PIN AND ADR(1).PIN AND ADR(5).PIN AND ADR(9).PIN AND ADR(10).PIN AND ADR(13).PIN AND ADR(2).PIN AND ADR(6).PIN AND ADR(11).PIN AND ADR(3).PIN AND ADR(7).PIN); |
FTCPE_ADR15: FTCPE port map (ADR(15),ADR_T(15),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT.LFBK,RESET,'0');
ADR_T(15) <= (ADR_14_OBUF.LFBK AND ADR(0).PIN AND ADR(4).PIN AND ADR(8).PIN AND ADR(12).PIN AND ADR(1).PIN AND ADR(5).PIN AND ADR(9).PIN AND ADR(10).PIN AND ADR(13).PIN AND ADR(2).PIN AND ADR(6).PIN AND ADR(11).PIN AND ADR(3).PIN AND ADR(7).PIN); |
AD_CLK <= ((M50 AND NOT DIV1 AND NOT DIV0)
OR (Teiler(9) AND DIV1 AND DIV0) OR (DIV1 AND NOT DIV0 AND Teiler(7).LFBK) OR (NOT DIV1 AND DIV0 AND Teiler(4).LFBK)); |
CS <= '0'; |
OE <= ((NOT CLK)
OR (NOT M50 AND NOT DIV1 AND NOT DIV0 AND RUN AND NOT ADR(15).PIN) OR (NOT Teiler(4) AND NOT DIV1 AND DIV0 AND RUN AND NOT ADR(15).PIN) OR (NOT Teiler(7) AND DIV1 AND NOT DIV0 AND RUN AND NOT ADR(15).PIN) OR (NOT Teiler(9) AND DIV1 AND DIV0 AND RUN AND NOT ADR(15).PIN)); |
FDCPE_STOP: FDCPE port map (STOP,STOP_D,NOT STOP_OBUF/STOP_OBUF_CLKF__$INT.LFBK,'0',RESET);
STOP_D <= ADR_15_OBUF.LFBK XOR STOP_D <= (ADR_14_OBUF.LFBK AND ADR(0).PIN AND ADR(4).PIN AND ADR(8).PIN AND ADR(12).PIN AND ADR(1).PIN AND ADR(5).PIN AND ADR(9).PIN AND ADR(10).PIN AND ADR(13).PIN AND ADR(2).PIN AND ADR(6).PIN AND ADR(11).PIN AND ADR(3).PIN AND ADR(7).PIN); |
STOP_OBUF/STOP_OBUF_CLKF__$INT <= ((CLK)
OR (NOT M50 AND NOT DIV1 AND NOT DIV0 AND RUN AND NOT ADR_15_OBUF.LFBK) OR (NOT Teiler(9) AND DIV1 AND DIV0 AND RUN AND NOT ADR_15_OBUF.LFBK) OR (DIV1 AND NOT DIV0 AND RUN AND NOT Teiler(7).LFBK AND NOT ADR_15_OBUF.LFBK) OR (NOT DIV1 AND DIV0 AND RUN AND NOT Teiler(4).LFBK AND NOT ADR_15_OBUF.LFBK)); |
FTCPE_Teiler4: FTCPE port map (Teiler(4),Teiler_T(4),M50,'0','0');
Teiler_T(4) <= (XLXI_67/Q(0).LFBK AND XLXI_67/Q(1).LFBK AND XLXI_67/Q(2).LFBK AND XLXI_67/Q(3).LFBK); |
FTCPE_Teiler7: FTCPE port map (Teiler(7),Teiler_T(7),M50,'0','0');
Teiler_T(7) <= (XLXI_67/Q(0).LFBK AND XLXI_67/Q(1).LFBK AND XLXI_67/Q(2).LFBK AND XLXI_67/Q(3).LFBK AND Teiler(4).LFBK AND XLXI_67/Q(5).LFBK AND XLXI_67/Q(6).LFBK); |
FTCPE_Teiler9: FTCPE port map (Teiler(9),Teiler_T(9),M50,'0','0');
Teiler_T(9) <= (Teiler(4) AND XLXI_67/Q(0) AND XLXI_67/Q(1) AND XLXI_67/Q(5) AND Teiler(7) AND XLXI_67/Q(2) AND XLXI_67/Q(6) AND XLXI_67/Q(3) AND XLXI_67/Q(8)); |
WE <= NOT (((NOT M50 AND NOT DIV1 AND NOT DIV0 AND RUN AND NOT ADR(15).PIN)
OR (NOT Teiler(4) AND NOT DIV1 AND DIV0 AND RUN AND NOT ADR(15).PIN) OR (NOT Teiler(7) AND DIV1 AND NOT DIV0 AND RUN AND NOT ADR(15).PIN) OR (NOT Teiler(9) AND DIV1 AND DIV0 AND RUN AND NOT ADR(15).PIN))); |
FTCPE_XLXI_67/Q0: FTCPE port map (XLXI_67/Q(0),'1',M50,'0','0'); |
FTCPE_XLXI_67/Q1: FTCPE port map (XLXI_67/Q(1),XLXI_67/Q(0).LFBK,M50,'0','0'); |
FTCPE_XLXI_67/Q2: FTCPE port map (XLXI_67/Q(2),XLXI_67/Q_T(2),M50,'0','0');
XLXI_67/Q_T(2) <= (XLXI_67/Q(0).LFBK AND XLXI_67/Q(1).LFBK); |
FTCPE_XLXI_67/Q3: FTCPE port map (XLXI_67/Q(3),XLXI_67/Q_T(3),M50,'0','0');
XLXI_67/Q_T(3) <= (XLXI_67/Q(0).LFBK AND XLXI_67/Q(1).LFBK AND XLXI_67/Q(2).LFBK); |
FTCPE_XLXI_67/Q5: FTCPE port map (XLXI_67/Q(5),XLXI_67/Q_T(5),M50,'0','0');
XLXI_67/Q_T(5) <= (XLXI_67/Q(0).LFBK AND XLXI_67/Q(1).LFBK AND XLXI_67/Q(2).LFBK AND XLXI_67/Q(3).LFBK AND Teiler(4).LFBK); |
FTCPE_XLXI_67/Q6: FTCPE port map (XLXI_67/Q(6),XLXI_67/Q_T(6),M50,'0','0');
XLXI_67/Q_T(6) <= (XLXI_67/Q(0).LFBK AND XLXI_67/Q(1).LFBK AND XLXI_67/Q(2).LFBK AND XLXI_67/Q(3).LFBK AND Teiler(4).LFBK AND XLXI_67/Q(5).LFBK); |
FTCPE_XLXI_67/Q8: FTCPE port map (XLXI_67/Q(8),XLXI_67/Q_T(8),M50,'0','0');
XLXI_67/Q_T(8) <= (XLXI_67/Q(0).LFBK AND XLXI_67/Q(1).LFBK AND XLXI_67/Q(2).LFBK AND XLXI_67/Q(3).LFBK AND Teiler(4).LFBK AND XLXI_67/Q(5).LFBK AND XLXI_67/Q(6).LFBK AND Teiler(7).LFBK); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); |