cpldfit: version L.33 Xilinx Inc. Fitter Report Design Name: MyScopeMain Date: 4-11-2010, 9:03PM Device Used: XC9572-15-PC44 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 32 /72 ( 44%) 61 /360 ( 17%) 79 /144 ( 55%) 27 /72 ( 37%) 27 /34 ( 79%) ** Function Block Resources ** Function Mcells FB Inps Signals Pterms IO Block Used/Tot Used/Tot Used Used/Tot Used/Tot FB1 6/18 23/36 23 11/90 5/ 9 FB2 6/18 13/36 13 12/90 6/ 9 FB3 5/18 12/36 12 14/90 5/ 8 FB4 15/18 31/36 31 24/90 5/ 8 ----- ----- ----- ----- 32/72 79/144 61/360 21/34 * - Resource is exhausted ** Global Control Resources ** Signal 'M50' mapped onto global clock net GCK1. Global output enable net(s) unused. Signal 'RESET' mapped onto global set/reset net GSR. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 4 4 | I/O : 25 28 Output : 6 6 | GCK/IO : 1 3 Bidirectional : 15 15 | GTS/IO : 0 2 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | GSR : 1 1 | ---- ---- Total 27 27 ** Power Data ** There are 32 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************* Summary of Mapped Logic ************************ ** 21 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State ADR<11> 2 12 FB1_2 1 I/O I/O STD FAST RESET ADR<13> 2 14 FB1_5 2 I/O I/O STD FAST RESET ADR<3> 2 4 FB1_8 4 I/O I/O STD FAST RESET ADR<9> 2 10 FB1_15 8 I/O I/O STD FAST RESET ADR<10> 2 11 FB1_17 9 I/O I/O STD FAST RESET ADR<12> 2 13 FB2_2 35 I/O I/O STD FAST RESET ADR<4> 2 5 FB2_5 36 I/O I/O STD FAST RESET ADR<5> 2 6 FB2_6 37 I/O I/O STD FAST RESET ADR<6> 2 7 FB2_8 38 I/O I/O STD FAST RESET ADR<7> 2 8 FB2_15 43 I/O I/O STD FAST RESET ADR<8> 2 9 FB2_17 44 I/O I/O STD FAST RESET OE 5 9 FB3_5 12 I/O O STD FAST WE 4 8 FB3_8 13 I/O O STD FAST ADR<1> 2 2 FB3_11 18 I/O I/O STD FAST RESET ADR<2> 2 3 FB3_14 19 I/O I/O STD FAST RESET ADR<0> 1 1 FB3_17 22 I/O I/O STD FAST RESET AD_CLK 4 6 FB4_2 24 I/O O STD FAST STOP 3 17 FB4_8 26 I/O O STD FAST SET ADR<14> 2 15 FB4_11 28 I/O O STD FAST RESET ADR<15> 2 16 FB4_14 29 I/O I/O STD FAST RESET CS 0 0 FB4_17 34 I/O O STD FAST ** 11 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State Teiler<9> 1 9 FB1_18 STD RESET XLXI_67/Q<8> 1 8 FB4_5 STD RESET XLXI_67/Q<6> 1 6 FB4_6 STD RESET XLXI_67/Q<5> 1 5 FB4_7 STD RESET XLXI_67/Q<3> 1 3 FB4_9 STD RESET XLXI_67/Q<2> 1 2 FB4_10 STD RESET XLXI_67/Q<1> 1 1 FB4_12 STD RESET XLXI_67/Q<0> 0 0 FB4_13 STD RESET Teiler<7> 1 7 FB4_15 STD RESET Teiler<4> 1 4 FB4_16 STD RESET STOP_OBUF/STOP_OBUF_CLKF__$INT 5 9 FB4_18 STD ** 6 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use M50 FB1_9 5~ GCK/I/O GCK/I RESET FB2_9 39~ GSR/I/O GSR DIV1 FB3_2 11 I/O I CLK FB3_9 14 I/O I DIV0 FB3_15 20 I/O I RUN FB4_15 33 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 23/13 Number of signals used by logic mapping into function block: 23 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 (b) ADR<11> 2 0 0 3 FB1_2 1 I/O I/O (unused) 0 0 0 5 FB1_3 (b) (unused) 0 0 0 5 FB1_4 (b) ADR<13> 2 0 0 3 FB1_5 2 I/O I/O (unused) 0 0 0 5 FB1_6 3 I/O (unused) 0 0 0 5 FB1_7 (b) ADR<3> 2 0 0 3 FB1_8 4 I/O I/O (unused) 0 0 0 5 FB1_9 5 GCK/I/O GCK/I (unused) 0 0 0 5 FB1_10 (b) (unused) 0 0 0 5 FB1_11 6 GCK/I/O (unused) 0 0 0 5 FB1_12 (b) (unused) 0 0 0 5 FB1_13 (b) (unused) 0 0 0 5 FB1_14 7 GCK/I/O ADR<9> 2 0 0 3 FB1_15 8 I/O I/O (unused) 0 0 0 5 FB1_16 (b) ADR<10> 2 0 0 3 FB1_17 9 I/O I/O Teiler<9> 1 0 0 4 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: ADR<0>.PIN 9: ADR<8>.PIN 17: XLXI_67/Q<0> 2: ADR<12>.PIN 10: ADR_10_OBUF.LFBK 18: XLXI_67/Q<1> 3: ADR<1>.PIN 11: ADR_11_OBUF.LFBK 19: XLXI_67/Q<2> 4: ADR<2>.PIN 12: ADR_3_OBUF.LFBK 20: XLXI_67/Q<3> 5: ADR<4>.PIN 13: ADR_9_OBUF.LFBK 21: XLXI_67/Q<5> 6: ADR<5>.PIN 14: STOP_OBUF/STOP_OBUF_CLKF__$INT 22: XLXI_67/Q<6> 7: ADR<6>.PIN 15: Teiler<4> 23: XLXI_67/Q<8> 8: ADR<7>.PIN 16: Teiler<7> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs ADR<11> X.XXXXXXXX.XXX.......................... 12 12 ADR<13> XXXXXXXXXXXXXX.......................... 14 14 ADR<3> X.XX.........X.......................... 4 4 ADR<9> X.XXXXXXX..X.X.......................... 10 10 ADR<10> X.XXXXXXX..XXX.......................... 11 11 Teiler<9> ..............XXXXXXXXX................. 9 9 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 13/23 Number of signals used by logic mapping into function block: 13 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 (b) ADR<12> 2 0 0 3 FB2_2 35 I/O I/O (unused) 0 0 0 5 FB2_3 (b) (unused) 0 0 0 5 FB2_4 (b) ADR<4> 2 0 0 3 FB2_5 36 I/O I/O ADR<5> 2 0 0 3 FB2_6 37 I/O I/O (unused) 0 0 0 5 FB2_7 (b) ADR<6> 2 0 0 3 FB2_8 38 I/O I/O (unused) 0 0 0 5 FB2_9 39 GSR/I/O GSR (unused) 0 0 0 5 FB2_10 (b) (unused) 0 0 0 5 FB2_11 40 GTS/I/O (unused) 0 0 0 5 FB2_12 (b) (unused) 0 0 0 5 FB2_13 (b) (unused) 0 0 0 5 FB2_14 42 GTS/I/O ADR<7> 2 0 0 3 FB2_15 43 I/O I/O (unused) 0 0 0 5 FB2_16 (b) ADR<8> 2 0 0 3 FB2_17 44 I/O I/O (unused) 0 0 0 5 FB2_18 (b) Signals Used by Logic in Function Block 1: ADR<0>.PIN 6: ADR<3>.PIN 10: ADR_6_OBUF.LFBK 2: ADR<10>.PIN 7: ADR<9>.PIN 11: ADR_7_OBUF.LFBK 3: ADR<11>.PIN 8: ADR_4_OBUF.LFBK 12: ADR_8_OBUF.LFBK 4: ADR<1>.PIN 9: ADR_5_OBUF.LFBK 13: STOP_OBUF/STOP_OBUF_CLKF__$INT 5: ADR<2>.PIN Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs ADR<12> XXXXXXXXXXXXX........................... 13 13 ADR<4> X..XXX......X........................... 5 5 ADR<5> X..XXX.X....X........................... 6 6 ADR<6> X..XXX.XX...X........................... 7 7 ADR<7> X..XXX.XXX..X........................... 8 8 ADR<8> X..XXX.XXXX.X........................... 9 9 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 12/24 Number of signals used by logic mapping into function block: 12 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) (unused) 0 0 0 5 FB3_2 11 I/O I (unused) 0 0 0 5 FB3_3 (b) (unused) 0 0 0 5 FB3_4 (b) OE 5 0 0 0 FB3_5 12 I/O O (unused) 0 0 0 5 FB3_6 (b) (unused) 0 0 0 5 FB3_7 (b) WE 4 0 0 1 FB3_8 13 I/O O (unused) 0 0 0 5 FB3_9 14 I/O I (unused) 0 0 0 5 FB3_10 (b) ADR<1> 2 0 0 3 FB3_11 18 I/O I/O (unused) 0 0 0 5 FB3_12 (b) (unused) 0 0 0 5 FB3_13 (b) ADR<2> 2 0 0 3 FB3_14 19 I/O I/O (unused) 0 0 0 5 FB3_15 20 I/O I (unused) 0 0 0 5 FB3_16 (b) ADR<0> 1 0 0 4 FB3_17 22 I/O I/O (unused) 0 0 0 5 FB3_18 (b) Signals Used by Logic in Function Block 1: ADR<15>.PIN 5: DIV0 9: STOP_OBUF/STOP_OBUF_CLKF__$INT 2: ADR_0_OBUF.LFBK 6: DIV1 10: Teiler<4> 3: ADR_1_OBUF.LFBK 7: M50 11: Teiler<7> 4: CLK 8: RUN 12: Teiler<9> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs OE X..XXXXX.XXX............................ 9 9 WE X...XXXX.XXX............................ 8 8 ADR<1> .X......X............................... 2 2 ADR<2> .XX.....X............................... 3 3 ADR<0> ........X............................... 1 1 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 31/5 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB4_1 (b) AD_CLK 4 0 0 1 FB4_2 24 I/O O (unused) 0 0 0 5 FB4_3 (b) (unused) 0 0 0 5 FB4_4 (b) XLXI_67/Q<8> 1 0 0 4 FB4_5 25 I/O (b) XLXI_67/Q<6> 1 0 0 4 FB4_6 (b) (b) XLXI_67/Q<5> 1 0 0 4 FB4_7 (b) (b) STOP 3 0 0 2 FB4_8 26 I/O O XLXI_67/Q<3> 1 0 0 4 FB4_9 27 I/O (b) XLXI_67/Q<2> 1 0 0 4 FB4_10 (b) (b) ADR<14> 2 0 0 3 FB4_11 28 I/O O XLXI_67/Q<1> 1 0 0 4 FB4_12 (b) (b) XLXI_67/Q<0> 0 0 0 5 FB4_13 (b) (b) ADR<15> 2 0 0 3 FB4_14 29 I/O I/O Teiler<7> 1 0 0 4 FB4_15 33 I/O I Teiler<4> 1 0 0 4 FB4_16 (b) (b) CS 0 0 0 5 FB4_17 34 I/O O STOP_OBUF/STOP_OBUF_CLKF__$INT 5 0 0 0 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: ADR<0>.PIN 12: ADR<7>.PIN 22: STOP_OBUF/STOP_OBUF_CLKF__$INT.LFBK 2: ADR<10>.PIN 13: ADR<8>.PIN 23: Teiler<4>.LFBK 3: ADR<11>.PIN 14: ADR<9>.PIN 24: Teiler<7>.LFBK 4: ADR<12>.PIN 15: ADR_14_OBUF.LFBK 25: Teiler<9> 5: ADR<13>.PIN 16: ADR_15_OBUF.LFBK 26: XLXI_67/Q<0>.LFBK 6: ADR<1>.PIN 17: CLK 27: XLXI_67/Q<1>.LFBK 7: ADR<2>.PIN 18: DIV0 28: XLXI_67/Q<2>.LFBK 8: ADR<3>.PIN 19: DIV1 29: XLXI_67/Q<3>.LFBK 9: ADR<4>.PIN 20: M50 30: XLXI_67/Q<5>.LFBK 10: ADR<5>.PIN 21: RUN 31: XLXI_67/Q<6>.LFBK 11: ADR<6>.PIN Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs AD_CLK .................XXX..XXX............... 6 6 XLXI_67/Q<8> ......................XX.XXXXXX......... 8 8 XLXI_67/Q<6> ......................X..XXXXX.......... 6 6 XLXI_67/Q<5> ......................X..XXXX........... 5 5 STOP XXXXXXXXXXXXXXXX.....X.................. 17 17 XLXI_67/Q<3> .........................XXX............ 3 3 XLXI_67/Q<2> .........................XX............. 2 2 ADR<14> XXXXXXXXXXXXXX.......X.................. 15 15 XLXI_67/Q<1> .........................X.............. 1 1 XLXI_67/Q<0> ........................................ 0 0 ADR<15> XXXXXXXXXXXXXXX......X.................. 16 16 Teiler<7> ......................X..XXXXXX......... 7 7 Teiler<4> .........................XXXX........... 4 4 CS ........................................ 0 0 STOP_OBUF/STOP_OBUF_CLKF__$INT ...............XXXXXX.XXX............... 9 9 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** FTCPE_ADR0: FTCPE port map (ADR(0),'1',NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0'); FTCPE_ADR1: FTCPE port map (ADR(1),ADR_0_OBUF.LFBK,NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0'); FTCPE_ADR2: FTCPE port map (ADR(2),ADR_T(2),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0'); ADR_T(2) <= (ADR_0_OBUF.LFBK AND ADR_1_OBUF.LFBK); FTCPE_ADR3: FTCPE port map (ADR(3),ADR_T(3),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0'); ADR_T(3) <= (ADR(0).PIN AND ADR(1).PIN AND ADR(2).PIN); FTCPE_ADR4: FTCPE port map (ADR(4),ADR_T(4),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0'); ADR_T(4) <= (ADR(0).PIN AND ADR(1).PIN AND ADR(2).PIN AND ADR(3).PIN); FTCPE_ADR5: FTCPE port map (ADR(5),ADR_T(5),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0'); ADR_T(5) <= (ADR_4_OBUF.LFBK AND ADR(0).PIN AND ADR(1).PIN AND ADR(2).PIN AND ADR(3).PIN); FTCPE_ADR6: FTCPE port map (ADR(6),ADR_T(6),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0'); ADR_T(6) <= (ADR_4_OBUF.LFBK AND ADR_5_OBUF.LFBK AND ADR(0).PIN AND ADR(1).PIN AND ADR(2).PIN AND ADR(3).PIN); FTCPE_ADR7: FTCPE port map (ADR(7),ADR_T(7),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0'); ADR_T(7) <= (ADR_4_OBUF.LFBK AND ADR_5_OBUF.LFBK AND ADR_6_OBUF.LFBK AND ADR(0).PIN AND ADR(1).PIN AND ADR(2).PIN AND ADR(3).PIN); FTCPE_ADR8: FTCPE port map (ADR(8),ADR_T(8),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0'); ADR_T(8) <= (ADR_4_OBUF.LFBK AND ADR_5_OBUF.LFBK AND ADR_6_OBUF.LFBK AND ADR_7_OBUF.LFBK AND ADR(0).PIN AND ADR(1).PIN AND ADR(2).PIN AND ADR(3).PIN); FTCPE_ADR9: FTCPE port map (ADR(9),ADR_T(9),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0'); ADR_T(9) <= (ADR_3_OBUF.LFBK AND ADR(0).PIN AND ADR(4).PIN AND ADR(8).PIN AND ADR(1).PIN AND ADR(5).PIN AND ADR(2).PIN AND ADR(6).PIN AND ADR(7).PIN); FTCPE_ADR10: FTCPE port map (ADR(10),ADR_T(10),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0'); ADR_T(10) <= (ADR_3_OBUF.LFBK AND ADR_9_OBUF.LFBK AND ADR(0).PIN AND ADR(4).PIN AND ADR(8).PIN AND ADR(1).PIN AND ADR(5).PIN AND ADR(2).PIN AND ADR(6).PIN AND ADR(7).PIN); FTCPE_ADR11: FTCPE port map (ADR(11),ADR_T(11),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0'); ADR_T(11) <= (ADR_3_OBUF.LFBK AND ADR_9_OBUF.LFBK AND ADR_10_OBUF.LFBK AND ADR(0).PIN AND ADR(4).PIN AND ADR(8).PIN AND ADR(1).PIN AND ADR(5).PIN AND ADR(2).PIN AND ADR(6).PIN AND ADR(7).PIN); FTCPE_ADR12: FTCPE port map (ADR(12),ADR_T(12),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0'); ADR_T(12) <= (ADR_4_OBUF.LFBK AND ADR_5_OBUF.LFBK AND ADR_6_OBUF.LFBK AND ADR_7_OBUF.LFBK AND ADR_8_OBUF.LFBK AND ADR(0).PIN AND ADR(1).PIN AND ADR(9).PIN AND ADR(10).PIN AND ADR(2).PIN AND ADR(11).PIN AND ADR(3).PIN); FTCPE_ADR13: FTCPE port map (ADR(13),ADR_T(13),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT,RESET,'0'); ADR_T(13) <= (ADR_3_OBUF.LFBK AND ADR_9_OBUF.LFBK AND ADR_10_OBUF.LFBK AND ADR_11_OBUF.LFBK AND ADR(0).PIN AND ADR(4).PIN AND ADR(8).PIN AND ADR(12).PIN AND ADR(1).PIN AND ADR(5).PIN AND ADR(2).PIN AND ADR(6).PIN AND ADR(7).PIN); FTCPE_ADR14: FTCPE port map (ADR(14),ADR_T(14),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT.LFBK,RESET,'0'); ADR_T(14) <= (ADR(0).PIN AND ADR(4).PIN AND ADR(8).PIN AND ADR(12).PIN AND ADR(1).PIN AND ADR(5).PIN AND ADR(9).PIN AND ADR(10).PIN AND ADR(13).PIN AND ADR(2).PIN AND ADR(6).PIN AND ADR(11).PIN AND ADR(3).PIN AND ADR(7).PIN); FTCPE_ADR15: FTCPE port map (ADR(15),ADR_T(15),NOT STOP_OBUF/STOP_OBUF_CLKF__$INT.LFBK,RESET,'0'); ADR_T(15) <= (ADR_14_OBUF.LFBK AND ADR(0).PIN AND ADR(4).PIN AND ADR(8).PIN AND ADR(12).PIN AND ADR(1).PIN AND ADR(5).PIN AND ADR(9).PIN AND ADR(10).PIN AND ADR(13).PIN AND ADR(2).PIN AND ADR(6).PIN AND ADR(11).PIN AND ADR(3).PIN AND ADR(7).PIN); AD_CLK <= ((M50 AND NOT DIV1 AND NOT DIV0) OR (Teiler(9) AND DIV1 AND DIV0) OR (DIV1 AND NOT DIV0 AND Teiler(7).LFBK) OR (NOT DIV1 AND DIV0 AND Teiler(4).LFBK)); CS <= '0'; OE <= ((NOT CLK) OR (NOT M50 AND NOT DIV1 AND NOT DIV0 AND RUN AND NOT ADR(15).PIN) OR (NOT Teiler(4) AND NOT DIV1 AND DIV0 AND RUN AND NOT ADR(15).PIN) OR (NOT Teiler(7) AND DIV1 AND NOT DIV0 AND RUN AND NOT ADR(15).PIN) OR (NOT Teiler(9) AND DIV1 AND DIV0 AND RUN AND NOT ADR(15).PIN)); FDCPE_STOP: FDCPE port map (STOP,STOP_D,NOT STOP_OBUF/STOP_OBUF_CLKF__$INT.LFBK,'0',RESET); STOP_D <= ADR_15_OBUF.LFBK XOR STOP_D <= (ADR_14_OBUF.LFBK AND ADR(0).PIN AND ADR(4).PIN AND ADR(8).PIN AND ADR(12).PIN AND ADR(1).PIN AND ADR(5).PIN AND ADR(9).PIN AND ADR(10).PIN AND ADR(13).PIN AND ADR(2).PIN AND ADR(6).PIN AND ADR(11).PIN AND ADR(3).PIN AND ADR(7).PIN); STOP_OBUF/STOP_OBUF_CLKF__$INT <= ((CLK) OR (NOT M50 AND NOT DIV1 AND NOT DIV0 AND RUN AND NOT ADR_15_OBUF.LFBK) OR (NOT Teiler(9) AND DIV1 AND DIV0 AND RUN AND NOT ADR_15_OBUF.LFBK) OR (DIV1 AND NOT DIV0 AND RUN AND NOT Teiler(7).LFBK AND NOT ADR_15_OBUF.LFBK) OR (NOT DIV1 AND DIV0 AND RUN AND NOT Teiler(4).LFBK AND NOT ADR_15_OBUF.LFBK)); FTCPE_Teiler4: FTCPE port map (Teiler(4),Teiler_T(4),M50,'0','0'); Teiler_T(4) <= (XLXI_67/Q(0).LFBK AND XLXI_67/Q(1).LFBK AND XLXI_67/Q(2).LFBK AND XLXI_67/Q(3).LFBK); FTCPE_Teiler7: FTCPE port map (Teiler(7),Teiler_T(7),M50,'0','0'); Teiler_T(7) <= (XLXI_67/Q(0).LFBK AND XLXI_67/Q(1).LFBK AND XLXI_67/Q(2).LFBK AND XLXI_67/Q(3).LFBK AND Teiler(4).LFBK AND XLXI_67/Q(5).LFBK AND XLXI_67/Q(6).LFBK); FTCPE_Teiler9: FTCPE port map (Teiler(9),Teiler_T(9),M50,'0','0'); Teiler_T(9) <= (Teiler(4) AND XLXI_67/Q(0) AND XLXI_67/Q(1) AND XLXI_67/Q(5) AND Teiler(7) AND XLXI_67/Q(2) AND XLXI_67/Q(6) AND XLXI_67/Q(3) AND XLXI_67/Q(8)); WE <= NOT (((NOT M50 AND NOT DIV1 AND NOT DIV0 AND RUN AND NOT ADR(15).PIN) OR (NOT Teiler(4) AND NOT DIV1 AND DIV0 AND RUN AND NOT ADR(15).PIN) OR (NOT Teiler(7) AND DIV1 AND NOT DIV0 AND RUN AND NOT ADR(15).PIN) OR (NOT Teiler(9) AND DIV1 AND DIV0 AND RUN AND NOT ADR(15).PIN))); FTCPE_XLXI_67/Q0: FTCPE port map (XLXI_67/Q(0),'1',M50,'0','0'); FTCPE_XLXI_67/Q1: FTCPE port map (XLXI_67/Q(1),XLXI_67/Q(0).LFBK,M50,'0','0'); FTCPE_XLXI_67/Q2: FTCPE port map (XLXI_67/Q(2),XLXI_67/Q_T(2),M50,'0','0'); XLXI_67/Q_T(2) <= (XLXI_67/Q(0).LFBK AND XLXI_67/Q(1).LFBK); FTCPE_XLXI_67/Q3: FTCPE port map (XLXI_67/Q(3),XLXI_67/Q_T(3),M50,'0','0'); XLXI_67/Q_T(3) <= (XLXI_67/Q(0).LFBK AND XLXI_67/Q(1).LFBK AND XLXI_67/Q(2).LFBK); FTCPE_XLXI_67/Q5: FTCPE port map (XLXI_67/Q(5),XLXI_67/Q_T(5),M50,'0','0'); XLXI_67/Q_T(5) <= (XLXI_67/Q(0).LFBK AND XLXI_67/Q(1).LFBK AND XLXI_67/Q(2).LFBK AND XLXI_67/Q(3).LFBK AND Teiler(4).LFBK); FTCPE_XLXI_67/Q6: FTCPE port map (XLXI_67/Q(6),XLXI_67/Q_T(6),M50,'0','0'); XLXI_67/Q_T(6) <= (XLXI_67/Q(0).LFBK AND XLXI_67/Q(1).LFBK AND XLXI_67/Q(2).LFBK AND XLXI_67/Q(3).LFBK AND Teiler(4).LFBK AND XLXI_67/Q(5).LFBK); FTCPE_XLXI_67/Q8: FTCPE port map (XLXI_67/Q(8),XLXI_67/Q_T(8),M50,'0','0'); XLXI_67/Q_T(8) <= (XLXI_67/Q(0).LFBK AND XLXI_67/Q(1).LFBK AND XLXI_67/Q(2).LFBK AND XLXI_67/Q(3).LFBK AND Teiler(4).LFBK AND XLXI_67/Q(5).LFBK AND XLXI_67/Q(6).LFBK AND Teiler(7).LFBK); Register Legend: FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC9572-15-PC44 -------------------------------- /6 5 4 3 2 1 44 43 42 41 40 \ | 7 39 | | 8 38 | | 9 37 | | 10 36 | | 11 XC9572-15-PC44 35 | | 12 34 | | 13 33 | | 14 32 | | 15 31 | | 16 30 | | 17 29 | \ 18 19 20 21 22 23 24 25 26 27 28 / -------------------------------- Pin Signal Pin Signal No. Name No. Name 1 ADR<11> 23 GND 2 ADR<13> 24 AD_CLK 3 TIE 25 TIE 4 ADR<3> 26 STOP 5 M50 27 TIE 6 TIE 28 ADR<14> 7 TIE 29 ADR<15> 8 ADR<9> 30 TDO 9 ADR<10> 31 GND 10 GND 32 VCC 11 DIV1 33 RUN 12 OE 34 CS 13 WE 35 ADR<12> 14 CLK 36 ADR<4> 15 TDI 37 ADR<5> 16 TMS 38 ADR<6> 17 TCK 39 RESET 18 ADR<1> 40 TIE 19 ADR<2> 41 VCC 20 DIV0 42 TIE 21 VCC 43 ADR<7> 22 ADR<0> 44 ADR<8> Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9572-15-PC44 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON FASTConnect/UIM optimzation : ON Local Feedback : ON Pin Feedback : ON Input Limit : 36 Pterm Limit : 25