| Counter Project Status (08/05/2010 - 10:23:27) | |||
| Project File: | Counter.ise | Implementation State: | Placed and Routed |
| Module Name: | main |
|
No Errors |
| Target Device: | xc4vlx25-11sf363 |
|
19 Warnings |
| Product Version: | ISE 11.5 |
|
All Signals Completely Routed |
| Design Goal: | Balanced |
|
All Constraints Met |
| Design Strategy: | Xilinx Default (unlocked) |
|
0 (Setup: 0, Hold: 0) (Timing Report) |
| Device Utilization Summary | [-] | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) | |
| Number of Slice Flip Flops | 4 | 21,504 | 1% | ||
| Number of 4 input LUTs | 3 | 21,504 | 1% | ||
| Number of occupied Slices | 2 | 10,752 | 1% | ||
| Number of Slices containing only related logic | 2 | 2 | 100% | ||
| Number of Slices containing unrelated logic | 0 | 2 | 0% | ||
| Total Number of 4 input LUTs | 3 | 21,504 | 1% | ||
| Number of bonded IOBs | 5 | 240 | 2% | ||
| Number of BUFG/BUFGCTRLs | 1 | 32 | 3% | ||
| Number used as BUFGs | 1 | ||||
| Average Fanout of Non-Clock Nets | 2.21 | ||||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | All Constraints Met | |||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Do 5. Aug 10:17:01 2010 | 0 | 18 Warnings | 0 | |
| Translation Report | Current | Do 5. Aug 10:17:05 2010 | 0 | 0 | 0 | |
| Map Report | Current | Do 5. Aug 10:17:11 2010 | 0 | 0 | 3 Infos | |
| Place and Route Report | Current | Do 5. Aug 10:17:25 2010 | 0 | 1 Warning | 4 Infos | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Current | Do 5. Aug 10:17:32 2010 | 0 | 0 | 3 Infos | |
| Bitgen Report | Out of Date | Do 5. Aug 09:51:22 2010 | 0 | 0 | 1 Info | |
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Out of Date | Do 5. Aug 09:40:47 2010 | |
| Post-Synthesis Simulation Model Report | Out of Date | Do 5. Aug 09:53:05 2010 | |
| Post-Place and Route Simulation Model Report | Current | Do 5. Aug 13:17:43 2010 | |