cpldfit: version G.36 Xilinx Inc. Fitter Report Design Name: avga Date: 3- 5-2005, 3:34PM Device Used: XC95144XL-5-TQ100 Fitting Status: Successful **************************** Resource Summary **************************** Macrocells Product Terms Registers Pins Function Block Used Used Used Used Inputs Used 105/144 ( 73%) 489 /720 ( 68%) 54 /144 ( 37%) 73 /81 ( 90%) 201/432 ( 47%) PIN RESOURCES: Signal Type Required Mapped | Pin Type Used Remaining ------------------------------------|--------------------------------------- Input : 10 10 | I/O : 65 8 Output : 44 44 | GCK/IO : 3 0 Bidirectional : 16 16 | GTS/IO : 4 0 GCK : 3 3 | GSR/IO : 1 0 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 73 73 MACROCELL RESOURCES: Total Macrocells Available 144 Registered Macrocells 54 Non-registered Macrocell driving I/O 42 GLOBAL RESOURCES: Signal 'AVR_ALE' mapped onto global clock net GCK1. Signal 'AVR_WR' mapped onto global clock net GCK2. Signal 'Clock' mapped onto global clock net GCK3. Global output enable net(s) unused. Global set/reset net(s) unused. POWER DATA: There are 105 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). There are a total of 105 macrocells used (MC). End of Resource Summary **************************** Errors and Warnings ************************* WARNING:Cpld:896 - Unable to map all desired signals into function block, FB2, because too many function block product terms are required. Buffering output signal AVR_AD<5> to allow all signals assigned to this function block to be placed. WARNING:Cpld:896 - Unable to map all desired signals into function block, FB2, because too many function block product terms are required. Buffering output signal AVR_AD<4> to allow all signals assigned to this function block to be placed. WARNING:Cpld:896 - Unable to map all desired signals into function block, FB2, because too many function block product terms are required. Buffering output signal AVR_AD<0> to allow all signals assigned to this function block to be placed. WARNING:Cpld:896 - Unable to map all desired signals into function block, FB2, because too many function block product terms are required. Buffering output signal AVR_AD<3> to allow all signals assigned to this function block to be placed. *************** Summary of Required Resources ****************** ** LOGIC ** Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init Name Pt Used Mode Rate # Type Use State $OpTx$$OpTx$FX_DC$65_INV$93 1 8 FB2_7 STD (b) (b) AVR_AD<0> 2 2 FB2_9 STD FAST 4 GTS/I/O I/O AVR_AD<0>_BUFR 16 15 FB2_1 STD (b) (b) AVR_AD<1> 13 15 FB2_11 STD FAST 6 I/O I/O AVR_AD<2> 13 15 FB2_12 STD FAST 7 I/O I/O AVR_AD<3> 2 2 FB2_14 STD FAST 8 I/O I/O AVR_AD<3>_BUFR 12 14 FB8_18 STD (b) (b) AVR_AD<4> 2 2 FB2_15 STD FAST 9 I/O I/O AVR_AD<4>_BUFR 22 13 FB1_10 STD (b) (b) AVR_AD<5> 2 2 FB2_17 STD FAST 10 I/O I/O AVR_AD<5>_BUFR 22 13 FB3_4 STD (b) (b) AVR_AD<6> 23 14 FB1_2 STD FAST 11 I/O I/O AVR_AD<7> 23 14 FB1_3 STD FAST 12 I/O I/O AVR_AL<0> 3 2 FB4_6 STD FAST 90 I/O O RESET AVR_AL<1> 3 2 FB4_8 STD FAST 91 I/O O RESET AVR_AL<2> 3 2 FB4_9 STD FAST 92 I/O O RESET AVR_AL<3> 3 2 FB4_11 STD FAST 93 I/O O RESET AVR_AL<4> 3 2 FB4_12 STD FAST 94 I/O O RESET AVR_AL<5> 3 2 FB4_14 STD FAST 95 I/O O RESET AVR_AL<6> 3 2 FB4_15 STD FAST 96 I/O O RESET AVR_AL<7> 3 2 FB4_17 STD FAST 97 I/O O RESET AVR_Clock 0 0 FB3_6 STD FAST 25 I/O O RESET Addr<0> 3 5 FB5_1 STD (b) (b) RESET Addr<10> 6 15 FB7_18 STD (b) (b) RESET Addr<11> 6 16 FB7_16 STD (b) (b) RESET Addr<12> 6 17 FB7_13 STD (b) (b) RESET Addr<13> 6 18 FB7_10 STD (b) (b) RESET Addr<14> 6 19 FB7_7 STD (b) (b) RESET Addr<15> 6 20 FB7_5 STD 52 I/O (b) RESET Addr<16> 6 21 FB7_4 STD (b) (b) RESET Addr<17> 6 22 FB5_18 STD (b) (b) RESET Addr<18> 6 23 FB5_17 STD 49 I/O (b) RESET Addr<1> 5 6 FB5_3 STD (b) (b) RESET Addr<2> 6 7 FB5_16 STD (b) (b) RESET Addr<3> 6 8 FB5_13 STD (b) (b) RESET Addr<4> 6 9 FB5_10 STD (b) (b) RESET Addr<5> 6 10 FB5_7 STD (b) (b) RESET Addr<6> 6 11 FB5_4 STD (b) (b) RESET Addr<7> 6 12 FB7_3 STD (b) (b) RESET Addr<8> 6 13 FB7_2 STD 50 I/O (b) RESET Addr<9> 6 14 FB7_1 STD (b) (b) RESET Bank<0> 3 4 FB1_16 STD (b) (b) RESET Bank<1> 3 4 FB1_12 STD 18 I/O I RESET Bank<2> 3 4 FB1_13 STD (b) (b) RESET Bank<3> 3 4 FB1_14 STD 19 I/O I RESET CS_CPLD 2 10 FB8_16 STD (b) (b) RESET CS_CPLD/CS_CPLD_SETF__$INT 1 7 FB2_4 STD (b) (b) Ext_CS<0> 2 10 FB2_5 STD FAST 1 GTS/I/O O RESET Ext_CS<1> 2 10 FB2_6 STD FAST 2 GTS/I/O O RESET Ext_CS<2> 2 10 FB2_8 STD FAST 3 GTS/I/O O RESET Ext_CS_0/Ext_CS_0_SETF__$INT 2 9 FB2_16 STD (b) (b) Ext_CS_1/Ext_CS_1_SETF__$INT 1 8 FB2_3 STD (b) (b) Ext_CS_2/Ext_CS_2_SETF__$INT 1 8 FB2_2 STD 99 GSR/I/O I Flag<0> 3 4 FB1_15 STD 20 I/O I RESET HCounter<0> 4 9 FB3_10 STD (b) (b) RESET HCounter<1> 6 10 FB3_13 STD (b) (b) RESET HCounter<2> 7 11 FB3_1 STD (b) (b) RESET HCounter<3> 7 11 FB3_17 STD 34 I/O (b) RESET HCounter<4> 7 11 FB3_16 STD (b) (b) RESET HCounter<5> 7 11 FB3_14 STD 32 I/O (b) RESET HCounter<6> 4 10 FB3_8 STD 27 GCK/I/O GCK/I RESET HCounter<7> 4 11 FB3_7 STD (b) (b) RESET HCounter<8> 5 11 FB3_12 STD 30 I/O (b) RESET HCounter<9> 5 11 FB3_11 STD 29 I/O (b) RESET Mtrien_AVR_AD 2 4 FB8_13 STD (b) (b) RESET SRAM_Addr<0> 3 4 FB7_6 STD FAST 53 I/O O SRAM_Addr<10> 3 4 FB8_6 STD FAST 65 I/O O SRAM_Addr<11> 3 4 FB8_8 STD FAST 66 I/O O SRAM_Addr<12> 3 4 FB8_9 STD FAST 67 I/O O SRAM_Addr<13> 3 4 FB8_11 STD FAST 68 I/O O SRAM_Addr<14> 3 4 FB8_12 STD FAST 70 I/O O SRAM_Addr<15> 3 5 FB8_14 STD FAST 71 I/O O SRAM_Addr<16> 3 5 FB8_15 STD FAST 72 I/O O SRAM_Addr<17> 3 5 FB8_17 STD FAST 73 I/O O SRAM_Addr<18> 3 5 FB6_2 STD FAST 74 I/O O SRAM_Addr<1> 3 4 FB7_8 STD FAST 54 I/O O SRAM_Addr<2> 3 4 FB7_9 STD FAST 55 I/O O SRAM_Addr<3> 3 4 FB7_11 STD FAST 56 I/O O SRAM_Addr<4> 3 4 FB7_12 STD FAST 58 I/O O SRAM_Addr<5> 3 4 FB7_14 STD FAST 59 I/O O SRAM_Addr<6> 3 4 FB7_15 STD FAST 60 I/O O SRAM_Addr<7> 3 4 FB7_17 STD FAST 61 I/O O SRAM_Addr<8> 3 4 FB8_2 STD FAST 63 I/O O SRAM_Addr<9> 3 4 FB8_5 STD FAST 64 I/O O SRAM_CS 3 8 FB4_5 STD FAST 89 I/O O SRAM_Data<0> 2 4 FB6_5 STD FAST 76 I/O I/O SRAM_Data<1> 2 4 FB6_6 STD FAST 77 I/O I/O SRAM_Data<2> 2 4 FB6_8 STD FAST 78 I/O I/O SRAM_Data<3> 2 4 FB6_9 STD FAST 79 I/O I/O SRAM_Data<4> 2 4 FB6_11 STD FAST 80 I/O I/O SRAM_Data<5> 2 4 FB6_12 STD FAST 81 I/O I/O SRAM_Data<6> 2 4 FB6_14 STD FAST 82 I/O I/O SRAM_Data<7> 2 4 FB6_15 STD FAST 85 I/O I/O SRAM_OE 2 3 FB6_17 STD FAST 86 I/O O SRAM_WR 2 3 FB4_2 STD FAST 87 I/O O VGA_CSync 1 1 FB5_12 STD FAST 42 I/O O VGA_HSync 1 1 FB5_14 STD FAST 43 I/O O VGA_RGB<0> 5 6 FB5_11 STD FAST 41 I/O O RESET VGA_RGB<1> 5 6 FB5_9 STD FAST 40 I/O O RESET VGA_RGB<2> 5 6 FB5_8 STD FAST 39 I/O O RESET VGA_RGB<3> 5 6 FB5_6 STD FAST 37 I/O O RESET VGA_RGB<4> 5 6 FB5_5 STD FAST 36 I/O O RESET VGA_RGB<5> 5 6 FB5_2 STD FAST 35 I/O O RESET VGA_Trace 3 5 FB3_9 STD FAST 28 I/O O VGA_VSync 1 1 FB5_15 STD FAST 46 I/O O ** INPUTS ** Signal Loc Pin Pin Pin Name # Type Use AVR_AH<0> FB1_5 13 I/O I AVR_AH<1> FB1_6 14 I/O I AVR_AH<2> FB1_8 15 I/O I AVR_AH<3> FB1_9 16 I/O I AVR_AH<4> FB1_11 17 I/O I AVR_AH<5> FB1_12 18 I/O I AVR_AH<6> FB1_14 19 I/O I AVR_AH<7> FB1_15 20 I/O I AVR_ALE FB1_17 22 GCK/I/O GCK AVR_RD FB3_5 24 I/O I AVR_WR FB3_2 23 GCK/I/O GCK/I Clock FB3_8 27 GCK/I/O GCK/I Reset FB2_2 99 GSR/I/O I End of Resources *********************Function Block Resource Summary*********************** Function # of FB Inputs Signals Total O/IO IO Block Macrocells Used Used Pt Used Req Avail FB1 8 22 22 83 0/2 11 FB2 15 31 31 62 3/6 10 FB3 13 24 24 81 2/0 10 FB4 10 17 17 29 10/0 10 FB5 18 30 30 83 9/0 10 FB6 10 15 15 21 2/8 10 FB7 18 31 31 84 8/0 10 FB8 13 31 31 46 10/0 10 ---- ----- ----- ----- 105 489 44/16 81 *********************************** FB1 *********************************** Number of function block inputs used/remaining: 22/32 Number of signals used by logic mapping into function block: 22 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 \/5 0 FB1_1 (b) (b) AVR_AD<6> 23 18<- 0 0 FB1_2 STD 11 I/O I/O AVR_AD<7> 23 20<- /\2 0 FB1_3 STD 12 I/O I/O (unused) 0 0 /\5 0 FB1_4 (b) (b) (unused) 0 0 /\5 0 FB1_5 13 I/O I (unused) 0 0 /\5 0 FB1_6 14 I/O I (unused) 0 0 /\5 0 FB1_7 (b) (b) (unused) 0 0 \/5 0 FB1_8 15 I/O I (unused) 0 0 \/5 0 FB1_9 16 I/O I AVR_AD<4>_BUFR 22 17<- 0 0 FB1_10 STD (b) (b) (unused) 0 0 /\5 0 FB1_11 17 I/O I Bank<1> 3 0 /\2 0 FB1_12 STD 18 I/O I Bank<2> 3 0 0 2 FB1_13 STD (b) (b) Bank<3> 3 0 0 2 FB1_14 STD 19 I/O I Flag<0> 3 0 0 2 FB1_15 STD 20 I/O I Bank<0> 3 0 \/1 1 FB1_16 STD (b) (b) (unused) 0 0 \/5 0 FB1_17 22 GCK/I/O GCK (unused) 0 0 \/5 0 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: AVR_AD<4> 9: AVR_AH<7> 16: SRAM_Data<6>.PIN 2: AVR_AD<6> 10: AVR_AL<0> 17: SRAM_Data<7>.PIN 3: AVR_AD<7> 11: AVR_RD 18: Reset 4: AVR_AH<2> 12: CS_CPLD 19: AVR_AD<0>.PIN 5: AVR_AH<3> 13: Clock 20: AVR_AD<1>.PIN 6: AVR_AH<4> 14: Mtrien_AVR_AD 21: AVR_AD<2>.PIN 7: AVR_AH<5> 15: SRAM_Data<4>.PIN 22: AVR_AD<3>.PIN 8: AVR_AH<6> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs AVR_AD<6> .X.XXXXXXXXXXX.X.X...................... 14 14 AVR_AD<7> ..XXXXXXXXXXXX..XX...................... 14 14 AVR_AD<4>_BUFR X..XXXXXXXXXX.X..X...................... 13 13 Bank<1> .........X.X.....X.X.................... 4 4 Bank<2> .........X.X.....X..X................... 4 4 Bank<3> .........X.X.....X...X.................. 4 4 Flag<0> .........X.X.....XX..................... 4 4 Bank<0> .........X.X.....XX..................... 4 4 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB2 *********************************** Number of function block inputs used/remaining: 31/23 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use AVR_AD<0>_BUFR 16 11<- 0 0 FB2_1 STD (b) (b) Ext_CS_2/Ext_CS_2_SETF__$INT 1 1<- /\5 0 FB2_2 STD 99 GSR/I/O I Ext_CS_1/Ext_CS_1_SETF__$INT 1 0 /\1 3 FB2_3 STD (b) (b) CS_CPLD/CS_CPLD_SETF__$INT 1 0 0 4 FB2_4 STD (b) (b) Ext_CS<0> 2 0 0 3 FB2_5 STD 1 GTS/I/O O Ext_CS<1> 2 0 0 3 FB2_6 STD 2 GTS/I/O O $OpTx$$OpTx$FX_DC$65_INV$93 1 0 0 4 FB2_7 STD (b) (b) Ext_CS<2> 2 0 0 3 FB2_8 STD 3 GTS/I/O O AVR_AD<0> 2 0 \/3 0 FB2_9 STD 4 GTS/I/O I/O (unused) 0 0 \/5 0 FB2_10 (b) (b) AVR_AD<1> 13 8<- 0 0 FB2_11 STD 6 I/O I/O AVR_AD<2> 13 8<- 0 0 FB2_12 STD 7 I/O I/O (unused) 0 0 /\5 0 FB2_13 (b) (b) AVR_AD<3> 2 0 /\3 0 FB2_14 STD 8 I/O I/O AVR_AD<4> 2 0 0 3 FB2_15 STD 9 I/O I/O Ext_CS_0/Ext_CS_0_SETF__$INT 2 0 0 3 FB2_16 STD (b) (b) AVR_AD<5> 2 0 \/1 2 FB2_17 STD 10 I/O I/O (unused) 0 0 \/5 0 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: AVR_AD<0> 12: AVR_AH<4> 22: Clock 2: AVR_AD<0>_BUFR 13: AVR_AH<5> 23: Ext_CS_0/Ext_CS_0_SETF__$INT 3: AVR_AD<1> 14: AVR_AH<6> 24: Ext_CS_1/Ext_CS_1_SETF__$INT 4: AVR_AD<2> 15: AVR_AH<7> 25: Ext_CS_2/Ext_CS_2_SETF__$INT 5: AVR_AD<3>_BUFR 16: AVR_AL<0> 26: Flag<0> 6: AVR_AD<4>_BUFR 17: AVR_RD 27: Mtrien_AVR_AD 7: AVR_AD<5>_BUFR 18: Bank<0> 28: SRAM_Data<0>.PIN 8: AVR_AH<0> 19: Bank<1> 29: SRAM_Data<1>.PIN 9: AVR_AH<1> 20: Bank<2> 30: SRAM_Data<2>.PIN 10: AVR_AH<2> 21: CS_CPLD 31: Reset 11: AVR_AH<3> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs AVR_AD<0>_BUFR X........XXXXXXXXX..XX...X.X..X......... 15 15 Ext_CS_2/Ext_CS_2_SETF__$INT ........XXXXXXX...............X......... 8 8 Ext_CS_1/Ext_CS_1_SETF__$INT .......X.XXXXXX...............X......... 8 8 CS_CPLD/CS_CPLD_SETF__$INT .........XXXXXX...............X......... 7 7 Ext_CS<0> .......XXXXXXXX.......X.......X......... 10 10 Ext_CS<1> .......XXXXXXXX........X......X......... 10 10 $OpTx$$OpTx$FX_DC$65_INV$93 .........XXXXXX.....X.........X......... 8 8 Ext_CS<2> .......XXXXXXXX.........X.....X......... 10 10 AVR_AD<0> .X........................X............. 2 2 AVR_AD<1> ..X......XXXXXXXX.X.XX....X.X.X......... 15 15 AVR_AD<2> ...X.....XXXXXXXX..XXX....X..XX......... 15 15 AVR_AD<3> ....X.....................X............. 2 2 AVR_AD<4> .....X....................X............. 2 2 Ext_CS_0/Ext_CS_0_SETF__$INT .......XXXXXXXX...............X......... 9 9 AVR_AD<5> ......X...................X............. 2 2 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB3 *********************************** Number of function block inputs used/remaining: 24/30 Number of signals used by logic mapping into function block: 24 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use HCounter<2> 7 2<- 0 0 FB3_1 STD (b) (b) (unused) 0 0 \/3 2 FB3_2 23 GCK/I/O GCK/I (unused) 0 0 \/5 0 FB3_3 (b) (b) AVR_AD<5>_BUFR 22 17<- 0 0 FB3_4 STD (b) (b) (unused) 0 0 /\5 0 FB3_5 24 I/O I AVR_Clock 0 0 /\4 1 FB3_6 STD 25 I/O O HCounter<7> 4 0 0 1 FB3_7 STD (b) (b) HCounter<6> 4 0 0 1 FB3_8 STD 27 GCK/I/O GCK/I VGA_Trace 3 0 \/2 0 FB3_9 STD 28 I/O O HCounter<0> 4 2<- \/3 0 FB3_10 STD (b) (b) HCounter<9> 5 3<- \/3 0 FB3_11 STD 29 I/O (b) HCounter<8> 5 3<- \/3 0 FB3_12 STD 30 I/O (b) HCounter<1> 6 3<- \/2 0 FB3_13 STD (b) (b) HCounter<5> 7 2<- 0 0 FB3_14 STD 32 I/O (b) (unused) 0 0 \/4 1 FB3_15 33 I/O (b) HCounter<4> 7 4<- \/2 0 FB3_16 STD (b) (b) HCounter<3> 7 2<- 0 0 FB3_17 STD 34 I/O (b) (unused) 0 0 \/2 3 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: AVR_AD<5> 9: AVR_RD 17: HCounter<4> 2: AVR_AH<2> 10: CS_CPLD 18: HCounter<5> 3: AVR_AH<3> 11: Clock 19: HCounter<6> 4: AVR_AH<4> 12: Flag<0> 20: HCounter<7> 5: AVR_AH<5> 13: HCounter<0> 21: HCounter<8> 6: AVR_AH<6> 14: HCounter<1> 22: HCounter<9> 7: AVR_AH<7> 15: HCounter<2> 23: SRAM_Data<5>.PIN 8: AVR_AL<0> 16: HCounter<3> 24: Reset Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs HCounter<2> ...........XXXXXXXXXXX.................. 11 11 AVR_AD<5>_BUFR XXXXXXXXXXX...........XX................ 13 13 AVR_Clock ........................................ 0 0 HCounter<7> ...........XXXXXXXXXXX.................. 11 11 HCounter<6> ...........XXXXXXXX.XX.................. 10 10 VGA_Trace ...........X.......XXX.X................ 5 5 HCounter<0> ...........XX..XXXXXXX.................. 9 9 HCounter<9> ...........XXXXXXXXXXX.................. 11 11 HCounter<8> ...........XXXXXXXXXXX.................. 11 11 HCounter<1> ...........XXX.XXXXXXX.................. 10 10 HCounter<5> ...........XXXXXXXXXXX.................. 11 11 HCounter<4> ...........XXXXXXXXXXX.................. 11 11 HCounter<3> ...........XXXXXXXXXXX.................. 11 11 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB4 *********************************** Number of function block inputs used/remaining: 17/37 Number of signals used by logic mapping into function block: 17 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB4_1 (b) SRAM_WR 2 0 0 3 FB4_2 STD 87 I/O O (unused) 0 0 0 5 FB4_3 (b) (unused) 0 0 0 5 FB4_4 (b) SRAM_CS 3 0 0 2 FB4_5 STD 89 I/O O AVR_AL<0> 3 0 0 2 FB4_6 STD 90 I/O O (unused) 0 0 0 5 FB4_7 (b) AVR_AL<1> 3 0 0 2 FB4_8 STD 91 I/O O AVR_AL<2> 3 0 0 2 FB4_9 STD 92 I/O O (unused) 0 0 0 5 FB4_10 (b) AVR_AL<3> 3 0 0 2 FB4_11 STD 93 I/O O AVR_AL<4> 3 0 0 2 FB4_12 STD 94 I/O O (unused) 0 0 0 5 FB4_13 (b) AVR_AL<5> 3 0 0 2 FB4_14 STD 95 I/O O AVR_AL<6> 3 0 0 2 FB4_15 STD 96 I/O O (unused) 0 0 0 5 FB4_16 (b) AVR_AL<7> 3 0 0 2 FB4_17 STD 97 I/O O (unused) 0 0 0 5 FB4_18 (b) Signals Used by Logic in Function Block 1: AVR_AH<2> 7: AVR_WR 13: AVR_AD<3>.PIN 2: AVR_AH<3> 8: Clock 14: AVR_AD<4>.PIN 3: AVR_AH<4> 9: Reset 15: AVR_AD<5>.PIN 4: AVR_AH<5> 10: AVR_AD<0>.PIN 16: AVR_AD<6>.PIN 5: AVR_AH<6> 11: AVR_AD<1>.PIN 17: AVR_AD<7>.PIN 6: AVR_AH<7> 12: AVR_AD<2>.PIN Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs SRAM_WR ......XXX............................... 3 3 SRAM_CS XXXXXX.XX............................... 8 8 AVR_AL<0> ........XX.............................. 2 2 AVR_AL<1> ........X.X............................. 2 2 AVR_AL<2> ........X..X............................ 2 2 AVR_AL<3> ........X...X........................... 2 2 AVR_AL<4> ........X....X.......................... 2 2 AVR_AL<5> ........X.....X......................... 2 2 AVR_AL<6> ........X......X........................ 2 2 AVR_AL<7> ........X.......X....................... 2 2 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB5 *********************************** Number of function block inputs used/remaining: 30/24 Number of signals used by logic mapping into function block: 30 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use Addr<0> 3 0 \/1 1 FB5_1 STD (b) (b) VGA_RGB<5> 5 1<- \/1 0 FB5_2 STD 35 I/O O Addr<1> 5 1<- \/1 0 FB5_3 STD (b) (b) Addr<6> 6 1<- 0 0 FB5_4 STD (b) (b) VGA_RGB<4> 5 0 0 0 FB5_5 STD 36 I/O O VGA_RGB<3> 5 0 0 0 FB5_6 STD 37 I/O O Addr<5> 6 1<- 0 0 FB5_7 STD (b) (b) VGA_RGB<2> 5 1<- /\1 0 FB5_8 STD 39 I/O O VGA_RGB<1> 5 1<- /\1 0 FB5_9 STD 40 I/O O Addr<4> 6 2<- /\1 0 FB5_10 STD (b) (b) VGA_RGB<0> 5 2<- /\2 0 FB5_11 STD 41 I/O O VGA_CSync 1 0 /\2 2 FB5_12 STD 42 I/O O Addr<3> 6 1<- 0 0 FB5_13 STD (b) (b) VGA_HSync 1 0 /\1 3 FB5_14 STD 43 I/O O VGA_VSync 1 0 \/3 1 FB5_15 STD 46 I/O O Addr<2> 6 3<- \/2 0 FB5_16 STD (b) (b) Addr<18> 6 2<- \/1 0 FB5_17 STD 49 I/O (b) Addr<17> 6 1<- 0 0 FB5_18 STD (b) (b) Signals Used by Logic in Function Block 1: Addr<0> 11: Addr<1> 21: HCounter<7> 2: Addr<10> 12: Addr<2> 22: HCounter<8> 3: Addr<11> 13: Addr<3> 23: HCounter<9> 4: Addr<12> 14: Addr<4> 24: SRAM_Data<0>.PIN 5: Addr<13> 15: Addr<5> 25: SRAM_Data<1>.PIN 6: Addr<14> 16: Addr<6> 26: SRAM_Data<2>.PIN 7: Addr<15> 17: Addr<7> 27: SRAM_Data<3>.PIN 8: Addr<16> 18: Addr<8> 28: SRAM_Data<4>.PIN 9: Addr<17> 19: Addr<9> 29: SRAM_Data<5>.PIN 10: Addr<18> 20: Flag<0> 30: Reset Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs Addr<0> X..................XXXX................. 5 5 VGA_RGB<5> ...................XXXX.....XX.......... 6 6 Addr<1> X.........X........XXXX................. 6 6 Addr<6> X.........XXXXXX...XXXX................. 11 11 VGA_RGB<4> ...................XXXX....X.X.......... 6 6 VGA_RGB<3> ...................XXXX...X..X.......... 6 6 Addr<5> X.........XXXXX....XXXX................. 10 10 VGA_RGB<2> ...................XXXX..X...X.......... 6 6 VGA_RGB<1> ...................XXXX.X....X.......... 6 6 Addr<4> X.........XXXX.....XXXX................. 9 9 VGA_RGB<0> ...................XXXXX.....X.......... 6 6 VGA_CSync .............................X.......... 1 1 Addr<3> X.........XXX......XXXX................. 8 8 VGA_HSync .............................X.......... 1 1 VGA_VSync .............................X.......... 1 1 Addr<2> X.........XX.......XXXX................. 7 7 Addr<18> XXXXXXXXXXXXXXXXXXXXXXX................. 23 23 Addr<17> XXXXXXXXX.XXXXXXXXXXXXX................. 22 22 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB6 *********************************** Number of function block inputs used/remaining: 15/39 Number of signals used by logic mapping into function block: 15 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB6_1 (b) SRAM_Addr<18> 3 0 0 2 FB6_2 STD 74 I/O O (unused) 0 0 0 5 FB6_3 (b) (unused) 0 0 0 5 FB6_4 (b) SRAM_Data<0> 2 0 0 3 FB6_5 STD 76 I/O I/O SRAM_Data<1> 2 0 0 3 FB6_6 STD 77 I/O I/O (unused) 0 0 0 5 FB6_7 (b) SRAM_Data<2> 2 0 0 3 FB6_8 STD 78 I/O I/O SRAM_Data<3> 2 0 0 3 FB6_9 STD 79 I/O I/O (unused) 0 0 0 5 FB6_10 (b) SRAM_Data<4> 2 0 0 3 FB6_11 STD 80 I/O I/O SRAM_Data<5> 2 0 0 3 FB6_12 STD 81 I/O I/O (unused) 0 0 0 5 FB6_13 (b) SRAM_Data<6> 2 0 0 3 FB6_14 STD 82 I/O I/O SRAM_Data<7> 2 0 0 3 FB6_15 STD 85 I/O I/O (unused) 0 0 0 5 FB6_16 (b) SRAM_OE 2 0 0 3 FB6_17 STD 86 I/O O (unused) 0 0 0 5 FB6_18 (b) Signals Used by Logic in Function Block 1: AVR_AH<7> 6: Clock 11: AVR_AD<3>.PIN 2: AVR_RD 7: Reset 12: AVR_AD<4>.PIN 3: AVR_WR 8: AVR_AD<0>.PIN 13: AVR_AD<5>.PIN 4: Addr<18> 9: AVR_AD<1>.PIN 14: AVR_AD<6>.PIN 5: Bank<3> 10: AVR_AD<2>.PIN 15: AVR_AD<7>.PIN Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs SRAM_Addr<18> X..XXXX................................. 5 5 SRAM_Data<0> ..X..XXX................................ 4 4 SRAM_Data<1> ..X..XX.X............................... 4 4 SRAM_Data<2> ..X..XX..X.............................. 4 4 SRAM_Data<3> ..X..XX...X............................. 4 4 SRAM_Data<4> ..X..XX....X............................ 4 4 SRAM_Data<5> ..X..XX.....X........................... 4 4 SRAM_Data<6> ..X..XX......X.......................... 4 4 SRAM_Data<7> ..X..XX.......X......................... 4 4 SRAM_OE .X...XX................................. 3 3 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB7 *********************************** Number of function block inputs used/remaining: 31/23 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use Addr<9> 6 2<- \/1 0 FB7_1 STD (b) (b) Addr<8> 6 1<- 0 0 FB7_2 STD 50 I/O (b) Addr<7> 6 1<- 0 0 FB7_3 STD (b) (b) Addr<16> 6 2<- /\1 0 FB7_4 STD (b) (b) Addr<15> 6 3<- /\2 0 FB7_5 STD 52 I/O (b) SRAM_Addr<0> 3 1<- /\3 0 FB7_6 STD 53 I/O O Addr<14> 6 2<- /\1 0 FB7_7 STD (b) (b) SRAM_Addr<1> 3 0 /\2 0 FB7_8 STD 54 I/O O SRAM_Addr<2> 3 0 0 2 FB7_9 STD 55 I/O O Addr<13> 6 1<- 0 0 FB7_10 STD (b) (b) SRAM_Addr<3> 3 0 /\1 1 FB7_11 STD 56 I/O O SRAM_Addr<4> 3 0 \/1 1 FB7_12 STD 58 I/O O Addr<12> 6 1<- 0 0 FB7_13 STD (b) (b) SRAM_Addr<5> 3 0 0 2 FB7_14 STD 59 I/O O SRAM_Addr<6> 3 0 \/2 0 FB7_15 STD 60 I/O O Addr<11> 6 2<- \/1 0 FB7_16 STD (b) (b) SRAM_Addr<7> 3 1<- \/3 0 FB7_17 STD 61 I/O O Addr<10> 6 3<- \/2 0 FB7_18 STD (b) (b) Signals Used by Logic in Function Block 1: AVR_AL<0> 12: Addr<12> 22: Addr<6> 2: AVR_AL<1> 13: Addr<13> 23: Addr<7> 3: AVR_AL<2> 14: Addr<14> 24: Addr<8> 4: AVR_AL<3> 15: Addr<15> 25: Addr<9> 5: AVR_AL<4> 16: Addr<16> 26: Clock 6: AVR_AL<5> 17: Addr<1> 27: Flag<0> 7: AVR_AL<6> 18: Addr<2> 28: HCounter<7> 8: AVR_AL<7> 19: Addr<3> 29: HCounter<8> 9: Addr<0> 20: Addr<4> 30: HCounter<9> 10: Addr<10> 21: Addr<5> 31: Reset 11: Addr<11> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs Addr<9> ........X.......XXXXXXXXX.XXXX.......... 14 14 Addr<8> ........X.......XXXXXXXX..XXXX.......... 13 13 Addr<7> ........X.......XXXXXXX...XXXX.......... 12 12 Addr<16> ........XXXXXXXXXXXXXXXXX.XXXX.......... 21 21 Addr<15> ........XXXXXXX.XXXXXXXXX.XXXX.......... 20 20 SRAM_Addr<0> X.......X................X....X......... 4 4 Addr<14> ........XXXXXX..XXXXXXXXX.XXXX.......... 19 19 SRAM_Addr<1> .X..............X........X....X......... 4 4 SRAM_Addr<2> ..X..............X.......X....X......... 4 4 Addr<13> ........XXXXX...XXXXXXXXX.XXXX.......... 18 18 SRAM_Addr<3> ...X..............X......X....X......... 4 4 SRAM_Addr<4> ....X..............X.....X....X......... 4 4 Addr<12> ........XXXX....XXXXXXXXX.XXXX.......... 17 17 SRAM_Addr<5> .....X..............X....X....X......... 4 4 SRAM_Addr<6> ......X..............X...X....X......... 4 4 Addr<11> ........XXX.....XXXXXXXXX.XXXX.......... 16 16 SRAM_Addr<7> .......X..............X..X....X......... 4 4 Addr<10> ........XX......XXXXXXXXX.XXXX.......... 15 15 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB8 *********************************** Number of function block inputs used/remaining: 31/23 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 /\5 0 FB8_1 (b) (b) SRAM_Addr<8> 3 0 0 2 FB8_2 STD 63 I/O O (unused) 0 0 0 5 FB8_3 (b) (unused) 0 0 0 5 FB8_4 (b) SRAM_Addr<9> 3 0 0 2 FB8_5 STD 64 I/O O SRAM_Addr<10> 3 0 0 2 FB8_6 STD 65 I/O O (unused) 0 0 0 5 FB8_7 (b) SRAM_Addr<11> 3 0 0 2 FB8_8 STD 66 I/O O SRAM_Addr<12> 3 0 0 2 FB8_9 STD 67 I/O O (unused) 0 0 0 5 FB8_10 (b) SRAM_Addr<13> 3 0 0 2 FB8_11 STD 68 I/O O SRAM_Addr<14> 3 0 0 2 FB8_12 STD 70 I/O O Mtrien_AVR_AD 2 0 0 3 FB8_13 STD (b) (b) SRAM_Addr<15> 3 0 0 2 FB8_14 STD 71 I/O O SRAM_Addr<16> 3 0 0 2 FB8_15 STD 72 I/O O CS_CPLD 2 0 0 3 FB8_16 STD (b) (b) SRAM_Addr<17> 3 0 \/2 0 FB8_17 STD 73 I/O O AVR_AD<3>_BUFR 12 7<- 0 0 FB8_18 STD (b) (b) Signals Used by Logic in Function Block 1: $OpTx$$OpTx$FX_DC$65_INV$93 12: AVR_RD 22: Addr<9> 2: AVR_AD<3> 13: Addr<10> 23: Bank<0> 3: AVR_AH<0> 14: Addr<11> 24: Bank<1> 4: AVR_AH<1> 15: Addr<12> 25: Bank<2> 5: AVR_AH<2> 16: Addr<13> 26: Bank<3> 6: AVR_AH<3> 17: Addr<14> 27: CS_CPLD 7: AVR_AH<4> 18: Addr<15> 28: CS_CPLD/CS_CPLD_SETF__$INT 8: AVR_AH<5> 19: Addr<16> 29: Clock 9: AVR_AH<6> 20: Addr<17> 30: SRAM_Data<3>.PIN 10: AVR_AH<7> 21: Addr<8> 31: Reset 11: AVR_AL<0> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs SRAM_Addr<8> ..X.................X.......X.X......... 4 4 SRAM_Addr<9> ...X.................X......X.X......... 4 4 SRAM_Addr<10> ....X.......X...............X.X......... 4 4 SRAM_Addr<11> .....X.......X..............X.X......... 4 4 SRAM_Addr<12> ......X.......X.............X.X......... 4 4 SRAM_Addr<13> .......X.......X............X.X......... 4 4 SRAM_Addr<14> ........X.......X...........X.X......... 4 4 Mtrien_AVR_AD X..........X................X.X......... 4 4 SRAM_Addr<15> .........X.......X....X.....X.X......... 5 5 SRAM_Addr<16> .........X........X....X....X.X......... 5 5 CS_CPLD ..XXXXXXXX.................X..X......... 10 10 SRAM_Addr<17> .........X.........X....X...X.X......... 5 5 AVR_AD<3>_BUFR .X..XXXXXXXX.............XX.XXX......... 14 14 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. ;;-----------------------------------------------------------------;; ; Implemented Equations. $OpTx$$OpTx$FX_DC$65_INV$93 <= (Reset AND AVR_AH(6) AND AVR_AH(5) AND AVR_AH(4) AND AVR_AH(3) AND AVR_AH(2) AND CS_CPLD AND NOT AVR_AH(7)); AVR_AD(0)_BUFR <= ((Ext_CS_2/Ext_CS_2_SETF__$INT.EXP) OR (EXP30_.EXP) OR (AVR_AD(0) AND Clock) OR (AVR_AD(0) AND AVR_RD) OR (AVR_AD(0) AND NOT Reset AND CS_CPLD) OR (AVR_AD(0) AND NOT Reset AND Flag(0) AND AVR_AL(0)) OR (SRAM_Data(0).PIN AND Reset AND NOT Clock AND NOT AVR_AH(2) AND NOT AVR_RD)); AVR_AD(3)_BUFR <= ((EXP36_.EXP) OR (SRAM_Addr_17_OBUFE.EXP) OR (AVR_AD(3) AND Clock) OR (AVR_AD(3) AND AVR_RD) OR (AVR_AD(3) AND NOT Reset AND CS_CPLD) OR (Reset AND NOT Clock AND SRAM_Data(3).PIN AND NOT AVR_AH(3) AND NOT AVR_RD) OR (Reset AND NOT Clock AND SRAM_Data(3).PIN AND NOT AVR_AH(2) AND NOT AVR_RD)); AVR_AD(4)_BUFR <= ((EXP24_.EXP) OR (EXP25_.EXP) OR (AVR_AD(4) AND Clock) OR (AVR_AD(4) AND AVR_RD) OR (AVR_AD(4) AND NOT Reset AND CS_CPLD) OR (Reset AND NOT Clock AND SRAM_Data(4).PIN AND NOT AVR_AH(3) AND NOT AVR_RD) OR (Reset AND NOT Clock AND SRAM_Data(4).PIN AND NOT AVR_AH(2) AND NOT AVR_RD)); AVR_AD(5)_BUFR <= ((EXP32_.EXP) OR (EXP33_.EXP) OR (AVR_AD(5) AND Clock) OR (AVR_AD(5) AND AVR_RD) OR (AVR_AD(5) AND NOT Reset AND CS_CPLD) OR (Reset AND NOT Clock AND SRAM_Data(5).PIN AND NOT AVR_AH(3) AND NOT AVR_RD) OR (Reset AND NOT Clock AND SRAM_Data(5).PIN AND NOT AVR_AH(2) AND NOT AVR_RD)); FTCPE_Addr0: FTCPE port map (Addr(0),Addr_T(0),NOT Clock,NOT Flag(0),'0'); Addr_T(0) <= ((Flag(0) AND NOT Addr(0) AND NOT HCounter(9)) OR (Flag(0) AND NOT Addr(0) AND NOT HCounter(7) AND NOT HCounter(8))); FTCPE_Addr10: FTCPE port map (Addr(10),Addr_T(10),NOT Clock,NOT Flag(0),'0'); Addr_T(10) <= ((SRAM_Addr_7_OBUFE.EXP) OR (Flag(0) AND Addr(10) AND NOT HCounter(9)) OR (Flag(0) AND Addr(10) AND NOT HCounter(7) AND NOT HCounter(8))); FTCPE_Addr11: FTCPE port map (Addr(11),Addr_T(11),NOT Clock,NOT Flag(0),'0'); Addr_T(11) <= ((SRAM_Addr_6_OBUFE.EXP) OR (Flag(0) AND Addr(11) AND NOT HCounter(9)) OR (Flag(0) AND Addr(11) AND NOT HCounter(7) AND NOT HCounter(8)) OR (NOT Flag(0) AND Addr(0) AND Addr(1) AND Addr(5) AND Addr(9) AND Addr(10) AND Addr(2) AND Addr(3) AND Addr(6) AND Addr(7) AND Addr(4) AND Addr(8))); FTCPE_Addr12: FTCPE port map (Addr(12),Addr_T(12),NOT Clock,NOT Flag(0),'0'); Addr_T(12) <= ((SRAM_Addr_4_OBUFE.EXP) OR (Flag(0) AND Addr(12) AND NOT HCounter(9)) OR (Flag(0) AND NOT HCounter(7) AND NOT HCounter(8) AND Addr(12)) OR (NOT Flag(0) AND Addr(0) AND Addr(1) AND Addr(5) AND Addr(9) AND Addr(10) AND Addr(11) AND Addr(2) AND Addr(3) AND Addr(6) AND Addr(7) AND Addr(4) AND Addr(8)) OR (Addr(0) AND Addr(1) AND Addr(5) AND Addr(9) AND Addr(10) AND Addr(11) AND Addr(2) AND Addr(3) AND Addr(6) AND Addr(7) AND HCounter(7) AND Addr(4) AND Addr(8) AND HCounter(9))); FTCPE_Addr13: FTCPE port map (Addr(13),Addr_T(13),NOT Clock,NOT Flag(0),'0'); Addr_T(13) <= ((SRAM_Addr_3_OBUFE.EXP) OR (Flag(0) AND Addr(13) AND NOT HCounter(9)) OR (Flag(0) AND Addr(13) AND NOT HCounter(7) AND NOT HCounter(8)) OR (NOT Flag(0) AND Addr(0) AND Addr(1) AND Addr(5) AND Addr(9) AND Addr(10) AND Addr(11) AND Addr(2) AND Addr(3) AND Addr(6) AND Addr(7) AND Addr(12) AND Addr(4) AND Addr(8)) OR (Addr(0) AND Addr(1) AND Addr(5) AND Addr(9) AND Addr(10) AND Addr(11) AND Addr(2) AND Addr(3) AND Addr(6) AND Addr(7) AND HCounter(7) AND Addr(12) AND Addr(4) AND Addr(8) AND HCounter(9))); FTCPE_Addr14: FTCPE port map (Addr(14),Addr_T(14),NOT Clock,NOT Flag(0),'0'); Addr_T(14) <= ((SRAM_Addr_1_OBUFE.EXP) OR (Flag(0) AND Addr(14) AND NOT HCounter(9)) OR (Flag(0) AND Addr(14) AND NOT HCounter(7) AND NOT HCounter(8)) OR (NOT Flag(0) AND Addr(0) AND Addr(13) AND Addr(1) AND Addr(5) AND Addr(9) AND Addr(10) AND Addr(11) AND Addr(2) AND Addr(3) AND Addr(6) AND Addr(7) AND Addr(12) AND Addr(4) AND Addr(8))); FTCPE_Addr15: FTCPE port map (Addr(15),Addr_T(15),NOT Clock,'0',NOT Flag(0)); Addr_T(15) <= ((SRAM_Addr_0_OBUFE.EXP) OR (Addr(0) AND Addr(13) AND Addr(1) AND Addr(5) AND Addr(9) AND Addr(10) AND Addr(11) AND Addr(14) AND Addr(2) AND Addr(3) AND Addr(6) AND Addr(7) AND HCounter(7) AND Addr(12) AND Addr(4) AND Addr(8) AND HCounter(9)) OR (Addr(0) AND Addr(13) AND Addr(1) AND Addr(5) AND Addr(9) AND Addr(10) AND Addr(11) AND Addr(14) AND Addr(2) AND Addr(3) AND Addr(6) AND Addr(7) AND HCounter(8) AND Addr(12) AND Addr(4) AND Addr(8) AND HCounter(9))); FTCPE_Addr16: FTCPE port map (Addr(16),Addr_T(16),NOT Clock,NOT Flag(0),'0'); Addr_T(16) <= ((Addr(15).EXP) OR (Flag(0) AND Addr(16) AND NOT HCounter(9)) OR (Flag(0) AND Addr(16) AND NOT HCounter(7) AND NOT HCounter(8)) OR (NOT Flag(0) AND Addr(0) AND Addr(13) AND Addr(15) AND Addr(1) AND Addr(5) AND Addr(9) AND Addr(10) AND Addr(11) AND Addr(14) AND Addr(2) AND Addr(3) AND Addr(6) AND Addr(7) AND Addr(12) AND Addr(4) AND Addr(8))); FTCPE_Addr17: FTCPE port map (Addr(17),Addr_T(17),NOT Clock,NOT Flag(0),'0'); Addr_T(17) <= ((Addr(18).EXP) OR (Flag(0) AND Addr(17) AND NOT HCounter(9)) OR (Flag(0) AND NOT HCounter(7) AND NOT HCounter(8) AND Addr(17)) OR (NOT Flag(0) AND Addr(0) AND Addr(13) AND Addr(15) AND Addr(1) AND Addr(5) AND Addr(9) AND Addr(10) AND Addr(11) AND Addr(14) AND Addr(16) AND Addr(2) AND Addr(3) AND Addr(6) AND Addr(7) AND Addr(12) AND Addr(4) AND Addr(8)) OR (Addr(0) AND Addr(13) AND Addr(15) AND Addr(1) AND Addr(5) AND Addr(9) AND Addr(10) AND Addr(11) AND Addr(14) AND Addr(16) AND Addr(2) AND Addr(3) AND Addr(6) AND Addr(7) AND HCounter(7) AND Addr(12) AND Addr(4) AND Addr(8) AND HCounter(9))); FTCPE_Addr18: FTCPE port map (Addr(18),Addr_T(18),NOT Clock,NOT Flag(0),'0'); Addr_T(18) <= ((Addr(2).EXP) OR (Flag(0) AND NOT HCounter(9) AND Addr(18)) OR (Flag(0) AND NOT HCounter(7) AND NOT HCounter(8) AND Addr(18)) OR (NOT Flag(0) AND Addr(0) AND Addr(13) AND Addr(15) AND Addr(1) AND Addr(5) AND Addr(9) AND Addr(10) AND Addr(11) AND Addr(14) AND Addr(16) AND Addr(2) AND Addr(3) AND Addr(6) AND Addr(7) AND Addr(12) AND Addr(17) AND Addr(4) AND Addr(8))); FDCPE_Addr1: FDCPE port map (Addr(1),Addr_D(1),NOT Clock,NOT Flag(0),'0'); Addr_D(1) <= ((Color(5).EXP) OR (Flag(0) AND NOT HCounter(9)) OR (Addr(0) AND Addr(1)) OR (NOT Addr(0) AND NOT Addr(1))); FDCPE_Addr2: FDCPE port map (Addr(2),Addr_D(2),NOT Clock,NOT Flag(0),'0'); Addr_D(2) <= ((HSync.EXP) OR (Flag(0) AND NOT HCounter(9)) OR (NOT Addr(0) AND NOT Addr(2))); FTCPE_Addr3: FTCPE port map (Addr(3),Addr_T(3),NOT Clock,NOT Flag(0),'0'); Addr_T(3) <= ((HSync$BUF0.EXP) OR (Flag(0) AND Addr(3) AND NOT HCounter(9)) OR (Flag(0) AND Addr(3) AND NOT HCounter(7) AND NOT HCounter(8)) OR (NOT Flag(0) AND Addr(0) AND Addr(1) AND Addr(2)) OR (Addr(0) AND Addr(1) AND Addr(2) AND HCounter(7) AND HCounter(9))); FTCPE_Addr4: FTCPE port map (Addr(4),Addr_T(4),NOT Clock,NOT Flag(0),'0'); Addr_T(4) <= ((Color(0).EXP) OR (Flag(0) AND Addr(4) AND NOT HCounter(9)) OR (Flag(0) AND NOT HCounter(7) AND NOT HCounter(8) AND Addr(4)) OR (NOT Flag(0) AND Addr(0) AND Addr(1) AND Addr(2) AND Addr(3))); FTCPE_Addr5: FTCPE port map (Addr(5),Addr_T(5),NOT Clock,NOT Flag(0),'0'); Addr_T(5) <= ((Color(2).EXP) OR (Flag(0) AND Addr(5) AND NOT HCounter(9)) OR (Flag(0) AND Addr(5) AND NOT HCounter(7) AND NOT HCounter(8)) OR (NOT Flag(0) AND Addr(0) AND Addr(1) AND Addr(2) AND Addr(3) AND Addr(4)) OR (Addr(0) AND Addr(1) AND Addr(2) AND Addr(3) AND HCounter(7) AND Addr(4) AND HCounter(9))); FTCPE_Addr6: FTCPE port map (Addr(6),Addr_T(6),NOT Clock,NOT Flag(0),'0'); Addr_T(6) <= ((Addr(1).EXP) OR (Flag(0) AND Addr(6) AND NOT HCounter(9)) OR (Flag(0) AND Addr(6) AND NOT HCounter(7) AND NOT HCounter(8)) OR (NOT Flag(0) AND Addr(0) AND Addr(1) AND Addr(5) AND Addr(2) AND Addr(3) AND Addr(4)) OR (Addr(0) AND Addr(1) AND Addr(5) AND Addr(2) AND Addr(3) AND HCounter(7) AND Addr(4) AND HCounter(9))); FTCPE_Addr7: FTCPE port map (Addr(7),Addr_T(7),NOT Clock,NOT Flag(0),'0'); Addr_T(7) <= ((Addr(16).EXP) OR (Flag(0) AND Addr(7) AND NOT HCounter(9)) OR (Flag(0) AND Addr(7) AND NOT HCounter(7) AND NOT HCounter(8)) OR (NOT Flag(0) AND Addr(0) AND Addr(1) AND Addr(5) AND Addr(2) AND Addr(3) AND Addr(6) AND Addr(4)) OR (Addr(0) AND Addr(1) AND Addr(5) AND Addr(2) AND Addr(3) AND Addr(6) AND HCounter(7) AND Addr(4) AND HCounter(9))); FTCPE_Addr8: FTCPE port map (Addr(8),Addr_T(8),NOT Clock,NOT Flag(0),'0'); Addr_T(8) <= ((Addr(9).EXP) OR (Flag(0) AND Addr(8) AND NOT HCounter(9)) OR (Flag(0) AND NOT HCounter(7) AND NOT HCounter(8) AND Addr(8)) OR (NOT Flag(0) AND Addr(0) AND Addr(1) AND Addr(5) AND Addr(2) AND Addr(3) AND Addr(6) AND Addr(7) AND Addr(4)) OR (Addr(0) AND Addr(1) AND Addr(5) AND Addr(2) AND Addr(3) AND Addr(6) AND Addr(7) AND HCounter(7) AND Addr(4) AND HCounter(9))); FTCPE_Addr9: FTCPE port map (Addr(9),Addr_T(9),NOT Clock,NOT Flag(0),'0'); Addr_T(9) <= ((Addr(10).EXP) OR (Flag(0) AND Addr(9) AND NOT HCounter(9)) OR (Flag(0) AND Addr(9) AND NOT HCounter(7) AND NOT HCounter(8)) OR (NOT Flag(0) AND Addr(0) AND Addr(1) AND Addr(5) AND Addr(2) AND Addr(3) AND Addr(6) AND Addr(7) AND Addr(4) AND Addr(8))); FDCPE_Bank0: FDCPE port map (Bank(0),AVR_AD(0).PIN,NOT AVR_WR,NOT Reset,'0',Bank_CE(0)); Bank_CE(0) <= (NOT AVR_AL(0) AND NOT CS_CPLD); FDCPE_Bank1: FDCPE port map (Bank(1),AVR_AD(1).PIN,NOT AVR_WR,NOT Reset,'0',Bank_CE(1)); Bank_CE(1) <= (NOT AVR_AL(0) AND NOT CS_CPLD); FDCPE_Bank2: FDCPE port map (Bank(2),AVR_AD(2).PIN,NOT AVR_WR,NOT Reset,'0',Bank_CE(2)); Bank_CE(2) <= (NOT AVR_AL(0) AND NOT CS_CPLD); FDCPE_Bank3: FDCPE port map (Bank(3),AVR_AD(3).PIN,NOT AVR_WR,NOT Reset,'0',Bank_CE(3)); Bank_CE(3) <= (NOT AVR_AL(0) AND NOT CS_CPLD); FDCPE_CS_CPLD: FDCPE port map (CS_CPLD,'0','0',CS_CPLD_CLR,NOT CS_CPLD/CS_CPLD_SETF__$INT); CS_CPLD_CLR <= (Reset AND AVR_AH(6) AND AVR_AH(5) AND AVR_AH(4) AND AVR_AH(3) AND AVR_AH(2) AND AVR_AH(1) AND AVR_AH(0) AND NOT AVR_AH(7)); CS_CPLD/CS_CPLD_SETF__$INT <= (Reset AND AVR_AH(6) AND AVR_AH(5) AND AVR_AH(4) AND AVR_AH(3) AND AVR_AH(2) AND NOT AVR_AH(7)); FTCPE_AVR_Clock: FTCPE port map (AVR_Clock,'1',Clock,'0','0'); FDCPE_VGA_RGB0: FDCPE port map (VGA_RGB_I(0),VGA_RGB(0),NOT Clock,NOT Flag(0),'0'); VGA_RGB(0) <= ((HSync$BUF1.EXP) OR (SRAM_Data(0).PIN AND NOT Flag(0))); VGA_RGB(0) <= VGA_RGB_I(0) when VGA_RGB_OE(0) = '1' else 'Z'; VGA_RGB_OE(0) <= Reset; FDCPE_VGA_RGB1: FDCPE port map (VGA_RGB_I(1),VGA_RGB(1),NOT Clock,NOT Flag(0),'0'); VGA_RGB(1) <= ((Addr(4).EXP) OR (SRAM_Data(1).PIN AND NOT Flag(0)) OR (SRAM_Data(1).PIN AND HCounter(7) AND HCounter(9))); VGA_RGB(1) <= VGA_RGB_I(1) when VGA_RGB_OE(1) = '1' else 'Z'; VGA_RGB_OE(1) <= Reset; FDCPE_VGA_RGB2: FDCPE port map (VGA_RGB_I(2),VGA_RGB(2),NOT Clock,NOT Flag(0),'0'); VGA_RGB(2) <= ((Color(1).EXP) OR (SRAM_Data(2).PIN AND NOT Flag(0)) OR (SRAM_Data(2).PIN AND HCounter(7) AND HCounter(9))); VGA_RGB(2) <= VGA_RGB_I(2) when VGA_RGB_OE(2) = '1' else 'Z'; VGA_RGB_OE(2) <= Reset; FDCPE_VGA_RGB3: FDCPE port map (VGA_RGB_I(3),VGA_RGB(3),NOT Clock,NOT Flag(0),'0'); VGA_RGB(3) <= ((SRAM_Data(3).PIN AND NOT Flag(0)) OR (SRAM_Data(3).PIN AND HCounter(7) AND HCounter(9)) OR (SRAM_Data(3).PIN AND HCounter(8) AND HCounter(9))); VGA_RGB(3) <= VGA_RGB_I(3) when VGA_RGB_OE(3) = '1' else 'Z'; VGA_RGB_OE(3) <= Reset; FDCPE_VGA_RGB4: FDCPE port map (VGA_RGB_I(4),VGA_RGB(4),NOT Clock,NOT Flag(0),'0'); VGA_RGB(4) <= ((SRAM_Data(4).PIN AND NOT Flag(0)) OR (SRAM_Data(4).PIN AND HCounter(7) AND HCounter(9)) OR (SRAM_Data(4).PIN AND HCounter(8) AND HCounter(9))); VGA_RGB(4) <= VGA_RGB_I(4) when VGA_RGB_OE(4) = '1' else 'Z'; VGA_RGB_OE(4) <= Reset; FDCPE_VGA_RGB5: FDCPE port map (VGA_RGB_I(5),VGA_RGB(5),NOT Clock,NOT Flag(0),'0'); VGA_RGB(5) <= ((Addr(0).EXP) OR (SRAM_Data(5).PIN AND NOT Flag(0)) OR (SRAM_Data(5).PIN AND HCounter(7) AND HCounter(9))); VGA_RGB(5) <= VGA_RGB_I(5) when VGA_RGB_OE(5) = '1' else 'Z'; VGA_RGB_OE(5) <= Reset; FDCPE_Ext_CS0: FDCPE port map (Ext_CS(0),'0','0',Ext_CS_CLR(0),NOT Ext_CS_0/Ext_CS_0_SETF__$INT); Ext_CS_CLR(0) <= (Reset AND AVR_AH(6) AND AVR_AH(5) AND AVR_AH(4) AND AVR_AH(3) AND AVR_AH(2) AND NOT AVR_AH(1) AND NOT AVR_AH(0) AND NOT AVR_AH(7)); Ext_CS_0/Ext_CS_0_SETF__$INT <= ((Reset AND AVR_AH(6) AND AVR_AH(5) AND AVR_AH(4) AND AVR_AH(3) AND AVR_AH(2) AND AVR_AH(1) AND AVR_AH(0) AND NOT AVR_AH(7)) OR (Reset AND AVR_AH(6) AND AVR_AH(5) AND AVR_AH(4) AND AVR_AH(3) AND AVR_AH(2) AND NOT AVR_AH(1) AND NOT AVR_AH(0) AND NOT AVR_AH(7))); FDCPE_Ext_CS1: FDCPE port map (Ext_CS(1),'0','0',Ext_CS_CLR(1),NOT Ext_CS_1/Ext_CS_1_SETF__$INT); Ext_CS_CLR(1) <= (Reset AND AVR_AH(6) AND AVR_AH(5) AND AVR_AH(4) AND AVR_AH(3) AND AVR_AH(2) AND NOT AVR_AH(1) AND AVR_AH(0) AND NOT AVR_AH(7)); Ext_CS_1/Ext_CS_1_SETF__$INT <= (Reset AND AVR_AH(6) AND AVR_AH(5) AND AVR_AH(4) AND AVR_AH(3) AND AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(7)); FDCPE_Ext_CS2: FDCPE port map (Ext_CS(2),'0','0',Ext_CS_CLR(2),NOT Ext_CS_2/Ext_CS_2_SETF__$INT); Ext_CS_CLR(2) <= (Reset AND AVR_AH(6) AND AVR_AH(5) AND AVR_AH(4) AND AVR_AH(3) AND AVR_AH(2) AND AVR_AH(1) AND NOT AVR_AH(0) AND NOT AVR_AH(7)); Ext_CS_2/Ext_CS_2_SETF__$INT <= Ext_CS_1/Ext_CS_1_SETF__$INT.EXP; FDCPE_Flag0: FDCPE port map (Flag(0),AVR_AD(0).PIN,NOT AVR_WR,NOT Reset,'0',Flag_CE(0)); Flag_CE(0) <= (AVR_AL(0) AND NOT CS_CPLD); FTCPE_HCounter0: FTCPE port map (HCounter(0),HCounter_T(0),Clock,NOT Flag(0),'0'); HCounter_T(0) <= ((Trace.EXP) OR (HCounter(7) AND HCounter(8) AND NOT HCounter(0) AND HCounter(9))); FDCPE_HCounter1: FDCPE port map (HCounter(1),HCounter_D(1),Clock,NOT Flag(0),'0'); HCounter_D(1) <= ((HCounter(8).EXP) OR (HCounter(0) AND HCounter(1)) OR (NOT HCounter(0) AND NOT HCounter(1))); FDCPE_HCounter2: FDCPE port map (HCounter(2),HCounter_D(2),Clock,NOT Flag(0),'0'); HCounter_D(2) <= ((EXP35_.EXP) OR (NOT HCounter(0) AND NOT HCounter(2)) OR (NOT HCounter(1) AND NOT HCounter(2)) OR (HCounter(7) AND HCounter(8) AND HCounter(9)) OR (HCounter(8) AND HCounter(6) AND HCounter(9))); FTCPE_HCounter3: FTCPE port map (HCounter(3),HCounter_T(3),Clock,NOT Flag(0),'0'); HCounter_T(3) <= ((HCounter(4).EXP) OR (HCounter(7) AND HCounter(8) AND HCounter(3) AND HCounter(9)) OR (HCounter(8) AND HCounter(3) AND HCounter(6) AND HCounter(9)) OR (NOT HCounter(8) AND HCounter(0) AND HCounter(1) AND HCounter(2)) OR (HCounter(0) AND NOT HCounter(9) AND HCounter(1) AND HCounter(2))); FTCPE_HCounter4: FTCPE port map (HCounter(4),HCounter_T(4),Clock,NOT Flag(0),'0'); HCounter_T(4) <= ((EXP34_.EXP) OR (HCounter(7) AND HCounter(8) AND HCounter(4) AND HCounter(9)) OR (HCounter(8) AND HCounter(4) AND HCounter(6) AND HCounter(9))); FTCPE_HCounter5: FTCPE port map (HCounter(5),HCounter_T(5),Clock,NOT Flag(0),'0'); HCounter_T(5) <= ((HCounter(1).EXP) OR (HCounter(7) AND HCounter(8) AND HCounter(5) AND HCounter(9)) OR (HCounter(8) AND HCounter(5) AND HCounter(6) AND HCounter(9)) OR (HCounter(8) AND HCounter(3) AND HCounter(4) AND HCounter(5) AND HCounter(9)) OR (NOT HCounter(8) AND HCounter(0) AND HCounter(3) AND HCounter(4) AND HCounter(1) AND HCounter(2))); FTCPE_HCounter6: FTCPE port map (HCounter(6),HCounter_T(6),Clock,NOT Flag(0),'0'); HCounter_T(6) <= ((HCounter(8) AND HCounter(6) AND HCounter(9)) OR (NOT HCounter(8) AND HCounter(0) AND HCounter(3) AND HCounter(4) AND HCounter(5) AND HCounter(1) AND HCounter(2)) OR (HCounter(0) AND HCounter(3) AND HCounter(4) AND HCounter(5) AND NOT HCounter(9) AND HCounter(1) AND HCounter(2))); FTCPE_HCounter7: FTCPE port map (HCounter(7),HCounter_T(7),Clock,NOT Flag(0),'0'); HCounter_T(7) <= ((HCounter(7) AND HCounter(8) AND HCounter(9)) OR (NOT HCounter(8) AND HCounter(0) AND HCounter(3) AND HCounter(4) AND HCounter(5) AND HCounter(6) AND HCounter(1) AND HCounter(2)) OR (HCounter(0) AND HCounter(3) AND HCounter(4) AND HCounter(5) AND HCounter(6) AND NOT HCounter(9) AND HCounter(1) AND HCounter(2))); FTCPE_HCounter8: FTCPE port map (HCounter(8),HCounter_T(8),Clock,NOT Flag(0),'0'); HCounter_T(8) <= ((HCounter(9).EXP) OR (HCounter(7) AND HCounter(0) AND HCounter(3) AND HCounter(4) AND HCounter(5) AND HCounter(6) AND HCounter(1) AND HCounter(2))); FTCPE_HCounter9: FTCPE port map (HCounter(9),HCounter_T(9),Clock,NOT Flag(0),'0'); HCounter_T(9) <= ((HCounter(0).EXP) OR (HCounter(7) AND HCounter(8) AND HCounter(0) AND HCounter(3) AND HCounter(4) AND HCounter(5) AND HCounter(6) AND HCounter(1) AND HCounter(2))); VGA_VSync_I <= '0'; VGA_VSync <= VGA_VSync_I when VGA_VSync_OE = '1' else 'Z'; VGA_VSync_OE <= Reset; VGA_HSync_I <= '0'; VGA_HSync <= VGA_HSync_I when VGA_HSync_OE = '1' else 'Z'; VGA_HSync_OE <= Reset; VGA_CSync_I <= '0'; VGA_CSync <= VGA_CSync_I when VGA_CSync_OE = '1' else 'Z'; VGA_CSync_OE <= Reset; FDCPE_AVR_AL0: FDCPE port map (AVR_AL_I(0),AVR_AD(0).PIN,AVR_ALE,NOT Reset,'0'); AVR_AL(0) <= AVR_AL_I(0) when AVR_AL_OE(0) = '1' else 'Z'; AVR_AL_OE(0) <= Reset; FDCPE_AVR_AL1: FDCPE port map (AVR_AL_I(1),AVR_AD(1).PIN,AVR_ALE,NOT Reset,'0'); AVR_AL(1) <= AVR_AL_I(1) when AVR_AL_OE(1) = '1' else 'Z'; AVR_AL_OE(1) <= Reset; FDCPE_AVR_AL2: FDCPE port map (AVR_AL_I(2),AVR_AD(2).PIN,AVR_ALE,NOT Reset,'0'); AVR_AL(2) <= AVR_AL_I(2) when AVR_AL_OE(2) = '1' else 'Z'; AVR_AL_OE(2) <= Reset; FDCPE_AVR_AL3: FDCPE port map (AVR_AL_I(3),AVR_AD(3).PIN,AVR_ALE,NOT Reset,'0'); AVR_AL(3) <= AVR_AL_I(3) when AVR_AL_OE(3) = '1' else 'Z'; AVR_AL_OE(3) <= Reset; FDCPE_AVR_AL4: FDCPE port map (AVR_AL_I(4),AVR_AD(4).PIN,AVR_ALE,NOT Reset,'0'); AVR_AL(4) <= AVR_AL_I(4) when AVR_AL_OE(4) = '1' else 'Z'; AVR_AL_OE(4) <= Reset; FDCPE_AVR_AL5: FDCPE port map (AVR_AL_I(5),AVR_AD(5).PIN,AVR_ALE,NOT Reset,'0'); AVR_AL(5) <= AVR_AL_I(5) when AVR_AL_OE(5) = '1' else 'Z'; AVR_AL_OE(5) <= Reset; FDCPE_AVR_AL6: FDCPE port map (AVR_AL_I(6),AVR_AD(6).PIN,AVR_ALE,NOT Reset,'0'); AVR_AL(6) <= AVR_AL_I(6) when AVR_AL_OE(6) = '1' else 'Z'; AVR_AL_OE(6) <= Reset; FDCPE_AVR_AL7: FDCPE port map (AVR_AL_I(7),AVR_AD(7).PIN,AVR_ALE,NOT Reset,'0'); AVR_AL(7) <= AVR_AL_I(7) when AVR_AL_OE(7) = '1' else 'Z'; AVR_AL_OE(7) <= Reset; AVR_AD_I(1) <= ((EXP28_.EXP) OR (AVR_AD(1) AND Clock) OR (AVR_AD(1) AND AVR_RD) OR (AVR_AD(1) AND NOT Reset AND CS_CPLD) OR (Reset AND NOT Clock AND SRAM_Data(1).PIN AND NOT AVR_AH(2) AND NOT AVR_RD)); AVR_AD(1) <= AVR_AD_I(1) when AVR_AD_OE(1) = '1' else 'Z'; AVR_AD_OE(1) <= NOT Mtrien_AVR_AD; AVR_AD_I(2) <= ((EXP29_.EXP) OR (AVR_AD(2) AND Clock) OR (AVR_AD(2) AND AVR_RD) OR (AVR_AD(2) AND NOT Reset AND CS_CPLD) OR (Reset AND NOT Clock AND SRAM_Data(2).PIN AND NOT AVR_AH(2) AND NOT AVR_RD)); AVR_AD(2) <= AVR_AD_I(2) when AVR_AD_OE(2) = '1' else 'Z'; AVR_AD_OE(2) <= NOT Mtrien_AVR_AD; AVR_AD_I(6) <= ((EXP18_.EXP) OR (Mtridata_AVR_AD(7).EXP) OR (AVR_AD(6) AND Clock) OR (AVR_AD(6) AND AVR_RD) OR (AVR_AD(6) AND NOT Reset AND CS_CPLD) OR (Reset AND NOT Clock AND NOT AVR_AH(2) AND NOT AVR_RD AND SRAM_Data(6).PIN)); AVR_AD(6) <= AVR_AD_I(6) when AVR_AD_OE(6) = '1' else 'Z'; AVR_AD_OE(6) <= NOT Mtrien_AVR_AD; AVR_AD_I(7) <= ((EXP19_.EXP) OR (AVR_AD(7) AND Clock) OR (AVR_AD(7) AND AVR_RD)); AVR_AD(7) <= AVR_AD_I(7) when AVR_AD_OE(7) = '1' else 'Z'; AVR_AD_OE(7) <= NOT Mtrien_AVR_AD; FDCPE_Mtrien_AVR_AD: FDCPE port map (Mtrien_AVR_AD,'0','0',Mtrien_AVR_AD_CLR,NOT Reset); Mtrien_AVR_AD_CLR <= (Reset AND NOT Clock AND NOT AVR_RD AND NOT $OpTx$$OpTx$FX_DC$65_INV$93); SRAM_Addr_I(0) <= ((Addr(14).EXP) OR (NOT Clock AND AVR_AL(0))); SRAM_Addr(0) <= SRAM_Addr_I(0) when SRAM_Addr_OE(0) = '1' else 'Z'; SRAM_Addr_OE(0) <= Reset; SRAM_Addr_I(10) <= ((Clock AND Addr(10)) OR (NOT Clock AND AVR_AH(2))); SRAM_Addr(10) <= SRAM_Addr_I(10) when SRAM_Addr_OE(10) = '1' else 'Z'; SRAM_Addr_OE(10) <= Reset; SRAM_Addr_I(11) <= ((Clock AND Addr(11)) OR (NOT Clock AND AVR_AH(3))); SRAM_Addr(11) <= SRAM_Addr_I(11) when SRAM_Addr_OE(11) = '1' else 'Z'; SRAM_Addr_OE(11) <= Reset; SRAM_Addr_I(12) <= ((Clock AND Addr(12)) OR (NOT Clock AND AVR_AH(4))); SRAM_Addr(12) <= SRAM_Addr_I(12) when SRAM_Addr_OE(12) = '1' else 'Z'; SRAM_Addr_OE(12) <= Reset; SRAM_Addr_I(13) <= ((Clock AND Addr(13)) OR (NOT Clock AND AVR_AH(5))); SRAM_Addr(13) <= SRAM_Addr_I(13) when SRAM_Addr_OE(13) = '1' else 'Z'; SRAM_Addr_OE(13) <= Reset; SRAM_Addr_I(14) <= ((Clock AND Addr(14)) OR (NOT Clock AND AVR_AH(6))); SRAM_Addr(14) <= SRAM_Addr_I(14) when SRAM_Addr_OE(14) = '1' else 'Z'; SRAM_Addr_OE(14) <= Reset; SRAM_Addr_I(15) <= ((Clock AND Addr(15)) OR (NOT Clock AND Bank(0) AND AVR_AH(7))); SRAM_Addr(15) <= SRAM_Addr_I(15) when SRAM_Addr_OE(15) = '1' else 'Z'; SRAM_Addr_OE(15) <= Reset; SRAM_Addr_I(16) <= ((Clock AND Addr(16)) OR (NOT Clock AND Bank(1) AND AVR_AH(7))); SRAM_Addr(16) <= SRAM_Addr_I(16) when SRAM_Addr_OE(16) = '1' else 'Z'; SRAM_Addr_OE(16) <= Reset; SRAM_Addr_I(17) <= ((Clock AND Addr(17)) OR (NOT Clock AND Bank(2) AND AVR_AH(7))); SRAM_Addr(17) <= SRAM_Addr_I(17) when SRAM_Addr_OE(17) = '1' else 'Z'; SRAM_Addr_OE(17) <= Reset; SRAM_Addr_I(18) <= ((Clock AND Addr(18)) OR (NOT Clock AND Bank(3) AND AVR_AH(7))); SRAM_Addr(18) <= SRAM_Addr_I(18) when SRAM_Addr_OE(18) = '1' else 'Z'; SRAM_Addr_OE(18) <= Reset; SRAM_Addr_I(1) <= ((Clock AND Addr(1)) OR (NOT Clock AND AVR_AL(1))); SRAM_Addr(1) <= SRAM_Addr_I(1) when SRAM_Addr_OE(1) = '1' else 'Z'; SRAM_Addr_OE(1) <= Reset; SRAM_Addr_I(2) <= ((Clock AND Addr(2)) OR (NOT Clock AND AVR_AL(2))); SRAM_Addr(2) <= SRAM_Addr_I(2) when SRAM_Addr_OE(2) = '1' else 'Z'; SRAM_Addr_OE(2) <= Reset; SRAM_Addr_I(3) <= ((Clock AND Addr(3)) OR (NOT Clock AND AVR_AL(3))); SRAM_Addr(3) <= SRAM_Addr_I(3) when SRAM_Addr_OE(3) = '1' else 'Z'; SRAM_Addr_OE(3) <= Reset; SRAM_Addr_I(4) <= ((Clock AND Addr(4)) OR (NOT Clock AND AVR_AL(4))); SRAM_Addr(4) <= SRAM_Addr_I(4) when SRAM_Addr_OE(4) = '1' else 'Z'; SRAM_Addr_OE(4) <= Reset; SRAM_Addr_I(5) <= ((Clock AND Addr(5)) OR (NOT Clock AND AVR_AL(5))); SRAM_Addr(5) <= SRAM_Addr_I(5) when SRAM_Addr_OE(5) = '1' else 'Z'; SRAM_Addr_OE(5) <= Reset; SRAM_Addr_I(6) <= ((Clock AND Addr(6)) OR (NOT Clock AND AVR_AL(6))); SRAM_Addr(6) <= SRAM_Addr_I(6) when SRAM_Addr_OE(6) = '1' else 'Z'; SRAM_Addr_OE(6) <= Reset; SRAM_Addr_I(7) <= ((Addr(11).EXP) OR (NOT Clock AND AVR_AL(7))); SRAM_Addr(7) <= SRAM_Addr_I(7) when SRAM_Addr_OE(7) = '1' else 'Z'; SRAM_Addr_OE(7) <= Reset; SRAM_Addr_I(8) <= ((Clock AND Addr(8)) OR (NOT Clock AND AVR_AH(0))); SRAM_Addr(8) <= SRAM_Addr_I(8) when SRAM_Addr_OE(8) = '1' else 'Z'; SRAM_Addr_OE(8) <= Reset; SRAM_Addr_I(9) <= ((Clock AND Addr(9)) OR (NOT Clock AND AVR_AH(1))); SRAM_Addr(9) <= SRAM_Addr_I(9) when SRAM_Addr_OE(9) = '1' else 'Z'; SRAM_Addr_OE(9) <= Reset; SRAM_CS_I <= ((NOT Reset AND NOT Clock) OR (NOT Clock AND AVR_AH(6) AND AVR_AH(5) AND AVR_AH(4) AND AVR_AH(3) AND AVR_AH(2) AND NOT AVR_AH(7))); SRAM_CS <= SRAM_CS_I when SRAM_CS_OE = '1' else 'Z'; SRAM_CS_OE <= Reset; SRAM_Data_I(0) <= AVR_AD(0).PIN; SRAM_Data(0) <= SRAM_Data_I(0) when SRAM_Data_OE(0) = '1' else 'Z'; SRAM_Data_OE(0) <= (Reset AND NOT Clock AND NOT AVR_WR); SRAM_Data_I(1) <= AVR_AD(1).PIN; SRAM_Data(1) <= SRAM_Data_I(1) when SRAM_Data_OE(1) = '1' else 'Z'; SRAM_Data_OE(1) <= (Reset AND NOT Clock AND NOT AVR_WR); SRAM_Data_I(2) <= AVR_AD(2).PIN; SRAM_Data(2) <= SRAM_Data_I(2) when SRAM_Data_OE(2) = '1' else 'Z'; SRAM_Data_OE(2) <= (Reset AND NOT Clock AND NOT AVR_WR); SRAM_Data_I(3) <= AVR_AD(3).PIN; SRAM_Data(3) <= SRAM_Data_I(3) when SRAM_Data_OE(3) = '1' else 'Z'; SRAM_Data_OE(3) <= (Reset AND NOT Clock AND NOT AVR_WR); SRAM_Data_I(4) <= AVR_AD(4).PIN; SRAM_Data(4) <= SRAM_Data_I(4) when SRAM_Data_OE(4) = '1' else 'Z'; SRAM_Data_OE(4) <= (Reset AND NOT Clock AND NOT AVR_WR); SRAM_Data_I(5) <= AVR_AD(5).PIN; SRAM_Data(5) <= SRAM_Data_I(5) when SRAM_Data_OE(5) = '1' else 'Z'; SRAM_Data_OE(5) <= (Reset AND NOT Clock AND NOT AVR_WR); SRAM_Data_I(6) <= AVR_AD(6).PIN; SRAM_Data(6) <= SRAM_Data_I(6) when SRAM_Data_OE(6) = '1' else 'Z'; SRAM_Data_OE(6) <= (Reset AND NOT Clock AND NOT AVR_WR); SRAM_Data_I(7) <= AVR_AD(7).PIN; SRAM_Data(7) <= SRAM_Data_I(7) when SRAM_Data_OE(7) = '1' else 'Z'; SRAM_Data_OE(7) <= (Reset AND NOT Clock AND NOT AVR_WR); SRAM_OE_I <= (NOT Clock AND AVR_RD); SRAM_OE <= SRAM_OE_I when SRAM_OE_OE = '1' else 'Z'; SRAM_OE_OE <= Reset; SRAM_WR_I <= NOT ((NOT Clock AND NOT AVR_WR)); SRAM_WR <= SRAM_WR_I when SRAM_WR_OE = '1' else 'Z'; SRAM_WR_OE <= Reset; VGA_Trace_I <= NOT (((Flag(0) AND NOT HCounter(9)) OR (Flag(0) AND NOT HCounter(7) AND NOT HCounter(8)))); VGA_Trace <= VGA_Trace_I when VGA_Trace_OE = '1' else 'Z'; VGA_Trace_OE <= Reset; AVR_AD_I(5) <= AVR_AD(5)_BUFR; AVR_AD(5) <= AVR_AD_I(5) when AVR_AD_OE(5) = '1' else 'Z'; AVR_AD_OE(5) <= NOT Mtrien_AVR_AD; AVR_AD_I(4) <= AVR_AD(4)_BUFR; AVR_AD(4) <= AVR_AD_I(4) when AVR_AD_OE(4) = '1' else 'Z'; AVR_AD_OE(4) <= NOT Mtrien_AVR_AD; AVR_AD_I(0) <= AVR_AD(0)_BUFR; AVR_AD(0) <= AVR_AD_I(0) when AVR_AD_OE(0) = '1' else 'Z'; AVR_AD_OE(0) <= NOT Mtrien_AVR_AD; AVR_AD_I(3) <= AVR_AD(3)_BUFR; AVR_AD(3) <= AVR_AD_I(3) when AVR_AD_OE(3) = '1' else 'Z'; AVR_AD_OE(3) <= NOT Mtrien_AVR_AD; Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); **************************** Device Pin Out **************************** Device : XC95144XL-5-TQ100 -------------------------------------------------- /100 98 96 94 92 90 88 86 84 82 80 78 76 \ | 99 97 95 93 91 89 87 85 83 81 79 77 | | 1 75 | | 2 74 | | 3 73 | | 4 72 | | 5 71 | | 6 70 | | 7 69 | | 8 68 | | 9 67 | | 10 66 | | 11 65 | | 12 64 | | 13 XC95144XL-5-TQ100 63 | | 14 62 | | 15 61 | | 16 60 | | 17 59 | | 18 58 | | 19 57 | | 20 56 | | 21 55 | | 22 54 | | 23 53 | | 24 52 | | 25 51 | | 27 29 31 33 35 37 39 41 43 45 47 49 | \26 28 30 32 34 36 38 40 42 44 46 48 50 / -------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 Ext_CS<0> 51 VCC 2 Ext_CS<1> 52 TIE 3 Ext_CS<2> 53 SRAM_Addr<0> 4 AVR_AD<0> 54 SRAM_Addr<1> 5 VCC 55 SRAM_Addr<2> 6 AVR_AD<1> 56 SRAM_Addr<3> 7 AVR_AD<2> 57 VCC 8 AVR_AD<3> 58 SRAM_Addr<4> 9 AVR_AD<4> 59 SRAM_Addr<5> 10 AVR_AD<5> 60 SRAM_Addr<6> 11 AVR_AD<6> 61 SRAM_Addr<7> 12 AVR_AD<7> 62 GND 13 AVR_AH<0> 63 SRAM_Addr<8> 14 AVR_AH<1> 64 SRAM_Addr<9> 15 AVR_AH<2> 65 SRAM_Addr<10> 16 AVR_AH<3> 66 SRAM_Addr<11> 17 AVR_AH<4> 67 SRAM_Addr<12> 18 AVR_AH<5> 68 SRAM_Addr<13> 19 AVR_AH<6> 69 GND 20 AVR_AH<7> 70 SRAM_Addr<14> 21 GND 71 SRAM_Addr<15> 22 AVR_ALE 72 SRAM_Addr<16> 23 AVR_WR 73 SRAM_Addr<17> 24 AVR_RD 74 SRAM_Addr<18> 25 AVR_Clock 75 GND 26 VCC 76 SRAM_Data<0> 27 Clock 77 SRAM_Data<1> 28 VGA_Trace 78 SRAM_Data<2> 29 TIE 79 SRAM_Data<3> 30 TIE 80 SRAM_Data<4> 31 GND 81 SRAM_Data<5> 32 TIE 82 SRAM_Data<6> 33 TIE 83 TDO 34 TIE 84 GND 35 VGA_RGB<5> 85 SRAM_Data<7> 36 VGA_RGB<4> 86 SRAM_OE 37 VGA_RGB<3> 87 SRAM_WR 38 VCC 88 VCC 39 VGA_RGB<2> 89 SRAM_CS 40 VGA_RGB<1> 90 AVR_AL<0> 41 VGA_RGB<0> 91 AVR_AL<1> 42 VGA_CSync 92 AVR_AL<2> 43 VGA_HSync 93 AVR_AL<3> 44 GND 94 AVR_AL<4> 45 TDI 95 AVR_AL<5> 46 VGA_VSync 96 AVR_AL<6> 47 TMS 97 AVR_AL<7> 48 TCK 98 VCC 49 TIE 99 Reset 50 TIE 100 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PE = Port Enable pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95144xl-5-TQ100 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : ON Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : AUTO Set Unused I/O Pin Termination : FLOAT Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 50