Equations

$OpTx$$OpTx$FX_DC$65_INV$93 <= (Reset AND AVR_AH(6) AND AVR_AH(5) AND AVR_AH(4) AND
      AVR_AH(3) AND AVR_AH(2) AND CS_CPLD AND NOT AVR_AH(7));
AVR_AD(0)_BUFR <= ((Ext_CS_2/Ext_CS_2_SETF__$INT.EXP)
      OR (EXP30_.EXP)
      OR (AVR_AD(0) AND Clock)
      OR (AVR_AD(0) AND AVR_RD)
      OR (AVR_AD(0) AND NOT Reset AND CS_CPLD)
      OR (AVR_AD(0) AND NOT Reset AND Flag(0) AND AVR_AL(0))
      OR (SRAM_Data(0).PIN AND Reset AND NOT Clock AND NOT AVR_AH(2) AND
      NOT AVR_RD));
AVR_AD(3)_BUFR <= ((EXP36_.EXP)
      OR (SRAM_Addr_17_OBUFE.EXP)
      OR (AVR_AD(3) AND Clock)
      OR (AVR_AD(3) AND AVR_RD)
      OR (AVR_AD(3) AND NOT Reset AND CS_CPLD)
      OR (Reset AND NOT Clock AND SRAM_Data(3).PIN AND NOT AVR_AH(3) AND
      NOT AVR_RD)
      OR (Reset AND NOT Clock AND SRAM_Data(3).PIN AND NOT AVR_AH(2) AND
      NOT AVR_RD));
AVR_AD(4)_BUFR <= ((EXP24_.EXP)
      OR (EXP25_.EXP)
      OR (AVR_AD(4) AND Clock)
      OR (AVR_AD(4) AND AVR_RD)
      OR (AVR_AD(4) AND NOT Reset AND CS_CPLD)
      OR (Reset AND NOT Clock AND SRAM_Data(4).PIN AND NOT AVR_AH(3) AND
      NOT AVR_RD)
      OR (Reset AND NOT Clock AND SRAM_Data(4).PIN AND NOT AVR_AH(2) AND
      NOT AVR_RD));
AVR_AD(5)_BUFR <= ((EXP32_.EXP)
      OR (EXP33_.EXP)
      OR (AVR_AD(5) AND Clock)
      OR (AVR_AD(5) AND AVR_RD)
      OR (AVR_AD(5) AND NOT Reset AND CS_CPLD)
      OR (Reset AND NOT Clock AND SRAM_Data(5).PIN AND NOT AVR_AH(3) AND
      NOT AVR_RD)
      OR (Reset AND NOT Clock AND SRAM_Data(5).PIN AND NOT AVR_AH(2) AND
      NOT AVR_RD));
FTCPE_Addr0: FTCPE port map (Addr(0),Addr_T(0),NOT Clock,NOT Flag(0),'0');
     Addr_T(0) <= ((Flag(0) AND NOT Addr(0) AND NOT HCounter(9))
      OR (Flag(0) AND NOT Addr(0) AND NOT HCounter(7) AND NOT HCounter(8)));
FTCPE_Addr10: FTCPE port map (Addr(10),Addr_T(10),NOT Clock,NOT Flag(0),'0');
     Addr_T(10) <= ((SRAM_Addr_7_OBUFE.EXP)
      OR (Flag(0) AND Addr(10) AND NOT HCounter(9))
      OR (Flag(0) AND Addr(10) AND NOT HCounter(7) AND NOT HCounter(8)));
FTCPE_Addr11: FTCPE port map (Addr(11),Addr_T(11),NOT Clock,NOT Flag(0),'0');
     Addr_T(11) <= ((SRAM_Addr_6_OBUFE.EXP)
      OR (Flag(0) AND Addr(11) AND NOT HCounter(9))
      OR (Flag(0) AND Addr(11) AND NOT HCounter(7) AND NOT HCounter(8))
      OR (NOT Flag(0) AND Addr(0) AND Addr(1) AND Addr(5) AND
      Addr(9) AND Addr(10) AND Addr(2) AND Addr(3) AND Addr(6) AND
      Addr(7) AND Addr(4) AND Addr(8)));
FTCPE_Addr12: FTCPE port map (Addr(12),Addr_T(12),NOT Clock,NOT Flag(0),'0');
     Addr_T(12) <= ((SRAM_Addr_4_OBUFE.EXP)
      OR (Flag(0) AND Addr(12) AND NOT HCounter(9))
      OR (Flag(0) AND NOT HCounter(7) AND NOT HCounter(8) AND Addr(12))
      OR (NOT Flag(0) AND Addr(0) AND Addr(1) AND Addr(5) AND
      Addr(9) AND Addr(10) AND Addr(11) AND Addr(2) AND Addr(3) AND
      Addr(6) AND Addr(7) AND Addr(4) AND Addr(8))
      OR (Addr(0) AND Addr(1) AND Addr(5) AND Addr(9) AND
      Addr(10) AND Addr(11) AND Addr(2) AND Addr(3) AND Addr(6) AND
      Addr(7) AND HCounter(7) AND Addr(4) AND Addr(8) AND HCounter(9)));
FTCPE_Addr13: FTCPE port map (Addr(13),Addr_T(13),NOT Clock,NOT Flag(0),'0');
     Addr_T(13) <= ((SRAM_Addr_3_OBUFE.EXP)
      OR (Flag(0) AND Addr(13) AND NOT HCounter(9))
      OR (Flag(0) AND Addr(13) AND NOT HCounter(7) AND NOT HCounter(8))
      OR (NOT Flag(0) AND Addr(0) AND Addr(1) AND Addr(5) AND
      Addr(9) AND Addr(10) AND Addr(11) AND Addr(2) AND Addr(3) AND
      Addr(6) AND Addr(7) AND Addr(12) AND Addr(4) AND Addr(8))
      OR (Addr(0) AND Addr(1) AND Addr(5) AND Addr(9) AND
      Addr(10) AND Addr(11) AND Addr(2) AND Addr(3) AND Addr(6) AND
      Addr(7) AND HCounter(7) AND Addr(12) AND Addr(4) AND Addr(8) AND
      HCounter(9)));
FTCPE_Addr14: FTCPE port map (Addr(14),Addr_T(14),NOT Clock,NOT Flag(0),'0');
     Addr_T(14) <= ((SRAM_Addr_1_OBUFE.EXP)
      OR (Flag(0) AND Addr(14) AND NOT HCounter(9))
      OR (Flag(0) AND Addr(14) AND NOT HCounter(7) AND NOT HCounter(8))
      OR (NOT Flag(0) AND Addr(0) AND Addr(13) AND Addr(1) AND
      Addr(5) AND Addr(9) AND Addr(10) AND Addr(11) AND Addr(2) AND
      Addr(3) AND Addr(6) AND Addr(7) AND Addr(12) AND Addr(4) AND
      Addr(8)));
FTCPE_Addr15: FTCPE port map (Addr(15),Addr_T(15),NOT Clock,'0',NOT Flag(0));
     Addr_T(15) <= ((SRAM_Addr_0_OBUFE.EXP)
      OR (Addr(0) AND Addr(13) AND Addr(1) AND Addr(5) AND
      Addr(9) AND Addr(10) AND Addr(11) AND Addr(14) AND Addr(2) AND
      Addr(3) AND Addr(6) AND Addr(7) AND HCounter(7) AND Addr(12) AND
      Addr(4) AND Addr(8) AND HCounter(9))
      OR (Addr(0) AND Addr(13) AND Addr(1) AND Addr(5) AND
      Addr(9) AND Addr(10) AND Addr(11) AND Addr(14) AND Addr(2) AND
      Addr(3) AND Addr(6) AND Addr(7) AND HCounter(8) AND Addr(12) AND
      Addr(4) AND Addr(8) AND HCounter(9)));
FTCPE_Addr16: FTCPE port map (Addr(16),Addr_T(16),NOT Clock,NOT Flag(0),'0');
     Addr_T(16) <= ((Addr(15).EXP)
      OR (Flag(0) AND Addr(16) AND NOT HCounter(9))
      OR (Flag(0) AND Addr(16) AND NOT HCounter(7) AND NOT HCounter(8))
      OR (NOT Flag(0) AND Addr(0) AND Addr(13) AND Addr(15) AND
      Addr(1) AND Addr(5) AND Addr(9) AND Addr(10) AND Addr(11) AND
      Addr(14) AND Addr(2) AND Addr(3) AND Addr(6) AND Addr(7) AND
      Addr(12) AND Addr(4) AND Addr(8)));
FTCPE_Addr17: FTCPE port map (Addr(17),Addr_T(17),NOT Clock,NOT Flag(0),'0');
     Addr_T(17) <= ((Addr(18).EXP)
      OR (Flag(0) AND Addr(17) AND NOT HCounter(9))
      OR (Flag(0) AND NOT HCounter(7) AND NOT HCounter(8) AND Addr(17))
      OR (NOT Flag(0) AND Addr(0) AND Addr(13) AND Addr(15) AND
      Addr(1) AND Addr(5) AND Addr(9) AND Addr(10) AND Addr(11) AND
      Addr(14) AND Addr(16) AND Addr(2) AND Addr(3) AND Addr(6) AND
      Addr(7) AND Addr(12) AND Addr(4) AND Addr(8))
      OR (Addr(0) AND Addr(13) AND Addr(15) AND Addr(1) AND
      Addr(5) AND Addr(9) AND Addr(10) AND Addr(11) AND Addr(14) AND
      Addr(16) AND Addr(2) AND Addr(3) AND Addr(6) AND Addr(7) AND
      HCounter(7) AND Addr(12) AND Addr(4) AND Addr(8) AND HCounter(9)));
FTCPE_Addr18: FTCPE port map (Addr(18),Addr_T(18),NOT Clock,NOT Flag(0),'0');
     Addr_T(18) <= ((Addr(2).EXP)
      OR (Flag(0) AND NOT HCounter(9) AND Addr(18))
      OR (Flag(0) AND NOT HCounter(7) AND NOT HCounter(8) AND Addr(18))
      OR (NOT Flag(0) AND Addr(0) AND Addr(13) AND Addr(15) AND
      Addr(1) AND Addr(5) AND Addr(9) AND Addr(10) AND Addr(11) AND
      Addr(14) AND Addr(16) AND Addr(2) AND Addr(3) AND Addr(6) AND
      Addr(7) AND Addr(12) AND Addr(17) AND Addr(4) AND Addr(8)));
FDCPE_Addr1: FDCPE port map (Addr(1),Addr_D(1),NOT Clock,NOT Flag(0),'0');
     Addr_D(1) <= ((Color(5).EXP)
      OR (Flag(0) AND NOT HCounter(9))
      OR (Addr(0) AND Addr(1))
      OR (NOT Addr(0) AND NOT Addr(1)));
FDCPE_Addr2: FDCPE port map (Addr(2),Addr_D(2),NOT Clock,NOT Flag(0),'0');
     Addr_D(2) <= ((HSync.EXP)
      OR (Flag(0) AND NOT HCounter(9))
      OR (NOT Addr(0) AND NOT Addr(2)));
FTCPE_Addr3: FTCPE port map (Addr(3),Addr_T(3),NOT Clock,NOT Flag(0),'0');
     Addr_T(3) <= ((HSync$BUF0.EXP)
      OR (Flag(0) AND Addr(3) AND NOT HCounter(9))
      OR (Flag(0) AND Addr(3) AND NOT HCounter(7) AND NOT HCounter(8))
      OR (NOT Flag(0) AND Addr(0) AND Addr(1) AND Addr(2))
      OR (Addr(0) AND Addr(1) AND Addr(2) AND HCounter(7) AND
      HCounter(9)));
FTCPE_Addr4: FTCPE port map (Addr(4),Addr_T(4),NOT Clock,NOT Flag(0),'0');
     Addr_T(4) <= ((Color(0).EXP)
      OR (Flag(0) AND Addr(4) AND NOT HCounter(9))
      OR (Flag(0) AND NOT HCounter(7) AND NOT HCounter(8) AND Addr(4))
      OR (NOT Flag(0) AND Addr(0) AND Addr(1) AND Addr(2) AND
      Addr(3)));
FTCPE_Addr5: FTCPE port map (Addr(5),Addr_T(5),NOT Clock,NOT Flag(0),'0');
     Addr_T(5) <= ((Color(2).EXP)
      OR (Flag(0) AND Addr(5) AND NOT HCounter(9))
      OR (Flag(0) AND Addr(5) AND NOT HCounter(7) AND NOT HCounter(8))
      OR (NOT Flag(0) AND Addr(0) AND Addr(1) AND Addr(2) AND
      Addr(3) AND Addr(4))
      OR (Addr(0) AND Addr(1) AND Addr(2) AND Addr(3) AND
      HCounter(7) AND Addr(4) AND HCounter(9)));
FTCPE_Addr6: FTCPE port map (Addr(6),Addr_T(6),NOT Clock,NOT Flag(0),'0');
     Addr_T(6) <= ((Addr(1).EXP)
      OR (Flag(0) AND Addr(6) AND NOT HCounter(9))
      OR (Flag(0) AND Addr(6) AND NOT HCounter(7) AND NOT HCounter(8))
      OR (NOT Flag(0) AND Addr(0) AND Addr(1) AND Addr(5) AND
      Addr(2) AND Addr(3) AND Addr(4))
      OR (Addr(0) AND Addr(1) AND Addr(5) AND Addr(2) AND
      Addr(3) AND HCounter(7) AND Addr(4) AND HCounter(9)));
FTCPE_Addr7: FTCPE port map (Addr(7),Addr_T(7),NOT Clock,NOT Flag(0),'0');
     Addr_T(7) <= ((Addr(16).EXP)
      OR (Flag(0) AND Addr(7) AND NOT HCounter(9))
      OR (Flag(0) AND Addr(7) AND NOT HCounter(7) AND NOT HCounter(8))
      OR (NOT Flag(0) AND Addr(0) AND Addr(1) AND Addr(5) AND
      Addr(2) AND Addr(3) AND Addr(6) AND Addr(4))
      OR (Addr(0) AND Addr(1) AND Addr(5) AND Addr(2) AND
      Addr(3) AND Addr(6) AND HCounter(7) AND Addr(4) AND HCounter(9)));
FTCPE_Addr8: FTCPE port map (Addr(8),Addr_T(8),NOT Clock,NOT Flag(0),'0');
     Addr_T(8) <= ((Addr(9).EXP)
      OR (Flag(0) AND Addr(8) AND NOT HCounter(9))
      OR (Flag(0) AND NOT HCounter(7) AND NOT HCounter(8) AND Addr(8))
      OR (NOT Flag(0) AND Addr(0) AND Addr(1) AND Addr(5) AND
      Addr(2) AND Addr(3) AND Addr(6) AND Addr(7) AND Addr(4))
      OR (Addr(0) AND Addr(1) AND Addr(5) AND Addr(2) AND
      Addr(3) AND Addr(6) AND Addr(7) AND HCounter(7) AND Addr(4) AND
      HCounter(9)));
FTCPE_Addr9: FTCPE port map (Addr(9),Addr_T(9),NOT Clock,NOT Flag(0),'0');
     Addr_T(9) <= ((Addr(10).EXP)
      OR (Flag(0) AND Addr(9) AND NOT HCounter(9))
      OR (Flag(0) AND Addr(9) AND NOT HCounter(7) AND NOT HCounter(8))
      OR (NOT Flag(0) AND Addr(0) AND Addr(1) AND Addr(5) AND
      Addr(2) AND Addr(3) AND Addr(6) AND Addr(7) AND Addr(4) AND
      Addr(8)));
FDCPE_Bank0: FDCPE port map (Bank(0),AVR_AD(0).PIN,NOT AVR_WR,NOT Reset,'0',Bank_CE(0));
     Bank_CE(0) <= (NOT AVR_AL(0) AND NOT CS_CPLD);
FDCPE_Bank1: FDCPE port map (Bank(1),AVR_AD(1).PIN,NOT AVR_WR,NOT Reset,'0',Bank_CE(1));
     Bank_CE(1) <= (NOT AVR_AL(0) AND NOT CS_CPLD);
FDCPE_Bank2: FDCPE port map (Bank(2),AVR_AD(2).PIN,NOT AVR_WR,NOT Reset,'0',Bank_CE(2));
     Bank_CE(2) <= (NOT AVR_AL(0) AND NOT CS_CPLD);
FDCPE_Bank3: FDCPE port map (Bank(3),AVR_AD(3).PIN,NOT AVR_WR,NOT Reset,'0',Bank_CE(3));
     Bank_CE(3) <= (NOT AVR_AL(0) AND NOT CS_CPLD);
FDCPE_CS_CPLD: FDCPE port map (CS_CPLD,'0','0',CS_CPLD_CLR,NOT CS_CPLD/CS_CPLD_SETF__$INT);
     CS_CPLD_CLR <= (Reset AND AVR_AH(6) AND AVR_AH(5) AND AVR_AH(4) AND
      AVR_AH(3) AND AVR_AH(2) AND AVR_AH(1) AND AVR_AH(0) AND NOT AVR_AH(7));
CS_CPLD/CS_CPLD_SETF__$INT <= (Reset AND AVR_AH(6) AND AVR_AH(5) AND AVR_AH(4) AND
      AVR_AH(3) AND AVR_AH(2) AND NOT AVR_AH(7));
FTCPE_AVR_Clock: FTCPE port map (AVR_Clock,'1',Clock,'0','0');
FDCPE_VGA_RGB0: FDCPE port map (VGA_RGB_I(0),VGA_RGB(0),NOT Clock,NOT Flag(0),'0');
     VGA_RGB(0) <= ((HSync$BUF1.EXP)
      OR (SRAM_Data(0).PIN AND NOT Flag(0)));
     VGA_RGB(0) <= VGA_RGB_I(0) when VGA_RGB_OE(0) = '1' else 'Z';
     VGA_RGB_OE(0) <= Reset;
FDCPE_VGA_RGB1: FDCPE port map (VGA_RGB_I(1),VGA_RGB(1),NOT Clock,NOT Flag(0),'0');
     VGA_RGB(1) <= ((Addr(4).EXP)
      OR (SRAM_Data(1).PIN AND NOT Flag(0))
      OR (SRAM_Data(1).PIN AND HCounter(7) AND HCounter(9)));
     VGA_RGB(1) <= VGA_RGB_I(1) when VGA_RGB_OE(1) = '1' else 'Z';
     VGA_RGB_OE(1) <= Reset;
FDCPE_VGA_RGB2: FDCPE port map (VGA_RGB_I(2),VGA_RGB(2),NOT Clock,NOT Flag(0),'0');
     VGA_RGB(2) <= ((Color(1).EXP)
      OR (SRAM_Data(2).PIN AND NOT Flag(0))
      OR (SRAM_Data(2).PIN AND HCounter(7) AND HCounter(9)));
     VGA_RGB(2) <= VGA_RGB_I(2) when VGA_RGB_OE(2) = '1' else 'Z';
     VGA_RGB_OE(2) <= Reset;
FDCPE_VGA_RGB3: FDCPE port map (VGA_RGB_I(3),VGA_RGB(3),NOT Clock,NOT Flag(0),'0');
     VGA_RGB(3) <= ((SRAM_Data(3).PIN AND NOT Flag(0))
      OR (SRAM_Data(3).PIN AND HCounter(7) AND HCounter(9))
      OR (SRAM_Data(3).PIN AND HCounter(8) AND HCounter(9)));
     VGA_RGB(3) <= VGA_RGB_I(3) when VGA_RGB_OE(3) = '1' else 'Z';
     VGA_RGB_OE(3) <= Reset;
FDCPE_VGA_RGB4: FDCPE port map (VGA_RGB_I(4),VGA_RGB(4),NOT Clock,NOT Flag(0),'0');
     VGA_RGB(4) <= ((SRAM_Data(4).PIN AND NOT Flag(0))
      OR (SRAM_Data(4).PIN AND HCounter(7) AND HCounter(9))
      OR (SRAM_Data(4).PIN AND HCounter(8) AND HCounter(9)));
     VGA_RGB(4) <= VGA_RGB_I(4) when VGA_RGB_OE(4) = '1' else 'Z';
     VGA_RGB_OE(4) <= Reset;
FDCPE_VGA_RGB5: FDCPE port map (VGA_RGB_I(5),VGA_RGB(5),NOT Clock,NOT Flag(0),'0');
     VGA_RGB(5) <= ((Addr(0).EXP)
      OR (SRAM_Data(5).PIN AND NOT Flag(0))
      OR (SRAM_Data(5).PIN AND HCounter(7) AND HCounter(9)));
     VGA_RGB(5) <= VGA_RGB_I(5) when VGA_RGB_OE(5) = '1' else 'Z';
     VGA_RGB_OE(5) <= Reset;
FDCPE_Ext_CS0: FDCPE port map (Ext_CS(0),'0','0',Ext_CS_CLR(0),NOT Ext_CS_0/Ext_CS_0_SETF__$INT);
     Ext_CS_CLR(0) <= (Reset AND AVR_AH(6) AND AVR_AH(5) AND AVR_AH(4) AND
      AVR_AH(3) AND AVR_AH(2) AND NOT AVR_AH(1) AND NOT AVR_AH(0) AND NOT AVR_AH(7));
Ext_CS_0/Ext_CS_0_SETF__$INT <= ((Reset AND AVR_AH(6) AND AVR_AH(5) AND AVR_AH(4) AND
      AVR_AH(3) AND AVR_AH(2) AND AVR_AH(1) AND AVR_AH(0) AND NOT AVR_AH(7))
      OR (Reset AND AVR_AH(6) AND AVR_AH(5) AND AVR_AH(4) AND
      AVR_AH(3) AND AVR_AH(2) AND NOT AVR_AH(1) AND NOT AVR_AH(0) AND NOT AVR_AH(7)));
FDCPE_Ext_CS1: FDCPE port map (Ext_CS(1),'0','0',Ext_CS_CLR(1),NOT Ext_CS_1/Ext_CS_1_SETF__$INT);
     Ext_CS_CLR(1) <= (Reset AND AVR_AH(6) AND AVR_AH(5) AND AVR_AH(4) AND
      AVR_AH(3) AND AVR_AH(2) AND NOT AVR_AH(1) AND AVR_AH(0) AND NOT AVR_AH(7));
Ext_CS_1/Ext_CS_1_SETF__$INT <= (Reset AND AVR_AH(6) AND AVR_AH(5) AND AVR_AH(4) AND
      AVR_AH(3) AND AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(7));
FDCPE_Ext_CS2: FDCPE port map (Ext_CS(2),'0','0',Ext_CS_CLR(2),NOT Ext_CS_2/Ext_CS_2_SETF__$INT);
     Ext_CS_CLR(2) <= (Reset AND AVR_AH(6) AND AVR_AH(5) AND AVR_AH(4) AND
      AVR_AH(3) AND AVR_AH(2) AND AVR_AH(1) AND NOT AVR_AH(0) AND NOT AVR_AH(7));
Ext_CS_2/Ext_CS_2_SETF__$INT <= Ext_CS_1/Ext_CS_1_SETF__$INT.EXP;
FDCPE_Flag0: FDCPE port map (Flag(0),AVR_AD(0).PIN,NOT AVR_WR,NOT Reset,'0',Flag_CE(0));
     Flag_CE(0) <= (AVR_AL(0) AND NOT CS_CPLD);
FTCPE_HCounter0: FTCPE port map (HCounter(0),HCounter_T(0),Clock,NOT Flag(0),'0');
     HCounter_T(0) <= ((Trace.EXP)
      OR (HCounter(7) AND HCounter(8) AND NOT HCounter(0) AND
      HCounter(9)));
FDCPE_HCounter1: FDCPE port map (HCounter(1),HCounter_D(1),Clock,NOT Flag(0),'0');
     HCounter_D(1) <= ((HCounter(8).EXP)
      OR (HCounter(0) AND HCounter(1))
      OR (NOT HCounter(0) AND NOT HCounter(1)));
FDCPE_HCounter2: FDCPE port map (HCounter(2),HCounter_D(2),Clock,NOT Flag(0),'0');
     HCounter_D(2) <= ((EXP35_.EXP)
      OR (NOT HCounter(0) AND NOT HCounter(2))
      OR (NOT HCounter(1) AND NOT HCounter(2))
      OR (HCounter(7) AND HCounter(8) AND HCounter(9))
      OR (HCounter(8) AND HCounter(6) AND HCounter(9)));
FTCPE_HCounter3: FTCPE port map (HCounter(3),HCounter_T(3),Clock,NOT Flag(0),'0');
     HCounter_T(3) <= ((HCounter(4).EXP)
      OR (HCounter(7) AND HCounter(8) AND HCounter(3) AND
      HCounter(9))
      OR (HCounter(8) AND HCounter(3) AND HCounter(6) AND
      HCounter(9))
      OR (NOT HCounter(8) AND HCounter(0) AND HCounter(1) AND
      HCounter(2))
      OR (HCounter(0) AND NOT HCounter(9) AND HCounter(1) AND
      HCounter(2)));
FTCPE_HCounter4: FTCPE port map (HCounter(4),HCounter_T(4),Clock,NOT Flag(0),'0');
     HCounter_T(4) <= ((EXP34_.EXP)
      OR (HCounter(7) AND HCounter(8) AND HCounter(4) AND
      HCounter(9))
      OR (HCounter(8) AND HCounter(4) AND HCounter(6) AND
      HCounter(9)));
FTCPE_HCounter5: FTCPE port map (HCounter(5),HCounter_T(5),Clock,NOT Flag(0),'0');
     HCounter_T(5) <= ((HCounter(1).EXP)
      OR (HCounter(7) AND HCounter(8) AND HCounter(5) AND
      HCounter(9))
      OR (HCounter(8) AND HCounter(5) AND HCounter(6) AND
      HCounter(9))
      OR (HCounter(8) AND HCounter(3) AND HCounter(4) AND
      HCounter(5) AND HCounter(9))
      OR (NOT HCounter(8) AND HCounter(0) AND HCounter(3) AND
      HCounter(4) AND HCounter(1) AND HCounter(2)));
FTCPE_HCounter6: FTCPE port map (HCounter(6),HCounter_T(6),Clock,NOT Flag(0),'0');
     HCounter_T(6) <= ((HCounter(8) AND HCounter(6) AND HCounter(9))
      OR (NOT HCounter(8) AND HCounter(0) AND HCounter(3) AND
      HCounter(4) AND HCounter(5) AND HCounter(1) AND HCounter(2))
      OR (HCounter(0) AND HCounter(3) AND HCounter(4) AND
      HCounter(5) AND NOT HCounter(9) AND HCounter(1) AND HCounter(2)));
FTCPE_HCounter7: FTCPE port map (HCounter(7),HCounter_T(7),Clock,NOT Flag(0),'0');
     HCounter_T(7) <= ((HCounter(7) AND HCounter(8) AND HCounter(9))
      OR (NOT HCounter(8) AND HCounter(0) AND HCounter(3) AND
      HCounter(4) AND HCounter(5) AND HCounter(6) AND HCounter(1) AND
      HCounter(2))
      OR (HCounter(0) AND HCounter(3) AND HCounter(4) AND
      HCounter(5) AND HCounter(6) AND NOT HCounter(9) AND HCounter(1) AND
      HCounter(2)));
FTCPE_HCounter8: FTCPE port map (HCounter(8),HCounter_T(8),Clock,NOT Flag(0),'0');
     HCounter_T(8) <= ((HCounter(9).EXP)
      OR (HCounter(7) AND HCounter(0) AND HCounter(3) AND
      HCounter(4) AND HCounter(5) AND HCounter(6) AND HCounter(1) AND
      HCounter(2)));
FTCPE_HCounter9: FTCPE port map (HCounter(9),HCounter_T(9),Clock,NOT Flag(0),'0');
     HCounter_T(9) <= ((HCounter(0).EXP)
      OR (HCounter(7) AND HCounter(8) AND HCounter(0) AND
      HCounter(3) AND HCounter(4) AND HCounter(5) AND HCounter(6) AND
      HCounter(1) AND HCounter(2)));
VGA_VSync_I <= '0';
     VGA_VSync <= VGA_VSync_I when VGA_VSync_OE = '1' else 'Z';
     VGA_VSync_OE <= Reset;
VGA_HSync_I <= '0';
     VGA_HSync <= VGA_HSync_I when VGA_HSync_OE = '1' else 'Z';
     VGA_HSync_OE <= Reset;
VGA_CSync_I <= '0';
     VGA_CSync <= VGA_CSync_I when VGA_CSync_OE = '1' else 'Z';
     VGA_CSync_OE <= Reset;
FDCPE_AVR_AL0: FDCPE port map (AVR_AL_I(0),AVR_AD(0).PIN,AVR_ALE,NOT Reset,'0');
     AVR_AL(0) <= AVR_AL_I(0) when AVR_AL_OE(0) = '1' else 'Z';
     AVR_AL_OE(0) <= Reset;
FDCPE_AVR_AL1: FDCPE port map (AVR_AL_I(1),AVR_AD(1).PIN,AVR_ALE,NOT Reset,'0');
     AVR_AL(1) <= AVR_AL_I(1) when AVR_AL_OE(1) = '1' else 'Z';
     AVR_AL_OE(1) <= Reset;
FDCPE_AVR_AL2: FDCPE port map (AVR_AL_I(2),AVR_AD(2).PIN,AVR_ALE,NOT Reset,'0');
     AVR_AL(2) <= AVR_AL_I(2) when AVR_AL_OE(2) = '1' else 'Z';
     AVR_AL_OE(2) <= Reset;
FDCPE_AVR_AL3: FDCPE port map (AVR_AL_I(3),AVR_AD(3).PIN,AVR_ALE,NOT Reset,'0');
     AVR_AL(3) <= AVR_AL_I(3) when AVR_AL_OE(3) = '1' else 'Z';
     AVR_AL_OE(3) <= Reset;
FDCPE_AVR_AL4: FDCPE port map (AVR_AL_I(4),AVR_AD(4).PIN,AVR_ALE,NOT Reset,'0');
     AVR_AL(4) <= AVR_AL_I(4) when AVR_AL_OE(4) = '1' else 'Z';
     AVR_AL_OE(4) <= Reset;
FDCPE_AVR_AL5: FDCPE port map (AVR_AL_I(5),AVR_AD(5).PIN,AVR_ALE,NOT Reset,'0');
     AVR_AL(5) <= AVR_AL_I(5) when AVR_AL_OE(5) = '1' else 'Z';
     AVR_AL_OE(5) <= Reset;
FDCPE_AVR_AL6: FDCPE port map (AVR_AL_I(6),AVR_AD(6).PIN,AVR_ALE,NOT Reset,'0');
     AVR_AL(6) <= AVR_AL_I(6) when AVR_AL_OE(6) = '1' else 'Z';
     AVR_AL_OE(6) <= Reset;
FDCPE_AVR_AL7: FDCPE port map (AVR_AL_I(7),AVR_AD(7).PIN,AVR_ALE,NOT Reset,'0');
     AVR_AL(7) <= AVR_AL_I(7) when AVR_AL_OE(7) = '1' else 'Z';
     AVR_AL_OE(7) <= Reset;
AVR_AD_I(1) <= ((EXP28_.EXP)
      OR (AVR_AD(1) AND Clock)
      OR (AVR_AD(1) AND AVR_RD)
      OR (AVR_AD(1) AND NOT Reset AND CS_CPLD)
      OR (Reset AND NOT Clock AND SRAM_Data(1).PIN AND NOT AVR_AH(2) AND
      NOT AVR_RD));
     AVR_AD(1) <= AVR_AD_I(1) when AVR_AD_OE(1) = '1' else 'Z';
     AVR_AD_OE(1) <= NOT Mtrien_AVR_AD;
AVR_AD_I(2) <= ((EXP29_.EXP)
      OR (AVR_AD(2) AND Clock)
      OR (AVR_AD(2) AND AVR_RD)
      OR (AVR_AD(2) AND NOT Reset AND CS_CPLD)
      OR (Reset AND NOT Clock AND SRAM_Data(2).PIN AND NOT AVR_AH(2) AND
      NOT AVR_RD));
     AVR_AD(2) <= AVR_AD_I(2) when AVR_AD_OE(2) = '1' else 'Z';
     AVR_AD_OE(2) <= NOT Mtrien_AVR_AD;
AVR_AD_I(6) <= ((EXP18_.EXP)
      OR (Mtridata_AVR_AD(7).EXP)
      OR (AVR_AD(6) AND Clock)
      OR (AVR_AD(6) AND AVR_RD)
      OR (AVR_AD(6) AND NOT Reset AND CS_CPLD)
      OR (Reset AND NOT Clock AND NOT AVR_AH(2) AND NOT AVR_RD AND
      SRAM_Data(6).PIN));
     AVR_AD(6) <= AVR_AD_I(6) when AVR_AD_OE(6) = '1' else 'Z';
     AVR_AD_OE(6) <= NOT Mtrien_AVR_AD;
AVR_AD_I(7) <= ((EXP19_.EXP)
      OR (AVR_AD(7) AND Clock)
      OR (AVR_AD(7) AND AVR_RD));
     AVR_AD(7) <= AVR_AD_I(7) when AVR_AD_OE(7) = '1' else 'Z';
     AVR_AD_OE(7) <= NOT Mtrien_AVR_AD;
FDCPE_Mtrien_AVR_AD: FDCPE port map (Mtrien_AVR_AD,'0','0',Mtrien_AVR_AD_CLR,NOT Reset);
     Mtrien_AVR_AD_CLR <= (Reset AND NOT Clock AND NOT AVR_RD AND
      NOT $OpTx$$OpTx$FX_DC$65_INV$93);
SRAM_Addr_I(0) <= ((Addr(14).EXP)
      OR (NOT Clock AND AVR_AL(0)));
     SRAM_Addr(0) <= SRAM_Addr_I(0) when SRAM_Addr_OE(0) = '1' else 'Z';
     SRAM_Addr_OE(0) <= Reset;
SRAM_Addr_I(10) <= ((Clock AND Addr(10))
      OR (NOT Clock AND AVR_AH(2)));
     SRAM_Addr(10) <= SRAM_Addr_I(10) when SRAM_Addr_OE(10) = '1' else 'Z';
     SRAM_Addr_OE(10) <= Reset;
SRAM_Addr_I(11) <= ((Clock AND Addr(11))
      OR (NOT Clock AND AVR_AH(3)));
     SRAM_Addr(11) <= SRAM_Addr_I(11) when SRAM_Addr_OE(11) = '1' else 'Z';
     SRAM_Addr_OE(11) <= Reset;
SRAM_Addr_I(12) <= ((Clock AND Addr(12))
      OR (NOT Clock AND AVR_AH(4)));
     SRAM_Addr(12) <= SRAM_Addr_I(12) when SRAM_Addr_OE(12) = '1' else 'Z';
     SRAM_Addr_OE(12) <= Reset;
SRAM_Addr_I(13) <= ((Clock AND Addr(13))
      OR (NOT Clock AND AVR_AH(5)));
     SRAM_Addr(13) <= SRAM_Addr_I(13) when SRAM_Addr_OE(13) = '1' else 'Z';
     SRAM_Addr_OE(13) <= Reset;
SRAM_Addr_I(14) <= ((Clock AND Addr(14))
      OR (NOT Clock AND AVR_AH(6)));
     SRAM_Addr(14) <= SRAM_Addr_I(14) when SRAM_Addr_OE(14) = '1' else 'Z';
     SRAM_Addr_OE(14) <= Reset;
SRAM_Addr_I(15) <= ((Clock AND Addr(15))
      OR (NOT Clock AND Bank(0) AND AVR_AH(7)));
     SRAM_Addr(15) <= SRAM_Addr_I(15) when SRAM_Addr_OE(15) = '1' else 'Z';
     SRAM_Addr_OE(15) <= Reset;
SRAM_Addr_I(16) <= ((Clock AND Addr(16))
      OR (NOT Clock AND Bank(1) AND AVR_AH(7)));
     SRAM_Addr(16) <= SRAM_Addr_I(16) when SRAM_Addr_OE(16) = '1' else 'Z';
     SRAM_Addr_OE(16) <= Reset;
SRAM_Addr_I(17) <= ((Clock AND Addr(17))
      OR (NOT Clock AND Bank(2) AND AVR_AH(7)));
     SRAM_Addr(17) <= SRAM_Addr_I(17) when SRAM_Addr_OE(17) = '1' else 'Z';
     SRAM_Addr_OE(17) <= Reset;
SRAM_Addr_I(18) <= ((Clock AND Addr(18))
      OR (NOT Clock AND Bank(3) AND AVR_AH(7)));
     SRAM_Addr(18) <= SRAM_Addr_I(18) when SRAM_Addr_OE(18) = '1' else 'Z';
     SRAM_Addr_OE(18) <= Reset;
SRAM_Addr_I(1) <= ((Clock AND Addr(1))
      OR (NOT Clock AND AVR_AL(1)));
     SRAM_Addr(1) <= SRAM_Addr_I(1) when SRAM_Addr_OE(1) = '1' else 'Z';
     SRAM_Addr_OE(1) <= Reset;
SRAM_Addr_I(2) <= ((Clock AND Addr(2))
      OR (NOT Clock AND AVR_AL(2)));
     SRAM_Addr(2) <= SRAM_Addr_I(2) when SRAM_Addr_OE(2) = '1' else 'Z';
     SRAM_Addr_OE(2) <= Reset;
SRAM_Addr_I(3) <= ((Clock AND Addr(3))
      OR (NOT Clock AND AVR_AL(3)));
     SRAM_Addr(3) <= SRAM_Addr_I(3) when SRAM_Addr_OE(3) = '1' else 'Z';
     SRAM_Addr_OE(3) <= Reset;
SRAM_Addr_I(4) <= ((Clock AND Addr(4))
      OR (NOT Clock AND AVR_AL(4)));
     SRAM_Addr(4) <= SRAM_Addr_I(4) when SRAM_Addr_OE(4) = '1' else 'Z';
     SRAM_Addr_OE(4) <= Reset;
SRAM_Addr_I(5) <= ((Clock AND Addr(5))
      OR (NOT Clock AND AVR_AL(5)));
     SRAM_Addr(5) <= SRAM_Addr_I(5) when SRAM_Addr_OE(5) = '1' else 'Z';
     SRAM_Addr_OE(5) <= Reset;
SRAM_Addr_I(6) <= ((Clock AND Addr(6))
      OR (NOT Clock AND AVR_AL(6)));
     SRAM_Addr(6) <= SRAM_Addr_I(6) when SRAM_Addr_OE(6) = '1' else 'Z';
     SRAM_Addr_OE(6) <= Reset;
SRAM_Addr_I(7) <= ((Addr(11).EXP)
      OR (NOT Clock AND AVR_AL(7)));
     SRAM_Addr(7) <= SRAM_Addr_I(7) when SRAM_Addr_OE(7) = '1' else 'Z';
     SRAM_Addr_OE(7) <= Reset;
SRAM_Addr_I(8) <= ((Clock AND Addr(8))
      OR (NOT Clock AND AVR_AH(0)));
     SRAM_Addr(8) <= SRAM_Addr_I(8) when SRAM_Addr_OE(8) = '1' else 'Z';
     SRAM_Addr_OE(8) <= Reset;
SRAM_Addr_I(9) <= ((Clock AND Addr(9))
      OR (NOT Clock AND AVR_AH(1)));
     SRAM_Addr(9) <= SRAM_Addr_I(9) when SRAM_Addr_OE(9) = '1' else 'Z';
     SRAM_Addr_OE(9) <= Reset;
SRAM_CS_I <= ((NOT Reset AND NOT Clock)
      OR (NOT Clock AND AVR_AH(6) AND AVR_AH(5) AND AVR_AH(4) AND
      AVR_AH(3) AND AVR_AH(2) AND NOT AVR_AH(7)));
     SRAM_CS <= SRAM_CS_I when SRAM_CS_OE = '1' else 'Z';
     SRAM_CS_OE <= Reset;
SRAM_Data_I(0) <= AVR_AD(0).PIN;
     SRAM_Data(0) <= SRAM_Data_I(0) when SRAM_Data_OE(0) = '1' else 'Z';
     SRAM_Data_OE(0) <= (Reset AND NOT Clock AND NOT AVR_WR);
SRAM_Data_I(1) <= AVR_AD(1).PIN;
     SRAM_Data(1) <= SRAM_Data_I(1) when SRAM_Data_OE(1) = '1' else 'Z';
     SRAM_Data_OE(1) <= (Reset AND NOT Clock AND NOT AVR_WR);
SRAM_Data_I(2) <= AVR_AD(2).PIN;
     SRAM_Data(2) <= SRAM_Data_I(2) when SRAM_Data_OE(2) = '1' else 'Z';
     SRAM_Data_OE(2) <= (Reset AND NOT Clock AND NOT AVR_WR);
SRAM_Data_I(3) <= AVR_AD(3).PIN;
     SRAM_Data(3) <= SRAM_Data_I(3) when SRAM_Data_OE(3) = '1' else 'Z';
     SRAM_Data_OE(3) <= (Reset AND NOT Clock AND NOT AVR_WR);
SRAM_Data_I(4) <= AVR_AD(4).PIN;
     SRAM_Data(4) <= SRAM_Data_I(4) when SRAM_Data_OE(4) = '1' else 'Z';
     SRAM_Data_OE(4) <= (Reset AND NOT Clock AND NOT AVR_WR);
SRAM_Data_I(5) <= AVR_AD(5).PIN;
     SRAM_Data(5) <= SRAM_Data_I(5) when SRAM_Data_OE(5) = '1' else 'Z';
     SRAM_Data_OE(5) <= (Reset AND NOT Clock AND NOT AVR_WR);
SRAM_Data_I(6) <= AVR_AD(6).PIN;
     SRAM_Data(6) <= SRAM_Data_I(6) when SRAM_Data_OE(6) = '1' else 'Z';
     SRAM_Data_OE(6) <= (Reset AND NOT Clock AND NOT AVR_WR);
SRAM_Data_I(7) <= AVR_AD(7).PIN;
     SRAM_Data(7) <= SRAM_Data_I(7) when SRAM_Data_OE(7) = '1' else 'Z';
     SRAM_Data_OE(7) <= (Reset AND NOT Clock AND NOT AVR_WR);
SRAM_OE_I <= (NOT Clock AND AVR_RD);
     SRAM_OE <= SRAM_OE_I when SRAM_OE_OE = '1' else 'Z';
     SRAM_OE_OE <= Reset;
SRAM_WR_I <= NOT ((NOT Clock AND NOT AVR_WR));
     SRAM_WR <= SRAM_WR_I when SRAM_WR_OE = '1' else 'Z';
     SRAM_WR_OE <= Reset;
VGA_Trace_I <= NOT (((Flag(0) AND NOT HCounter(9))
      OR (Flag(0) AND NOT HCounter(7) AND NOT HCounter(8))));
     VGA_Trace <= VGA_Trace_I when VGA_Trace_OE = '1' else 'Z';
     VGA_Trace_OE <= Reset;
AVR_AD_I(5) <= AVR_AD(5)_BUFR;
     AVR_AD(5) <= AVR_AD_I(5) when AVR_AD_OE(5) = '1' else 'Z';
     AVR_AD_OE(5) <= NOT Mtrien_AVR_AD;
AVR_AD_I(4) <= AVR_AD(4)_BUFR;
     AVR_AD(4) <= AVR_AD_I(4) when AVR_AD_OE(4) = '1' else 'Z';
     AVR_AD_OE(4) <= NOT Mtrien_AVR_AD;
AVR_AD_I(0) <= AVR_AD(0)_BUFR;
     AVR_AD(0) <= AVR_AD_I(0) when AVR_AD_OE(0) = '1' else 'Z';
     AVR_AD_OE(0) <= NOT Mtrien_AVR_AD;
AVR_AD_I(3) <= AVR_AD(3)_BUFR;
     AVR_AD(3) <= AVR_AD_I(3) when AVR_AD_OE(3) = '1' else 'Z';
     AVR_AD_OE(3) <= NOT Mtrien_AVR_AD;
Register Legend:
      FDCPE (Q,D,C,CLR,PRE,CE);
      FTCPE (Q,D,C,CLR,PRE,CE);
      LDCP (Q,D,G,CLR,PRE);