Design Name | avga |
Device, Speed (SpeedFile Version) | XC95144XL, -5 (3.0) |
Date Created | Sat Mar 05 15:34:57 2005 |
Created By | Timing Report Generator: version G.36 |
Copyright | Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. |
Performance Summary | |
---|---|
Min. Clock Period | 6.300 ns. |
Max. Clock Frequency (fSYSTEM) | 158.730 MHz. |
Limited by Cycle Time for Clock | |
Clock to Setup (tCYC) | 6.300 ns. |
Pad to Pad Delay (tPD) | 9.400 ns. |
Setup to Clock at the Pad (tSU) | 4.400 ns. |
Clock Pad to Output Pad Delay (tCO) | 11.300 ns. |
Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
---|---|---|---|---|
TS_Clock | 20.0 | 0.0 | 0 | 0 |
TS_AVR_WR | 20.0 | 0.0 | 0 | 0 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|
Clock | fEXT (MHz) | Reason |
---|---|---|
AVR_ALE | 178.571 | Limited by Clock Pulse Width for AVR_ALE |
AVR_WR | 178.571 | Limited by Clock Pulse Width for AVR_WR |
Clock | 158.730 | Limited by Cycle Time for Clock |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
AVR_AD<0> | 3.700 | 0.000 |
AVR_AD<1> | 3.700 | 0.000 |
AVR_AD<2> | 3.700 | 0.000 |
AVR_AD<3> | 3.700 | 0.000 |
AVR_AD<4> | 3.700 | 0.000 |
AVR_AD<5> | 3.700 | 0.000 |
AVR_AD<6> | 3.700 | 0.000 |
AVR_AD<7> | 3.700 | 0.000 |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
AVR_AD<0> | 3.700 | 0.000 |
AVR_AD<1> | 3.700 | 0.000 |
AVR_AD<2> | 3.700 | 0.000 |
AVR_AD<3> | 3.700 | 0.000 |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
SRAM_Data<0> | 4.400 | 0.000 |
SRAM_Data<1> | 4.400 | 0.000 |
SRAM_Data<2> | 4.400 | 0.000 |
SRAM_Data<3> | 3.700 | 0.000 |
SRAM_Data<4> | 3.700 | 0.000 |
SRAM_Data<5> | 4.400 | 0.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
AVR_AD<0> | 11.300 |
AVR_AD<3> | 11.000 |
AVR_AD<4> | 11.000 |
AVR_AD<5> | 11.000 |
AVR_AD<7> | 8.200 |
AVR_AD<1> | 7.900 |
AVR_AD<2> | 7.900 |
AVR_AD<6> | 7.900 |
SRAM_Addr<0> | 6.900 |
SRAM_Addr<1> | 6.900 |
SRAM_Addr<2> | 6.900 |
SRAM_Addr<3> | 6.900 |
SRAM_Addr<4> | 6.900 |
SRAM_Addr<5> | 6.900 |
SRAM_Addr<6> | 6.900 |
SRAM_Addr<7> | 6.900 |
AVR_AL<0> | 3.500 |
AVR_AL<1> | 3.500 |
AVR_AL<2> | 3.500 |
AVR_AL<3> | 3.500 |
AVR_AL<4> | 3.500 |
AVR_AL<5> | 3.500 |
AVR_AL<6> | 3.500 |
AVR_AL<7> | 3.500 |
Destination Pad | Clock (edge) to Pad |
---|---|
AVR_AD<0> | 11.300 |
AVR_AD<3> | 11.000 |
AVR_AD<1> | 7.900 |
AVR_AD<2> | 7.900 |
SRAM_Addr<15> | 6.900 |
SRAM_Addr<16> | 6.900 |
SRAM_Addr<17> | 6.900 |
SRAM_Addr<18> | 6.900 |
VGA_Trace | 6.900 |
Destination Pad | Clock (edge) to Pad |
---|---|
SRAM_Addr<0> | 7.600 |
SRAM_Addr<7> | 7.600 |
SRAM_Addr<10> | 6.900 |
SRAM_Addr<11> | 6.900 |
SRAM_Addr<12> | 6.900 |
SRAM_Addr<13> | 6.900 |
SRAM_Addr<14> | 6.900 |
SRAM_Addr<15> | 6.900 |
SRAM_Addr<16> | 6.900 |
SRAM_Addr<17> | 6.900 |
SRAM_Addr<18> | 6.900 |
SRAM_Addr<1> | 6.900 |
SRAM_Addr<2> | 6.900 |
SRAM_Addr<3> | 6.900 |
SRAM_Addr<4> | 6.900 |
SRAM_Addr<5> | 6.900 |
SRAM_Addr<6> | 6.900 |
SRAM_Addr<8> | 6.900 |
SRAM_Addr<9> | 6.900 |
VGA_Trace | 6.900 |
AVR_Clock | 3.500 |
VGA_RGB<0> | 3.500 |
VGA_RGB<1> | 3.500 |
VGA_RGB<2> | 3.500 |
VGA_RGB<3> | 3.500 |
VGA_RGB<4> | 3.500 |
VGA_RGB<5> | 3.500 |
Source | Destination | Delay |
---|---|---|
Addr<0>.Q | Addr<10>.D | 6.300 |
Addr<0>.Q | Addr<11>.D | 6.300 |
Addr<0>.Q | Addr<12>.D | 6.300 |
Addr<0>.Q | Addr<13>.D | 6.300 |
Addr<0>.Q | Addr<14>.D | 6.300 |
Addr<0>.Q | Addr<15>.D | 6.300 |
Addr<0>.Q | Addr<16>.D | 6.300 |
Addr<0>.Q | Addr<17>.D | 6.300 |
Addr<0>.Q | Addr<18>.D | 6.300 |
Addr<0>.Q | Addr<2>.D | 6.300 |
Addr<0>.Q | Addr<3>.D | 6.300 |
Addr<0>.Q | Addr<4>.D | 6.300 |
Addr<0>.Q | Addr<5>.D | 6.300 |
Addr<0>.Q | Addr<6>.D | 6.300 |
Addr<0>.Q | Addr<7>.D | 6.300 |
Addr<0>.Q | Addr<8>.D | 6.300 |
Addr<0>.Q | Addr<9>.D | 6.300 |
Addr<10>.Q | Addr<11>.D | 6.300 |
Addr<10>.Q | Addr<12>.D | 6.300 |
Addr<10>.Q | Addr<13>.D | 6.300 |
Addr<10>.Q | Addr<14>.D | 6.300 |
Addr<10>.Q | Addr<15>.D | 6.300 |
Addr<10>.Q | Addr<16>.D | 6.300 |
Addr<10>.Q | Addr<17>.D | 6.300 |
Addr<10>.Q | Addr<18>.D | 6.300 |
Addr<11>.Q | Addr<12>.D | 6.300 |
Addr<11>.Q | Addr<13>.D | 6.300 |
Addr<11>.Q | Addr<14>.D | 6.300 |
Addr<11>.Q | Addr<15>.D | 6.300 |
Addr<11>.Q | Addr<16>.D | 6.300 |
Addr<11>.Q | Addr<17>.D | 6.300 |
Addr<11>.Q | Addr<18>.D | 6.300 |
Addr<12>.Q | Addr<13>.D | 6.300 |
Addr<12>.Q | Addr<14>.D | 6.300 |
Addr<12>.Q | Addr<15>.D | 6.300 |
Addr<12>.Q | Addr<16>.D | 6.300 |
Addr<12>.Q | Addr<17>.D | 6.300 |
Addr<12>.Q | Addr<18>.D | 6.300 |
Addr<13>.Q | Addr<14>.D | 6.300 |
Addr<13>.Q | Addr<15>.D | 6.300 |
Addr<13>.Q | Addr<16>.D | 6.300 |
Addr<13>.Q | Addr<17>.D | 6.300 |
Addr<13>.Q | Addr<18>.D | 6.300 |
Addr<14>.Q | Addr<15>.D | 6.300 |
Addr<14>.Q | Addr<16>.D | 6.300 |
Addr<14>.Q | Addr<17>.D | 6.300 |
Addr<14>.Q | Addr<18>.D | 6.300 |
Addr<15>.Q | Addr<15>.D | 6.300 |
Addr<15>.Q | Addr<16>.D | 6.300 |
Addr<15>.Q | Addr<17>.D | 6.300 |
Addr<15>.Q | Addr<18>.D | 6.300 |
Addr<16>.Q | Addr<17>.D | 6.300 |
Addr<16>.Q | Addr<18>.D | 6.300 |
Addr<17>.Q | Addr<18>.D | 6.300 |
Addr<1>.Q | Addr<10>.D | 6.300 |
Addr<1>.Q | Addr<11>.D | 6.300 |
Addr<1>.Q | Addr<12>.D | 6.300 |
Addr<1>.Q | Addr<13>.D | 6.300 |
Addr<1>.Q | Addr<14>.D | 6.300 |
Addr<1>.Q | Addr<15>.D | 6.300 |
Addr<1>.Q | Addr<16>.D | 6.300 |
Addr<1>.Q | Addr<17>.D | 6.300 |
Addr<1>.Q | Addr<18>.D | 6.300 |
Addr<1>.Q | Addr<2>.D | 6.300 |
Addr<1>.Q | Addr<3>.D | 6.300 |
Addr<1>.Q | Addr<4>.D | 6.300 |
Addr<1>.Q | Addr<5>.D | 6.300 |
Addr<1>.Q | Addr<6>.D | 6.300 |
Addr<1>.Q | Addr<7>.D | 6.300 |
Addr<1>.Q | Addr<8>.D | 6.300 |
Addr<1>.Q | Addr<9>.D | 6.300 |
Addr<2>.Q | Addr<10>.D | 6.300 |
Addr<2>.Q | Addr<11>.D | 6.300 |
Addr<2>.Q | Addr<12>.D | 6.300 |
Addr<2>.Q | Addr<13>.D | 6.300 |
Addr<2>.Q | Addr<14>.D | 6.300 |
Addr<2>.Q | Addr<15>.D | 6.300 |
Addr<2>.Q | Addr<16>.D | 6.300 |
Addr<2>.Q | Addr<17>.D | 6.300 |
Addr<2>.Q | Addr<18>.D | 6.300 |
Addr<2>.Q | Addr<2>.D | 6.300 |
Addr<2>.Q | Addr<3>.D | 6.300 |
Addr<2>.Q | Addr<4>.D | 6.300 |
Addr<2>.Q | Addr<5>.D | 6.300 |
Addr<2>.Q | Addr<6>.D | 6.300 |
Addr<2>.Q | Addr<7>.D | 6.300 |
Addr<2>.Q | Addr<8>.D | 6.300 |
Addr<2>.Q | Addr<9>.D | 6.300 |
Addr<3>.Q | Addr<10>.D | 6.300 |
Addr<3>.Q | Addr<11>.D | 6.300 |
Addr<3>.Q | Addr<12>.D | 6.300 |
Addr<3>.Q | Addr<13>.D | 6.300 |
Addr<3>.Q | Addr<14>.D | 6.300 |
Addr<3>.Q | Addr<15>.D | 6.300 |
Addr<3>.Q | Addr<16>.D | 6.300 |
Addr<3>.Q | Addr<17>.D | 6.300 |
Addr<3>.Q | Addr<18>.D | 6.300 |
Addr<3>.Q | Addr<4>.D | 6.300 |
Addr<3>.Q | Addr<5>.D | 6.300 |
Addr<3>.Q | Addr<6>.D | 6.300 |
Addr<3>.Q | Addr<7>.D | 6.300 |
Addr<3>.Q | Addr<8>.D | 6.300 |
Addr<3>.Q | Addr<9>.D | 6.300 |
Addr<4>.Q | Addr<10>.D | 6.300 |
Addr<4>.Q | Addr<11>.D | 6.300 |
Addr<4>.Q | Addr<12>.D | 6.300 |
Addr<4>.Q | Addr<13>.D | 6.300 |
Addr<4>.Q | Addr<14>.D | 6.300 |
Addr<4>.Q | Addr<15>.D | 6.300 |
Addr<4>.Q | Addr<16>.D | 6.300 |
Addr<4>.Q | Addr<17>.D | 6.300 |
Addr<4>.Q | Addr<18>.D | 6.300 |
Addr<4>.Q | Addr<5>.D | 6.300 |
Addr<4>.Q | Addr<6>.D | 6.300 |
Addr<4>.Q | Addr<7>.D | 6.300 |
Addr<4>.Q | Addr<8>.D | 6.300 |
Addr<4>.Q | Addr<9>.D | 6.300 |
Addr<5>.Q | Addr<10>.D | 6.300 |
Addr<5>.Q | Addr<11>.D | 6.300 |
Addr<5>.Q | Addr<12>.D | 6.300 |
Addr<5>.Q | Addr<13>.D | 6.300 |
Addr<5>.Q | Addr<14>.D | 6.300 |
Addr<5>.Q | Addr<15>.D | 6.300 |
Addr<5>.Q | Addr<16>.D | 6.300 |
Addr<5>.Q | Addr<17>.D | 6.300 |
Addr<5>.Q | Addr<18>.D | 6.300 |
Addr<5>.Q | Addr<6>.D | 6.300 |
Addr<5>.Q | Addr<7>.D | 6.300 |
Addr<5>.Q | Addr<8>.D | 6.300 |
Addr<5>.Q | Addr<9>.D | 6.300 |
Addr<6>.Q | Addr<10>.D | 6.300 |
Addr<6>.Q | Addr<11>.D | 6.300 |
Addr<6>.Q | Addr<12>.D | 6.300 |
Addr<6>.Q | Addr<13>.D | 6.300 |
Addr<6>.Q | Addr<14>.D | 6.300 |
Addr<6>.Q | Addr<15>.D | 6.300 |
Addr<6>.Q | Addr<16>.D | 6.300 |
Addr<6>.Q | Addr<17>.D | 6.300 |
Addr<6>.Q | Addr<18>.D | 6.300 |
Addr<6>.Q | Addr<7>.D | 6.300 |
Addr<6>.Q | Addr<8>.D | 6.300 |
Addr<6>.Q | Addr<9>.D | 6.300 |
Addr<7>.Q | Addr<10>.D | 6.300 |
Addr<7>.Q | Addr<11>.D | 6.300 |
Addr<7>.Q | Addr<12>.D | 6.300 |
Addr<7>.Q | Addr<13>.D | 6.300 |
Addr<7>.Q | Addr<14>.D | 6.300 |
Addr<7>.Q | Addr<15>.D | 6.300 |
Addr<7>.Q | Addr<16>.D | 6.300 |
Addr<7>.Q | Addr<17>.D | 6.300 |
Addr<7>.Q | Addr<18>.D | 6.300 |
Addr<7>.Q | Addr<8>.D | 6.300 |
Addr<7>.Q | Addr<9>.D | 6.300 |
Addr<8>.Q | Addr<10>.D | 6.300 |
Addr<8>.Q | Addr<11>.D | 6.300 |
Addr<8>.Q | Addr<12>.D | 6.300 |
Addr<8>.Q | Addr<13>.D | 6.300 |
Addr<8>.Q | Addr<14>.D | 6.300 |
Addr<8>.Q | Addr<15>.D | 6.300 |
Addr<8>.Q | Addr<16>.D | 6.300 |
Addr<8>.Q | Addr<17>.D | 6.300 |
Addr<8>.Q | Addr<18>.D | 6.300 |
Addr<8>.Q | Addr<9>.D | 6.300 |
Addr<9>.Q | Addr<10>.D | 6.300 |
Addr<9>.Q | Addr<11>.D | 6.300 |
Addr<9>.Q | Addr<12>.D | 6.300 |
Addr<9>.Q | Addr<13>.D | 6.300 |
Addr<9>.Q | Addr<14>.D | 6.300 |
Addr<9>.Q | Addr<15>.D | 6.300 |
Addr<9>.Q | Addr<16>.D | 6.300 |
Addr<9>.Q | Addr<17>.D | 6.300 |
Addr<9>.Q | Addr<18>.D | 6.300 |
HCounter<0>.Q | HCounter<0>.D | 6.300 |
HCounter<0>.Q | HCounter<2>.D | 6.300 |
HCounter<0>.Q | HCounter<3>.D | 6.300 |
HCounter<0>.Q | HCounter<4>.D | 6.300 |
HCounter<0>.Q | HCounter<5>.D | 6.300 |
HCounter<1>.Q | HCounter<2>.D | 6.300 |
HCounter<1>.Q | HCounter<3>.D | 6.300 |
HCounter<1>.Q | HCounter<4>.D | 6.300 |
HCounter<1>.Q | HCounter<5>.D | 6.300 |
HCounter<2>.Q | HCounter<2>.D | 6.300 |
HCounter<2>.Q | HCounter<3>.D | 6.300 |
HCounter<2>.Q | HCounter<4>.D | 6.300 |
HCounter<2>.Q | HCounter<5>.D | 6.300 |
HCounter<3>.Q | HCounter<0>.D | 6.300 |
HCounter<3>.Q | HCounter<1>.D | 6.300 |
HCounter<3>.Q | HCounter<2>.D | 6.300 |
HCounter<3>.Q | HCounter<3>.D | 6.300 |
HCounter<3>.Q | HCounter<4>.D | 6.300 |
HCounter<3>.Q | HCounter<5>.D | 6.300 |
HCounter<3>.Q | HCounter<8>.D | 6.300 |
HCounter<3>.Q | HCounter<9>.D | 6.300 |
HCounter<4>.Q | HCounter<0>.D | 6.300 |
HCounter<4>.Q | HCounter<1>.D | 6.300 |
HCounter<4>.Q | HCounter<2>.D | 6.300 |
HCounter<4>.Q | HCounter<3>.D | 6.300 |
HCounter<4>.Q | HCounter<4>.D | 6.300 |
HCounter<4>.Q | HCounter<5>.D | 6.300 |
HCounter<4>.Q | HCounter<8>.D | 6.300 |
HCounter<4>.Q | HCounter<9>.D | 6.300 |
HCounter<5>.Q | HCounter<0>.D | 6.300 |
HCounter<5>.Q | HCounter<1>.D | 6.300 |
HCounter<5>.Q | HCounter<2>.D | 6.300 |
HCounter<5>.Q | HCounter<3>.D | 6.300 |
HCounter<5>.Q | HCounter<4>.D | 6.300 |
HCounter<5>.Q | HCounter<8>.D | 6.300 |
HCounter<5>.Q | HCounter<9>.D | 6.300 |
HCounter<6>.Q | HCounter<0>.D | 6.300 |
HCounter<6>.Q | HCounter<1>.D | 6.300 |
HCounter<6>.Q | HCounter<3>.D | 6.300 |
HCounter<6>.Q | HCounter<4>.D | 6.300 |
HCounter<6>.Q | HCounter<5>.D | 6.300 |
HCounter<6>.Q | HCounter<8>.D | 6.300 |
HCounter<6>.Q | HCounter<9>.D | 6.300 |
HCounter<7>.Q | Addr<10>.D | 6.300 |
HCounter<7>.Q | Addr<11>.D | 6.300 |
HCounter<7>.Q | Addr<14>.D | 6.300 |
HCounter<7>.Q | Addr<15>.D | 6.300 |
HCounter<7>.Q | Addr<16>.D | 6.300 |
HCounter<7>.Q | Addr<18>.D | 6.300 |
HCounter<7>.Q | Addr<1>.D | 6.300 |
HCounter<7>.Q | Addr<2>.D | 6.300 |
HCounter<7>.Q | Addr<4>.D | 6.300 |
HCounter<7>.Q | Addr<9>.D | 6.300 |
HCounter<7>.Q | HCounter<1>.D | 6.300 |
HCounter<7>.Q | HCounter<3>.D | 6.300 |
HCounter<7>.Q | HCounter<4>.D | 6.300 |
HCounter<7>.Q | HCounter<5>.D | 6.300 |
HCounter<7>.Q | HCounter<8>.D | 6.300 |
HCounter<7>.Q | HCounter<9>.D | 6.300 |
HCounter<7>.Q | VGA_RGB<0>.D | 6.300 |
HCounter<8>.Q | Addr<10>.D | 6.300 |
HCounter<8>.Q | Addr<11>.D | 6.300 |
HCounter<8>.Q | Addr<12>.D | 6.300 |
HCounter<8>.Q | Addr<13>.D | 6.300 |
HCounter<8>.Q | Addr<14>.D | 6.300 |
HCounter<8>.Q | Addr<15>.D | 6.300 |
HCounter<8>.Q | Addr<16>.D | 6.300 |
HCounter<8>.Q | Addr<17>.D | 6.300 |
HCounter<8>.Q | Addr<18>.D | 6.300 |
HCounter<8>.Q | Addr<1>.D | 6.300 |
HCounter<8>.Q | Addr<2>.D | 6.300 |
HCounter<8>.Q | Addr<3>.D | 6.300 |
HCounter<8>.Q | Addr<4>.D | 6.300 |
HCounter<8>.Q | Addr<5>.D | 6.300 |
HCounter<8>.Q | Addr<6>.D | 6.300 |
HCounter<8>.Q | Addr<7>.D | 6.300 |
HCounter<8>.Q | Addr<8>.D | 6.300 |
HCounter<8>.Q | Addr<9>.D | 6.300 |
HCounter<8>.Q | HCounter<0>.D | 6.300 |
HCounter<8>.Q | HCounter<1>.D | 6.300 |
HCounter<8>.Q | HCounter<2>.D | 6.300 |
HCounter<8>.Q | HCounter<3>.D | 6.300 |
HCounter<8>.Q | HCounter<4>.D | 6.300 |
HCounter<8>.Q | HCounter<8>.D | 6.300 |
HCounter<8>.Q | HCounter<9>.D | 6.300 |
HCounter<8>.Q | VGA_RGB<0>.D | 6.300 |
HCounter<8>.Q | VGA_RGB<1>.D | 6.300 |
HCounter<8>.Q | VGA_RGB<2>.D | 6.300 |
HCounter<8>.Q | VGA_RGB<5>.D | 6.300 |
HCounter<9>.Q | Addr<10>.D | 6.300 |
HCounter<9>.Q | Addr<11>.D | 6.300 |
HCounter<9>.Q | Addr<12>.D | 6.300 |
HCounter<9>.Q | Addr<13>.D | 6.300 |
HCounter<9>.Q | Addr<14>.D | 6.300 |
HCounter<9>.Q | Addr<15>.D | 6.300 |
HCounter<9>.Q | Addr<16>.D | 6.300 |
HCounter<9>.Q | Addr<17>.D | 6.300 |
HCounter<9>.Q | Addr<18>.D | 6.300 |
HCounter<9>.Q | Addr<3>.D | 6.300 |
HCounter<9>.Q | Addr<4>.D | 6.300 |
HCounter<9>.Q | Addr<5>.D | 6.300 |
HCounter<9>.Q | Addr<6>.D | 6.300 |
HCounter<9>.Q | Addr<7>.D | 6.300 |
HCounter<9>.Q | Addr<8>.D | 6.300 |
HCounter<9>.Q | Addr<9>.D | 6.300 |
HCounter<9>.Q | HCounter<0>.D | 6.300 |
HCounter<9>.Q | HCounter<1>.D | 6.300 |
HCounter<9>.Q | HCounter<2>.D | 6.300 |
HCounter<9>.Q | HCounter<3>.D | 6.300 |
HCounter<9>.Q | HCounter<4>.D | 6.300 |
HCounter<9>.Q | HCounter<5>.D | 6.300 |
HCounter<9>.Q | HCounter<8>.D | 6.300 |
HCounter<9>.Q | HCounter<9>.D | 6.300 |
HCounter<9>.Q | VGA_RGB<0>.D | 6.300 |
HCounter<9>.Q | VGA_RGB<1>.D | 6.300 |
HCounter<9>.Q | VGA_RGB<2>.D | 6.300 |
HCounter<9>.Q | VGA_RGB<5>.D | 6.300 |
Addr<0>.Q | Addr<0>.D | 5.600 |
Addr<0>.Q | Addr<1>.D | 5.600 |
Addr<10>.Q | Addr<10>.D | 5.600 |
Addr<11>.Q | Addr<11>.D | 5.600 |
Addr<12>.Q | Addr<12>.D | 5.600 |
Addr<13>.Q | Addr<13>.D | 5.600 |
Addr<14>.Q | Addr<14>.D | 5.600 |
Addr<16>.Q | Addr<16>.D | 5.600 |
Addr<17>.Q | Addr<17>.D | 5.600 |
Addr<18>.Q | Addr<18>.D | 5.600 |
Addr<1>.Q | Addr<1>.D | 5.600 |
Addr<3>.Q | Addr<3>.D | 5.600 |
Addr<4>.Q | Addr<4>.D | 5.600 |
Addr<5>.Q | Addr<5>.D | 5.600 |
Addr<6>.Q | Addr<6>.D | 5.600 |
Addr<7>.Q | Addr<7>.D | 5.600 |
Addr<8>.Q | Addr<8>.D | 5.600 |
Addr<9>.Q | Addr<9>.D | 5.600 |
HCounter<0>.Q | HCounter<1>.D | 5.600 |
HCounter<0>.Q | HCounter<6>.D | 5.600 |
HCounter<0>.Q | HCounter<7>.D | 5.600 |
HCounter<0>.Q | HCounter<8>.D | 5.600 |
HCounter<0>.Q | HCounter<9>.D | 5.600 |
HCounter<1>.Q | HCounter<1>.D | 5.600 |
HCounter<1>.Q | HCounter<6>.D | 5.600 |
HCounter<1>.Q | HCounter<7>.D | 5.600 |
HCounter<1>.Q | HCounter<8>.D | 5.600 |
HCounter<1>.Q | HCounter<9>.D | 5.600 |
HCounter<2>.Q | HCounter<6>.D | 5.600 |
HCounter<2>.Q | HCounter<7>.D | 5.600 |
HCounter<2>.Q | HCounter<8>.D | 5.600 |
HCounter<2>.Q | HCounter<9>.D | 5.600 |
HCounter<3>.Q | HCounter<6>.D | 5.600 |
HCounter<3>.Q | HCounter<7>.D | 5.600 |
HCounter<4>.Q | HCounter<6>.D | 5.600 |
HCounter<4>.Q | HCounter<7>.D | 5.600 |
HCounter<5>.Q | HCounter<5>.D | 5.600 |
HCounter<5>.Q | HCounter<6>.D | 5.600 |
HCounter<5>.Q | HCounter<7>.D | 5.600 |
HCounter<6>.Q | HCounter<2>.D | 5.600 |
HCounter<6>.Q | HCounter<6>.D | 5.600 |
HCounter<6>.Q | HCounter<7>.D | 5.600 |
HCounter<7>.Q | Addr<0>.D | 5.600 |
HCounter<7>.Q | Addr<12>.D | 5.600 |
HCounter<7>.Q | Addr<13>.D | 5.600 |
HCounter<7>.Q | Addr<17>.D | 5.600 |
HCounter<7>.Q | Addr<3>.D | 5.600 |
HCounter<7>.Q | Addr<5>.D | 5.600 |
HCounter<7>.Q | Addr<6>.D | 5.600 |
HCounter<7>.Q | Addr<7>.D | 5.600 |
HCounter<7>.Q | Addr<8>.D | 5.600 |
HCounter<7>.Q | HCounter<0>.D | 5.600 |
HCounter<7>.Q | HCounter<2>.D | 5.600 |
HCounter<7>.Q | HCounter<7>.D | 5.600 |
HCounter<7>.Q | VGA_RGB<1>.D | 5.600 |
HCounter<7>.Q | VGA_RGB<2>.D | 5.600 |
HCounter<7>.Q | VGA_RGB<3>.D | 5.600 |
HCounter<7>.Q | VGA_RGB<4>.D | 5.600 |
HCounter<7>.Q | VGA_RGB<5>.D | 5.600 |
HCounter<8>.Q | Addr<0>.D | 5.600 |
HCounter<8>.Q | HCounter<5>.D | 5.600 |
HCounter<8>.Q | HCounter<6>.D | 5.600 |
HCounter<8>.Q | HCounter<7>.D | 5.600 |
HCounter<8>.Q | VGA_RGB<3>.D | 5.600 |
HCounter<8>.Q | VGA_RGB<4>.D | 5.600 |
HCounter<9>.Q | Addr<0>.D | 5.600 |
HCounter<9>.Q | Addr<1>.D | 5.600 |
HCounter<9>.Q | Addr<2>.D | 5.600 |
HCounter<9>.Q | HCounter<6>.D | 5.600 |
HCounter<9>.Q | HCounter<7>.D | 5.600 |
HCounter<9>.Q | VGA_RGB<3>.D | 5.600 |
HCounter<9>.Q | VGA_RGB<4>.D | 5.600 |
Source Pad | Destination Pad | Delay |
---|---|---|
AVR_AH<2> | AVR_AD<0> | 9.400 |
AVR_AH<2> | AVR_AD<4> | 9.400 |
AVR_AH<2> | AVR_AD<5> | 9.400 |
AVR_AH<3> | AVR_AD<0> | 9.400 |
AVR_AH<3> | AVR_AD<4> | 9.400 |
AVR_AH<3> | AVR_AD<5> | 9.400 |
AVR_AH<4> | AVR_AD<0> | 9.400 |
AVR_AH<4> | AVR_AD<4> | 9.400 |
AVR_AH<4> | AVR_AD<5> | 9.400 |
AVR_AH<5> | AVR_AD<0> | 9.400 |
AVR_AH<5> | AVR_AD<4> | 9.400 |
AVR_AH<5> | AVR_AD<5> | 9.400 |
AVR_AH<6> | AVR_AD<0> | 9.400 |
AVR_AH<6> | AVR_AD<4> | 9.400 |
AVR_AH<6> | AVR_AD<5> | 9.400 |
AVR_AH<7> | AVR_AD<0> | 9.400 |
AVR_AH<7> | AVR_AD<4> | 9.400 |
AVR_AH<7> | AVR_AD<5> | 9.400 |
AVR_RD | AVR_AD<0> | 9.400 |
Clock | AVR_AD<0> | 9.400 |
Reset | AVR_AD<4> | 9.400 |
Reset | AVR_AD<5> | 9.400 |
AVR_AH<2> | AVR_AD<3> | 9.100 |
AVR_AH<3> | AVR_AD<3> | 9.100 |
AVR_AH<4> | AVR_AD<3> | 9.100 |
AVR_AH<5> | AVR_AD<3> | 9.100 |
AVR_AH<6> | AVR_AD<3> | 9.100 |
AVR_AH<7> | AVR_AD<3> | 9.100 |
AVR_RD | AVR_AD<3> | 9.100 |
AVR_RD | AVR_AD<4> | 9.100 |
AVR_RD | AVR_AD<5> | 9.100 |
Clock | AVR_AD<3> | 9.100 |
Clock | AVR_AD<4> | 9.100 |
Clock | AVR_AD<5> | 9.100 |
Reset | AVR_AD<0> | 9.100 |
Reset | AVR_AD<3> | 9.100 |
SRAM_Data<4> | AVR_AD<4> | 7.900 |
SRAM_Data<5> | AVR_AD<5> | 7.900 |
SRAM_Data<0> | AVR_AD<0> | 7.600 |
SRAM_Data<3> | AVR_AD<3> | 7.600 |
AVR_WR | SRAM_Data<0> | 7.000 |
AVR_WR | SRAM_Data<1> | 7.000 |
AVR_WR | SRAM_Data<2> | 7.000 |
AVR_WR | SRAM_Data<3> | 7.000 |
AVR_WR | SRAM_Data<4> | 7.000 |
AVR_WR | SRAM_Data<5> | 7.000 |
AVR_WR | SRAM_Data<6> | 7.000 |
AVR_WR | SRAM_Data<7> | 7.000 |
Clock | SRAM_Data<0> | 7.000 |
Clock | SRAM_Data<1> | 7.000 |
Clock | SRAM_Data<2> | 7.000 |
Clock | SRAM_Data<3> | 7.000 |
Clock | SRAM_Data<4> | 7.000 |
Clock | SRAM_Data<5> | 7.000 |
Clock | SRAM_Data<6> | 7.000 |
Clock | SRAM_Data<7> | 7.000 |
Reset | AVR_AL<0> | 7.000 |
Reset | AVR_AL<1> | 7.000 |
Reset | AVR_AL<2> | 7.000 |
Reset | AVR_AL<3> | 7.000 |
Reset | AVR_AL<4> | 7.000 |
Reset | AVR_AL<5> | 7.000 |
Reset | AVR_AL<6> | 7.000 |
Reset | AVR_AL<7> | 7.000 |
Reset | SRAM_Addr<0> | 7.000 |
Reset | SRAM_Addr<10> | 7.000 |
Reset | SRAM_Addr<11> | 7.000 |
Reset | SRAM_Addr<12> | 7.000 |
Reset | SRAM_Addr<13> | 7.000 |
Reset | SRAM_Addr<14> | 7.000 |
Reset | SRAM_Addr<15> | 7.000 |
Reset | SRAM_Addr<16> | 7.000 |
Reset | SRAM_Addr<17> | 7.000 |
Reset | SRAM_Addr<18> | 7.000 |
Reset | SRAM_Addr<1> | 7.000 |
Reset | SRAM_Addr<2> | 7.000 |
Reset | SRAM_Addr<3> | 7.000 |
Reset | SRAM_Addr<4> | 7.000 |
Reset | SRAM_Addr<5> | 7.000 |
Reset | SRAM_Addr<6> | 7.000 |
Reset | SRAM_Addr<7> | 7.000 |
Reset | SRAM_Addr<8> | 7.000 |
Reset | SRAM_Addr<9> | 7.000 |
Reset | SRAM_CS | 7.000 |
Reset | SRAM_Data<0> | 7.000 |
Reset | SRAM_Data<1> | 7.000 |
Reset | SRAM_Data<2> | 7.000 |
Reset | SRAM_Data<3> | 7.000 |
Reset | SRAM_Data<4> | 7.000 |
Reset | SRAM_Data<5> | 7.000 |
Reset | SRAM_Data<6> | 7.000 |
Reset | SRAM_Data<7> | 7.000 |
Reset | SRAM_OE | 7.000 |
Reset | SRAM_WR | 7.000 |
Reset | VGA_CSync | 7.000 |
Reset | VGA_HSync | 7.000 |
Reset | VGA_RGB<0> | 7.000 |
Reset | VGA_RGB<1> | 7.000 |
Reset | VGA_RGB<2> | 7.000 |
Reset | VGA_RGB<3> | 7.000 |
Reset | VGA_RGB<4> | 7.000 |
Reset | VGA_RGB<5> | 7.000 |
Reset | VGA_Trace | 7.000 |
Reset | VGA_VSync | 7.000 |
AVR_AH<2> | AVR_AD<6> | 6.600 |
AVR_AH<2> | AVR_AD<7> | 6.600 |
AVR_AH<3> | AVR_AD<6> | 6.600 |
AVR_AH<3> | AVR_AD<7> | 6.600 |
AVR_AH<4> | AVR_AD<6> | 6.600 |
AVR_AH<4> | AVR_AD<7> | 6.600 |
AVR_AH<5> | AVR_AD<6> | 6.600 |
AVR_AH<5> | AVR_AD<7> | 6.600 |
AVR_AH<6> | AVR_AD<6> | 6.600 |
AVR_AH<6> | AVR_AD<7> | 6.600 |
AVR_AH<7> | AVR_AD<6> | 6.600 |
AVR_AH<7> | AVR_AD<7> | 6.600 |
Reset | AVR_AD<7> | 6.600 |
SRAM_Data<7> | AVR_AD<7> | 6.600 |
Reset | AVR_AD<6> | 6.300 |
SRAM_Data<6> | AVR_AD<6> | 6.300 |
AVR_AH<2> | AVR_AD<1> | 6.000 |
AVR_AH<2> | AVR_AD<2> | 6.000 |
AVR_AH<3> | AVR_AD<1> | 6.000 |
AVR_AH<3> | AVR_AD<2> | 6.000 |
AVR_AH<4> | AVR_AD<1> | 6.000 |
AVR_AH<4> | AVR_AD<2> | 6.000 |
AVR_AH<5> | AVR_AD<1> | 6.000 |
AVR_AH<5> | AVR_AD<2> | 6.000 |
AVR_AH<6> | AVR_AD<1> | 6.000 |
AVR_AH<6> | AVR_AD<2> | 6.000 |
AVR_AH<7> | AVR_AD<1> | 6.000 |
AVR_AH<7> | AVR_AD<2> | 6.000 |
AVR_RD | AVR_AD<1> | 6.000 |
AVR_RD | AVR_AD<2> | 6.000 |
AVR_RD | AVR_AD<7> | 6.000 |
Clock | AVR_AD<1> | 6.000 |
Clock | AVR_AD<2> | 6.000 |
Clock | AVR_AD<7> | 6.000 |
Reset | AVR_AD<1> | 6.000 |
Reset | AVR_AD<2> | 6.000 |
AVR_RD | AVR_AD<6> | 5.700 |
Clock | AVR_AD<6> | 5.700 |
Clock | SRAM_Addr<0> | 5.700 |
Clock | SRAM_Addr<7> | 5.700 |
AVR_AD<0> | SRAM_Data<0> | 5.000 |
AVR_AD<1> | SRAM_Data<1> | 5.000 |
AVR_AD<2> | SRAM_Data<2> | 5.000 |
AVR_AD<3> | SRAM_Data<3> | 5.000 |
AVR_AD<4> | SRAM_Data<4> | 5.000 |
AVR_AD<5> | SRAM_Data<5> | 5.000 |
AVR_AH<0> | SRAM_Addr<8> | 5.000 |
AVR_AH<1> | SRAM_Addr<9> | 5.000 |
AVR_AH<2> | SRAM_Addr<10> | 5.000 |
AVR_AH<2> | SRAM_CS | 5.000 |
AVR_AH<3> | SRAM_Addr<11> | 5.000 |
AVR_AH<3> | SRAM_CS | 5.000 |
AVR_AH<4> | SRAM_Addr<12> | 5.000 |
AVR_AH<4> | SRAM_CS | 5.000 |
AVR_AH<5> | SRAM_Addr<13> | 5.000 |
AVR_AH<5> | SRAM_CS | 5.000 |
AVR_AH<6> | SRAM_Addr<14> | 5.000 |
AVR_AH<6> | SRAM_CS | 5.000 |
AVR_AH<7> | SRAM_Addr<15> | 5.000 |
AVR_AH<7> | SRAM_Addr<16> | 5.000 |
AVR_AH<7> | SRAM_Addr<17> | 5.000 |
AVR_AH<7> | SRAM_Addr<18> | 5.000 |
AVR_AH<7> | SRAM_CS | 5.000 |
AVR_RD | SRAM_OE | 5.000 |
AVR_WR | SRAM_WR | 5.000 |
Clock | SRAM_Addr<10> | 5.000 |
Clock | SRAM_Addr<11> | 5.000 |
Clock | SRAM_Addr<12> | 5.000 |
Clock | SRAM_Addr<13> | 5.000 |
Clock | SRAM_Addr<14> | 5.000 |
Clock | SRAM_Addr<15> | 5.000 |
Clock | SRAM_Addr<16> | 5.000 |
Clock | SRAM_Addr<17> | 5.000 |
Clock | SRAM_Addr<18> | 5.000 |
Clock | SRAM_Addr<1> | 5.000 |
Clock | SRAM_Addr<2> | 5.000 |
Clock | SRAM_Addr<3> | 5.000 |
Clock | SRAM_Addr<4> | 5.000 |
Clock | SRAM_Addr<5> | 5.000 |
Clock | SRAM_Addr<6> | 5.000 |
Clock | SRAM_Addr<8> | 5.000 |
Clock | SRAM_Addr<9> | 5.000 |
Clock | SRAM_CS | 5.000 |
Clock | SRAM_OE | 5.000 |
Clock | SRAM_WR | 5.000 |
SRAM_Data<1> | AVR_AD<1> | 4.200 |
SRAM_Data<2> | AVR_AD<2> | 4.200 |
AVR_AD<6> | SRAM_Data<6> | 3.500 |
AVR_AD<7> | SRAM_Data<7> | 3.500 |