---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:28:29 08/24/2010 -- Design Name: -- Module Name: PWM - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity PWM is Port ( clk : in STD_LOGIC; pwmvalue : in STD_LOGIC_VECTOR (7 downto 0); pwmout : out STD_LOGIC := '0'); end PWM; architecture Behavioral of PWM is signal cnt : integer range 0 to 254 := 0; begin process begin wait until rising_edge(clk); -- Zähler if (cnt<254) then cnt <= cnt+1; else cnt <= 0; end if; end process; -- Vergleicher pwmout <= '0' when (cnt>=to_integer(unsigned(pwmvalue))) else '1'; end Behavioral;