# ############################################################################## # Created by Base System Builder Wizard for Xilinx EDK 11.4 Build EDK_LS4.68 # Wed Sep 15 09:02:39 2010 # Target Board: Xilinx Virtex 6 ML605 Evaluation Platform Rev 1 # Family: virtex6 # Device: xc6vlx240t # Package: ff1156 # Speed Grade: -1 # Processor number: 1 # Processor 1: microblaze_0 # System clock frequency: 100.0 # Debug Interface: On-Chip HW Debug Module # ############################################################################## PARAMETER VERSION = 2.1.0 PORT fpga_0_LEDs_8Bit_GPIO_IO_pin = fpga_0_LEDs_8Bit_GPIO_IO_pin, DIR = IO, VEC = [0:7] PORT fpga_0_Push_Buttons_5Bit_GPIO_IO_pin = fpga_0_Push_Buttons_5Bit_GPIO_IO_pin, DIR = IO, VEC = [0:4] PORT fpga_0_DDR3_SDRAM_DDR3_Clk_pin = fpga_0_DDR3_SDRAM_DDR3_Clk_pin, DIR = O PORT fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin = fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin, DIR = O PORT fpga_0_DDR3_SDRAM_DDR3_CE_pin = fpga_0_DDR3_SDRAM_DDR3_CE_pin, DIR = O PORT fpga_0_DDR3_SDRAM_DDR3_CS_n_pin = fpga_0_DDR3_SDRAM_DDR3_CS_n_pin, DIR = O PORT fpga_0_DDR3_SDRAM_DDR3_ODT_pin = fpga_0_DDR3_SDRAM_DDR3_ODT_pin, DIR = O PORT fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin = fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin, DIR = O PORT fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin = fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin, DIR = O PORT fpga_0_DDR3_SDRAM_DDR3_WE_n_pin = fpga_0_DDR3_SDRAM_DDR3_WE_n_pin, DIR = O PORT fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin = fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin, DIR = O, VEC = [2:0] PORT fpga_0_DDR3_SDRAM_DDR3_Addr_pin = fpga_0_DDR3_SDRAM_DDR3_Addr_pin, DIR = O, VEC = [12:0] PORT fpga_0_DDR3_SDRAM_DDR3_DQ_pin = fpga_0_DDR3_SDRAM_DDR3_DQ_pin, DIR = IO, VEC = [31:0] PORT fpga_0_DDR3_SDRAM_DDR3_DM_pin = fpga_0_DDR3_SDRAM_DDR3_DM_pin, DIR = O, VEC = [3:0] PORT fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin = fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin, DIR = O PORT fpga_0_DDR3_SDRAM_DDR3_DQS_pin = fpga_0_DDR3_SDRAM_DDR3_DQS_pin, DIR = IO, VEC = [3:0] PORT fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin = fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin, DIR = IO, VEC = [3:0] PORT fpga_0_clk_1_sys_clk_p_pin = dcm_clk_s, DIR = I, SIGIS = CLK, DIFFERENTIAL_POLARITY = P, CLK_FREQ = 200000000 PORT fpga_0_clk_1_sys_clk_n_pin = dcm_clk_s, DIR = I, SIGIS = CLK, DIFFERENTIAL_POLARITY = N, CLK_FREQ = 200000000 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1 BEGIN microblaze PARAMETER INSTANCE = microblaze_0 PARAMETER C_INTERCONNECT = 1 PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_ICACHE_BASEADDR = 0x50000000 PARAMETER C_ICACHE_HIGHADDR = 0x5fffffff PARAMETER C_CACHE_BYTE_SIZE = 32768 PARAMETER C_ICACHE_ALWAYS_USED = 1 PARAMETER C_DCACHE_BASEADDR = 0x50000000 PARAMETER C_DCACHE_HIGHADDR = 0x5fffffff PARAMETER C_DCACHE_BYTE_SIZE = 65536 PARAMETER C_DCACHE_ALWAYS_USED = 1 PARAMETER HW_VER = 7.20.d PARAMETER C_USE_ICACHE = 1 PARAMETER C_USE_DCACHE = 1 BUS_INTERFACE DLMB = dlmb BUS_INTERFACE ILMB = ilmb BUS_INTERFACE DPLB = mb_plb BUS_INTERFACE IPLB = mb_plb BUS_INTERFACE DXCL = microblaze_0_DXCL BUS_INTERFACE IXCL = microblaze_0_IXCL BUS_INTERFACE DEBUG = microblaze_0_mdm_bus PORT MB_RESET = mb_reset PORT INTERRUPT = xps_intc_0_Irq END BEGIN plb_v46 PARAMETER INSTANCE = mb_plb PARAMETER HW_VER = 1.04.a PORT PLB_Clk = clk_100_0000MHzMMCM0 PORT SYS_Rst = sys_bus_reset END BEGIN lmb_v10 PARAMETER INSTANCE = ilmb PARAMETER HW_VER = 1.00.a PORT LMB_Clk = clk_100_0000MHzMMCM0 PORT SYS_Rst = sys_bus_reset END BEGIN lmb_v10 PARAMETER INSTANCE = dlmb PARAMETER HW_VER = 1.00.a PORT LMB_Clk = clk_100_0000MHzMMCM0 PORT SYS_Rst = sys_bus_reset END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = dlmb_cntlr PARAMETER HW_VER = 2.10.b PARAMETER C_BASEADDR = 0xc2210000 PARAMETER C_HIGHADDR = 0xc221ffff BUS_INTERFACE SLMB = dlmb BUS_INTERFACE BRAM_PORT = dlmb_port END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = ilmb_cntlr PARAMETER HW_VER = 2.10.b PARAMETER C_BASEADDR = 0xc2210000 PARAMETER C_HIGHADDR = 0xc221ffff BUS_INTERFACE SLMB = ilmb BUS_INTERFACE BRAM_PORT = ilmb_port END BEGIN bram_block PARAMETER INSTANCE = lmb_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = ilmb_port BUS_INTERFACE PORTB = dlmb_port END BEGIN xps_gpio PARAMETER INSTANCE = LEDs_8Bit PARAMETER C_ALL_INPUTS = 0 PARAMETER C_GPIO_WIDTH = 8 PARAMETER C_INTERRUPT_PRESENT = 0 PARAMETER C_IS_DUAL = 0 PARAMETER HW_VER = 2.00.a PARAMETER C_BASEADDR = 0x81420000 PARAMETER C_HIGHADDR = 0x8142ffff BUS_INTERFACE SPLB = mb_plb PORT GPIO_IO = fpga_0_LEDs_8Bit_GPIO_IO_pin END BEGIN xps_gpio PARAMETER INSTANCE = Push_Buttons_5Bit PARAMETER C_ALL_INPUTS = 1 PARAMETER C_GPIO_WIDTH = 5 PARAMETER C_INTERRUPT_PRESENT = 1 PARAMETER C_IS_DUAL = 0 PARAMETER HW_VER = 2.00.a PARAMETER C_BASEADDR = 0x81400000 PARAMETER C_HIGHADDR = 0x8140ffff BUS_INTERFACE SPLB = mb_plb PORT GPIO_IO = fpga_0_Push_Buttons_5Bit_GPIO_IO_pin PORT IP2INTC_Irpt = Push_Buttons_5Bit_IP2INTC_Irpt END BEGIN mpmc PARAMETER INSTANCE = DDR3_SDRAM PARAMETER C_NUM_PORTS = 2 PARAMETER C_MMCM_EXT_LOC = MMCM_ADV_X0Y9 PARAMETER C_MEM_TYPE = DDR3 PARAMETER C_MEM_PARTNO = MT4JSF6464HY-1G1 PARAMETER C_MEM_ODT_TYPE = 1 PARAMETER C_MEM_REG_DIMM = 0 PARAMETER C_MEM_CLK_WIDTH = 1 PARAMETER C_MEM_ODT_WIDTH = 1 PARAMETER C_MEM_CE_WIDTH = 1 PARAMETER C_MEM_CS_N_WIDTH = 1 PARAMETER C_MEM_ADDR_WIDTH = 13 PARAMETER C_MEM_BANKADDR_WIDTH = 3 PARAMETER C_MEM_DATA_WIDTH = 32 PARAMETER C_MEM_DM_WIDTH = 4 PARAMETER C_MEM_DQS_WIDTH = 4 PARAMETER C_MEM_NDQS_COL0 = 3 PARAMETER C_MEM_NDQS_COL1 = 1 PARAMETER C_MEM_DQS_LOC_COL0 = 0x000000000000000000000000000000020100 PARAMETER C_MEM_DQS_LOC_COL1 = 0x000000000000000000000000000000000003 PARAMETER C_PIM0_BASETYPE = 1 PARAMETER C_PIM1_BASETYPE = 1 PARAMETER HW_VER = 5.04.a PARAMETER C_MPMC_BASEADDR = 0x50000000 PARAMETER C_MPMC_HIGHADDR = 0x5fffffff BUS_INTERFACE XCL0 = microblaze_0_IXCL BUS_INTERFACE XCL1 = microblaze_0_DXCL PORT MPMC_Clk0 = clk_200_0000MHzMMCM0 PORT MPMC_Clk_200MHz = clk_200_0000MHzMMCM0 PORT MPMC_Rst = sys_periph_reset PORT MPMC_Clk_Mem = clk_400_0000MHzMMCM0 PORT MPMC_Clk_Wr_I0 = clk_400_0000MHzMMCM0_nobuf_varphase PORT MPMC_DCM_PSEN = MPMC_DCM_PSEN PORT MPMC_DCM_PSINCDEC = MPMC_DCM_PSINCDEC PORT MPMC_DCM_PSDONE = MPMC_DCM_PSDONE PORT DDR3_Clk = fpga_0_DDR3_SDRAM_DDR3_Clk_pin PORT DDR3_Clk_n = fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin PORT DDR3_CE = fpga_0_DDR3_SDRAM_DDR3_CE_pin PORT DDR3_CS_n = fpga_0_DDR3_SDRAM_DDR3_CS_n_pin PORT DDR3_ODT = fpga_0_DDR3_SDRAM_DDR3_ODT_pin PORT DDR3_RAS_n = fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin PORT DDR3_CAS_n = fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin PORT DDR3_WE_n = fpga_0_DDR3_SDRAM_DDR3_WE_n_pin PORT DDR3_BankAddr = fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin PORT DDR3_Addr = fpga_0_DDR3_SDRAM_DDR3_Addr_pin PORT DDR3_DQ = fpga_0_DDR3_SDRAM_DDR3_DQ_pin PORT DDR3_DM = fpga_0_DDR3_SDRAM_DDR3_DM_pin PORT DDR3_Reset_n = fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin PORT DDR3_DQS = fpga_0_DDR3_SDRAM_DDR3_DQS_pin PORT DDR3_DQS_n = fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin END BEGIN clock_generator PARAMETER INSTANCE = clock_generator_0 PARAMETER C_EXT_RESET_HIGH = 1 PARAMETER C_CLKIN_FREQ = 200000000 PARAMETER C_PSDONE_GROUP = MMCM0_FB PARAMETER C_CLKOUT0_FREQ = 100000000 PARAMETER C_CLKOUT0_PHASE = 0 PARAMETER C_CLKOUT0_GROUP = MMCM0 PARAMETER C_CLKOUT0_BUF = TRUE PARAMETER C_CLKOUT1_FREQ = 200000000 PARAMETER C_CLKOUT1_PHASE = 0 PARAMETER C_CLKOUT1_GROUP = MMCM0 PARAMETER C_CLKOUT1_BUF = TRUE PARAMETER C_CLKOUT2_FREQ = 400000000 PARAMETER C_CLKOUT2_PHASE = 0 PARAMETER C_CLKOUT2_GROUP = MMCM0 PARAMETER C_CLKOUT2_BUF = TRUE PARAMETER C_CLKOUT3_FREQ = 400000000 PARAMETER C_CLKOUT3_PHASE = 0 PARAMETER C_CLKOUT3_GROUP = MMCM0 PARAMETER C_CLKOUT3_BUF = FALSE PARAMETER C_CLKOUT3_VARIABLE_PHASE = TRUE PARAMETER HW_VER = 3.02.a PORT CLKIN = dcm_clk_s PORT CLKOUT0 = clk_100_0000MHzMMCM0 PORT CLKOUT1 = clk_200_0000MHzMMCM0 PORT CLKOUT2 = clk_400_0000MHzMMCM0 PORT CLKOUT3 = clk_400_0000MHzMMCM0_nobuf_varphase PORT PSCLK = clk_200_0000MHzMMCM0 PORT PSEN = MPMC_DCM_PSEN PORT PSINCDEC = MPMC_DCM_PSINCDEC PORT PSDONE = MPMC_DCM_PSDONE PORT RST = sys_rst_s PORT LOCKED = Dcm_all_locked END BEGIN mdm PARAMETER INSTANCE = mdm_0 PARAMETER C_MB_DBG_PORTS = 1 PARAMETER C_USE_UART = 1 PARAMETER C_UART_WIDTH = 8 PARAMETER HW_VER = 1.00.g PARAMETER C_BASEADDR = 0x84400000 PARAMETER C_HIGHADDR = 0x8440ffff BUS_INTERFACE SPLB = mb_plb BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus PORT Debug_SYS_Rst = Debug_SYS_Rst END BEGIN proc_sys_reset PARAMETER INSTANCE = proc_sys_reset_0 PARAMETER C_EXT_RESET_HIGH = 1 PARAMETER HW_VER = 2.00.a PORT Slowest_sync_clk = clk_100_0000MHzMMCM0 PORT Ext_Reset_In = sys_rst_s PORT MB_Debug_Sys_Rst = Debug_SYS_Rst PORT Dcm_locked = Dcm_all_locked PORT MB_Reset = mb_reset PORT Bus_Struct_Reset = sys_bus_reset PORT Peripheral_Reset = sys_periph_reset END BEGIN xps_intc PARAMETER INSTANCE = xps_intc_0 PARAMETER HW_VER = 2.00.a PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x0000FFFF BUS_INTERFACE SPLB = mb_plb PORT Intr = Push_Buttons_5Bit_IP2INTC_Irpt PORT Irq = xps_intc_0_Irq END