Device Utilization Summary | [-] |
Slice Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Registers |
5,670 |
301,440 |
1% |
|
Number used as Flip Flops |
5,668 |
|
|
|
Number used as Latches |
0 |
|
|
|
Number used as Latch-thrus |
1 |
|
|
|
Number used as AND/OR logics |
1 |
|
|
|
Number of Slice LUTs |
5,883 |
150,720 |
3% |
|
Number used as logic |
4,291 |
150,720 |
2% |
|
Number using O6 output only |
3,762 |
|
|
|
Number using O5 output only |
243 |
|
|
|
Number using O5 and O6 |
286 |
|
|
|
Number used as ROM |
0 |
|
|
|
Number used as Memory |
555 |
58,400 |
1% |
|
Number used as Dual Port RAM |
296 |
|
|
|
Number using O6 output only |
16 |
|
|
|
Number using O5 output only |
0 |
|
|
|
Number using O5 and O6 |
280 |
|
|
|
Number used as Single Port RAM |
0 |
|
|
|
Number used as Shift Register |
259 |
|
|
|
Number using O6 output only |
254 |
|
|
|
Number using O5 output only |
1 |
|
|
|
Number using O5 and O6 |
4 |
|
|
|
Number used exclusively as route-thrus |
1,037 |
|
|
|
Number with same-slice register load |
999 |
|
|
|
Number with same-slice carry load |
27 |
|
|
|
Number with other load |
11 |
|
|
|
Number of occupied Slices |
2,149 |
37,680 |
5% |
|
Number of LUT Flip Flop pairs used |
6,187 |
|
|
|
Number with an unused Flip Flop |
1,943 |
6,187 |
31% |
|
Number with an unused LUT |
304 |
6,187 |
4% |
|
Number of fully used LUT-FF pairs |
3,940 |
6,187 |
63% |
|
Number of unique control sets |
272 |
|
|
|
Number of slice register sites lost to control set restrictions |
1,149 |
301,440 |
1% |
|
Number of bonded IOBs |
80 |
600 |
13% |
|
Number of LOCed IOBs |
80 |
80 |
100% |
|
IOB Flip Flops |
1 |
|
|
|
IOB Master Pads |
5 |
|
|
|
IOB Slave Pads |
5 |
|
|
|
Number of RAMB36E1/FIFO36E1s |
56 |
416 |
13% |
|
Number using RAMB36E1 only |
56 |
|
|
|
Number using FIFO36E1 only |
0 |
|
|
|
Number of RAMB18E1/FIFO18E1s |
0 |
832 |
0% |
|
Number of BUFG/BUFGCTRLs |
4 |
32 |
12% |
|
Number used as BUFGs |
4 |
|
|
|
Number used as BUFGCTRLs |
0 |
|
|
|
Number of ILOGICE1/ISERDESE1s |
36 |
720 |
5% |
|
Number used as ILOGICE1s |
0 |
|
|
|
Number used as ISERDESE1s |
36 |
|
|
|
Number of OLOGICE1/OSERDESE1s |
75 |
720 |
10% |
|
Number used as OLOGICE1s |
1 |
|
|
|
Number used as OSERDESE1s |
74 |
|
|
|
Number of BSCANs |
1 |
4 |
25% |
|
Number of BUFHCEs |
0 |
144 |
0% |
|
Number of BUFOs |
0 |
36 |
0% |
|
Number of BUFIODQSs |
4 |
72 |
5% |
|
Number of BUFRs |
2 |
36 |
5% |
|
Number of LOCed BUFRs |
2 |
2 |
100% |
|
Number of CAPTUREs |
0 |
1 |
0% |
|
Number of DCIs |
0 |
18 |
0% |
|
Number of DSP48E1s |
3 |
768 |
1% |
|
Number of EFUSE_USRs |
0 |
1 |
0% |
|
Number of GTXE1s |
0 |
20 |
0% |
|
Number of IBUFDS_GTXE1s |
0 |
12 |
0% |
|
Number of ICAPs |
0 |
2 |
0% |
|
Number of IDELAYCTRLs |
2 |
18 |
11% |
|
Number of IODELAYE1s |
46 |
720 |
6% |
|
Number of LOCed IODELAYE1s |
6 |
46 |
13% |
|
Number of MMCM_ADVs |
2 |
12 |
16% |
|
Number of LOCed MMCM_ADVs |
2 |
2 |
100% |
|
Number of PCIE_2_0s |
0 |
2 |
0% |
|
Number of PMVs |
0 |
2 |
0% |
|
Number of PMVBRAMs |
0 |
54 |
0% |
|
Number of PMVIOBs |
0 |
5 |
0% |
|
Number of STARTUPs |
0 |
1 |
0% |
|
Number of SYSMONs |
0 |
1 |
0% |
|
Number of TEMAC_SINGLEs |
0 |
4 |
0% |
|
Average Fanout of Non-Clock Nets |
3.66 |
|
|
|