library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.std_logic_ARITH.ALL; use IEEE.std_logic_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Fifo16Bit_to_8_Bit is Port ( CLK_100MHZ : in std_logic; SPRAM_ADDRESS_FIFO_CYLCE : out std_logic_vector (12 downto 0); DATA_FROM_SPRAM : in std_logic_VECTOR (24 downto 0); FIFO_ENABLE : in std_logic; FIFO_DATA_OUT : out std_logic_VECTOR(7 downto 0); CLK_921600 : in std_logic; FIFO_EMPTY : OUT std_logic; FIFO_READ_ENABLE : in std_logic ); end Fifo16Bit_to_8_Bit; architecture Behavioral of Fifo16Bit_to_8_Bit is component Fifo port ( rst: IN std_logic; wr_clk: IN std_logic; rd_clk: IN std_logic; din: IN std_logic_VECTOR(15 downto 0); wr_en: IN std_logic; rd_en: IN std_logic; dout: OUT std_logic_VECTOR(7 downto 0); full: OUT std_logic; empty: OUT std_logic); end component; Signal FIFO_WRITE_ENABLE : std_logic; Signal FIFO_DATA_IN : std_logic_vector (15 downto 0); --Signal FIFO_DATA_OUT : std_logic_VECTOR(7 downto 0); --Signal FIFO_FULL : std_logic; --Signal FIFO_EMPTY : std_logic; Signal SPRAM_WRITE_TO_FIFO_ADRESS : std_logic_vector (12 downto 0); Signal WRITE_ENABLE : std_logic; signal READ_ENABLE : std_logic; type FSM_FIFO_WRITE is (TRACKING, WRITE_FIFO, WAIT_STATE); Signal CURRENT_STATE : FSM_FIFO_WRITE:= TRACKING; Signal NEXT_STATE : FSM_FIFO_WRITE; Signal JUMP_NEXT_STATE_ENABLE : std_logic; begin SPRAM_ADDRESS_FIFO_CYLCE <= SPRAM_WRITE_TO_FIFO_ADRESS; --------------------------------------------------------------------------------------------- -- DIESE STATEMACHINE IST FÜR DAS ERZEUGEN DES FIFO WRITE ENABLES SIGNALS ZUSTÄNDIG, DIESER -- AUTOMAT WIRD VON FIFO_ENABLE GETRIGGERT --------------------------------------------------------------------------------------------- SWITCH_STATE: Process (CLK_100MHZ) Begin if rising_edge (CLK_100MHZ) then CURRENT_STATE <= NEXT_STATE; FIFO_DATA_IN <= DATA_FROM_SPRAM(24 downto 9); end if; End Process SWITCH_STATE; FIFO_FSM_PROCEDURE: Process (CURRENT_STATE,FIFO_ENABLE,JUMP_NEXT_STATE_ENABLE) Begin case CURRENT_STATE is when TRACKING => WRITE_ENABLE <= '0'; if FIFO_ENABLE = '1' then -- entspricht letzter steigender Rechteckflanke NEXT_STATE <= WRITE_FIFO; else NEXT_STATE <= TRACKING; end if; when WRITE_FIFO => WRITE_ENABLE <= '1'; if JUMP_NEXT_STATE_ENABLE = '1' then NEXT_STATE <= WAIT_STATE; else NEXT_STATE <= WRITE_FIFO; end if; when WAIT_STATE => WRITE_ENABLE <= '0'; if FIFO_ENABLE = '1' then NEXT_STATE <= WAIT_STATE; else NEXT_STATE <= TRACKING; end if; end case; end process FIFO_FSM_PROCEDURE; -- DIESER PROZESS BESTIMMT ZUM EINEM DAS FIFO WRITE ENABLE ZUM ANDEREN ERZEUGT ES DEN -- ADRESS ZYKLUS DES SPRAMS WENN DIE DATEN VOM SPRAM INS FIFO GESCHRIEBEN WERDEN SOLLEN BRAM_TO_FIFO: Process (CLK_100MHz) Begin if falling_edge (CLK_100MHZ) then if WRITE_ENABLE = '1' then -- solange Adressvergleich bis "1110000011111" erreicht ist -> letzter Wert if SPRAM_WRITE_TO_FIFO_ADRESS >= "1110000011111" then --"1110000011111" SPRAM_WRITE_TO_FIFO_ADRESS <= SPRAM_WRITE_TO_FIFO_ADRESS; FIFO_WRITE_ENABLE <= '0'; JUMP_NEXT_STATE_ENABLE <= '0'; else JUMP_NEXT_STATE_ENABLE <= '1'; FIFO_WRITE_ENABLE <= '1'; SPRAM_WRITE_TO_FIFO_ADRESS <= SPRAM_WRITE_TO_FIFO_ADRESS + 1; end if; else JUMP_NEXT_STATE_ENABLE <= '0'; FIFO_WRITE_ENABLE <= '0'; SPRAM_WRITE_TO_FIFO_ADRESS <= "0000000000000"; end if; end if; End Process BRAM_TO_FIFO; Component1 : Fifo port map ( rst => '0', wr_clk => CLK_100MHZ, rd_clk => CLK_921600, din => FIFO_DATA_IN, wr_en => FIFO_WRITE_ENABLE, rd_en => FIFO_READ_ENABLE, dout => FIFO_DATA_OUT, full => open, empty => FIFO_EMPTY); end Behavioral;